1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 * 8 * All MC4_MISCi registers are shared between cores on a node. 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/kobject.h> 13 #include <linux/percpu.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sysfs.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/smp.h> 21 #include <linux/string.h> 22 23 #include <asm/amd_nb.h> 24 #include <asm/traps.h> 25 #include <asm/apic.h> 26 #include <asm/mce.h> 27 #include <asm/msr.h> 28 #include <asm/trace/irq_vectors.h> 29 30 #include "internal.h" 31 32 #define NR_BLOCKS 5 33 #define THRESHOLD_MAX 0xFFF 34 #define INT_TYPE_APIC 0x00020000 35 #define MASK_VALID_HI 0x80000000 36 #define MASK_CNTP_HI 0x40000000 37 #define MASK_LOCKED_HI 0x20000000 38 #define MASK_LVTOFF_HI 0x00F00000 39 #define MASK_COUNT_EN_HI 0x00080000 40 #define MASK_INT_TYPE_HI 0x00060000 41 #define MASK_OVERFLOW_HI 0x00010000 42 #define MASK_ERR_COUNT_HI 0x00000FFF 43 #define MASK_BLKPTR_LO 0xFF000000 44 #define MCG_XBLK_ADDR 0xC0000400 45 46 /* Deferred error settings */ 47 #define MSR_CU_DEF_ERR 0xC0000410 48 #define MASK_DEF_LVTOFF 0x000000F0 49 #define MASK_DEF_INT_TYPE 0x00000006 50 #define DEF_LVT_OFF 0x2 51 #define DEF_INT_TYPE_APIC 0x2 52 53 /* Scalable MCA: */ 54 55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 56 #define SMCA_THR_LVT_OFF 0xF000 57 58 static bool thresholding_irq_en; 59 60 static const char * const th_names[] = { 61 "load_store", 62 "insn_fetch", 63 "combined_unit", 64 "decode_unit", 65 "northbridge", 66 "execution_unit", 67 }; 68 69 static const char * const smca_umc_block_names[] = { 70 "dram_ecc", 71 "misc_umc" 72 }; 73 74 struct smca_bank_name { 75 const char *name; /* Short name for sysfs */ 76 const char *long_name; /* Long name for pretty-printing */ 77 }; 78 79 static struct smca_bank_name smca_names[] = { 80 [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 81 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 82 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 83 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 84 [SMCA_RESERVED] = { "reserved", "Reserved" }, 85 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 86 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 87 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 88 [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 89 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 90 91 /* UMC v2 is separate because both of them can exist in a single system. */ 92 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 93 [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, 94 [SMCA_PB] = { "param_block", "Parameter Block" }, 95 [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 96 [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, 97 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 98 [SMCA_MPDMA] = { "mpdma", "MPDMA Unit" }, 99 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 100 [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, 101 [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, 102 [SMCA_NBIF] = { "nbif", "NBIF Unit" }, 103 [SMCA_SHUB] = { "shub", "System Hub Unit" }, 104 [SMCA_SATA] = { "sata", "SATA Unit" }, 105 [SMCA_USB] = { "usb", "USB Unit" }, 106 [SMCA_GMI_PCS] = { "gmi_pcs", "Global Memory Interconnect PCS Unit" }, 107 [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, 108 [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, 109 [SMCA_GMI_PHY] = { "gmi_phy", "Global Memory Interconnect PHY Unit" }, 110 }; 111 112 static const char *smca_get_name(enum smca_bank_types t) 113 { 114 if (t >= N_SMCA_BANK_TYPES) 115 return NULL; 116 117 return smca_names[t].name; 118 } 119 120 const char *smca_get_long_name(enum smca_bank_types t) 121 { 122 if (t >= N_SMCA_BANK_TYPES) 123 return NULL; 124 125 return smca_names[t].long_name; 126 } 127 EXPORT_SYMBOL_GPL(smca_get_long_name); 128 129 enum smca_bank_types smca_get_bank_type(unsigned int bank) 130 { 131 struct smca_bank *b; 132 133 if (bank >= MAX_NR_BANKS) 134 return N_SMCA_BANK_TYPES; 135 136 b = &smca_banks[bank]; 137 if (!b->hwid) 138 return N_SMCA_BANK_TYPES; 139 140 return b->hwid->bank_type; 141 } 142 EXPORT_SYMBOL_GPL(smca_get_bank_type); 143 144 static struct smca_hwid smca_hwid_mcatypes[] = { 145 /* { bank_type, hwid_mcatype } */ 146 147 /* Reserved type */ 148 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 149 150 /* ZN Core (HWID=0xB0) MCA types */ 151 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 152 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 153 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 154 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 155 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 156 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 157 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 158 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 159 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 160 161 /* Data Fabric MCA types */ 162 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 163 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 164 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 165 166 /* Unified Memory Controller MCA type */ 167 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 168 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 169 170 /* Parameter Block MCA type */ 171 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 172 173 /* Platform Security Processor MCA type */ 174 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 175 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 176 177 /* System Management Unit MCA type */ 178 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 179 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 180 181 /* Microprocessor 5 Unit MCA type */ 182 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 183 184 /* MPDMA MCA type */ 185 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, 186 187 /* Northbridge IO Unit MCA type */ 188 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 189 190 /* PCI Express Unit MCA type */ 191 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 192 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 193 194 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 195 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 196 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 197 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, 198 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, 199 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 200 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 201 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 202 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 203 }; 204 205 struct smca_bank smca_banks[MAX_NR_BANKS]; 206 EXPORT_SYMBOL_GPL(smca_banks); 207 208 /* 209 * In SMCA enabled processors, we can have multiple banks for a given IP type. 210 * So to define a unique name for each bank, we use a temp c-string to append 211 * the MCA_IPID[InstanceId] to type's name in get_name(). 212 * 213 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 214 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 215 */ 216 #define MAX_MCATYPE_NAME_LEN 30 217 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 218 219 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 220 221 /* 222 * A list of the banks enabled on each logical CPU. Controls which respective 223 * descriptors to initialize later in mce_threshold_create_device(). 224 */ 225 static DEFINE_PER_CPU(unsigned int, bank_map); 226 227 /* Map of banks that have more than MCA_MISC0 available. */ 228 static DEFINE_PER_CPU(u32, smca_misc_banks_map); 229 230 static void amd_threshold_interrupt(void); 231 static void amd_deferred_error_interrupt(void); 232 233 static void default_deferred_error_interrupt(void) 234 { 235 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 236 } 237 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 238 239 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 240 { 241 u32 low, high; 242 243 /* 244 * For SMCA enabled processors, BLKPTR field of the first MISC register 245 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 246 */ 247 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 248 return; 249 250 if (!(low & MCI_CONFIG_MCAX)) 251 return; 252 253 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 254 return; 255 256 if (low & MASK_BLKPTR_LO) 257 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 258 259 } 260 261 static void smca_configure(unsigned int bank, unsigned int cpu) 262 { 263 unsigned int i, hwid_mcatype; 264 struct smca_hwid *s_hwid; 265 u32 high, low; 266 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 267 268 /* Set appropriate bits in MCA_CONFIG */ 269 if (!rdmsr_safe(smca_config, &low, &high)) { 270 /* 271 * OS is required to set the MCAX bit to acknowledge that it is 272 * now using the new MSR ranges and new registers under each 273 * bank. It also means that the OS will configure deferred 274 * errors in the new MCx_CONFIG register. If the bit is not set, 275 * uncorrectable errors will cause a system panic. 276 * 277 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 278 */ 279 high |= BIT(0); 280 281 /* 282 * SMCA sets the Deferred Error Interrupt type per bank. 283 * 284 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 285 * if the DeferredIntType bit field is available. 286 * 287 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 288 * high portion of the MSR). OS should set this to 0x1 to enable 289 * APIC based interrupt. First, check that no interrupt has been 290 * set. 291 */ 292 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 293 high |= BIT(5); 294 295 wrmsr(smca_config, low, high); 296 } 297 298 smca_set_misc_banks_map(bank, cpu); 299 300 /* Return early if this bank was already initialized. */ 301 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) 302 return; 303 304 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 305 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 306 return; 307 } 308 309 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 310 (high & MCI_IPID_MCATYPE) >> 16); 311 312 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 313 s_hwid = &smca_hwid_mcatypes[i]; 314 if (hwid_mcatype == s_hwid->hwid_mcatype) { 315 smca_banks[bank].hwid = s_hwid; 316 smca_banks[bank].id = low; 317 smca_banks[bank].sysfs_id = s_hwid->count++; 318 break; 319 } 320 } 321 } 322 323 struct thresh_restart { 324 struct threshold_block *b; 325 int reset; 326 int set_lvt_off; 327 int lvt_off; 328 u16 old_limit; 329 }; 330 331 static inline bool is_shared_bank(int bank) 332 { 333 /* 334 * Scalable MCA provides for only one core to have access to the MSRs of 335 * a shared bank. 336 */ 337 if (mce_flags.smca) 338 return false; 339 340 /* Bank 4 is for northbridge reporting and is thus shared */ 341 return (bank == 4); 342 } 343 344 static const char *bank4_names(const struct threshold_block *b) 345 { 346 switch (b->address) { 347 /* MSR4_MISC0 */ 348 case 0x00000413: 349 return "dram"; 350 351 case 0xc0000408: 352 return "ht_links"; 353 354 case 0xc0000409: 355 return "l3_cache"; 356 357 default: 358 WARN(1, "Funny MSR: 0x%08x\n", b->address); 359 return ""; 360 } 361 }; 362 363 364 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 365 { 366 /* 367 * bank 4 supports APIC LVT interrupts implicitly since forever. 368 */ 369 if (bank == 4) 370 return true; 371 372 /* 373 * IntP: interrupt present; if this bit is set, the thresholding 374 * bank can generate APIC LVT interrupts 375 */ 376 return msr_high_bits & BIT(28); 377 } 378 379 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 380 { 381 int msr = (hi & MASK_LVTOFF_HI) >> 20; 382 383 if (apic < 0) { 384 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 385 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 386 b->bank, b->block, b->address, hi, lo); 387 return 0; 388 } 389 390 if (apic != msr) { 391 /* 392 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 393 * the BIOS provides the value. The original field where LVT offset 394 * was set is reserved. Return early here: 395 */ 396 if (mce_flags.smca) 397 return 0; 398 399 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 400 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 401 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 402 return 0; 403 } 404 405 return 1; 406 }; 407 408 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 409 static void threshold_restart_bank(void *_tr) 410 { 411 struct thresh_restart *tr = _tr; 412 u32 hi, lo; 413 414 /* sysfs write might race against an offline operation */ 415 if (this_cpu_read(threshold_banks)) 416 return; 417 418 rdmsr(tr->b->address, lo, hi); 419 420 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 421 tr->reset = 1; /* limit cannot be lower than err count */ 422 423 if (tr->reset) { /* reset err count and overflow bit */ 424 hi = 425 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 426 (THRESHOLD_MAX - tr->b->threshold_limit); 427 } else if (tr->old_limit) { /* change limit w/o reset */ 428 int new_count = (hi & THRESHOLD_MAX) + 429 (tr->old_limit - tr->b->threshold_limit); 430 431 hi = (hi & ~MASK_ERR_COUNT_HI) | 432 (new_count & THRESHOLD_MAX); 433 } 434 435 /* clear IntType */ 436 hi &= ~MASK_INT_TYPE_HI; 437 438 if (!tr->b->interrupt_capable) 439 goto done; 440 441 if (tr->set_lvt_off) { 442 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 443 /* set new lvt offset */ 444 hi &= ~MASK_LVTOFF_HI; 445 hi |= tr->lvt_off << 20; 446 } 447 } 448 449 if (tr->b->interrupt_enable) 450 hi |= INT_TYPE_APIC; 451 452 done: 453 454 hi |= MASK_COUNT_EN_HI; 455 wrmsr(tr->b->address, lo, hi); 456 } 457 458 static void mce_threshold_block_init(struct threshold_block *b, int offset) 459 { 460 struct thresh_restart tr = { 461 .b = b, 462 .set_lvt_off = 1, 463 .lvt_off = offset, 464 }; 465 466 b->threshold_limit = THRESHOLD_MAX; 467 threshold_restart_bank(&tr); 468 }; 469 470 static int setup_APIC_mce_threshold(int reserved, int new) 471 { 472 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 473 APIC_EILVT_MSG_FIX, 0)) 474 return new; 475 476 return reserved; 477 } 478 479 static int setup_APIC_deferred_error(int reserved, int new) 480 { 481 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 482 APIC_EILVT_MSG_FIX, 0)) 483 return new; 484 485 return reserved; 486 } 487 488 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 489 { 490 u32 low = 0, high = 0; 491 int def_offset = -1, def_new; 492 493 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 494 return; 495 496 def_new = (low & MASK_DEF_LVTOFF) >> 4; 497 if (!(low & MASK_DEF_LVTOFF)) { 498 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 499 def_new = DEF_LVT_OFF; 500 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 501 } 502 503 def_offset = setup_APIC_deferred_error(def_offset, def_new); 504 if ((def_offset == def_new) && 505 (deferred_error_int_vector != amd_deferred_error_interrupt)) 506 deferred_error_int_vector = amd_deferred_error_interrupt; 507 508 if (!mce_flags.smca) 509 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 510 511 wrmsr(MSR_CU_DEF_ERR, low, high); 512 } 513 514 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 515 unsigned int cpu) 516 { 517 if (!block) 518 return MSR_AMD64_SMCA_MCx_MISC(bank); 519 520 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 521 return 0; 522 523 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 524 } 525 526 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 527 unsigned int bank, unsigned int block, 528 unsigned int cpu) 529 { 530 u32 addr = 0, offset = 0; 531 532 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 533 return addr; 534 535 if (mce_flags.smca) 536 return smca_get_block_address(bank, block, cpu); 537 538 /* Fall back to method we used for older processors: */ 539 switch (block) { 540 case 0: 541 addr = mca_msr_reg(bank, MCA_MISC); 542 break; 543 case 1: 544 offset = ((low & MASK_BLKPTR_LO) >> 21); 545 if (offset) 546 addr = MCG_XBLK_ADDR + offset; 547 break; 548 default: 549 addr = ++current_addr; 550 } 551 return addr; 552 } 553 554 static int 555 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 556 int offset, u32 misc_high) 557 { 558 unsigned int cpu = smp_processor_id(); 559 u32 smca_low, smca_high; 560 struct threshold_block b; 561 int new; 562 563 if (!block) 564 per_cpu(bank_map, cpu) |= (1 << bank); 565 566 memset(&b, 0, sizeof(b)); 567 b.cpu = cpu; 568 b.bank = bank; 569 b.block = block; 570 b.address = addr; 571 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 572 573 if (!b.interrupt_capable) 574 goto done; 575 576 b.interrupt_enable = 1; 577 578 if (!mce_flags.smca) { 579 new = (misc_high & MASK_LVTOFF_HI) >> 20; 580 goto set_offset; 581 } 582 583 /* Gather LVT offset for thresholding: */ 584 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 585 goto out; 586 587 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 588 589 set_offset: 590 offset = setup_APIC_mce_threshold(offset, new); 591 if (offset == new) 592 thresholding_irq_en = true; 593 594 done: 595 mce_threshold_block_init(&b, offset); 596 597 out: 598 return offset; 599 } 600 601 bool amd_filter_mce(struct mce *m) 602 { 603 enum smca_bank_types bank_type = smca_get_bank_type(m->bank); 604 struct cpuinfo_x86 *c = &boot_cpu_data; 605 606 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 607 if (c->x86 == 0x17 && 608 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 609 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 610 return true; 611 612 /* NB GART TLB error reporting is disabled by default. */ 613 if (c->x86 < 0x17) { 614 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 615 return true; 616 } 617 618 return false; 619 } 620 621 /* 622 * Turn off thresholding banks for the following conditions: 623 * - MC4_MISC thresholding is not supported on Family 0x15. 624 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 625 * Models 0x10-0x2F due to Erratum #1114. 626 */ 627 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 628 { 629 int i, num_msrs; 630 u64 hwcr; 631 bool need_toggle; 632 u32 msrs[NR_BLOCKS]; 633 634 if (c->x86 == 0x15 && bank == 4) { 635 msrs[0] = 0x00000413; /* MC4_MISC0 */ 636 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 637 num_msrs = 2; 638 } else if (c->x86 == 0x17 && 639 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 640 641 if (smca_get_bank_type(bank) != SMCA_IF) 642 return; 643 644 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 645 num_msrs = 1; 646 } else { 647 return; 648 } 649 650 rdmsrl(MSR_K7_HWCR, hwcr); 651 652 /* McStatusWrEn has to be set */ 653 need_toggle = !(hwcr & BIT(18)); 654 if (need_toggle) 655 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 656 657 /* Clear CntP bit safely */ 658 for (i = 0; i < num_msrs; i++) 659 msr_clear_bit(msrs[i], 62); 660 661 /* restore old settings */ 662 if (need_toggle) 663 wrmsrl(MSR_K7_HWCR, hwcr); 664 } 665 666 /* cpu init entry point, called from mce.c with preempt off */ 667 void mce_amd_feature_init(struct cpuinfo_x86 *c) 668 { 669 unsigned int bank, block, cpu = smp_processor_id(); 670 u32 low = 0, high = 0, address = 0; 671 int offset = -1; 672 673 674 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 675 if (mce_flags.smca) 676 smca_configure(bank, cpu); 677 678 disable_err_thresholding(c, bank); 679 680 for (block = 0; block < NR_BLOCKS; ++block) { 681 address = get_block_address(address, low, high, bank, block, cpu); 682 if (!address) 683 break; 684 685 if (rdmsr_safe(address, &low, &high)) 686 break; 687 688 if (!(high & MASK_VALID_HI)) 689 continue; 690 691 if (!(high & MASK_CNTP_HI) || 692 (high & MASK_LOCKED_HI)) 693 continue; 694 695 offset = prepare_threshold_block(bank, block, address, offset, high); 696 } 697 } 698 699 if (mce_flags.succor) 700 deferred_error_interrupt_enable(c); 701 } 702 703 bool amd_mce_is_memory_error(struct mce *m) 704 { 705 /* ErrCodeExt[20:16] */ 706 u8 xec = (m->status >> 16) & 0x1f; 707 708 if (mce_flags.smca) 709 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; 710 711 return m->bank == 4 && xec == 0x8; 712 } 713 714 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 715 { 716 struct mce m; 717 718 mce_setup(&m); 719 720 m.status = status; 721 m.misc = misc; 722 m.bank = bank; 723 m.tsc = rdtsc(); 724 725 if (m.status & MCI_STATUS_ADDRV) { 726 m.addr = addr; 727 728 /* 729 * Extract [55:<lsb>] where lsb is the least significant 730 * *valid* bit of the address bits. 731 */ 732 if (mce_flags.smca) { 733 u8 lsb = (m.addr >> 56) & 0x3f; 734 735 m.addr &= GENMASK_ULL(55, lsb); 736 } 737 } 738 739 if (mce_flags.smca) { 740 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 741 742 if (m.status & MCI_STATUS_SYNDV) 743 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 744 } 745 746 mce_log(&m); 747 } 748 749 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 750 { 751 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 752 inc_irq_stat(irq_deferred_error_count); 753 deferred_error_int_vector(); 754 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 755 ack_APIC_irq(); 756 } 757 758 /* 759 * Returns true if the logged error is deferred. False, otherwise. 760 */ 761 static inline bool 762 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 763 { 764 u64 status, addr = 0; 765 766 rdmsrl(msr_stat, status); 767 if (!(status & MCI_STATUS_VAL)) 768 return false; 769 770 if (status & MCI_STATUS_ADDRV) 771 rdmsrl(msr_addr, addr); 772 773 __log_error(bank, status, addr, misc); 774 775 wrmsrl(msr_stat, 0); 776 777 return status & MCI_STATUS_DEFERRED; 778 } 779 780 /* 781 * We have three scenarios for checking for Deferred errors: 782 * 783 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 784 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 785 * clear MCA_DESTAT. 786 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 787 * log it. 788 */ 789 static void log_error_deferred(unsigned int bank) 790 { 791 bool defrd; 792 793 defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), 794 mca_msr_reg(bank, MCA_ADDR), 0); 795 796 if (!mce_flags.smca) 797 return; 798 799 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 800 if (defrd) { 801 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 802 return; 803 } 804 805 /* 806 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 807 * for a valid error. 808 */ 809 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 810 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 811 } 812 813 /* APIC interrupt handler for deferred errors */ 814 static void amd_deferred_error_interrupt(void) 815 { 816 unsigned int bank; 817 818 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 819 log_error_deferred(bank); 820 } 821 822 static void log_error_thresholding(unsigned int bank, u64 misc) 823 { 824 _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc); 825 } 826 827 static void log_and_reset_block(struct threshold_block *block) 828 { 829 struct thresh_restart tr; 830 u32 low = 0, high = 0; 831 832 if (!block) 833 return; 834 835 if (rdmsr_safe(block->address, &low, &high)) 836 return; 837 838 if (!(high & MASK_OVERFLOW_HI)) 839 return; 840 841 /* Log the MCE which caused the threshold event. */ 842 log_error_thresholding(block->bank, ((u64)high << 32) | low); 843 844 /* Reset threshold block after logging error. */ 845 memset(&tr, 0, sizeof(tr)); 846 tr.b = block; 847 threshold_restart_bank(&tr); 848 } 849 850 /* 851 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 852 * goes off when error_count reaches threshold_limit. 853 */ 854 static void amd_threshold_interrupt(void) 855 { 856 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 857 struct threshold_bank **bp = this_cpu_read(threshold_banks); 858 unsigned int bank, cpu = smp_processor_id(); 859 860 /* 861 * Validate that the threshold bank has been initialized already. The 862 * handler is installed at boot time, but on a hotplug event the 863 * interrupt might fire before the data has been initialized. 864 */ 865 if (!bp) 866 return; 867 868 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 869 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 870 continue; 871 872 first_block = bp[bank]->blocks; 873 if (!first_block) 874 continue; 875 876 /* 877 * The first block is also the head of the list. Check it first 878 * before iterating over the rest. 879 */ 880 log_and_reset_block(first_block); 881 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 882 log_and_reset_block(block); 883 } 884 } 885 886 /* 887 * Sysfs Interface 888 */ 889 890 struct threshold_attr { 891 struct attribute attr; 892 ssize_t (*show) (struct threshold_block *, char *); 893 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 894 }; 895 896 #define SHOW_FIELDS(name) \ 897 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 898 { \ 899 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 900 } 901 SHOW_FIELDS(interrupt_enable) 902 SHOW_FIELDS(threshold_limit) 903 904 static ssize_t 905 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 906 { 907 struct thresh_restart tr; 908 unsigned long new; 909 910 if (!b->interrupt_capable) 911 return -EINVAL; 912 913 if (kstrtoul(buf, 0, &new) < 0) 914 return -EINVAL; 915 916 b->interrupt_enable = !!new; 917 918 memset(&tr, 0, sizeof(tr)); 919 tr.b = b; 920 921 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 922 return -ENODEV; 923 924 return size; 925 } 926 927 static ssize_t 928 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 929 { 930 struct thresh_restart tr; 931 unsigned long new; 932 933 if (kstrtoul(buf, 0, &new) < 0) 934 return -EINVAL; 935 936 if (new > THRESHOLD_MAX) 937 new = THRESHOLD_MAX; 938 if (new < 1) 939 new = 1; 940 941 memset(&tr, 0, sizeof(tr)); 942 tr.old_limit = b->threshold_limit; 943 b->threshold_limit = new; 944 tr.b = b; 945 946 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 947 return -ENODEV; 948 949 return size; 950 } 951 952 static ssize_t show_error_count(struct threshold_block *b, char *buf) 953 { 954 u32 lo, hi; 955 956 /* CPU might be offline by now */ 957 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 958 return -ENODEV; 959 960 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 961 (THRESHOLD_MAX - b->threshold_limit))); 962 } 963 964 static struct threshold_attr error_count = { 965 .attr = {.name = __stringify(error_count), .mode = 0444 }, 966 .show = show_error_count, 967 }; 968 969 #define RW_ATTR(val) \ 970 static struct threshold_attr val = { \ 971 .attr = {.name = __stringify(val), .mode = 0644 }, \ 972 .show = show_## val, \ 973 .store = store_## val, \ 974 }; 975 976 RW_ATTR(interrupt_enable); 977 RW_ATTR(threshold_limit); 978 979 static struct attribute *default_attrs[] = { 980 &threshold_limit.attr, 981 &error_count.attr, 982 NULL, /* possibly interrupt_enable if supported, see below */ 983 NULL, 984 }; 985 986 #define to_block(k) container_of(k, struct threshold_block, kobj) 987 #define to_attr(a) container_of(a, struct threshold_attr, attr) 988 989 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 990 { 991 struct threshold_block *b = to_block(kobj); 992 struct threshold_attr *a = to_attr(attr); 993 ssize_t ret; 994 995 ret = a->show ? a->show(b, buf) : -EIO; 996 997 return ret; 998 } 999 1000 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1001 const char *buf, size_t count) 1002 { 1003 struct threshold_block *b = to_block(kobj); 1004 struct threshold_attr *a = to_attr(attr); 1005 ssize_t ret; 1006 1007 ret = a->store ? a->store(b, buf, count) : -EIO; 1008 1009 return ret; 1010 } 1011 1012 static const struct sysfs_ops threshold_ops = { 1013 .show = show, 1014 .store = store, 1015 }; 1016 1017 static void threshold_block_release(struct kobject *kobj); 1018 1019 static struct kobj_type threshold_ktype = { 1020 .sysfs_ops = &threshold_ops, 1021 .default_attrs = default_attrs, 1022 .release = threshold_block_release, 1023 }; 1024 1025 static const char *get_name(unsigned int bank, struct threshold_block *b) 1026 { 1027 enum smca_bank_types bank_type; 1028 1029 if (!mce_flags.smca) { 1030 if (b && bank == 4) 1031 return bank4_names(b); 1032 1033 return th_names[bank]; 1034 } 1035 1036 bank_type = smca_get_bank_type(bank); 1037 if (bank_type >= N_SMCA_BANK_TYPES) 1038 return NULL; 1039 1040 if (b && bank_type == SMCA_UMC) { 1041 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1042 return smca_umc_block_names[b->block]; 1043 return NULL; 1044 } 1045 1046 if (smca_banks[bank].hwid->count == 1) 1047 return smca_get_name(bank_type); 1048 1049 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1050 "%s_%x", smca_get_name(bank_type), 1051 smca_banks[bank].sysfs_id); 1052 return buf_mcatype; 1053 } 1054 1055 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1056 unsigned int bank, unsigned int block, 1057 u32 address) 1058 { 1059 struct threshold_block *b = NULL; 1060 u32 low, high; 1061 int err; 1062 1063 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1064 return 0; 1065 1066 if (rdmsr_safe(address, &low, &high)) 1067 return 0; 1068 1069 if (!(high & MASK_VALID_HI)) { 1070 if (block) 1071 goto recurse; 1072 else 1073 return 0; 1074 } 1075 1076 if (!(high & MASK_CNTP_HI) || 1077 (high & MASK_LOCKED_HI)) 1078 goto recurse; 1079 1080 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1081 if (!b) 1082 return -ENOMEM; 1083 1084 b->block = block; 1085 b->bank = bank; 1086 b->cpu = cpu; 1087 b->address = address; 1088 b->interrupt_enable = 0; 1089 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1090 b->threshold_limit = THRESHOLD_MAX; 1091 1092 if (b->interrupt_capable) { 1093 threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 1094 b->interrupt_enable = 1; 1095 } else { 1096 threshold_ktype.default_attrs[2] = NULL; 1097 } 1098 1099 INIT_LIST_HEAD(&b->miscj); 1100 1101 /* This is safe as @tb is not visible yet */ 1102 if (tb->blocks) 1103 list_add(&b->miscj, &tb->blocks->miscj); 1104 else 1105 tb->blocks = b; 1106 1107 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b)); 1108 if (err) 1109 goto out_free; 1110 recurse: 1111 address = get_block_address(address, low, high, bank, ++block, cpu); 1112 if (!address) 1113 return 0; 1114 1115 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1116 if (err) 1117 goto out_free; 1118 1119 if (b) 1120 kobject_uevent(&b->kobj, KOBJ_ADD); 1121 1122 return 0; 1123 1124 out_free: 1125 if (b) { 1126 list_del(&b->miscj); 1127 kobject_put(&b->kobj); 1128 } 1129 return err; 1130 } 1131 1132 static int __threshold_add_blocks(struct threshold_bank *b) 1133 { 1134 struct list_head *head = &b->blocks->miscj; 1135 struct threshold_block *pos = NULL; 1136 struct threshold_block *tmp = NULL; 1137 int err = 0; 1138 1139 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1140 if (err) 1141 return err; 1142 1143 list_for_each_entry_safe(pos, tmp, head, miscj) { 1144 1145 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1146 if (err) { 1147 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1148 kobject_del(&pos->kobj); 1149 1150 return err; 1151 } 1152 } 1153 return err; 1154 } 1155 1156 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1157 unsigned int bank) 1158 { 1159 struct device *dev = this_cpu_read(mce_device); 1160 struct amd_northbridge *nb = NULL; 1161 struct threshold_bank *b = NULL; 1162 const char *name = get_name(bank, NULL); 1163 int err = 0; 1164 1165 if (!dev) 1166 return -ENODEV; 1167 1168 if (is_shared_bank(bank)) { 1169 nb = node_to_amd_nb(topology_die_id(cpu)); 1170 1171 /* threshold descriptor already initialized on this node? */ 1172 if (nb && nb->bank4) { 1173 /* yes, use it */ 1174 b = nb->bank4; 1175 err = kobject_add(b->kobj, &dev->kobj, name); 1176 if (err) 1177 goto out; 1178 1179 bp[bank] = b; 1180 refcount_inc(&b->cpus); 1181 1182 err = __threshold_add_blocks(b); 1183 1184 goto out; 1185 } 1186 } 1187 1188 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1189 if (!b) { 1190 err = -ENOMEM; 1191 goto out; 1192 } 1193 1194 /* Associate the bank with the per-CPU MCE device */ 1195 b->kobj = kobject_create_and_add(name, &dev->kobj); 1196 if (!b->kobj) { 1197 err = -EINVAL; 1198 goto out_free; 1199 } 1200 1201 if (is_shared_bank(bank)) { 1202 b->shared = 1; 1203 refcount_set(&b->cpus, 1); 1204 1205 /* nb is already initialized, see above */ 1206 if (nb) { 1207 WARN_ON(nb->bank4); 1208 nb->bank4 = b; 1209 } 1210 } 1211 1212 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); 1213 if (err) 1214 goto out_kobj; 1215 1216 bp[bank] = b; 1217 return 0; 1218 1219 out_kobj: 1220 kobject_put(b->kobj); 1221 out_free: 1222 kfree(b); 1223 out: 1224 return err; 1225 } 1226 1227 static void threshold_block_release(struct kobject *kobj) 1228 { 1229 kfree(to_block(kobj)); 1230 } 1231 1232 static void deallocate_threshold_blocks(struct threshold_bank *bank) 1233 { 1234 struct threshold_block *pos, *tmp; 1235 1236 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 1237 list_del(&pos->miscj); 1238 kobject_put(&pos->kobj); 1239 } 1240 1241 kobject_put(&bank->blocks->kobj); 1242 } 1243 1244 static void __threshold_remove_blocks(struct threshold_bank *b) 1245 { 1246 struct threshold_block *pos = NULL; 1247 struct threshold_block *tmp = NULL; 1248 1249 kobject_del(b->kobj); 1250 1251 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1252 kobject_del(&pos->kobj); 1253 } 1254 1255 static void threshold_remove_bank(struct threshold_bank *bank) 1256 { 1257 struct amd_northbridge *nb; 1258 1259 if (!bank->blocks) 1260 goto out_free; 1261 1262 if (!bank->shared) 1263 goto out_dealloc; 1264 1265 if (!refcount_dec_and_test(&bank->cpus)) { 1266 __threshold_remove_blocks(bank); 1267 return; 1268 } else { 1269 /* 1270 * The last CPU on this node using the shared bank is going 1271 * away, remove that bank now. 1272 */ 1273 nb = node_to_amd_nb(topology_die_id(smp_processor_id())); 1274 nb->bank4 = NULL; 1275 } 1276 1277 out_dealloc: 1278 deallocate_threshold_blocks(bank); 1279 1280 out_free: 1281 kobject_put(bank->kobj); 1282 kfree(bank); 1283 } 1284 1285 int mce_threshold_remove_device(unsigned int cpu) 1286 { 1287 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1288 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1289 1290 if (!bp) 1291 return 0; 1292 1293 /* 1294 * Clear the pointer before cleaning up, so that the interrupt won't 1295 * touch anything of this. 1296 */ 1297 this_cpu_write(threshold_banks, NULL); 1298 1299 for (bank = 0; bank < numbanks; bank++) { 1300 if (bp[bank]) { 1301 threshold_remove_bank(bp[bank]); 1302 bp[bank] = NULL; 1303 } 1304 } 1305 kfree(bp); 1306 return 0; 1307 } 1308 1309 /** 1310 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1311 * @cpu: The plugged in CPU 1312 * 1313 * Create directories and files for all valid threshold banks. 1314 * 1315 * This is invoked from the CPU hotplug callback which was installed in 1316 * mcheck_init_device(). The invocation happens in context of the hotplug 1317 * thread running on @cpu. The callback is invoked on all CPUs which are 1318 * online when the callback is installed or during a real hotplug event. 1319 */ 1320 int mce_threshold_create_device(unsigned int cpu) 1321 { 1322 unsigned int numbanks, bank; 1323 struct threshold_bank **bp; 1324 int err; 1325 1326 if (!mce_flags.amd_threshold) 1327 return 0; 1328 1329 bp = this_cpu_read(threshold_banks); 1330 if (bp) 1331 return 0; 1332 1333 numbanks = this_cpu_read(mce_num_banks); 1334 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 1335 if (!bp) 1336 return -ENOMEM; 1337 1338 for (bank = 0; bank < numbanks; ++bank) { 1339 if (!(this_cpu_read(bank_map) & (1 << bank))) 1340 continue; 1341 err = threshold_create_bank(bp, cpu, bank); 1342 if (err) 1343 goto out_err; 1344 } 1345 this_cpu_write(threshold_banks, bp); 1346 1347 if (thresholding_irq_en) 1348 mce_threshold_vector = amd_threshold_interrupt; 1349 return 0; 1350 out_err: 1351 mce_threshold_remove_device(cpu); 1352 return err; 1353 } 1354