1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 * 8 * All MC4_MISCi registers are shared between cores on a node. 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/kobject.h> 13 #include <linux/percpu.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sysfs.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/smp.h> 21 #include <linux/string.h> 22 23 #include <asm/amd_nb.h> 24 #include <asm/traps.h> 25 #include <asm/apic.h> 26 #include <asm/mce.h> 27 #include <asm/msr.h> 28 #include <asm/trace/irq_vectors.h> 29 30 #include "internal.h" 31 32 #define NR_BLOCKS 5 33 #define THRESHOLD_MAX 0xFFF 34 #define INT_TYPE_APIC 0x00020000 35 #define MASK_VALID_HI 0x80000000 36 #define MASK_CNTP_HI 0x40000000 37 #define MASK_LOCKED_HI 0x20000000 38 #define MASK_LVTOFF_HI 0x00F00000 39 #define MASK_COUNT_EN_HI 0x00080000 40 #define MASK_INT_TYPE_HI 0x00060000 41 #define MASK_OVERFLOW_HI 0x00010000 42 #define MASK_ERR_COUNT_HI 0x00000FFF 43 #define MASK_BLKPTR_LO 0xFF000000 44 #define MCG_XBLK_ADDR 0xC0000400 45 46 /* Deferred error settings */ 47 #define MSR_CU_DEF_ERR 0xC0000410 48 #define MASK_DEF_LVTOFF 0x000000F0 49 #define MASK_DEF_INT_TYPE 0x00000006 50 #define DEF_LVT_OFF 0x2 51 #define DEF_INT_TYPE_APIC 0x2 52 53 /* Scalable MCA: */ 54 55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 56 #define SMCA_THR_LVT_OFF 0xF000 57 58 static bool thresholding_irq_en; 59 60 static const char * const th_names[] = { 61 "load_store", 62 "insn_fetch", 63 "combined_unit", 64 "decode_unit", 65 "northbridge", 66 "execution_unit", 67 }; 68 69 static const char * const smca_umc_block_names[] = { 70 "dram_ecc", 71 "misc_umc" 72 }; 73 74 struct smca_bank_name { 75 const char *name; /* Short name for sysfs */ 76 const char *long_name; /* Long name for pretty-printing */ 77 }; 78 79 static struct smca_bank_name smca_names[] = { 80 [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 81 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 82 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 83 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 84 [SMCA_RESERVED] = { "reserved", "Reserved" }, 85 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 86 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 87 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 88 [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 89 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 90 91 /* UMC v2 is separate because both of them can exist in a single system. */ 92 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 93 [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, 94 [SMCA_PB] = { "param_block", "Parameter Block" }, 95 [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 96 [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, 97 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 98 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 99 [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, 100 [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, 101 [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, 102 [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, 103 }; 104 105 static const char *smca_get_name(enum smca_bank_types t) 106 { 107 if (t >= N_SMCA_BANK_TYPES) 108 return NULL; 109 110 return smca_names[t].name; 111 } 112 113 const char *smca_get_long_name(enum smca_bank_types t) 114 { 115 if (t >= N_SMCA_BANK_TYPES) 116 return NULL; 117 118 return smca_names[t].long_name; 119 } 120 EXPORT_SYMBOL_GPL(smca_get_long_name); 121 122 enum smca_bank_types smca_get_bank_type(unsigned int bank) 123 { 124 struct smca_bank *b; 125 126 if (bank >= MAX_NR_BANKS) 127 return N_SMCA_BANK_TYPES; 128 129 b = &smca_banks[bank]; 130 if (!b->hwid) 131 return N_SMCA_BANK_TYPES; 132 133 return b->hwid->bank_type; 134 } 135 EXPORT_SYMBOL_GPL(smca_get_bank_type); 136 137 static struct smca_hwid smca_hwid_mcatypes[] = { 138 /* { bank_type, hwid_mcatype } */ 139 140 /* Reserved type */ 141 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 142 143 /* ZN Core (HWID=0xB0) MCA types */ 144 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 145 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 146 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 147 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 148 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 149 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 150 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 151 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 152 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 153 154 /* Data Fabric MCA types */ 155 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 156 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 157 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 158 159 /* Unified Memory Controller MCA type */ 160 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 161 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 162 163 /* Parameter Block MCA type */ 164 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 165 166 /* Platform Security Processor MCA type */ 167 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 168 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 169 170 /* System Management Unit MCA type */ 171 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 172 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 173 174 /* Microprocessor 5 Unit MCA type */ 175 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 176 177 /* Northbridge IO Unit MCA type */ 178 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 179 180 /* PCI Express Unit MCA type */ 181 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 182 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 183 184 /* xGMI PCS MCA type */ 185 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 186 187 /* xGMI PHY MCA type */ 188 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 189 190 /* WAFL PHY MCA type */ 191 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 192 }; 193 194 struct smca_bank smca_banks[MAX_NR_BANKS]; 195 EXPORT_SYMBOL_GPL(smca_banks); 196 197 /* 198 * In SMCA enabled processors, we can have multiple banks for a given IP type. 199 * So to define a unique name for each bank, we use a temp c-string to append 200 * the MCA_IPID[InstanceId] to type's name in get_name(). 201 * 202 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 203 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 204 */ 205 #define MAX_MCATYPE_NAME_LEN 30 206 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 207 208 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 209 210 /* 211 * A list of the banks enabled on each logical CPU. Controls which respective 212 * descriptors to initialize later in mce_threshold_create_device(). 213 */ 214 static DEFINE_PER_CPU(unsigned int, bank_map); 215 216 /* Map of banks that have more than MCA_MISC0 available. */ 217 static DEFINE_PER_CPU(u32, smca_misc_banks_map); 218 219 static void amd_threshold_interrupt(void); 220 static void amd_deferred_error_interrupt(void); 221 222 static void default_deferred_error_interrupt(void) 223 { 224 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 225 } 226 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 227 228 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 229 { 230 u32 low, high; 231 232 /* 233 * For SMCA enabled processors, BLKPTR field of the first MISC register 234 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 235 */ 236 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 237 return; 238 239 if (!(low & MCI_CONFIG_MCAX)) 240 return; 241 242 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 243 return; 244 245 if (low & MASK_BLKPTR_LO) 246 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 247 248 } 249 250 static void smca_configure(unsigned int bank, unsigned int cpu) 251 { 252 unsigned int i, hwid_mcatype; 253 struct smca_hwid *s_hwid; 254 u32 high, low; 255 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 256 257 /* Set appropriate bits in MCA_CONFIG */ 258 if (!rdmsr_safe(smca_config, &low, &high)) { 259 /* 260 * OS is required to set the MCAX bit to acknowledge that it is 261 * now using the new MSR ranges and new registers under each 262 * bank. It also means that the OS will configure deferred 263 * errors in the new MCx_CONFIG register. If the bit is not set, 264 * uncorrectable errors will cause a system panic. 265 * 266 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 267 */ 268 high |= BIT(0); 269 270 /* 271 * SMCA sets the Deferred Error Interrupt type per bank. 272 * 273 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 274 * if the DeferredIntType bit field is available. 275 * 276 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 277 * high portion of the MSR). OS should set this to 0x1 to enable 278 * APIC based interrupt. First, check that no interrupt has been 279 * set. 280 */ 281 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 282 high |= BIT(5); 283 284 wrmsr(smca_config, low, high); 285 } 286 287 smca_set_misc_banks_map(bank, cpu); 288 289 /* Return early if this bank was already initialized. */ 290 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) 291 return; 292 293 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 294 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 295 return; 296 } 297 298 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 299 (high & MCI_IPID_MCATYPE) >> 16); 300 301 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 302 s_hwid = &smca_hwid_mcatypes[i]; 303 if (hwid_mcatype == s_hwid->hwid_mcatype) { 304 smca_banks[bank].hwid = s_hwid; 305 smca_banks[bank].id = low; 306 smca_banks[bank].sysfs_id = s_hwid->count++; 307 break; 308 } 309 } 310 } 311 312 struct thresh_restart { 313 struct threshold_block *b; 314 int reset; 315 int set_lvt_off; 316 int lvt_off; 317 u16 old_limit; 318 }; 319 320 static inline bool is_shared_bank(int bank) 321 { 322 /* 323 * Scalable MCA provides for only one core to have access to the MSRs of 324 * a shared bank. 325 */ 326 if (mce_flags.smca) 327 return false; 328 329 /* Bank 4 is for northbridge reporting and is thus shared */ 330 return (bank == 4); 331 } 332 333 static const char *bank4_names(const struct threshold_block *b) 334 { 335 switch (b->address) { 336 /* MSR4_MISC0 */ 337 case 0x00000413: 338 return "dram"; 339 340 case 0xc0000408: 341 return "ht_links"; 342 343 case 0xc0000409: 344 return "l3_cache"; 345 346 default: 347 WARN(1, "Funny MSR: 0x%08x\n", b->address); 348 return ""; 349 } 350 }; 351 352 353 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 354 { 355 /* 356 * bank 4 supports APIC LVT interrupts implicitly since forever. 357 */ 358 if (bank == 4) 359 return true; 360 361 /* 362 * IntP: interrupt present; if this bit is set, the thresholding 363 * bank can generate APIC LVT interrupts 364 */ 365 return msr_high_bits & BIT(28); 366 } 367 368 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 369 { 370 int msr = (hi & MASK_LVTOFF_HI) >> 20; 371 372 if (apic < 0) { 373 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 374 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 375 b->bank, b->block, b->address, hi, lo); 376 return 0; 377 } 378 379 if (apic != msr) { 380 /* 381 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 382 * the BIOS provides the value. The original field where LVT offset 383 * was set is reserved. Return early here: 384 */ 385 if (mce_flags.smca) 386 return 0; 387 388 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 389 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 390 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 391 return 0; 392 } 393 394 return 1; 395 }; 396 397 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 398 static void threshold_restart_bank(void *_tr) 399 { 400 struct thresh_restart *tr = _tr; 401 u32 hi, lo; 402 403 /* sysfs write might race against an offline operation */ 404 if (this_cpu_read(threshold_banks)) 405 return; 406 407 rdmsr(tr->b->address, lo, hi); 408 409 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 410 tr->reset = 1; /* limit cannot be lower than err count */ 411 412 if (tr->reset) { /* reset err count and overflow bit */ 413 hi = 414 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 415 (THRESHOLD_MAX - tr->b->threshold_limit); 416 } else if (tr->old_limit) { /* change limit w/o reset */ 417 int new_count = (hi & THRESHOLD_MAX) + 418 (tr->old_limit - tr->b->threshold_limit); 419 420 hi = (hi & ~MASK_ERR_COUNT_HI) | 421 (new_count & THRESHOLD_MAX); 422 } 423 424 /* clear IntType */ 425 hi &= ~MASK_INT_TYPE_HI; 426 427 if (!tr->b->interrupt_capable) 428 goto done; 429 430 if (tr->set_lvt_off) { 431 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 432 /* set new lvt offset */ 433 hi &= ~MASK_LVTOFF_HI; 434 hi |= tr->lvt_off << 20; 435 } 436 } 437 438 if (tr->b->interrupt_enable) 439 hi |= INT_TYPE_APIC; 440 441 done: 442 443 hi |= MASK_COUNT_EN_HI; 444 wrmsr(tr->b->address, lo, hi); 445 } 446 447 static void mce_threshold_block_init(struct threshold_block *b, int offset) 448 { 449 struct thresh_restart tr = { 450 .b = b, 451 .set_lvt_off = 1, 452 .lvt_off = offset, 453 }; 454 455 b->threshold_limit = THRESHOLD_MAX; 456 threshold_restart_bank(&tr); 457 }; 458 459 static int setup_APIC_mce_threshold(int reserved, int new) 460 { 461 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 462 APIC_EILVT_MSG_FIX, 0)) 463 return new; 464 465 return reserved; 466 } 467 468 static int setup_APIC_deferred_error(int reserved, int new) 469 { 470 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 471 APIC_EILVT_MSG_FIX, 0)) 472 return new; 473 474 return reserved; 475 } 476 477 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 478 { 479 u32 low = 0, high = 0; 480 int def_offset = -1, def_new; 481 482 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 483 return; 484 485 def_new = (low & MASK_DEF_LVTOFF) >> 4; 486 if (!(low & MASK_DEF_LVTOFF)) { 487 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 488 def_new = DEF_LVT_OFF; 489 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 490 } 491 492 def_offset = setup_APIC_deferred_error(def_offset, def_new); 493 if ((def_offset == def_new) && 494 (deferred_error_int_vector != amd_deferred_error_interrupt)) 495 deferred_error_int_vector = amd_deferred_error_interrupt; 496 497 if (!mce_flags.smca) 498 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 499 500 wrmsr(MSR_CU_DEF_ERR, low, high); 501 } 502 503 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 504 unsigned int cpu) 505 { 506 if (!block) 507 return MSR_AMD64_SMCA_MCx_MISC(bank); 508 509 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 510 return 0; 511 512 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 513 } 514 515 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 516 unsigned int bank, unsigned int block, 517 unsigned int cpu) 518 { 519 u32 addr = 0, offset = 0; 520 521 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 522 return addr; 523 524 if (mce_flags.smca) 525 return smca_get_block_address(bank, block, cpu); 526 527 /* Fall back to method we used for older processors: */ 528 switch (block) { 529 case 0: 530 addr = mca_msr_reg(bank, MCA_MISC); 531 break; 532 case 1: 533 offset = ((low & MASK_BLKPTR_LO) >> 21); 534 if (offset) 535 addr = MCG_XBLK_ADDR + offset; 536 break; 537 default: 538 addr = ++current_addr; 539 } 540 return addr; 541 } 542 543 static int 544 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 545 int offset, u32 misc_high) 546 { 547 unsigned int cpu = smp_processor_id(); 548 u32 smca_low, smca_high; 549 struct threshold_block b; 550 int new; 551 552 if (!block) 553 per_cpu(bank_map, cpu) |= (1 << bank); 554 555 memset(&b, 0, sizeof(b)); 556 b.cpu = cpu; 557 b.bank = bank; 558 b.block = block; 559 b.address = addr; 560 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 561 562 if (!b.interrupt_capable) 563 goto done; 564 565 b.interrupt_enable = 1; 566 567 if (!mce_flags.smca) { 568 new = (misc_high & MASK_LVTOFF_HI) >> 20; 569 goto set_offset; 570 } 571 572 /* Gather LVT offset for thresholding: */ 573 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 574 goto out; 575 576 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 577 578 set_offset: 579 offset = setup_APIC_mce_threshold(offset, new); 580 if (offset == new) 581 thresholding_irq_en = true; 582 583 done: 584 mce_threshold_block_init(&b, offset); 585 586 out: 587 return offset; 588 } 589 590 bool amd_filter_mce(struct mce *m) 591 { 592 enum smca_bank_types bank_type = smca_get_bank_type(m->bank); 593 struct cpuinfo_x86 *c = &boot_cpu_data; 594 595 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 596 if (c->x86 == 0x17 && 597 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 598 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 599 return true; 600 601 /* NB GART TLB error reporting is disabled by default. */ 602 if (c->x86 < 0x17) { 603 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 604 return true; 605 } 606 607 return false; 608 } 609 610 /* 611 * Turn off thresholding banks for the following conditions: 612 * - MC4_MISC thresholding is not supported on Family 0x15. 613 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 614 * Models 0x10-0x2F due to Erratum #1114. 615 */ 616 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 617 { 618 int i, num_msrs; 619 u64 hwcr; 620 bool need_toggle; 621 u32 msrs[NR_BLOCKS]; 622 623 if (c->x86 == 0x15 && bank == 4) { 624 msrs[0] = 0x00000413; /* MC4_MISC0 */ 625 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 626 num_msrs = 2; 627 } else if (c->x86 == 0x17 && 628 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 629 630 if (smca_get_bank_type(bank) != SMCA_IF) 631 return; 632 633 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 634 num_msrs = 1; 635 } else { 636 return; 637 } 638 639 rdmsrl(MSR_K7_HWCR, hwcr); 640 641 /* McStatusWrEn has to be set */ 642 need_toggle = !(hwcr & BIT(18)); 643 if (need_toggle) 644 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 645 646 /* Clear CntP bit safely */ 647 for (i = 0; i < num_msrs; i++) 648 msr_clear_bit(msrs[i], 62); 649 650 /* restore old settings */ 651 if (need_toggle) 652 wrmsrl(MSR_K7_HWCR, hwcr); 653 } 654 655 /* cpu init entry point, called from mce.c with preempt off */ 656 void mce_amd_feature_init(struct cpuinfo_x86 *c) 657 { 658 unsigned int bank, block, cpu = smp_processor_id(); 659 u32 low = 0, high = 0, address = 0; 660 int offset = -1; 661 662 663 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 664 if (mce_flags.smca) 665 smca_configure(bank, cpu); 666 667 disable_err_thresholding(c, bank); 668 669 for (block = 0; block < NR_BLOCKS; ++block) { 670 address = get_block_address(address, low, high, bank, block, cpu); 671 if (!address) 672 break; 673 674 if (rdmsr_safe(address, &low, &high)) 675 break; 676 677 if (!(high & MASK_VALID_HI)) 678 continue; 679 680 if (!(high & MASK_CNTP_HI) || 681 (high & MASK_LOCKED_HI)) 682 continue; 683 684 offset = prepare_threshold_block(bank, block, address, offset, high); 685 } 686 } 687 688 if (mce_flags.succor) 689 deferred_error_interrupt_enable(c); 690 } 691 692 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) 693 { 694 u64 dram_base_addr, dram_limit_addr, dram_hole_base; 695 /* We start from the normalized address */ 696 u64 ret_addr = norm_addr; 697 698 u32 tmp; 699 700 u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; 701 u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; 702 u8 intlv_addr_sel, intlv_addr_bit; 703 u8 num_intlv_bits, hashed_bit; 704 u8 lgcy_mmio_hole_en, base = 0; 705 u8 cs_mask, cs_id = 0; 706 bool hash_enabled = false; 707 708 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ 709 if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) 710 goto out_err; 711 712 /* Remove HiAddrOffset from normalized address, if enabled: */ 713 if (tmp & BIT(0)) { 714 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; 715 716 if (norm_addr >= hi_addr_offset) { 717 ret_addr -= hi_addr_offset; 718 base = 1; 719 } 720 } 721 722 /* Read D18F0x110 (DramBaseAddress). */ 723 if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) 724 goto out_err; 725 726 /* Check if address range is valid. */ 727 if (!(tmp & BIT(0))) { 728 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", 729 __func__, tmp); 730 goto out_err; 731 } 732 733 lgcy_mmio_hole_en = tmp & BIT(1); 734 intlv_num_chan = (tmp >> 4) & 0xF; 735 intlv_addr_sel = (tmp >> 8) & 0x7; 736 dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; 737 738 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ 739 if (intlv_addr_sel > 3) { 740 pr_err("%s: Invalid interleave address select %d.\n", 741 __func__, intlv_addr_sel); 742 goto out_err; 743 } 744 745 /* Read D18F0x114 (DramLimitAddress). */ 746 if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) 747 goto out_err; 748 749 intlv_num_sockets = (tmp >> 8) & 0x1; 750 intlv_num_dies = (tmp >> 10) & 0x3; 751 dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); 752 753 intlv_addr_bit = intlv_addr_sel + 8; 754 755 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ 756 switch (intlv_num_chan) { 757 case 0: intlv_num_chan = 0; break; 758 case 1: intlv_num_chan = 1; break; 759 case 3: intlv_num_chan = 2; break; 760 case 5: intlv_num_chan = 3; break; 761 case 7: intlv_num_chan = 4; break; 762 763 case 8: intlv_num_chan = 1; 764 hash_enabled = true; 765 break; 766 default: 767 pr_err("%s: Invalid number of interleaved channels %d.\n", 768 __func__, intlv_num_chan); 769 goto out_err; 770 } 771 772 num_intlv_bits = intlv_num_chan; 773 774 if (intlv_num_dies > 2) { 775 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", 776 __func__, intlv_num_dies); 777 goto out_err; 778 } 779 780 num_intlv_bits += intlv_num_dies; 781 782 /* Add a bit if sockets are interleaved. */ 783 num_intlv_bits += intlv_num_sockets; 784 785 /* Assert num_intlv_bits <= 4 */ 786 if (num_intlv_bits > 4) { 787 pr_err("%s: Invalid interleave bits %d.\n", 788 __func__, num_intlv_bits); 789 goto out_err; 790 } 791 792 if (num_intlv_bits > 0) { 793 u64 temp_addr_x, temp_addr_i, temp_addr_y; 794 u8 die_id_bit, sock_id_bit, cs_fabric_id; 795 796 /* 797 * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. 798 * This is the fabric id for this coherent slave. Use 799 * umc/channel# as instance id of the coherent slave 800 * for FICAA. 801 */ 802 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) 803 goto out_err; 804 805 cs_fabric_id = (tmp >> 8) & 0xFF; 806 die_id_bit = 0; 807 808 /* If interleaved over more than 1 channel: */ 809 if (intlv_num_chan) { 810 die_id_bit = intlv_num_chan; 811 cs_mask = (1 << die_id_bit) - 1; 812 cs_id = cs_fabric_id & cs_mask; 813 } 814 815 sock_id_bit = die_id_bit; 816 817 /* Read D18F1x208 (SystemFabricIdMask). */ 818 if (intlv_num_dies || intlv_num_sockets) 819 if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) 820 goto out_err; 821 822 /* If interleaved over more than 1 die. */ 823 if (intlv_num_dies) { 824 sock_id_bit = die_id_bit + intlv_num_dies; 825 die_id_shift = (tmp >> 24) & 0xF; 826 die_id_mask = (tmp >> 8) & 0xFF; 827 828 cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; 829 } 830 831 /* If interleaved over more than 1 socket. */ 832 if (intlv_num_sockets) { 833 socket_id_shift = (tmp >> 28) & 0xF; 834 socket_id_mask = (tmp >> 16) & 0xFF; 835 836 cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; 837 } 838 839 /* 840 * The pre-interleaved address consists of XXXXXXIIIYYYYY 841 * where III is the ID for this CS, and XXXXXXYYYYY are the 842 * address bits from the post-interleaved address. 843 * "num_intlv_bits" has been calculated to tell us how many "I" 844 * bits there are. "intlv_addr_bit" tells us how many "Y" bits 845 * there are (where "I" starts). 846 */ 847 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); 848 temp_addr_i = (cs_id << intlv_addr_bit); 849 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; 850 ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; 851 } 852 853 /* Add dram base address */ 854 ret_addr += dram_base_addr; 855 856 /* If legacy MMIO hole enabled */ 857 if (lgcy_mmio_hole_en) { 858 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) 859 goto out_err; 860 861 dram_hole_base = tmp & GENMASK(31, 24); 862 if (ret_addr >= dram_hole_base) 863 ret_addr += (BIT_ULL(32) - dram_hole_base); 864 } 865 866 if (hash_enabled) { 867 /* Save some parentheses and grab ls-bit at the end. */ 868 hashed_bit = (ret_addr >> 12) ^ 869 (ret_addr >> 18) ^ 870 (ret_addr >> 21) ^ 871 (ret_addr >> 30) ^ 872 cs_id; 873 874 hashed_bit &= BIT(0); 875 876 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) 877 ret_addr ^= BIT(intlv_addr_bit); 878 } 879 880 /* Is calculated system address is above DRAM limit address? */ 881 if (ret_addr > dram_limit_addr) 882 goto out_err; 883 884 *sys_addr = ret_addr; 885 return 0; 886 887 out_err: 888 return -EINVAL; 889 } 890 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); 891 892 bool amd_mce_is_memory_error(struct mce *m) 893 { 894 /* ErrCodeExt[20:16] */ 895 u8 xec = (m->status >> 16) & 0x1f; 896 897 if (mce_flags.smca) 898 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; 899 900 return m->bank == 4 && xec == 0x8; 901 } 902 903 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 904 { 905 struct mce m; 906 907 mce_setup(&m); 908 909 m.status = status; 910 m.misc = misc; 911 m.bank = bank; 912 m.tsc = rdtsc(); 913 914 if (m.status & MCI_STATUS_ADDRV) { 915 m.addr = addr; 916 917 /* 918 * Extract [55:<lsb>] where lsb is the least significant 919 * *valid* bit of the address bits. 920 */ 921 if (mce_flags.smca) { 922 u8 lsb = (m.addr >> 56) & 0x3f; 923 924 m.addr &= GENMASK_ULL(55, lsb); 925 } 926 } 927 928 if (mce_flags.smca) { 929 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 930 931 if (m.status & MCI_STATUS_SYNDV) 932 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 933 } 934 935 mce_log(&m); 936 } 937 938 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 939 { 940 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 941 inc_irq_stat(irq_deferred_error_count); 942 deferred_error_int_vector(); 943 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 944 ack_APIC_irq(); 945 } 946 947 /* 948 * Returns true if the logged error is deferred. False, otherwise. 949 */ 950 static inline bool 951 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 952 { 953 u64 status, addr = 0; 954 955 rdmsrl(msr_stat, status); 956 if (!(status & MCI_STATUS_VAL)) 957 return false; 958 959 if (status & MCI_STATUS_ADDRV) 960 rdmsrl(msr_addr, addr); 961 962 __log_error(bank, status, addr, misc); 963 964 wrmsrl(msr_stat, 0); 965 966 return status & MCI_STATUS_DEFERRED; 967 } 968 969 /* 970 * We have three scenarios for checking for Deferred errors: 971 * 972 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 973 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 974 * clear MCA_DESTAT. 975 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 976 * log it. 977 */ 978 static void log_error_deferred(unsigned int bank) 979 { 980 bool defrd; 981 982 defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), 983 mca_msr_reg(bank, MCA_ADDR), 0); 984 985 if (!mce_flags.smca) 986 return; 987 988 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 989 if (defrd) { 990 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 991 return; 992 } 993 994 /* 995 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 996 * for a valid error. 997 */ 998 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 999 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 1000 } 1001 1002 /* APIC interrupt handler for deferred errors */ 1003 static void amd_deferred_error_interrupt(void) 1004 { 1005 unsigned int bank; 1006 1007 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 1008 log_error_deferred(bank); 1009 } 1010 1011 static void log_error_thresholding(unsigned int bank, u64 misc) 1012 { 1013 _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc); 1014 } 1015 1016 static void log_and_reset_block(struct threshold_block *block) 1017 { 1018 struct thresh_restart tr; 1019 u32 low = 0, high = 0; 1020 1021 if (!block) 1022 return; 1023 1024 if (rdmsr_safe(block->address, &low, &high)) 1025 return; 1026 1027 if (!(high & MASK_OVERFLOW_HI)) 1028 return; 1029 1030 /* Log the MCE which caused the threshold event. */ 1031 log_error_thresholding(block->bank, ((u64)high << 32) | low); 1032 1033 /* Reset threshold block after logging error. */ 1034 memset(&tr, 0, sizeof(tr)); 1035 tr.b = block; 1036 threshold_restart_bank(&tr); 1037 } 1038 1039 /* 1040 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 1041 * goes off when error_count reaches threshold_limit. 1042 */ 1043 static void amd_threshold_interrupt(void) 1044 { 1045 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 1046 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1047 unsigned int bank, cpu = smp_processor_id(); 1048 1049 /* 1050 * Validate that the threshold bank has been initialized already. The 1051 * handler is installed at boot time, but on a hotplug event the 1052 * interrupt might fire before the data has been initialized. 1053 */ 1054 if (!bp) 1055 return; 1056 1057 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 1058 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1059 continue; 1060 1061 first_block = bp[bank]->blocks; 1062 if (!first_block) 1063 continue; 1064 1065 /* 1066 * The first block is also the head of the list. Check it first 1067 * before iterating over the rest. 1068 */ 1069 log_and_reset_block(first_block); 1070 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 1071 log_and_reset_block(block); 1072 } 1073 } 1074 1075 /* 1076 * Sysfs Interface 1077 */ 1078 1079 struct threshold_attr { 1080 struct attribute attr; 1081 ssize_t (*show) (struct threshold_block *, char *); 1082 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 1083 }; 1084 1085 #define SHOW_FIELDS(name) \ 1086 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 1087 { \ 1088 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 1089 } 1090 SHOW_FIELDS(interrupt_enable) 1091 SHOW_FIELDS(threshold_limit) 1092 1093 static ssize_t 1094 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 1095 { 1096 struct thresh_restart tr; 1097 unsigned long new; 1098 1099 if (!b->interrupt_capable) 1100 return -EINVAL; 1101 1102 if (kstrtoul(buf, 0, &new) < 0) 1103 return -EINVAL; 1104 1105 b->interrupt_enable = !!new; 1106 1107 memset(&tr, 0, sizeof(tr)); 1108 tr.b = b; 1109 1110 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 1111 return -ENODEV; 1112 1113 return size; 1114 } 1115 1116 static ssize_t 1117 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 1118 { 1119 struct thresh_restart tr; 1120 unsigned long new; 1121 1122 if (kstrtoul(buf, 0, &new) < 0) 1123 return -EINVAL; 1124 1125 if (new > THRESHOLD_MAX) 1126 new = THRESHOLD_MAX; 1127 if (new < 1) 1128 new = 1; 1129 1130 memset(&tr, 0, sizeof(tr)); 1131 tr.old_limit = b->threshold_limit; 1132 b->threshold_limit = new; 1133 tr.b = b; 1134 1135 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 1136 return -ENODEV; 1137 1138 return size; 1139 } 1140 1141 static ssize_t show_error_count(struct threshold_block *b, char *buf) 1142 { 1143 u32 lo, hi; 1144 1145 /* CPU might be offline by now */ 1146 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 1147 return -ENODEV; 1148 1149 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 1150 (THRESHOLD_MAX - b->threshold_limit))); 1151 } 1152 1153 static struct threshold_attr error_count = { 1154 .attr = {.name = __stringify(error_count), .mode = 0444 }, 1155 .show = show_error_count, 1156 }; 1157 1158 #define RW_ATTR(val) \ 1159 static struct threshold_attr val = { \ 1160 .attr = {.name = __stringify(val), .mode = 0644 }, \ 1161 .show = show_## val, \ 1162 .store = store_## val, \ 1163 }; 1164 1165 RW_ATTR(interrupt_enable); 1166 RW_ATTR(threshold_limit); 1167 1168 static struct attribute *default_attrs[] = { 1169 &threshold_limit.attr, 1170 &error_count.attr, 1171 NULL, /* possibly interrupt_enable if supported, see below */ 1172 NULL, 1173 }; 1174 1175 #define to_block(k) container_of(k, struct threshold_block, kobj) 1176 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1177 1178 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1179 { 1180 struct threshold_block *b = to_block(kobj); 1181 struct threshold_attr *a = to_attr(attr); 1182 ssize_t ret; 1183 1184 ret = a->show ? a->show(b, buf) : -EIO; 1185 1186 return ret; 1187 } 1188 1189 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1190 const char *buf, size_t count) 1191 { 1192 struct threshold_block *b = to_block(kobj); 1193 struct threshold_attr *a = to_attr(attr); 1194 ssize_t ret; 1195 1196 ret = a->store ? a->store(b, buf, count) : -EIO; 1197 1198 return ret; 1199 } 1200 1201 static const struct sysfs_ops threshold_ops = { 1202 .show = show, 1203 .store = store, 1204 }; 1205 1206 static void threshold_block_release(struct kobject *kobj); 1207 1208 static struct kobj_type threshold_ktype = { 1209 .sysfs_ops = &threshold_ops, 1210 .default_attrs = default_attrs, 1211 .release = threshold_block_release, 1212 }; 1213 1214 static const char *get_name(unsigned int bank, struct threshold_block *b) 1215 { 1216 enum smca_bank_types bank_type; 1217 1218 if (!mce_flags.smca) { 1219 if (b && bank == 4) 1220 return bank4_names(b); 1221 1222 return th_names[bank]; 1223 } 1224 1225 bank_type = smca_get_bank_type(bank); 1226 if (bank_type >= N_SMCA_BANK_TYPES) 1227 return NULL; 1228 1229 if (b && bank_type == SMCA_UMC) { 1230 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1231 return smca_umc_block_names[b->block]; 1232 return NULL; 1233 } 1234 1235 if (smca_banks[bank].hwid->count == 1) 1236 return smca_get_name(bank_type); 1237 1238 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1239 "%s_%x", smca_get_name(bank_type), 1240 smca_banks[bank].sysfs_id); 1241 return buf_mcatype; 1242 } 1243 1244 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1245 unsigned int bank, unsigned int block, 1246 u32 address) 1247 { 1248 struct threshold_block *b = NULL; 1249 u32 low, high; 1250 int err; 1251 1252 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1253 return 0; 1254 1255 if (rdmsr_safe(address, &low, &high)) 1256 return 0; 1257 1258 if (!(high & MASK_VALID_HI)) { 1259 if (block) 1260 goto recurse; 1261 else 1262 return 0; 1263 } 1264 1265 if (!(high & MASK_CNTP_HI) || 1266 (high & MASK_LOCKED_HI)) 1267 goto recurse; 1268 1269 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1270 if (!b) 1271 return -ENOMEM; 1272 1273 b->block = block; 1274 b->bank = bank; 1275 b->cpu = cpu; 1276 b->address = address; 1277 b->interrupt_enable = 0; 1278 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1279 b->threshold_limit = THRESHOLD_MAX; 1280 1281 if (b->interrupt_capable) { 1282 threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 1283 b->interrupt_enable = 1; 1284 } else { 1285 threshold_ktype.default_attrs[2] = NULL; 1286 } 1287 1288 INIT_LIST_HEAD(&b->miscj); 1289 1290 /* This is safe as @tb is not visible yet */ 1291 if (tb->blocks) 1292 list_add(&b->miscj, &tb->blocks->miscj); 1293 else 1294 tb->blocks = b; 1295 1296 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b)); 1297 if (err) 1298 goto out_free; 1299 recurse: 1300 address = get_block_address(address, low, high, bank, ++block, cpu); 1301 if (!address) 1302 return 0; 1303 1304 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1305 if (err) 1306 goto out_free; 1307 1308 if (b) 1309 kobject_uevent(&b->kobj, KOBJ_ADD); 1310 1311 return 0; 1312 1313 out_free: 1314 if (b) { 1315 list_del(&b->miscj); 1316 kobject_put(&b->kobj); 1317 } 1318 return err; 1319 } 1320 1321 static int __threshold_add_blocks(struct threshold_bank *b) 1322 { 1323 struct list_head *head = &b->blocks->miscj; 1324 struct threshold_block *pos = NULL; 1325 struct threshold_block *tmp = NULL; 1326 int err = 0; 1327 1328 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1329 if (err) 1330 return err; 1331 1332 list_for_each_entry_safe(pos, tmp, head, miscj) { 1333 1334 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1335 if (err) { 1336 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1337 kobject_del(&pos->kobj); 1338 1339 return err; 1340 } 1341 } 1342 return err; 1343 } 1344 1345 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1346 unsigned int bank) 1347 { 1348 struct device *dev = this_cpu_read(mce_device); 1349 struct amd_northbridge *nb = NULL; 1350 struct threshold_bank *b = NULL; 1351 const char *name = get_name(bank, NULL); 1352 int err = 0; 1353 1354 if (!dev) 1355 return -ENODEV; 1356 1357 if (is_shared_bank(bank)) { 1358 nb = node_to_amd_nb(topology_die_id(cpu)); 1359 1360 /* threshold descriptor already initialized on this node? */ 1361 if (nb && nb->bank4) { 1362 /* yes, use it */ 1363 b = nb->bank4; 1364 err = kobject_add(b->kobj, &dev->kobj, name); 1365 if (err) 1366 goto out; 1367 1368 bp[bank] = b; 1369 refcount_inc(&b->cpus); 1370 1371 err = __threshold_add_blocks(b); 1372 1373 goto out; 1374 } 1375 } 1376 1377 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1378 if (!b) { 1379 err = -ENOMEM; 1380 goto out; 1381 } 1382 1383 /* Associate the bank with the per-CPU MCE device */ 1384 b->kobj = kobject_create_and_add(name, &dev->kobj); 1385 if (!b->kobj) { 1386 err = -EINVAL; 1387 goto out_free; 1388 } 1389 1390 if (is_shared_bank(bank)) { 1391 b->shared = 1; 1392 refcount_set(&b->cpus, 1); 1393 1394 /* nb is already initialized, see above */ 1395 if (nb) { 1396 WARN_ON(nb->bank4); 1397 nb->bank4 = b; 1398 } 1399 } 1400 1401 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); 1402 if (err) 1403 goto out_kobj; 1404 1405 bp[bank] = b; 1406 return 0; 1407 1408 out_kobj: 1409 kobject_put(b->kobj); 1410 out_free: 1411 kfree(b); 1412 out: 1413 return err; 1414 } 1415 1416 static void threshold_block_release(struct kobject *kobj) 1417 { 1418 kfree(to_block(kobj)); 1419 } 1420 1421 static void deallocate_threshold_blocks(struct threshold_bank *bank) 1422 { 1423 struct threshold_block *pos, *tmp; 1424 1425 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 1426 list_del(&pos->miscj); 1427 kobject_put(&pos->kobj); 1428 } 1429 1430 kobject_put(&bank->blocks->kobj); 1431 } 1432 1433 static void __threshold_remove_blocks(struct threshold_bank *b) 1434 { 1435 struct threshold_block *pos = NULL; 1436 struct threshold_block *tmp = NULL; 1437 1438 kobject_del(b->kobj); 1439 1440 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1441 kobject_del(&pos->kobj); 1442 } 1443 1444 static void threshold_remove_bank(struct threshold_bank *bank) 1445 { 1446 struct amd_northbridge *nb; 1447 1448 if (!bank->blocks) 1449 goto out_free; 1450 1451 if (!bank->shared) 1452 goto out_dealloc; 1453 1454 if (!refcount_dec_and_test(&bank->cpus)) { 1455 __threshold_remove_blocks(bank); 1456 return; 1457 } else { 1458 /* 1459 * The last CPU on this node using the shared bank is going 1460 * away, remove that bank now. 1461 */ 1462 nb = node_to_amd_nb(topology_die_id(smp_processor_id())); 1463 nb->bank4 = NULL; 1464 } 1465 1466 out_dealloc: 1467 deallocate_threshold_blocks(bank); 1468 1469 out_free: 1470 kobject_put(bank->kobj); 1471 kfree(bank); 1472 } 1473 1474 int mce_threshold_remove_device(unsigned int cpu) 1475 { 1476 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1477 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1478 1479 if (!bp) 1480 return 0; 1481 1482 /* 1483 * Clear the pointer before cleaning up, so that the interrupt won't 1484 * touch anything of this. 1485 */ 1486 this_cpu_write(threshold_banks, NULL); 1487 1488 for (bank = 0; bank < numbanks; bank++) { 1489 if (bp[bank]) { 1490 threshold_remove_bank(bp[bank]); 1491 bp[bank] = NULL; 1492 } 1493 } 1494 kfree(bp); 1495 return 0; 1496 } 1497 1498 /** 1499 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1500 * @cpu: The plugged in CPU 1501 * 1502 * Create directories and files for all valid threshold banks. 1503 * 1504 * This is invoked from the CPU hotplug callback which was installed in 1505 * mcheck_init_device(). The invocation happens in context of the hotplug 1506 * thread running on @cpu. The callback is invoked on all CPUs which are 1507 * online when the callback is installed or during a real hotplug event. 1508 */ 1509 int mce_threshold_create_device(unsigned int cpu) 1510 { 1511 unsigned int numbanks, bank; 1512 struct threshold_bank **bp; 1513 int err; 1514 1515 if (!mce_flags.amd_threshold) 1516 return 0; 1517 1518 bp = this_cpu_read(threshold_banks); 1519 if (bp) 1520 return 0; 1521 1522 numbanks = this_cpu_read(mce_num_banks); 1523 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 1524 if (!bp) 1525 return -ENOMEM; 1526 1527 for (bank = 0; bank < numbanks; ++bank) { 1528 if (!(this_cpu_read(bank_map) & (1 << bank))) 1529 continue; 1530 err = threshold_create_bank(bp, cpu, bank); 1531 if (err) 1532 goto out_err; 1533 } 1534 this_cpu_write(threshold_banks, bp); 1535 1536 if (thresholding_irq_en) 1537 mce_threshold_vector = amd_threshold_interrupt; 1538 return 0; 1539 out_err: 1540 mce_threshold_remove_device(cpu); 1541 return err; 1542 } 1543