13817d2b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * (c) 2005-2016 Advanced Micro Devices, Inc. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * Written by Jacob Shin - AMD, Inc. 621afaf18SBorislav Petkov * Maintained by: Borislav Petkov <bp@alien8.de> 721afaf18SBorislav Petkov * 821afaf18SBorislav Petkov * All MC4_MISCi registers are shared between cores on a node. 921afaf18SBorislav Petkov */ 1021afaf18SBorislav Petkov #include <linux/interrupt.h> 1121afaf18SBorislav Petkov #include <linux/notifier.h> 1221afaf18SBorislav Petkov #include <linux/kobject.h> 1321afaf18SBorislav Petkov #include <linux/percpu.h> 1421afaf18SBorislav Petkov #include <linux/errno.h> 1521afaf18SBorislav Petkov #include <linux/sched.h> 1621afaf18SBorislav Petkov #include <linux/sysfs.h> 1721afaf18SBorislav Petkov #include <linux/slab.h> 1821afaf18SBorislav Petkov #include <linux/init.h> 1921afaf18SBorislav Petkov #include <linux/cpu.h> 2021afaf18SBorislav Petkov #include <linux/smp.h> 2121afaf18SBorislav Petkov #include <linux/string.h> 2221afaf18SBorislav Petkov 2321afaf18SBorislav Petkov #include <asm/amd_nb.h> 24312a4661SLinus Torvalds #include <asm/traps.h> 2521afaf18SBorislav Petkov #include <asm/apic.h> 2621afaf18SBorislav Petkov #include <asm/mce.h> 2721afaf18SBorislav Petkov #include <asm/msr.h> 2821afaf18SBorislav Petkov #include <asm/trace/irq_vectors.h> 2921afaf18SBorislav Petkov 3021afaf18SBorislav Petkov #include "internal.h" 3121afaf18SBorislav Petkov 3221afaf18SBorislav Petkov #define NR_BLOCKS 5 3321afaf18SBorislav Petkov #define THRESHOLD_MAX 0xFFF 3421afaf18SBorislav Petkov #define INT_TYPE_APIC 0x00020000 3521afaf18SBorislav Petkov #define MASK_VALID_HI 0x80000000 3621afaf18SBorislav Petkov #define MASK_CNTP_HI 0x40000000 3721afaf18SBorislav Petkov #define MASK_LOCKED_HI 0x20000000 3821afaf18SBorislav Petkov #define MASK_LVTOFF_HI 0x00F00000 3921afaf18SBorislav Petkov #define MASK_COUNT_EN_HI 0x00080000 4021afaf18SBorislav Petkov #define MASK_INT_TYPE_HI 0x00060000 4121afaf18SBorislav Petkov #define MASK_OVERFLOW_HI 0x00010000 4221afaf18SBorislav Petkov #define MASK_ERR_COUNT_HI 0x00000FFF 4321afaf18SBorislav Petkov #define MASK_BLKPTR_LO 0xFF000000 4421afaf18SBorislav Petkov #define MCG_XBLK_ADDR 0xC0000400 4521afaf18SBorislav Petkov 4621afaf18SBorislav Petkov /* Deferred error settings */ 4721afaf18SBorislav Petkov #define MSR_CU_DEF_ERR 0xC0000410 4821afaf18SBorislav Petkov #define MASK_DEF_LVTOFF 0x000000F0 4921afaf18SBorislav Petkov #define MASK_DEF_INT_TYPE 0x00000006 5021afaf18SBorislav Petkov #define DEF_LVT_OFF 0x2 5121afaf18SBorislav Petkov #define DEF_INT_TYPE_APIC 0x2 5221afaf18SBorislav Petkov 5321afaf18SBorislav Petkov /* Scalable MCA: */ 5421afaf18SBorislav Petkov 5521afaf18SBorislav Petkov /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 5621afaf18SBorislav Petkov #define SMCA_THR_LVT_OFF 0xF000 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov static bool thresholding_irq_en; 5921afaf18SBorislav Petkov 6021afaf18SBorislav Petkov static const char * const th_names[] = { 6121afaf18SBorislav Petkov "load_store", 6221afaf18SBorislav Petkov "insn_fetch", 6321afaf18SBorislav Petkov "combined_unit", 6421afaf18SBorislav Petkov "decode_unit", 6521afaf18SBorislav Petkov "northbridge", 6621afaf18SBorislav Petkov "execution_unit", 6721afaf18SBorislav Petkov }; 6821afaf18SBorislav Petkov 6921afaf18SBorislav Petkov static const char * const smca_umc_block_names[] = { 7021afaf18SBorislav Petkov "dram_ecc", 7121afaf18SBorislav Petkov "misc_umc" 7221afaf18SBorislav Petkov }; 7321afaf18SBorislav Petkov 74*91f75eb4SYazen Ghannam #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype)) 75*91f75eb4SYazen Ghannam 76*91f75eb4SYazen Ghannam struct smca_hwid { 77*91f75eb4SYazen Ghannam unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */ 78*91f75eb4SYazen Ghannam u32 hwid_mcatype; /* (hwid,mcatype) tuple */ 79*91f75eb4SYazen Ghannam }; 80*91f75eb4SYazen Ghannam 81*91f75eb4SYazen Ghannam struct smca_bank { 82*91f75eb4SYazen Ghannam const struct smca_hwid *hwid; 83*91f75eb4SYazen Ghannam u32 id; /* Value of MCA_IPID[InstanceId]. */ 84*91f75eb4SYazen Ghannam u8 sysfs_id; /* Value used for sysfs name. */ 85*91f75eb4SYazen Ghannam }; 86*91f75eb4SYazen Ghannam 87*91f75eb4SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); 88*91f75eb4SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); 89*91f75eb4SYazen Ghannam 9021afaf18SBorislav Petkov struct smca_bank_name { 9121afaf18SBorislav Petkov const char *name; /* Short name for sysfs */ 9221afaf18SBorislav Petkov const char *long_name; /* Long name for pretty-printing */ 9321afaf18SBorislav Petkov }; 9421afaf18SBorislav Petkov 9521afaf18SBorislav Petkov static struct smca_bank_name smca_names[] = { 9694a311ceSMuralidhara M K [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 9721afaf18SBorislav Petkov [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 9821afaf18SBorislav Petkov [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 9921afaf18SBorislav Petkov [SMCA_DE] = { "decode_unit", "Decode Unit" }, 10021afaf18SBorislav Petkov [SMCA_RESERVED] = { "reserved", "Reserved" }, 10121afaf18SBorislav Petkov [SMCA_EX] = { "execution_unit", "Execution Unit" }, 10221afaf18SBorislav Petkov [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 10321afaf18SBorislav Petkov [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 10494a311ceSMuralidhara M K [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 10521afaf18SBorislav Petkov [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 10694a311ceSMuralidhara M K 10794a311ceSMuralidhara M K /* UMC v2 is separate because both of them can exist in a single system. */ 10821afaf18SBorislav Petkov [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 10994a311ceSMuralidhara M K [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, 11021afaf18SBorislav Petkov [SMCA_PB] = { "param_block", "Parameter Block" }, 11194a311ceSMuralidhara M K [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 11294a311ceSMuralidhara M K [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, 113cbfa447eSYazen Ghannam [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 1145176a93aSYazen Ghannam [SMCA_MPDMA] = { "mpdma", "MPDMA Unit" }, 115cbfa447eSYazen Ghannam [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 11694a311ceSMuralidhara M K [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, 11794a311ceSMuralidhara M K [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, 1185176a93aSYazen Ghannam [SMCA_NBIF] = { "nbif", "NBIF Unit" }, 1195176a93aSYazen Ghannam [SMCA_SHUB] = { "shub", "System Hub Unit" }, 1205176a93aSYazen Ghannam [SMCA_SATA] = { "sata", "SATA Unit" }, 1215176a93aSYazen Ghannam [SMCA_USB] = { "usb", "USB Unit" }, 1225176a93aSYazen Ghannam [SMCA_GMI_PCS] = { "gmi_pcs", "Global Memory Interconnect PCS Unit" }, 12394a311ceSMuralidhara M K [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, 12494a311ceSMuralidhara M K [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, 1255176a93aSYazen Ghannam [SMCA_GMI_PHY] = { "gmi_phy", "Global Memory Interconnect PHY Unit" }, 12621afaf18SBorislav Petkov }; 12721afaf18SBorislav Petkov 128312a4661SLinus Torvalds static const char *smca_get_name(enum smca_bank_types t) 12921afaf18SBorislav Petkov { 13021afaf18SBorislav Petkov if (t >= N_SMCA_BANK_TYPES) 13121afaf18SBorislav Petkov return NULL; 13221afaf18SBorislav Petkov 13321afaf18SBorislav Petkov return smca_names[t].name; 13421afaf18SBorislav Petkov } 13521afaf18SBorislav Petkov 13621afaf18SBorislav Petkov const char *smca_get_long_name(enum smca_bank_types t) 13721afaf18SBorislav Petkov { 13821afaf18SBorislav Petkov if (t >= N_SMCA_BANK_TYPES) 13921afaf18SBorislav Petkov return NULL; 14021afaf18SBorislav Petkov 14121afaf18SBorislav Petkov return smca_names[t].long_name; 14221afaf18SBorislav Petkov } 14321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(smca_get_long_name); 14421afaf18SBorislav Petkov 145*91f75eb4SYazen Ghannam enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) 14621afaf18SBorislav Petkov { 14721afaf18SBorislav Petkov struct smca_bank *b; 14821afaf18SBorislav Petkov 14921afaf18SBorislav Petkov if (bank >= MAX_NR_BANKS) 15021afaf18SBorislav Petkov return N_SMCA_BANK_TYPES; 15121afaf18SBorislav Petkov 152*91f75eb4SYazen Ghannam b = &per_cpu(smca_banks, cpu)[bank]; 15321afaf18SBorislav Petkov if (!b->hwid) 15421afaf18SBorislav Petkov return N_SMCA_BANK_TYPES; 15521afaf18SBorislav Petkov 15621afaf18SBorislav Petkov return b->hwid->bank_type; 15721afaf18SBorislav Petkov } 158f38ce910SMukul Joshi EXPORT_SYMBOL_GPL(smca_get_bank_type); 15921afaf18SBorislav Petkov 160*91f75eb4SYazen Ghannam static const struct smca_hwid smca_hwid_mcatypes[] = { 161368d1887SYazen Ghannam /* { bank_type, hwid_mcatype } */ 16221afaf18SBorislav Petkov 16321afaf18SBorislav Petkov /* Reserved type */ 164368d1887SYazen Ghannam { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 16521afaf18SBorislav Petkov 16621afaf18SBorislav Petkov /* ZN Core (HWID=0xB0) MCA types */ 167368d1887SYazen Ghannam { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 168368d1887SYazen Ghannam { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 169368d1887SYazen Ghannam { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 170368d1887SYazen Ghannam { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 171368d1887SYazen Ghannam { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 17221afaf18SBorislav Petkov /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 173368d1887SYazen Ghannam { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 174368d1887SYazen Ghannam { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 175368d1887SYazen Ghannam { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 17621afaf18SBorislav Petkov 17721afaf18SBorislav Petkov /* Data Fabric MCA types */ 178368d1887SYazen Ghannam { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 179368d1887SYazen Ghannam { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 180368d1887SYazen Ghannam { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 18121afaf18SBorislav Petkov 18221afaf18SBorislav Petkov /* Unified Memory Controller MCA type */ 183368d1887SYazen Ghannam { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 18494a311ceSMuralidhara M K { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 18521afaf18SBorislav Petkov 18621afaf18SBorislav Petkov /* Parameter Block MCA type */ 187368d1887SYazen Ghannam { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 18821afaf18SBorislav Petkov 18921afaf18SBorislav Petkov /* Platform Security Processor MCA type */ 190368d1887SYazen Ghannam { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 191368d1887SYazen Ghannam { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 19221afaf18SBorislav Petkov 19321afaf18SBorislav Petkov /* System Management Unit MCA type */ 194368d1887SYazen Ghannam { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 195368d1887SYazen Ghannam { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 196cbfa447eSYazen Ghannam 197cbfa447eSYazen Ghannam /* Microprocessor 5 Unit MCA type */ 198368d1887SYazen Ghannam { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 199cbfa447eSYazen Ghannam 2005176a93aSYazen Ghannam /* MPDMA MCA type */ 2015176a93aSYazen Ghannam { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, 2025176a93aSYazen Ghannam 203cbfa447eSYazen Ghannam /* Northbridge IO Unit MCA type */ 204368d1887SYazen Ghannam { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 205cbfa447eSYazen Ghannam 206cbfa447eSYazen Ghannam /* PCI Express Unit MCA type */ 207368d1887SYazen Ghannam { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 20894a311ceSMuralidhara M K { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 20994a311ceSMuralidhara M K 21094a311ceSMuralidhara M K { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 2115176a93aSYazen Ghannam { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 2125176a93aSYazen Ghannam { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 2135176a93aSYazen Ghannam { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, 2145176a93aSYazen Ghannam { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, 2155176a93aSYazen Ghannam { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 21694a311ceSMuralidhara M K { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 21794a311ceSMuralidhara M K { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 2185176a93aSYazen Ghannam { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 21921afaf18SBorislav Petkov }; 22021afaf18SBorislav Petkov 22121afaf18SBorislav Petkov /* 22221afaf18SBorislav Petkov * In SMCA enabled processors, we can have multiple banks for a given IP type. 22321afaf18SBorislav Petkov * So to define a unique name for each bank, we use a temp c-string to append 22421afaf18SBorislav Petkov * the MCA_IPID[InstanceId] to type's name in get_name(). 22521afaf18SBorislav Petkov * 22621afaf18SBorislav Petkov * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 22721afaf18SBorislav Petkov * is greater than 8 plus 1 (for underscore) plus length of longest type name. 22821afaf18SBorislav Petkov */ 22921afaf18SBorislav Petkov #define MAX_MCATYPE_NAME_LEN 30 23021afaf18SBorislav Petkov static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 23121afaf18SBorislav Petkov 23221afaf18SBorislav Petkov static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 233cca9cc05SThomas Gleixner 234cca9cc05SThomas Gleixner /* 235cca9cc05SThomas Gleixner * A list of the banks enabled on each logical CPU. Controls which respective 236cca9cc05SThomas Gleixner * descriptors to initialize later in mce_threshold_create_device(). 237cca9cc05SThomas Gleixner */ 238cca9cc05SThomas Gleixner static DEFINE_PER_CPU(unsigned int, bank_map); 23921afaf18SBorislav Petkov 24095d057f5SYazen Ghannam /* Map of banks that have more than MCA_MISC0 available. */ 24195d057f5SYazen Ghannam static DEFINE_PER_CPU(u32, smca_misc_banks_map); 24295d057f5SYazen Ghannam 24321afaf18SBorislav Petkov static void amd_threshold_interrupt(void); 24421afaf18SBorislav Petkov static void amd_deferred_error_interrupt(void); 24521afaf18SBorislav Petkov 24621afaf18SBorislav Petkov static void default_deferred_error_interrupt(void) 24721afaf18SBorislav Petkov { 24821afaf18SBorislav Petkov pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 24921afaf18SBorislav Petkov } 25021afaf18SBorislav Petkov void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 25121afaf18SBorislav Petkov 25295d057f5SYazen Ghannam static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 25395d057f5SYazen Ghannam { 25495d057f5SYazen Ghannam u32 low, high; 25595d057f5SYazen Ghannam 25695d057f5SYazen Ghannam /* 25795d057f5SYazen Ghannam * For SMCA enabled processors, BLKPTR field of the first MISC register 25895d057f5SYazen Ghannam * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 25995d057f5SYazen Ghannam */ 26095d057f5SYazen Ghannam if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 26195d057f5SYazen Ghannam return; 26295d057f5SYazen Ghannam 26395d057f5SYazen Ghannam if (!(low & MCI_CONFIG_MCAX)) 26495d057f5SYazen Ghannam return; 26595d057f5SYazen Ghannam 26695d057f5SYazen Ghannam if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 26795d057f5SYazen Ghannam return; 26895d057f5SYazen Ghannam 26995d057f5SYazen Ghannam if (low & MASK_BLKPTR_LO) 27095d057f5SYazen Ghannam per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 27195d057f5SYazen Ghannam 27295d057f5SYazen Ghannam } 27395d057f5SYazen Ghannam 27421afaf18SBorislav Petkov static void smca_configure(unsigned int bank, unsigned int cpu) 27521afaf18SBorislav Petkov { 276*91f75eb4SYazen Ghannam u8 *bank_counts = this_cpu_ptr(smca_bank_counts); 277*91f75eb4SYazen Ghannam const struct smca_hwid *s_hwid; 27821afaf18SBorislav Petkov unsigned int i, hwid_mcatype; 27921afaf18SBorislav Petkov u32 high, low; 28021afaf18SBorislav Petkov u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 28121afaf18SBorislav Petkov 28221afaf18SBorislav Petkov /* Set appropriate bits in MCA_CONFIG */ 28321afaf18SBorislav Petkov if (!rdmsr_safe(smca_config, &low, &high)) { 28421afaf18SBorislav Petkov /* 28521afaf18SBorislav Petkov * OS is required to set the MCAX bit to acknowledge that it is 28621afaf18SBorislav Petkov * now using the new MSR ranges and new registers under each 28721afaf18SBorislav Petkov * bank. It also means that the OS will configure deferred 28821afaf18SBorislav Petkov * errors in the new MCx_CONFIG register. If the bit is not set, 28921afaf18SBorislav Petkov * uncorrectable errors will cause a system panic. 29021afaf18SBorislav Petkov * 29121afaf18SBorislav Petkov * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 29221afaf18SBorislav Petkov */ 29321afaf18SBorislav Petkov high |= BIT(0); 29421afaf18SBorislav Petkov 29521afaf18SBorislav Petkov /* 29621afaf18SBorislav Petkov * SMCA sets the Deferred Error Interrupt type per bank. 29721afaf18SBorislav Petkov * 29821afaf18SBorislav Petkov * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 29921afaf18SBorislav Petkov * if the DeferredIntType bit field is available. 30021afaf18SBorislav Petkov * 30121afaf18SBorislav Petkov * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 30221afaf18SBorislav Petkov * high portion of the MSR). OS should set this to 0x1 to enable 30321afaf18SBorislav Petkov * APIC based interrupt. First, check that no interrupt has been 30421afaf18SBorislav Petkov * set. 30521afaf18SBorislav Petkov */ 30621afaf18SBorislav Petkov if ((low & BIT(5)) && !((high >> 5) & 0x3)) 30721afaf18SBorislav Petkov high |= BIT(5); 30821afaf18SBorislav Petkov 30921afaf18SBorislav Petkov wrmsr(smca_config, low, high); 31021afaf18SBorislav Petkov } 31121afaf18SBorislav Petkov 31295d057f5SYazen Ghannam smca_set_misc_banks_map(bank, cpu); 31395d057f5SYazen Ghannam 314246ff09fSKonstantin Khlebnikov if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 31521afaf18SBorislav Petkov pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 31621afaf18SBorislav Petkov return; 31721afaf18SBorislav Petkov } 31821afaf18SBorislav Petkov 31921afaf18SBorislav Petkov hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 32021afaf18SBorislav Petkov (high & MCI_IPID_MCATYPE) >> 16); 32121afaf18SBorislav Petkov 32221afaf18SBorislav Petkov for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 32321afaf18SBorislav Petkov s_hwid = &smca_hwid_mcatypes[i]; 324*91f75eb4SYazen Ghannam 32521afaf18SBorislav Petkov if (hwid_mcatype == s_hwid->hwid_mcatype) { 326*91f75eb4SYazen Ghannam this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; 327*91f75eb4SYazen Ghannam this_cpu_ptr(smca_banks)[bank].id = low; 328*91f75eb4SYazen Ghannam this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; 32921afaf18SBorislav Petkov break; 33021afaf18SBorislav Petkov } 33121afaf18SBorislav Petkov } 33221afaf18SBorislav Petkov } 33321afaf18SBorislav Petkov 33421afaf18SBorislav Petkov struct thresh_restart { 33521afaf18SBorislav Petkov struct threshold_block *b; 33621afaf18SBorislav Petkov int reset; 33721afaf18SBorislav Petkov int set_lvt_off; 33821afaf18SBorislav Petkov int lvt_off; 33921afaf18SBorislav Petkov u16 old_limit; 34021afaf18SBorislav Petkov }; 34121afaf18SBorislav Petkov 34221afaf18SBorislav Petkov static inline bool is_shared_bank(int bank) 34321afaf18SBorislav Petkov { 34421afaf18SBorislav Petkov /* 34521afaf18SBorislav Petkov * Scalable MCA provides for only one core to have access to the MSRs of 34621afaf18SBorislav Petkov * a shared bank. 34721afaf18SBorislav Petkov */ 34821afaf18SBorislav Petkov if (mce_flags.smca) 34921afaf18SBorislav Petkov return false; 35021afaf18SBorislav Petkov 35121afaf18SBorislav Petkov /* Bank 4 is for northbridge reporting and is thus shared */ 35221afaf18SBorislav Petkov return (bank == 4); 35321afaf18SBorislav Petkov } 35421afaf18SBorislav Petkov 35521afaf18SBorislav Petkov static const char *bank4_names(const struct threshold_block *b) 35621afaf18SBorislav Petkov { 35721afaf18SBorislav Petkov switch (b->address) { 35821afaf18SBorislav Petkov /* MSR4_MISC0 */ 35921afaf18SBorislav Petkov case 0x00000413: 36021afaf18SBorislav Petkov return "dram"; 36121afaf18SBorislav Petkov 36221afaf18SBorislav Petkov case 0xc0000408: 36321afaf18SBorislav Petkov return "ht_links"; 36421afaf18SBorislav Petkov 36521afaf18SBorislav Petkov case 0xc0000409: 36621afaf18SBorislav Petkov return "l3_cache"; 36721afaf18SBorislav Petkov 36821afaf18SBorislav Petkov default: 36921afaf18SBorislav Petkov WARN(1, "Funny MSR: 0x%08x\n", b->address); 37021afaf18SBorislav Petkov return ""; 37121afaf18SBorislav Petkov } 37221afaf18SBorislav Petkov }; 37321afaf18SBorislav Petkov 37421afaf18SBorislav Petkov 37521afaf18SBorislav Petkov static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 37621afaf18SBorislav Petkov { 37721afaf18SBorislav Petkov /* 37821afaf18SBorislav Petkov * bank 4 supports APIC LVT interrupts implicitly since forever. 37921afaf18SBorislav Petkov */ 38021afaf18SBorislav Petkov if (bank == 4) 38121afaf18SBorislav Petkov return true; 38221afaf18SBorislav Petkov 38321afaf18SBorislav Petkov /* 38421afaf18SBorislav Petkov * IntP: interrupt present; if this bit is set, the thresholding 38521afaf18SBorislav Petkov * bank can generate APIC LVT interrupts 38621afaf18SBorislav Petkov */ 38721afaf18SBorislav Petkov return msr_high_bits & BIT(28); 38821afaf18SBorislav Petkov } 38921afaf18SBorislav Petkov 39021afaf18SBorislav Petkov static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 39121afaf18SBorislav Petkov { 39221afaf18SBorislav Petkov int msr = (hi & MASK_LVTOFF_HI) >> 20; 39321afaf18SBorislav Petkov 39421afaf18SBorislav Petkov if (apic < 0) { 39521afaf18SBorislav Petkov pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 39621afaf18SBorislav Petkov "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 39721afaf18SBorislav Petkov b->bank, b->block, b->address, hi, lo); 39821afaf18SBorislav Petkov return 0; 39921afaf18SBorislav Petkov } 40021afaf18SBorislav Petkov 40121afaf18SBorislav Petkov if (apic != msr) { 40221afaf18SBorislav Petkov /* 40321afaf18SBorislav Petkov * On SMCA CPUs, LVT offset is programmed at a different MSR, and 40421afaf18SBorislav Petkov * the BIOS provides the value. The original field where LVT offset 40521afaf18SBorislav Petkov * was set is reserved. Return early here: 40621afaf18SBorislav Petkov */ 40721afaf18SBorislav Petkov if (mce_flags.smca) 40821afaf18SBorislav Petkov return 0; 40921afaf18SBorislav Petkov 41021afaf18SBorislav Petkov pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 41121afaf18SBorislav Petkov "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 41221afaf18SBorislav Petkov b->cpu, apic, b->bank, b->block, b->address, hi, lo); 41321afaf18SBorislav Petkov return 0; 41421afaf18SBorislav Petkov } 41521afaf18SBorislav Petkov 41621afaf18SBorislav Petkov return 1; 41721afaf18SBorislav Petkov }; 41821afaf18SBorislav Petkov 41921afaf18SBorislav Petkov /* Reprogram MCx_MISC MSR behind this threshold bank. */ 42021afaf18SBorislav Petkov static void threshold_restart_bank(void *_tr) 42121afaf18SBorislav Petkov { 42221afaf18SBorislav Petkov struct thresh_restart *tr = _tr; 42321afaf18SBorislav Petkov u32 hi, lo; 42421afaf18SBorislav Petkov 425a037f3caSThomas Gleixner /* sysfs write might race against an offline operation */ 426a037f3caSThomas Gleixner if (this_cpu_read(threshold_banks)) 427a037f3caSThomas Gleixner return; 428a037f3caSThomas Gleixner 42921afaf18SBorislav Petkov rdmsr(tr->b->address, lo, hi); 43021afaf18SBorislav Petkov 43121afaf18SBorislav Petkov if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 43221afaf18SBorislav Petkov tr->reset = 1; /* limit cannot be lower than err count */ 43321afaf18SBorislav Petkov 43421afaf18SBorislav Petkov if (tr->reset) { /* reset err count and overflow bit */ 43521afaf18SBorislav Petkov hi = 43621afaf18SBorislav Petkov (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 43721afaf18SBorislav Petkov (THRESHOLD_MAX - tr->b->threshold_limit); 43821afaf18SBorislav Petkov } else if (tr->old_limit) { /* change limit w/o reset */ 43921afaf18SBorislav Petkov int new_count = (hi & THRESHOLD_MAX) + 44021afaf18SBorislav Petkov (tr->old_limit - tr->b->threshold_limit); 44121afaf18SBorislav Petkov 44221afaf18SBorislav Petkov hi = (hi & ~MASK_ERR_COUNT_HI) | 44321afaf18SBorislav Petkov (new_count & THRESHOLD_MAX); 44421afaf18SBorislav Petkov } 44521afaf18SBorislav Petkov 44621afaf18SBorislav Petkov /* clear IntType */ 44721afaf18SBorislav Petkov hi &= ~MASK_INT_TYPE_HI; 44821afaf18SBorislav Petkov 44921afaf18SBorislav Petkov if (!tr->b->interrupt_capable) 45021afaf18SBorislav Petkov goto done; 45121afaf18SBorislav Petkov 45221afaf18SBorislav Petkov if (tr->set_lvt_off) { 45321afaf18SBorislav Petkov if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 45421afaf18SBorislav Petkov /* set new lvt offset */ 45521afaf18SBorislav Petkov hi &= ~MASK_LVTOFF_HI; 45621afaf18SBorislav Petkov hi |= tr->lvt_off << 20; 45721afaf18SBorislav Petkov } 45821afaf18SBorislav Petkov } 45921afaf18SBorislav Petkov 46021afaf18SBorislav Petkov if (tr->b->interrupt_enable) 46121afaf18SBorislav Petkov hi |= INT_TYPE_APIC; 46221afaf18SBorislav Petkov 46321afaf18SBorislav Petkov done: 46421afaf18SBorislav Petkov 46521afaf18SBorislav Petkov hi |= MASK_COUNT_EN_HI; 46621afaf18SBorislav Petkov wrmsr(tr->b->address, lo, hi); 46721afaf18SBorislav Petkov } 46821afaf18SBorislav Petkov 46921afaf18SBorislav Petkov static void mce_threshold_block_init(struct threshold_block *b, int offset) 47021afaf18SBorislav Petkov { 47121afaf18SBorislav Petkov struct thresh_restart tr = { 47221afaf18SBorislav Petkov .b = b, 47321afaf18SBorislav Petkov .set_lvt_off = 1, 47421afaf18SBorislav Petkov .lvt_off = offset, 47521afaf18SBorislav Petkov }; 47621afaf18SBorislav Petkov 47721afaf18SBorislav Petkov b->threshold_limit = THRESHOLD_MAX; 47821afaf18SBorislav Petkov threshold_restart_bank(&tr); 47921afaf18SBorislav Petkov }; 48021afaf18SBorislav Petkov 48121afaf18SBorislav Petkov static int setup_APIC_mce_threshold(int reserved, int new) 48221afaf18SBorislav Petkov { 48321afaf18SBorislav Petkov if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 48421afaf18SBorislav Petkov APIC_EILVT_MSG_FIX, 0)) 48521afaf18SBorislav Petkov return new; 48621afaf18SBorislav Petkov 48721afaf18SBorislav Petkov return reserved; 48821afaf18SBorislav Petkov } 48921afaf18SBorislav Petkov 49021afaf18SBorislav Petkov static int setup_APIC_deferred_error(int reserved, int new) 49121afaf18SBorislav Petkov { 49221afaf18SBorislav Petkov if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 49321afaf18SBorislav Petkov APIC_EILVT_MSG_FIX, 0)) 49421afaf18SBorislav Petkov return new; 49521afaf18SBorislav Petkov 49621afaf18SBorislav Petkov return reserved; 49721afaf18SBorislav Petkov } 49821afaf18SBorislav Petkov 49921afaf18SBorislav Petkov static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 50021afaf18SBorislav Petkov { 50121afaf18SBorislav Petkov u32 low = 0, high = 0; 50221afaf18SBorislav Petkov int def_offset = -1, def_new; 50321afaf18SBorislav Petkov 50421afaf18SBorislav Petkov if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 50521afaf18SBorislav Petkov return; 50621afaf18SBorislav Petkov 50721afaf18SBorislav Petkov def_new = (low & MASK_DEF_LVTOFF) >> 4; 50821afaf18SBorislav Petkov if (!(low & MASK_DEF_LVTOFF)) { 50921afaf18SBorislav Petkov pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 51021afaf18SBorislav Petkov def_new = DEF_LVT_OFF; 51121afaf18SBorislav Petkov low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 51221afaf18SBorislav Petkov } 51321afaf18SBorislav Petkov 51421afaf18SBorislav Petkov def_offset = setup_APIC_deferred_error(def_offset, def_new); 51521afaf18SBorislav Petkov if ((def_offset == def_new) && 51621afaf18SBorislav Petkov (deferred_error_int_vector != amd_deferred_error_interrupt)) 51721afaf18SBorislav Petkov deferred_error_int_vector = amd_deferred_error_interrupt; 51821afaf18SBorislav Petkov 51921afaf18SBorislav Petkov if (!mce_flags.smca) 52021afaf18SBorislav Petkov low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 52121afaf18SBorislav Petkov 52221afaf18SBorislav Petkov wrmsr(MSR_CU_DEF_ERR, low, high); 52321afaf18SBorislav Petkov } 52421afaf18SBorislav Petkov 52595d057f5SYazen Ghannam static u32 smca_get_block_address(unsigned int bank, unsigned int block, 52695d057f5SYazen Ghannam unsigned int cpu) 52721afaf18SBorislav Petkov { 52821afaf18SBorislav Petkov if (!block) 52921afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_MISC(bank); 53021afaf18SBorislav Petkov 53195d057f5SYazen Ghannam if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 53295d057f5SYazen Ghannam return 0; 53321afaf18SBorislav Petkov 53495d057f5SYazen Ghannam return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 53521afaf18SBorislav Petkov } 53621afaf18SBorislav Petkov 53721afaf18SBorislav Petkov static u32 get_block_address(u32 current_addr, u32 low, u32 high, 53895d057f5SYazen Ghannam unsigned int bank, unsigned int block, 53995d057f5SYazen Ghannam unsigned int cpu) 54021afaf18SBorislav Petkov { 54121afaf18SBorislav Petkov u32 addr = 0, offset = 0; 54221afaf18SBorislav Petkov 543c7d314f3SYazen Ghannam if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 54421afaf18SBorislav Petkov return addr; 54521afaf18SBorislav Petkov 54621afaf18SBorislav Petkov if (mce_flags.smca) 54795d057f5SYazen Ghannam return smca_get_block_address(bank, block, cpu); 54821afaf18SBorislav Petkov 54921afaf18SBorislav Petkov /* Fall back to method we used for older processors: */ 55021afaf18SBorislav Petkov switch (block) { 55121afaf18SBorislav Petkov case 0: 5528121b8f9SBorislav Petkov addr = mca_msr_reg(bank, MCA_MISC); 55321afaf18SBorislav Petkov break; 55421afaf18SBorislav Petkov case 1: 55521afaf18SBorislav Petkov offset = ((low & MASK_BLKPTR_LO) >> 21); 55621afaf18SBorislav Petkov if (offset) 55721afaf18SBorislav Petkov addr = MCG_XBLK_ADDR + offset; 55821afaf18SBorislav Petkov break; 55921afaf18SBorislav Petkov default: 56021afaf18SBorislav Petkov addr = ++current_addr; 56121afaf18SBorislav Petkov } 56221afaf18SBorislav Petkov return addr; 56321afaf18SBorislav Petkov } 56421afaf18SBorislav Petkov 56521afaf18SBorislav Petkov static int 56621afaf18SBorislav Petkov prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 56721afaf18SBorislav Petkov int offset, u32 misc_high) 56821afaf18SBorislav Petkov { 56921afaf18SBorislav Petkov unsigned int cpu = smp_processor_id(); 57021afaf18SBorislav Petkov u32 smca_low, smca_high; 57121afaf18SBorislav Petkov struct threshold_block b; 57221afaf18SBorislav Petkov int new; 57321afaf18SBorislav Petkov 57421afaf18SBorislav Petkov if (!block) 57521afaf18SBorislav Petkov per_cpu(bank_map, cpu) |= (1 << bank); 57621afaf18SBorislav Petkov 57721afaf18SBorislav Petkov memset(&b, 0, sizeof(b)); 57821afaf18SBorislav Petkov b.cpu = cpu; 57921afaf18SBorislav Petkov b.bank = bank; 58021afaf18SBorislav Petkov b.block = block; 58121afaf18SBorislav Petkov b.address = addr; 58221afaf18SBorislav Petkov b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 58321afaf18SBorislav Petkov 58421afaf18SBorislav Petkov if (!b.interrupt_capable) 58521afaf18SBorislav Petkov goto done; 58621afaf18SBorislav Petkov 58721afaf18SBorislav Petkov b.interrupt_enable = 1; 58821afaf18SBorislav Petkov 58921afaf18SBorislav Petkov if (!mce_flags.smca) { 59021afaf18SBorislav Petkov new = (misc_high & MASK_LVTOFF_HI) >> 20; 59121afaf18SBorislav Petkov goto set_offset; 59221afaf18SBorislav Petkov } 59321afaf18SBorislav Petkov 59421afaf18SBorislav Petkov /* Gather LVT offset for thresholding: */ 59521afaf18SBorislav Petkov if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 59621afaf18SBorislav Petkov goto out; 59721afaf18SBorislav Petkov 59821afaf18SBorislav Petkov new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 59921afaf18SBorislav Petkov 60021afaf18SBorislav Petkov set_offset: 60121afaf18SBorislav Petkov offset = setup_APIC_mce_threshold(offset, new); 60221afaf18SBorislav Petkov if (offset == new) 60321afaf18SBorislav Petkov thresholding_irq_en = true; 60421afaf18SBorislav Petkov 60521afaf18SBorislav Petkov done: 60621afaf18SBorislav Petkov mce_threshold_block_init(&b, offset); 60721afaf18SBorislav Petkov 60821afaf18SBorislav Petkov out: 60921afaf18SBorislav Petkov return offset; 61021afaf18SBorislav Petkov } 61121afaf18SBorislav Petkov 61271a84402SYazen Ghannam bool amd_filter_mce(struct mce *m) 61330aa3d26SShirish S { 614*91f75eb4SYazen Ghannam enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); 61571a84402SYazen Ghannam struct cpuinfo_x86 *c = &boot_cpu_data; 61671a84402SYazen Ghannam 61771a84402SYazen Ghannam /* See Family 17h Models 10h-2Fh Erratum #1114. */ 61871a84402SYazen Ghannam if (c->x86 == 0x17 && 61971a84402SYazen Ghannam c->x86_model >= 0x10 && c->x86_model <= 0x2F && 6203e0fdec8SBorislav Petkov bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 62171a84402SYazen Ghannam return true; 62271a84402SYazen Ghannam 6233e0fdec8SBorislav Petkov /* NB GART TLB error reporting is disabled by default. */ 6243e0fdec8SBorislav Petkov if (c->x86 < 0x17) { 6253e0fdec8SBorislav Petkov if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 6263e0fdec8SBorislav Petkov return true; 6273e0fdec8SBorislav Petkov } 6283e0fdec8SBorislav Petkov 62971a84402SYazen Ghannam return false; 63071a84402SYazen Ghannam } 63171a84402SYazen Ghannam 63271a84402SYazen Ghannam /* 63371a84402SYazen Ghannam * Turn off thresholding banks for the following conditions: 63471a84402SYazen Ghannam * - MC4_MISC thresholding is not supported on Family 0x15. 63571a84402SYazen Ghannam * - Prevent possible spurious interrupts from the IF bank on Family 0x17 63671a84402SYazen Ghannam * Models 0x10-0x2F due to Erratum #1114. 63771a84402SYazen Ghannam */ 63847cd84e9SBorislav Petkov static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 63971a84402SYazen Ghannam { 64071a84402SYazen Ghannam int i, num_msrs; 64130aa3d26SShirish S u64 hwcr; 64230aa3d26SShirish S bool need_toggle; 64371a84402SYazen Ghannam u32 msrs[NR_BLOCKS]; 64430aa3d26SShirish S 64571a84402SYazen Ghannam if (c->x86 == 0x15 && bank == 4) { 64671a84402SYazen Ghannam msrs[0] = 0x00000413; /* MC4_MISC0 */ 64771a84402SYazen Ghannam msrs[1] = 0xc0000408; /* MC4_MISC1 */ 64871a84402SYazen Ghannam num_msrs = 2; 64971a84402SYazen Ghannam } else if (c->x86 == 0x17 && 65071a84402SYazen Ghannam (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 65171a84402SYazen Ghannam 652*91f75eb4SYazen Ghannam if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) 65330aa3d26SShirish S return; 65430aa3d26SShirish S 65571a84402SYazen Ghannam msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 65671a84402SYazen Ghannam num_msrs = 1; 65771a84402SYazen Ghannam } else { 65871a84402SYazen Ghannam return; 65971a84402SYazen Ghannam } 66071a84402SYazen Ghannam 66130aa3d26SShirish S rdmsrl(MSR_K7_HWCR, hwcr); 66230aa3d26SShirish S 66330aa3d26SShirish S /* McStatusWrEn has to be set */ 66430aa3d26SShirish S need_toggle = !(hwcr & BIT(18)); 66530aa3d26SShirish S if (need_toggle) 66630aa3d26SShirish S wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 66730aa3d26SShirish S 66830aa3d26SShirish S /* Clear CntP bit safely */ 66971a84402SYazen Ghannam for (i = 0; i < num_msrs; i++) 67030aa3d26SShirish S msr_clear_bit(msrs[i], 62); 67130aa3d26SShirish S 67230aa3d26SShirish S /* restore old settings */ 67330aa3d26SShirish S if (need_toggle) 67430aa3d26SShirish S wrmsrl(MSR_K7_HWCR, hwcr); 67530aa3d26SShirish S } 67630aa3d26SShirish S 67721afaf18SBorislav Petkov /* cpu init entry point, called from mce.c with preempt off */ 67821afaf18SBorislav Petkov void mce_amd_feature_init(struct cpuinfo_x86 *c) 67921afaf18SBorislav Petkov { 68021afaf18SBorislav Petkov unsigned int bank, block, cpu = smp_processor_id(); 681c7d314f3SYazen Ghannam u32 low = 0, high = 0, address = 0; 68221afaf18SBorislav Petkov int offset = -1; 68321afaf18SBorislav Petkov 684c7d314f3SYazen Ghannam 685c7d314f3SYazen Ghannam for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 68621afaf18SBorislav Petkov if (mce_flags.smca) 68721afaf18SBorislav Petkov smca_configure(bank, cpu); 68821afaf18SBorislav Petkov 68971a84402SYazen Ghannam disable_err_thresholding(c, bank); 69071a84402SYazen Ghannam 69121afaf18SBorislav Petkov for (block = 0; block < NR_BLOCKS; ++block) { 69295d057f5SYazen Ghannam address = get_block_address(address, low, high, bank, block, cpu); 69321afaf18SBorislav Petkov if (!address) 69421afaf18SBorislav Petkov break; 69521afaf18SBorislav Petkov 69621afaf18SBorislav Petkov if (rdmsr_safe(address, &low, &high)) 69721afaf18SBorislav Petkov break; 69821afaf18SBorislav Petkov 69921afaf18SBorislav Petkov if (!(high & MASK_VALID_HI)) 70021afaf18SBorislav Petkov continue; 70121afaf18SBorislav Petkov 70221afaf18SBorislav Petkov if (!(high & MASK_CNTP_HI) || 70321afaf18SBorislav Petkov (high & MASK_LOCKED_HI)) 70421afaf18SBorislav Petkov continue; 70521afaf18SBorislav Petkov 70621afaf18SBorislav Petkov offset = prepare_threshold_block(bank, block, address, offset, high); 70721afaf18SBorislav Petkov } 70821afaf18SBorislav Petkov } 70921afaf18SBorislav Petkov 71021afaf18SBorislav Petkov if (mce_flags.succor) 71121afaf18SBorislav Petkov deferred_error_interrupt_enable(c); 71221afaf18SBorislav Petkov } 71321afaf18SBorislav Petkov 71421afaf18SBorislav Petkov bool amd_mce_is_memory_error(struct mce *m) 71521afaf18SBorislav Petkov { 71621afaf18SBorislav Petkov /* ErrCodeExt[20:16] */ 71721afaf18SBorislav Petkov u8 xec = (m->status >> 16) & 0x1f; 71821afaf18SBorislav Petkov 71921afaf18SBorislav Petkov if (mce_flags.smca) 720*91f75eb4SYazen Ghannam return smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC && xec == 0x0; 72121afaf18SBorislav Petkov 72221afaf18SBorislav Petkov return m->bank == 4 && xec == 0x8; 72321afaf18SBorislav Petkov } 72421afaf18SBorislav Petkov 72521afaf18SBorislav Petkov static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 72621afaf18SBorislav Petkov { 72721afaf18SBorislav Petkov struct mce m; 72821afaf18SBorislav Petkov 72921afaf18SBorislav Petkov mce_setup(&m); 73021afaf18SBorislav Petkov 73121afaf18SBorislav Petkov m.status = status; 73221afaf18SBorislav Petkov m.misc = misc; 73321afaf18SBorislav Petkov m.bank = bank; 73421afaf18SBorislav Petkov m.tsc = rdtsc(); 73521afaf18SBorislav Petkov 73621afaf18SBorislav Petkov if (m.status & MCI_STATUS_ADDRV) { 73721afaf18SBorislav Petkov m.addr = addr; 73821afaf18SBorislav Petkov 73921afaf18SBorislav Petkov /* 74021afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 74121afaf18SBorislav Petkov * *valid* bit of the address bits. 74221afaf18SBorislav Petkov */ 74321afaf18SBorislav Petkov if (mce_flags.smca) { 74421afaf18SBorislav Petkov u8 lsb = (m.addr >> 56) & 0x3f; 74521afaf18SBorislav Petkov 74621afaf18SBorislav Petkov m.addr &= GENMASK_ULL(55, lsb); 74721afaf18SBorislav Petkov } 74821afaf18SBorislav Petkov } 74921afaf18SBorislav Petkov 75021afaf18SBorislav Petkov if (mce_flags.smca) { 75121afaf18SBorislav Petkov rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 75221afaf18SBorislav Petkov 75321afaf18SBorislav Petkov if (m.status & MCI_STATUS_SYNDV) 75421afaf18SBorislav Petkov rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 75521afaf18SBorislav Petkov } 75621afaf18SBorislav Petkov 75721afaf18SBorislav Petkov mce_log(&m); 75821afaf18SBorislav Petkov } 75921afaf18SBorislav Petkov 760720909a7SThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 76121afaf18SBorislav Petkov { 76221afaf18SBorislav Petkov trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 76321afaf18SBorislav Petkov inc_irq_stat(irq_deferred_error_count); 76421afaf18SBorislav Petkov deferred_error_int_vector(); 76521afaf18SBorislav Petkov trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 766720909a7SThomas Gleixner ack_APIC_irq(); 76721afaf18SBorislav Petkov } 76821afaf18SBorislav Petkov 76921afaf18SBorislav Petkov /* 77021afaf18SBorislav Petkov * Returns true if the logged error is deferred. False, otherwise. 77121afaf18SBorislav Petkov */ 77221afaf18SBorislav Petkov static inline bool 77321afaf18SBorislav Petkov _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 77421afaf18SBorislav Petkov { 77521afaf18SBorislav Petkov u64 status, addr = 0; 77621afaf18SBorislav Petkov 77721afaf18SBorislav Petkov rdmsrl(msr_stat, status); 77821afaf18SBorislav Petkov if (!(status & MCI_STATUS_VAL)) 77921afaf18SBorislav Petkov return false; 78021afaf18SBorislav Petkov 78121afaf18SBorislav Petkov if (status & MCI_STATUS_ADDRV) 78221afaf18SBorislav Petkov rdmsrl(msr_addr, addr); 78321afaf18SBorislav Petkov 78421afaf18SBorislav Petkov __log_error(bank, status, addr, misc); 78521afaf18SBorislav Petkov 78621afaf18SBorislav Petkov wrmsrl(msr_stat, 0); 78721afaf18SBorislav Petkov 78821afaf18SBorislav Petkov return status & MCI_STATUS_DEFERRED; 78921afaf18SBorislav Petkov } 79021afaf18SBorislav Petkov 79121afaf18SBorislav Petkov /* 79221afaf18SBorislav Petkov * We have three scenarios for checking for Deferred errors: 79321afaf18SBorislav Petkov * 79421afaf18SBorislav Petkov * 1) Non-SMCA systems check MCA_STATUS and log error if found. 79521afaf18SBorislav Petkov * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 79621afaf18SBorislav Petkov * clear MCA_DESTAT. 79721afaf18SBorislav Petkov * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 79821afaf18SBorislav Petkov * log it. 79921afaf18SBorislav Petkov */ 80021afaf18SBorislav Petkov static void log_error_deferred(unsigned int bank) 80121afaf18SBorislav Petkov { 80221afaf18SBorislav Petkov bool defrd; 80321afaf18SBorislav Petkov 8048121b8f9SBorislav Petkov defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), 8058121b8f9SBorislav Petkov mca_msr_reg(bank, MCA_ADDR), 0); 80621afaf18SBorislav Petkov 80721afaf18SBorislav Petkov if (!mce_flags.smca) 80821afaf18SBorislav Petkov return; 80921afaf18SBorislav Petkov 81021afaf18SBorislav Petkov /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 81121afaf18SBorislav Petkov if (defrd) { 81221afaf18SBorislav Petkov wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 81321afaf18SBorislav Petkov return; 81421afaf18SBorislav Petkov } 81521afaf18SBorislav Petkov 81621afaf18SBorislav Petkov /* 81721afaf18SBorislav Petkov * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 81821afaf18SBorislav Petkov * for a valid error. 81921afaf18SBorislav Petkov */ 82021afaf18SBorislav Petkov _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 82121afaf18SBorislav Petkov MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 82221afaf18SBorislav Petkov } 82321afaf18SBorislav Petkov 82421afaf18SBorislav Petkov /* APIC interrupt handler for deferred errors */ 82521afaf18SBorislav Petkov static void amd_deferred_error_interrupt(void) 82621afaf18SBorislav Petkov { 82721afaf18SBorislav Petkov unsigned int bank; 82821afaf18SBorislav Petkov 829c7d314f3SYazen Ghannam for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 83021afaf18SBorislav Petkov log_error_deferred(bank); 83121afaf18SBorislav Petkov } 83221afaf18SBorislav Petkov 83321afaf18SBorislav Petkov static void log_error_thresholding(unsigned int bank, u64 misc) 83421afaf18SBorislav Petkov { 8358121b8f9SBorislav Petkov _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc); 83621afaf18SBorislav Petkov } 83721afaf18SBorislav Petkov 83821afaf18SBorislav Petkov static void log_and_reset_block(struct threshold_block *block) 83921afaf18SBorislav Petkov { 84021afaf18SBorislav Petkov struct thresh_restart tr; 84121afaf18SBorislav Petkov u32 low = 0, high = 0; 84221afaf18SBorislav Petkov 84321afaf18SBorislav Petkov if (!block) 84421afaf18SBorislav Petkov return; 84521afaf18SBorislav Petkov 84621afaf18SBorislav Petkov if (rdmsr_safe(block->address, &low, &high)) 84721afaf18SBorislav Petkov return; 84821afaf18SBorislav Petkov 84921afaf18SBorislav Petkov if (!(high & MASK_OVERFLOW_HI)) 85021afaf18SBorislav Petkov return; 85121afaf18SBorislav Petkov 85221afaf18SBorislav Petkov /* Log the MCE which caused the threshold event. */ 85321afaf18SBorislav Petkov log_error_thresholding(block->bank, ((u64)high << 32) | low); 85421afaf18SBorislav Petkov 85521afaf18SBorislav Petkov /* Reset threshold block after logging error. */ 85621afaf18SBorislav Petkov memset(&tr, 0, sizeof(tr)); 85721afaf18SBorislav Petkov tr.b = block; 85821afaf18SBorislav Petkov threshold_restart_bank(&tr); 85921afaf18SBorislav Petkov } 86021afaf18SBorislav Petkov 86121afaf18SBorislav Petkov /* 86221afaf18SBorislav Petkov * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 86321afaf18SBorislav Petkov * goes off when error_count reaches threshold_limit. 86421afaf18SBorislav Petkov */ 86521afaf18SBorislav Petkov static void amd_threshold_interrupt(void) 86621afaf18SBorislav Petkov { 86721afaf18SBorislav Petkov struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 868cca9cc05SThomas Gleixner struct threshold_bank **bp = this_cpu_read(threshold_banks); 86921afaf18SBorislav Petkov unsigned int bank, cpu = smp_processor_id(); 87021afaf18SBorislav Petkov 871cca9cc05SThomas Gleixner /* 872cca9cc05SThomas Gleixner * Validate that the threshold bank has been initialized already. The 873cca9cc05SThomas Gleixner * handler is installed at boot time, but on a hotplug event the 874cca9cc05SThomas Gleixner * interrupt might fire before the data has been initialized. 875cca9cc05SThomas Gleixner */ 876cca9cc05SThomas Gleixner if (!bp) 877cca9cc05SThomas Gleixner return; 878cca9cc05SThomas Gleixner 879c7d314f3SYazen Ghannam for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 88021afaf18SBorislav Petkov if (!(per_cpu(bank_map, cpu) & (1 << bank))) 88121afaf18SBorislav Petkov continue; 88221afaf18SBorislav Petkov 883cca9cc05SThomas Gleixner first_block = bp[bank]->blocks; 88421afaf18SBorislav Petkov if (!first_block) 88521afaf18SBorislav Petkov continue; 88621afaf18SBorislav Petkov 88721afaf18SBorislav Petkov /* 88821afaf18SBorislav Petkov * The first block is also the head of the list. Check it first 88921afaf18SBorislav Petkov * before iterating over the rest. 89021afaf18SBorislav Petkov */ 89121afaf18SBorislav Petkov log_and_reset_block(first_block); 89221afaf18SBorislav Petkov list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 89321afaf18SBorislav Petkov log_and_reset_block(block); 89421afaf18SBorislav Petkov } 89521afaf18SBorislav Petkov } 89621afaf18SBorislav Petkov 89721afaf18SBorislav Petkov /* 89821afaf18SBorislav Petkov * Sysfs Interface 89921afaf18SBorislav Petkov */ 90021afaf18SBorislav Petkov 90121afaf18SBorislav Petkov struct threshold_attr { 90221afaf18SBorislav Petkov struct attribute attr; 90321afaf18SBorislav Petkov ssize_t (*show) (struct threshold_block *, char *); 90421afaf18SBorislav Petkov ssize_t (*store) (struct threshold_block *, const char *, size_t count); 90521afaf18SBorislav Petkov }; 90621afaf18SBorislav Petkov 90721afaf18SBorislav Petkov #define SHOW_FIELDS(name) \ 90821afaf18SBorislav Petkov static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 90921afaf18SBorislav Petkov { \ 91021afaf18SBorislav Petkov return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 91121afaf18SBorislav Petkov } 91221afaf18SBorislav Petkov SHOW_FIELDS(interrupt_enable) 91321afaf18SBorislav Petkov SHOW_FIELDS(threshold_limit) 91421afaf18SBorislav Petkov 91521afaf18SBorislav Petkov static ssize_t 91621afaf18SBorislav Petkov store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 91721afaf18SBorislav Petkov { 91821afaf18SBorislav Petkov struct thresh_restart tr; 91921afaf18SBorislav Petkov unsigned long new; 92021afaf18SBorislav Petkov 92121afaf18SBorislav Petkov if (!b->interrupt_capable) 92221afaf18SBorislav Petkov return -EINVAL; 92321afaf18SBorislav Petkov 92421afaf18SBorislav Petkov if (kstrtoul(buf, 0, &new) < 0) 92521afaf18SBorislav Petkov return -EINVAL; 92621afaf18SBorislav Petkov 92721afaf18SBorislav Petkov b->interrupt_enable = !!new; 92821afaf18SBorislav Petkov 92921afaf18SBorislav Petkov memset(&tr, 0, sizeof(tr)); 93021afaf18SBorislav Petkov tr.b = b; 93121afaf18SBorislav Petkov 932a037f3caSThomas Gleixner if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 933a037f3caSThomas Gleixner return -ENODEV; 93421afaf18SBorislav Petkov 93521afaf18SBorislav Petkov return size; 93621afaf18SBorislav Petkov } 93721afaf18SBorislav Petkov 93821afaf18SBorislav Petkov static ssize_t 93921afaf18SBorislav Petkov store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 94021afaf18SBorislav Petkov { 94121afaf18SBorislav Petkov struct thresh_restart tr; 94221afaf18SBorislav Petkov unsigned long new; 94321afaf18SBorislav Petkov 94421afaf18SBorislav Petkov if (kstrtoul(buf, 0, &new) < 0) 94521afaf18SBorislav Petkov return -EINVAL; 94621afaf18SBorislav Petkov 94721afaf18SBorislav Petkov if (new > THRESHOLD_MAX) 94821afaf18SBorislav Petkov new = THRESHOLD_MAX; 94921afaf18SBorislav Petkov if (new < 1) 95021afaf18SBorislav Petkov new = 1; 95121afaf18SBorislav Petkov 95221afaf18SBorislav Petkov memset(&tr, 0, sizeof(tr)); 95321afaf18SBorislav Petkov tr.old_limit = b->threshold_limit; 95421afaf18SBorislav Petkov b->threshold_limit = new; 95521afaf18SBorislav Petkov tr.b = b; 95621afaf18SBorislav Petkov 957a037f3caSThomas Gleixner if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 958a037f3caSThomas Gleixner return -ENODEV; 95921afaf18SBorislav Petkov 96021afaf18SBorislav Petkov return size; 96121afaf18SBorislav Petkov } 96221afaf18SBorislav Petkov 96321afaf18SBorislav Petkov static ssize_t show_error_count(struct threshold_block *b, char *buf) 96421afaf18SBorislav Petkov { 96521afaf18SBorislav Petkov u32 lo, hi; 96621afaf18SBorislav Petkov 967a037f3caSThomas Gleixner /* CPU might be offline by now */ 968a037f3caSThomas Gleixner if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 969a037f3caSThomas Gleixner return -ENODEV; 97021afaf18SBorislav Petkov 97121afaf18SBorislav Petkov return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 97221afaf18SBorislav Petkov (THRESHOLD_MAX - b->threshold_limit))); 97321afaf18SBorislav Petkov } 97421afaf18SBorislav Petkov 97521afaf18SBorislav Petkov static struct threshold_attr error_count = { 97621afaf18SBorislav Petkov .attr = {.name = __stringify(error_count), .mode = 0444 }, 97721afaf18SBorislav Petkov .show = show_error_count, 97821afaf18SBorislav Petkov }; 97921afaf18SBorislav Petkov 98021afaf18SBorislav Petkov #define RW_ATTR(val) \ 98121afaf18SBorislav Petkov static struct threshold_attr val = { \ 98221afaf18SBorislav Petkov .attr = {.name = __stringify(val), .mode = 0644 }, \ 98321afaf18SBorislav Petkov .show = show_## val, \ 98421afaf18SBorislav Petkov .store = store_## val, \ 98521afaf18SBorislav Petkov }; 98621afaf18SBorislav Petkov 98721afaf18SBorislav Petkov RW_ATTR(interrupt_enable); 98821afaf18SBorislav Petkov RW_ATTR(threshold_limit); 98921afaf18SBorislav Petkov 99021afaf18SBorislav Petkov static struct attribute *default_attrs[] = { 99121afaf18SBorislav Petkov &threshold_limit.attr, 99221afaf18SBorislav Petkov &error_count.attr, 99321afaf18SBorislav Petkov NULL, /* possibly interrupt_enable if supported, see below */ 99421afaf18SBorislav Petkov NULL, 99521afaf18SBorislav Petkov }; 99621afaf18SBorislav Petkov 99721afaf18SBorislav Petkov #define to_block(k) container_of(k, struct threshold_block, kobj) 99821afaf18SBorislav Petkov #define to_attr(a) container_of(a, struct threshold_attr, attr) 99921afaf18SBorislav Petkov 100021afaf18SBorislav Petkov static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 100121afaf18SBorislav Petkov { 100221afaf18SBorislav Petkov struct threshold_block *b = to_block(kobj); 100321afaf18SBorislav Petkov struct threshold_attr *a = to_attr(attr); 100421afaf18SBorislav Petkov ssize_t ret; 100521afaf18SBorislav Petkov 100621afaf18SBorislav Petkov ret = a->show ? a->show(b, buf) : -EIO; 100721afaf18SBorislav Petkov 100821afaf18SBorislav Petkov return ret; 100921afaf18SBorislav Petkov } 101021afaf18SBorislav Petkov 101121afaf18SBorislav Petkov static ssize_t store(struct kobject *kobj, struct attribute *attr, 101221afaf18SBorislav Petkov const char *buf, size_t count) 101321afaf18SBorislav Petkov { 101421afaf18SBorislav Petkov struct threshold_block *b = to_block(kobj); 101521afaf18SBorislav Petkov struct threshold_attr *a = to_attr(attr); 101621afaf18SBorislav Petkov ssize_t ret; 101721afaf18SBorislav Petkov 101821afaf18SBorislav Petkov ret = a->store ? a->store(b, buf, count) : -EIO; 101921afaf18SBorislav Petkov 102021afaf18SBorislav Petkov return ret; 102121afaf18SBorislav Petkov } 102221afaf18SBorislav Petkov 102321afaf18SBorislav Petkov static const struct sysfs_ops threshold_ops = { 102421afaf18SBorislav Petkov .show = show, 102521afaf18SBorislav Petkov .store = store, 102621afaf18SBorislav Petkov }; 102721afaf18SBorislav Petkov 102851dede9cSThomas Gleixner static void threshold_block_release(struct kobject *kobj); 102951dede9cSThomas Gleixner 103021afaf18SBorislav Petkov static struct kobj_type threshold_ktype = { 103121afaf18SBorislav Petkov .sysfs_ops = &threshold_ops, 103221afaf18SBorislav Petkov .default_attrs = default_attrs, 103351dede9cSThomas Gleixner .release = threshold_block_release, 103421afaf18SBorislav Petkov }; 103521afaf18SBorislav Petkov 1036*91f75eb4SYazen Ghannam static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) 103721afaf18SBorislav Petkov { 103821afaf18SBorislav Petkov enum smca_bank_types bank_type; 103921afaf18SBorislav Petkov 104021afaf18SBorislav Petkov if (!mce_flags.smca) { 104121afaf18SBorislav Petkov if (b && bank == 4) 104221afaf18SBorislav Petkov return bank4_names(b); 104321afaf18SBorislav Petkov 104421afaf18SBorislav Petkov return th_names[bank]; 104521afaf18SBorislav Petkov } 104621afaf18SBorislav Petkov 1047*91f75eb4SYazen Ghannam bank_type = smca_get_bank_type(cpu, bank); 104821afaf18SBorislav Petkov if (bank_type >= N_SMCA_BANK_TYPES) 104921afaf18SBorislav Petkov return NULL; 105021afaf18SBorislav Petkov 105121afaf18SBorislav Petkov if (b && bank_type == SMCA_UMC) { 105221afaf18SBorislav Petkov if (b->block < ARRAY_SIZE(smca_umc_block_names)) 105321afaf18SBorislav Petkov return smca_umc_block_names[b->block]; 105421afaf18SBorislav Petkov return NULL; 105521afaf18SBorislav Petkov } 105621afaf18SBorislav Petkov 1057*91f75eb4SYazen Ghannam if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1) 105821afaf18SBorislav Petkov return smca_get_name(bank_type); 105921afaf18SBorislav Petkov 106021afaf18SBorislav Petkov snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1061*91f75eb4SYazen Ghannam "%s_%u", smca_get_name(bank_type), 1062*91f75eb4SYazen Ghannam per_cpu(smca_banks, cpu)[bank].sysfs_id); 106321afaf18SBorislav Petkov return buf_mcatype; 106421afaf18SBorislav Petkov } 106521afaf18SBorislav Petkov 10666e5cf31fSBorislav Petkov static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 10676e5cf31fSBorislav Petkov unsigned int bank, unsigned int block, 10686e5cf31fSBorislav Petkov u32 address) 106921afaf18SBorislav Petkov { 107021afaf18SBorislav Petkov struct threshold_block *b = NULL; 107121afaf18SBorislav Petkov u32 low, high; 107221afaf18SBorislav Petkov int err; 107321afaf18SBorislav Petkov 10746458de97SThomas Gleixner if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 107521afaf18SBorislav Petkov return 0; 107621afaf18SBorislav Petkov 10776458de97SThomas Gleixner if (rdmsr_safe(address, &low, &high)) 107821afaf18SBorislav Petkov return 0; 107921afaf18SBorislav Petkov 108021afaf18SBorislav Petkov if (!(high & MASK_VALID_HI)) { 108121afaf18SBorislav Petkov if (block) 108221afaf18SBorislav Petkov goto recurse; 108321afaf18SBorislav Petkov else 108421afaf18SBorislav Petkov return 0; 108521afaf18SBorislav Petkov } 108621afaf18SBorislav Petkov 108721afaf18SBorislav Petkov if (!(high & MASK_CNTP_HI) || 108821afaf18SBorislav Petkov (high & MASK_LOCKED_HI)) 108921afaf18SBorislav Petkov goto recurse; 109021afaf18SBorislav Petkov 109121afaf18SBorislav Petkov b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 109221afaf18SBorislav Petkov if (!b) 109321afaf18SBorislav Petkov return -ENOMEM; 109421afaf18SBorislav Petkov 109521afaf18SBorislav Petkov b->block = block; 109621afaf18SBorislav Petkov b->bank = bank; 109721afaf18SBorislav Petkov b->cpu = cpu; 109821afaf18SBorislav Petkov b->address = address; 109921afaf18SBorislav Petkov b->interrupt_enable = 0; 110021afaf18SBorislav Petkov b->interrupt_capable = lvt_interrupt_supported(bank, high); 110121afaf18SBorislav Petkov b->threshold_limit = THRESHOLD_MAX; 110221afaf18SBorislav Petkov 110321afaf18SBorislav Petkov if (b->interrupt_capable) { 110421afaf18SBorislav Petkov threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 110521afaf18SBorislav Petkov b->interrupt_enable = 1; 110621afaf18SBorislav Petkov } else { 110721afaf18SBorislav Petkov threshold_ktype.default_attrs[2] = NULL; 110821afaf18SBorislav Petkov } 110921afaf18SBorislav Petkov 111021afaf18SBorislav Petkov INIT_LIST_HEAD(&b->miscj); 111121afaf18SBorislav Petkov 1112cca9cc05SThomas Gleixner /* This is safe as @tb is not visible yet */ 11136e5cf31fSBorislav Petkov if (tb->blocks) 11146e5cf31fSBorislav Petkov list_add(&b->miscj, &tb->blocks->miscj); 11156e5cf31fSBorislav Petkov else 11166e5cf31fSBorislav Petkov tb->blocks = b; 111721afaf18SBorislav Petkov 1118*91f75eb4SYazen Ghannam err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); 111921afaf18SBorislav Petkov if (err) 112021afaf18SBorislav Petkov goto out_free; 112121afaf18SBorislav Petkov recurse: 112295d057f5SYazen Ghannam address = get_block_address(address, low, high, bank, ++block, cpu); 112321afaf18SBorislav Petkov if (!address) 112421afaf18SBorislav Petkov return 0; 112521afaf18SBorislav Petkov 11266e5cf31fSBorislav Petkov err = allocate_threshold_blocks(cpu, tb, bank, block, address); 112721afaf18SBorislav Petkov if (err) 112821afaf18SBorislav Petkov goto out_free; 112921afaf18SBorislav Petkov 113021afaf18SBorislav Petkov if (b) 113121afaf18SBorislav Petkov kobject_uevent(&b->kobj, KOBJ_ADD); 113221afaf18SBorislav Petkov 1133ada018b1SThomas Gleixner return 0; 113421afaf18SBorislav Petkov 113521afaf18SBorislav Petkov out_free: 113621afaf18SBorislav Petkov if (b) { 113721afaf18SBorislav Petkov list_del(&b->miscj); 1138ada018b1SThomas Gleixner kobject_put(&b->kobj); 113921afaf18SBorislav Petkov } 114021afaf18SBorislav Petkov return err; 114121afaf18SBorislav Petkov } 114221afaf18SBorislav Petkov 114321afaf18SBorislav Petkov static int __threshold_add_blocks(struct threshold_bank *b) 114421afaf18SBorislav Petkov { 114521afaf18SBorislav Petkov struct list_head *head = &b->blocks->miscj; 114621afaf18SBorislav Petkov struct threshold_block *pos = NULL; 114721afaf18SBorislav Petkov struct threshold_block *tmp = NULL; 114821afaf18SBorislav Petkov int err = 0; 114921afaf18SBorislav Petkov 115021afaf18SBorislav Petkov err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 115121afaf18SBorislav Petkov if (err) 115221afaf18SBorislav Petkov return err; 115321afaf18SBorislav Petkov 115421afaf18SBorislav Petkov list_for_each_entry_safe(pos, tmp, head, miscj) { 115521afaf18SBorislav Petkov 115621afaf18SBorislav Petkov err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 115721afaf18SBorislav Petkov if (err) { 115821afaf18SBorislav Petkov list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 115921afaf18SBorislav Petkov kobject_del(&pos->kobj); 116021afaf18SBorislav Petkov 116121afaf18SBorislav Petkov return err; 116221afaf18SBorislav Petkov } 116321afaf18SBorislav Petkov } 116421afaf18SBorislav Petkov return err; 116521afaf18SBorislav Petkov } 116621afaf18SBorislav Petkov 11676458de97SThomas Gleixner static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 11686458de97SThomas Gleixner unsigned int bank) 116921afaf18SBorislav Petkov { 11706458de97SThomas Gleixner struct device *dev = this_cpu_read(mce_device); 117121afaf18SBorislav Petkov struct amd_northbridge *nb = NULL; 117221afaf18SBorislav Petkov struct threshold_bank *b = NULL; 1173*91f75eb4SYazen Ghannam const char *name = get_name(cpu, bank, NULL); 117421afaf18SBorislav Petkov int err = 0; 117521afaf18SBorislav Petkov 117621afaf18SBorislav Petkov if (!dev) 117721afaf18SBorislav Petkov return -ENODEV; 117821afaf18SBorislav Petkov 117921afaf18SBorislav Petkov if (is_shared_bank(bank)) { 1180db970bd2SYazen Ghannam nb = node_to_amd_nb(topology_die_id(cpu)); 118121afaf18SBorislav Petkov 118221afaf18SBorislav Petkov /* threshold descriptor already initialized on this node? */ 118321afaf18SBorislav Petkov if (nb && nb->bank4) { 118421afaf18SBorislav Petkov /* yes, use it */ 118521afaf18SBorislav Petkov b = nb->bank4; 118621afaf18SBorislav Petkov err = kobject_add(b->kobj, &dev->kobj, name); 118721afaf18SBorislav Petkov if (err) 118821afaf18SBorislav Petkov goto out; 118921afaf18SBorislav Petkov 11906458de97SThomas Gleixner bp[bank] = b; 119121afaf18SBorislav Petkov refcount_inc(&b->cpus); 119221afaf18SBorislav Petkov 119321afaf18SBorislav Petkov err = __threshold_add_blocks(b); 119421afaf18SBorislav Petkov 119521afaf18SBorislav Petkov goto out; 119621afaf18SBorislav Petkov } 119721afaf18SBorislav Petkov } 119821afaf18SBorislav Petkov 119921afaf18SBorislav Petkov b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 120021afaf18SBorislav Petkov if (!b) { 120121afaf18SBorislav Petkov err = -ENOMEM; 120221afaf18SBorislav Petkov goto out; 120321afaf18SBorislav Petkov } 120421afaf18SBorislav Petkov 1205ada018b1SThomas Gleixner /* Associate the bank with the per-CPU MCE device */ 120621afaf18SBorislav Petkov b->kobj = kobject_create_and_add(name, &dev->kobj); 120721afaf18SBorislav Petkov if (!b->kobj) { 120821afaf18SBorislav Petkov err = -EINVAL; 120921afaf18SBorislav Petkov goto out_free; 121021afaf18SBorislav Petkov } 121121afaf18SBorislav Petkov 121221afaf18SBorislav Petkov if (is_shared_bank(bank)) { 1213f26d2580SThomas Gleixner b->shared = 1; 121421afaf18SBorislav Petkov refcount_set(&b->cpus, 1); 121521afaf18SBorislav Petkov 121621afaf18SBorislav Petkov /* nb is already initialized, see above */ 121721afaf18SBorislav Petkov if (nb) { 121821afaf18SBorislav Petkov WARN_ON(nb->bank4); 121921afaf18SBorislav Petkov nb->bank4 = b; 122021afaf18SBorislav Petkov } 122121afaf18SBorislav Petkov } 122221afaf18SBorislav Petkov 12238121b8f9SBorislav Petkov err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); 12246e5cf31fSBorislav Petkov if (err) 1225ada018b1SThomas Gleixner goto out_kobj; 12266e5cf31fSBorislav Petkov 12276458de97SThomas Gleixner bp[bank] = b; 12286e5cf31fSBorislav Petkov return 0; 122921afaf18SBorislav Petkov 1230ada018b1SThomas Gleixner out_kobj: 1231ada018b1SThomas Gleixner kobject_put(b->kobj); 123221afaf18SBorislav Petkov out_free: 123321afaf18SBorislav Petkov kfree(b); 123421afaf18SBorislav Petkov out: 123521afaf18SBorislav Petkov return err; 123621afaf18SBorislav Petkov } 123721afaf18SBorislav Petkov 123851dede9cSThomas Gleixner static void threshold_block_release(struct kobject *kobj) 123951dede9cSThomas Gleixner { 124051dede9cSThomas Gleixner kfree(to_block(kobj)); 124151dede9cSThomas Gleixner } 124251dede9cSThomas Gleixner 1243f26d2580SThomas Gleixner static void deallocate_threshold_blocks(struct threshold_bank *bank) 124421afaf18SBorislav Petkov { 1245f26d2580SThomas Gleixner struct threshold_block *pos, *tmp; 124621afaf18SBorislav Petkov 1247f26d2580SThomas Gleixner list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 124821afaf18SBorislav Petkov list_del(&pos->miscj); 124951dede9cSThomas Gleixner kobject_put(&pos->kobj); 125021afaf18SBorislav Petkov } 125121afaf18SBorislav Petkov 1252f26d2580SThomas Gleixner kobject_put(&bank->blocks->kobj); 125321afaf18SBorislav Petkov } 125421afaf18SBorislav Petkov 125521afaf18SBorislav Petkov static void __threshold_remove_blocks(struct threshold_bank *b) 125621afaf18SBorislav Petkov { 125721afaf18SBorislav Petkov struct threshold_block *pos = NULL; 125821afaf18SBorislav Petkov struct threshold_block *tmp = NULL; 125921afaf18SBorislav Petkov 126021afaf18SBorislav Petkov kobject_del(b->kobj); 126121afaf18SBorislav Petkov 126221afaf18SBorislav Petkov list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 126321afaf18SBorislav Petkov kobject_del(&pos->kobj); 126421afaf18SBorislav Petkov } 126521afaf18SBorislav Petkov 1266f26d2580SThomas Gleixner static void threshold_remove_bank(struct threshold_bank *bank) 126721afaf18SBorislav Petkov { 126821afaf18SBorislav Petkov struct amd_northbridge *nb; 126921afaf18SBorislav Petkov 1270f26d2580SThomas Gleixner if (!bank->blocks) 1271f26d2580SThomas Gleixner goto out_free; 127221afaf18SBorislav Petkov 1273f26d2580SThomas Gleixner if (!bank->shared) 1274f26d2580SThomas Gleixner goto out_dealloc; 127521afaf18SBorislav Petkov 1276f26d2580SThomas Gleixner if (!refcount_dec_and_test(&bank->cpus)) { 1277f26d2580SThomas Gleixner __threshold_remove_blocks(bank); 127821afaf18SBorislav Petkov return; 127921afaf18SBorislav Petkov } else { 128021afaf18SBorislav Petkov /* 1281f26d2580SThomas Gleixner * The last CPU on this node using the shared bank is going 1282f26d2580SThomas Gleixner * away, remove that bank now. 128321afaf18SBorislav Petkov */ 1284db970bd2SYazen Ghannam nb = node_to_amd_nb(topology_die_id(smp_processor_id())); 128521afaf18SBorislav Petkov nb->bank4 = NULL; 128621afaf18SBorislav Petkov } 128721afaf18SBorislav Petkov 1288f26d2580SThomas Gleixner out_dealloc: 1289f26d2580SThomas Gleixner deallocate_threshold_blocks(bank); 129021afaf18SBorislav Petkov 1291f26d2580SThomas Gleixner out_free: 1292f26d2580SThomas Gleixner kobject_put(bank->kobj); 1293f26d2580SThomas Gleixner kfree(bank); 129421afaf18SBorislav Petkov } 129521afaf18SBorislav Petkov 129621afaf18SBorislav Petkov int mce_threshold_remove_device(unsigned int cpu) 129721afaf18SBorislav Petkov { 1298c9bf318fSThomas Gleixner struct threshold_bank **bp = this_cpu_read(threshold_banks); 1299f26d2580SThomas Gleixner unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 130021afaf18SBorislav Petkov 1301c9bf318fSThomas Gleixner if (!bp) 1302c9bf318fSThomas Gleixner return 0; 1303c9bf318fSThomas Gleixner 1304f26d2580SThomas Gleixner /* 1305f26d2580SThomas Gleixner * Clear the pointer before cleaning up, so that the interrupt won't 1306f26d2580SThomas Gleixner * touch anything of this. 1307f26d2580SThomas Gleixner */ 1308c9bf318fSThomas Gleixner this_cpu_write(threshold_banks, NULL); 1309f26d2580SThomas Gleixner 1310f26d2580SThomas Gleixner for (bank = 0; bank < numbanks; bank++) { 1311f26d2580SThomas Gleixner if (bp[bank]) { 1312f26d2580SThomas Gleixner threshold_remove_bank(bp[bank]); 1313f26d2580SThomas Gleixner bp[bank] = NULL; 1314f26d2580SThomas Gleixner } 1315f26d2580SThomas Gleixner } 1316c9bf318fSThomas Gleixner kfree(bp); 131721afaf18SBorislav Petkov return 0; 131821afaf18SBorislav Petkov } 131921afaf18SBorislav Petkov 13206e7a41c6SThomas Gleixner /** 13216e7a41c6SThomas Gleixner * mce_threshold_create_device - Create the per-CPU MCE threshold device 13226e7a41c6SThomas Gleixner * @cpu: The plugged in CPU 13236e7a41c6SThomas Gleixner * 13246e7a41c6SThomas Gleixner * Create directories and files for all valid threshold banks. 13256e7a41c6SThomas Gleixner * 13266e7a41c6SThomas Gleixner * This is invoked from the CPU hotplug callback which was installed in 13276e7a41c6SThomas Gleixner * mcheck_init_device(). The invocation happens in context of the hotplug 13286e7a41c6SThomas Gleixner * thread running on @cpu. The callback is invoked on all CPUs which are 13296e7a41c6SThomas Gleixner * online when the callback is installed or during a real hotplug event. 13306e7a41c6SThomas Gleixner */ 133121afaf18SBorislav Petkov int mce_threshold_create_device(unsigned int cpu) 133221afaf18SBorislav Petkov { 13336458de97SThomas Gleixner unsigned int numbanks, bank; 133421afaf18SBorislav Petkov struct threshold_bank **bp; 13356e7a41c6SThomas Gleixner int err; 133621afaf18SBorislav Petkov 1337c9bf318fSThomas Gleixner if (!mce_flags.amd_threshold) 1338c9bf318fSThomas Gleixner return 0; 1339c9bf318fSThomas Gleixner 13406458de97SThomas Gleixner bp = this_cpu_read(threshold_banks); 134121afaf18SBorislav Petkov if (bp) 134221afaf18SBorislav Petkov return 0; 134321afaf18SBorislav Petkov 13446458de97SThomas Gleixner numbanks = this_cpu_read(mce_num_banks); 13456458de97SThomas Gleixner bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 134621afaf18SBorislav Petkov if (!bp) 134721afaf18SBorislav Petkov return -ENOMEM; 134821afaf18SBorislav Petkov 13496458de97SThomas Gleixner for (bank = 0; bank < numbanks; ++bank) { 13506458de97SThomas Gleixner if (!(this_cpu_read(bank_map) & (1 << bank))) 135121afaf18SBorislav Petkov continue; 13526458de97SThomas Gleixner err = threshold_create_bank(bp, cpu, bank); 135321afaf18SBorislav Petkov if (err) 13546e7a41c6SThomas Gleixner goto out_err; 135521afaf18SBorislav Petkov } 13566458de97SThomas Gleixner this_cpu_write(threshold_banks, bp); 135721afaf18SBorislav Petkov 135821afaf18SBorislav Petkov if (thresholding_irq_en) 135921afaf18SBorislav Petkov mce_threshold_vector = amd_threshold_interrupt; 136021afaf18SBorislav Petkov return 0; 13616e7a41c6SThomas Gleixner out_err: 13626e7a41c6SThomas Gleixner mce_threshold_remove_device(cpu); 13636e7a41c6SThomas Gleixner return err; 136421afaf18SBorislav Petkov } 1365