121afaf18SBorislav Petkov /* 221afaf18SBorislav Petkov * (c) 2005-2016 Advanced Micro Devices, Inc. 321afaf18SBorislav Petkov * Your use of this code is subject to the terms and conditions of the 421afaf18SBorislav Petkov * GNU general public license version 2. See "COPYING" or 521afaf18SBorislav Petkov * http://www.gnu.org/licenses/gpl.html 621afaf18SBorislav Petkov * 721afaf18SBorislav Petkov * Written by Jacob Shin - AMD, Inc. 821afaf18SBorislav Petkov * Maintained by: Borislav Petkov <bp@alien8.de> 921afaf18SBorislav Petkov * 1021afaf18SBorislav Petkov * All MC4_MISCi registers are shared between cores on a node. 1121afaf18SBorislav Petkov */ 1221afaf18SBorislav Petkov #include <linux/interrupt.h> 1321afaf18SBorislav Petkov #include <linux/notifier.h> 1421afaf18SBorislav Petkov #include <linux/kobject.h> 1521afaf18SBorislav Petkov #include <linux/percpu.h> 1621afaf18SBorislav Petkov #include <linux/errno.h> 1721afaf18SBorislav Petkov #include <linux/sched.h> 1821afaf18SBorislav Petkov #include <linux/sysfs.h> 1921afaf18SBorislav Petkov #include <linux/slab.h> 2021afaf18SBorislav Petkov #include <linux/init.h> 2121afaf18SBorislav Petkov #include <linux/cpu.h> 2221afaf18SBorislav Petkov #include <linux/smp.h> 2321afaf18SBorislav Petkov #include <linux/string.h> 2421afaf18SBorislav Petkov 2521afaf18SBorislav Petkov #include <asm/amd_nb.h> 26312a4661SLinus Torvalds #include <asm/traps.h> 2721afaf18SBorislav Petkov #include <asm/apic.h> 2821afaf18SBorislav Petkov #include <asm/mce.h> 2921afaf18SBorislav Petkov #include <asm/msr.h> 3021afaf18SBorislav Petkov #include <asm/trace/irq_vectors.h> 3121afaf18SBorislav Petkov 3221afaf18SBorislav Petkov #include "internal.h" 3321afaf18SBorislav Petkov 3421afaf18SBorislav Petkov #define NR_BLOCKS 5 3521afaf18SBorislav Petkov #define THRESHOLD_MAX 0xFFF 3621afaf18SBorislav Petkov #define INT_TYPE_APIC 0x00020000 3721afaf18SBorislav Petkov #define MASK_VALID_HI 0x80000000 3821afaf18SBorislav Petkov #define MASK_CNTP_HI 0x40000000 3921afaf18SBorislav Petkov #define MASK_LOCKED_HI 0x20000000 4021afaf18SBorislav Petkov #define MASK_LVTOFF_HI 0x00F00000 4121afaf18SBorislav Petkov #define MASK_COUNT_EN_HI 0x00080000 4221afaf18SBorislav Petkov #define MASK_INT_TYPE_HI 0x00060000 4321afaf18SBorislav Petkov #define MASK_OVERFLOW_HI 0x00010000 4421afaf18SBorislav Petkov #define MASK_ERR_COUNT_HI 0x00000FFF 4521afaf18SBorislav Petkov #define MASK_BLKPTR_LO 0xFF000000 4621afaf18SBorislav Petkov #define MCG_XBLK_ADDR 0xC0000400 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov /* Deferred error settings */ 4921afaf18SBorislav Petkov #define MSR_CU_DEF_ERR 0xC0000410 5021afaf18SBorislav Petkov #define MASK_DEF_LVTOFF 0x000000F0 5121afaf18SBorislav Petkov #define MASK_DEF_INT_TYPE 0x00000006 5221afaf18SBorislav Petkov #define DEF_LVT_OFF 0x2 5321afaf18SBorislav Petkov #define DEF_INT_TYPE_APIC 0x2 5421afaf18SBorislav Petkov 5521afaf18SBorislav Petkov /* Scalable MCA: */ 5621afaf18SBorislav Petkov 5721afaf18SBorislav Petkov /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 5821afaf18SBorislav Petkov #define SMCA_THR_LVT_OFF 0xF000 5921afaf18SBorislav Petkov 6021afaf18SBorislav Petkov static bool thresholding_irq_en; 6121afaf18SBorislav Petkov 6221afaf18SBorislav Petkov static const char * const th_names[] = { 6321afaf18SBorislav Petkov "load_store", 6421afaf18SBorislav Petkov "insn_fetch", 6521afaf18SBorislav Petkov "combined_unit", 6621afaf18SBorislav Petkov "decode_unit", 6721afaf18SBorislav Petkov "northbridge", 6821afaf18SBorislav Petkov "execution_unit", 6921afaf18SBorislav Petkov }; 7021afaf18SBorislav Petkov 7121afaf18SBorislav Petkov static const char * const smca_umc_block_names[] = { 7221afaf18SBorislav Petkov "dram_ecc", 7321afaf18SBorislav Petkov "misc_umc" 7421afaf18SBorislav Petkov }; 7521afaf18SBorislav Petkov 7621afaf18SBorislav Petkov struct smca_bank_name { 7721afaf18SBorislav Petkov const char *name; /* Short name for sysfs */ 7821afaf18SBorislav Petkov const char *long_name; /* Long name for pretty-printing */ 7921afaf18SBorislav Petkov }; 8021afaf18SBorislav Petkov 8121afaf18SBorislav Petkov static struct smca_bank_name smca_names[] = { 8221afaf18SBorislav Petkov [SMCA_LS] = { "load_store", "Load Store Unit" }, 8321afaf18SBorislav Petkov [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 8421afaf18SBorislav Petkov [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 8521afaf18SBorislav Petkov [SMCA_DE] = { "decode_unit", "Decode Unit" }, 8621afaf18SBorislav Petkov [SMCA_RESERVED] = { "reserved", "Reserved" }, 8721afaf18SBorislav Petkov [SMCA_EX] = { "execution_unit", "Execution Unit" }, 8821afaf18SBorislav Petkov [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 8921afaf18SBorislav Petkov [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 9021afaf18SBorislav Petkov [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, 9121afaf18SBorislav Petkov [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 9221afaf18SBorislav Petkov [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 9321afaf18SBorislav Petkov [SMCA_PB] = { "param_block", "Parameter Block" }, 9421afaf18SBorislav Petkov [SMCA_PSP] = { "psp", "Platform Security Processor" }, 9521afaf18SBorislav Petkov [SMCA_SMU] = { "smu", "System Management Unit" }, 9621afaf18SBorislav Petkov }; 9721afaf18SBorislav Petkov 9821afaf18SBorislav Petkov static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init = 9921afaf18SBorislav Petkov { 10021afaf18SBorislav Petkov [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 } 10121afaf18SBorislav Petkov }; 10221afaf18SBorislav Petkov 103312a4661SLinus Torvalds static const char *smca_get_name(enum smca_bank_types t) 10421afaf18SBorislav Petkov { 10521afaf18SBorislav Petkov if (t >= N_SMCA_BANK_TYPES) 10621afaf18SBorislav Petkov return NULL; 10721afaf18SBorislav Petkov 10821afaf18SBorislav Petkov return smca_names[t].name; 10921afaf18SBorislav Petkov } 11021afaf18SBorislav Petkov 11121afaf18SBorislav Petkov const char *smca_get_long_name(enum smca_bank_types t) 11221afaf18SBorislav Petkov { 11321afaf18SBorislav Petkov if (t >= N_SMCA_BANK_TYPES) 11421afaf18SBorislav Petkov return NULL; 11521afaf18SBorislav Petkov 11621afaf18SBorislav Petkov return smca_names[t].long_name; 11721afaf18SBorislav Petkov } 11821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(smca_get_long_name); 11921afaf18SBorislav Petkov 12021afaf18SBorislav Petkov static enum smca_bank_types smca_get_bank_type(unsigned int bank) 12121afaf18SBorislav Petkov { 12221afaf18SBorislav Petkov struct smca_bank *b; 12321afaf18SBorislav Petkov 12421afaf18SBorislav Petkov if (bank >= MAX_NR_BANKS) 12521afaf18SBorislav Petkov return N_SMCA_BANK_TYPES; 12621afaf18SBorislav Petkov 12721afaf18SBorislav Petkov b = &smca_banks[bank]; 12821afaf18SBorislav Petkov if (!b->hwid) 12921afaf18SBorislav Petkov return N_SMCA_BANK_TYPES; 13021afaf18SBorislav Petkov 13121afaf18SBorislav Petkov return b->hwid->bank_type; 13221afaf18SBorislav Petkov } 13321afaf18SBorislav Petkov 13421afaf18SBorislav Petkov static struct smca_hwid smca_hwid_mcatypes[] = { 13521afaf18SBorislav Petkov /* { bank_type, hwid_mcatype, xec_bitmap } */ 13621afaf18SBorislav Petkov 13721afaf18SBorislav Petkov /* Reserved type */ 13821afaf18SBorislav Petkov { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 }, 13921afaf18SBorislav Petkov 14021afaf18SBorislav Petkov /* ZN Core (HWID=0xB0) MCA types */ 14121afaf18SBorislav Petkov { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, 14221afaf18SBorislav Petkov { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, 14321afaf18SBorislav Petkov { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, 14421afaf18SBorislav Petkov { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, 14521afaf18SBorislav Petkov /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 14621afaf18SBorislav Petkov { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, 14721afaf18SBorislav Petkov { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, 14821afaf18SBorislav Petkov { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, 14921afaf18SBorislav Petkov 15021afaf18SBorislav Petkov /* Data Fabric MCA types */ 15121afaf18SBorislav Petkov { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, 15221afaf18SBorislav Petkov { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, 15321afaf18SBorislav Petkov 15421afaf18SBorislav Petkov /* Unified Memory Controller MCA type */ 15521afaf18SBorislav Petkov { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, 15621afaf18SBorislav Petkov 15721afaf18SBorislav Petkov /* Parameter Block MCA type */ 15821afaf18SBorislav Petkov { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, 15921afaf18SBorislav Petkov 16021afaf18SBorislav Petkov /* Platform Security Processor MCA type */ 16121afaf18SBorislav Petkov { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, 16221afaf18SBorislav Petkov 16321afaf18SBorislav Petkov /* System Management Unit MCA type */ 16421afaf18SBorislav Petkov { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, 16521afaf18SBorislav Petkov }; 16621afaf18SBorislav Petkov 16721afaf18SBorislav Petkov struct smca_bank smca_banks[MAX_NR_BANKS]; 16821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(smca_banks); 16921afaf18SBorislav Petkov 17021afaf18SBorislav Petkov /* 17121afaf18SBorislav Petkov * In SMCA enabled processors, we can have multiple banks for a given IP type. 17221afaf18SBorislav Petkov * So to define a unique name for each bank, we use a temp c-string to append 17321afaf18SBorislav Petkov * the MCA_IPID[InstanceId] to type's name in get_name(). 17421afaf18SBorislav Petkov * 17521afaf18SBorislav Petkov * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 17621afaf18SBorislav Petkov * is greater than 8 plus 1 (for underscore) plus length of longest type name. 17721afaf18SBorislav Petkov */ 17821afaf18SBorislav Petkov #define MAX_MCATYPE_NAME_LEN 30 17921afaf18SBorislav Petkov static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 18021afaf18SBorislav Petkov 18121afaf18SBorislav Petkov static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 18221afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ 18321afaf18SBorislav Petkov 18421afaf18SBorislav Petkov static void amd_threshold_interrupt(void); 18521afaf18SBorislav Petkov static void amd_deferred_error_interrupt(void); 18621afaf18SBorislav Petkov 18721afaf18SBorislav Petkov static void default_deferred_error_interrupt(void) 18821afaf18SBorislav Petkov { 18921afaf18SBorislav Petkov pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 19021afaf18SBorislav Petkov } 19121afaf18SBorislav Petkov void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 19221afaf18SBorislav Petkov 19321afaf18SBorislav Petkov static void smca_configure(unsigned int bank, unsigned int cpu) 19421afaf18SBorislav Petkov { 19521afaf18SBorislav Petkov unsigned int i, hwid_mcatype; 19621afaf18SBorislav Petkov struct smca_hwid *s_hwid; 19721afaf18SBorislav Petkov u32 high, low; 19821afaf18SBorislav Petkov u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 19921afaf18SBorislav Petkov 20021afaf18SBorislav Petkov /* Set appropriate bits in MCA_CONFIG */ 20121afaf18SBorislav Petkov if (!rdmsr_safe(smca_config, &low, &high)) { 20221afaf18SBorislav Petkov /* 20321afaf18SBorislav Petkov * OS is required to set the MCAX bit to acknowledge that it is 20421afaf18SBorislav Petkov * now using the new MSR ranges and new registers under each 20521afaf18SBorislav Petkov * bank. It also means that the OS will configure deferred 20621afaf18SBorislav Petkov * errors in the new MCx_CONFIG register. If the bit is not set, 20721afaf18SBorislav Petkov * uncorrectable errors will cause a system panic. 20821afaf18SBorislav Petkov * 20921afaf18SBorislav Petkov * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 21021afaf18SBorislav Petkov */ 21121afaf18SBorislav Petkov high |= BIT(0); 21221afaf18SBorislav Petkov 21321afaf18SBorislav Petkov /* 21421afaf18SBorislav Petkov * SMCA sets the Deferred Error Interrupt type per bank. 21521afaf18SBorislav Petkov * 21621afaf18SBorislav Petkov * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 21721afaf18SBorislav Petkov * if the DeferredIntType bit field is available. 21821afaf18SBorislav Petkov * 21921afaf18SBorislav Petkov * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 22021afaf18SBorislav Petkov * high portion of the MSR). OS should set this to 0x1 to enable 22121afaf18SBorislav Petkov * APIC based interrupt. First, check that no interrupt has been 22221afaf18SBorislav Petkov * set. 22321afaf18SBorislav Petkov */ 22421afaf18SBorislav Petkov if ((low & BIT(5)) && !((high >> 5) & 0x3)) 22521afaf18SBorislav Petkov high |= BIT(5); 22621afaf18SBorislav Petkov 22721afaf18SBorislav Petkov wrmsr(smca_config, low, high); 22821afaf18SBorislav Petkov } 22921afaf18SBorislav Petkov 23021afaf18SBorislav Petkov /* Return early if this bank was already initialized. */ 23121afaf18SBorislav Petkov if (smca_banks[bank].hwid) 23221afaf18SBorislav Petkov return; 23321afaf18SBorislav Petkov 23421afaf18SBorislav Petkov if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 23521afaf18SBorislav Petkov pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 23621afaf18SBorislav Petkov return; 23721afaf18SBorislav Petkov } 23821afaf18SBorislav Petkov 23921afaf18SBorislav Petkov hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 24021afaf18SBorislav Petkov (high & MCI_IPID_MCATYPE) >> 16); 24121afaf18SBorislav Petkov 24221afaf18SBorislav Petkov for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 24321afaf18SBorislav Petkov s_hwid = &smca_hwid_mcatypes[i]; 24421afaf18SBorislav Petkov if (hwid_mcatype == s_hwid->hwid_mcatype) { 24521afaf18SBorislav Petkov smca_banks[bank].hwid = s_hwid; 24621afaf18SBorislav Petkov smca_banks[bank].id = low; 24721afaf18SBorislav Petkov smca_banks[bank].sysfs_id = s_hwid->count++; 24821afaf18SBorislav Petkov break; 24921afaf18SBorislav Petkov } 25021afaf18SBorislav Petkov } 25121afaf18SBorislav Petkov } 25221afaf18SBorislav Petkov 25321afaf18SBorislav Petkov struct thresh_restart { 25421afaf18SBorislav Petkov struct threshold_block *b; 25521afaf18SBorislav Petkov int reset; 25621afaf18SBorislav Petkov int set_lvt_off; 25721afaf18SBorislav Petkov int lvt_off; 25821afaf18SBorislav Petkov u16 old_limit; 25921afaf18SBorislav Petkov }; 26021afaf18SBorislav Petkov 26121afaf18SBorislav Petkov static inline bool is_shared_bank(int bank) 26221afaf18SBorislav Petkov { 26321afaf18SBorislav Petkov /* 26421afaf18SBorislav Petkov * Scalable MCA provides for only one core to have access to the MSRs of 26521afaf18SBorislav Petkov * a shared bank. 26621afaf18SBorislav Petkov */ 26721afaf18SBorislav Petkov if (mce_flags.smca) 26821afaf18SBorislav Petkov return false; 26921afaf18SBorislav Petkov 27021afaf18SBorislav Petkov /* Bank 4 is for northbridge reporting and is thus shared */ 27121afaf18SBorislav Petkov return (bank == 4); 27221afaf18SBorislav Petkov } 27321afaf18SBorislav Petkov 27421afaf18SBorislav Petkov static const char *bank4_names(const struct threshold_block *b) 27521afaf18SBorislav Petkov { 27621afaf18SBorislav Petkov switch (b->address) { 27721afaf18SBorislav Petkov /* MSR4_MISC0 */ 27821afaf18SBorislav Petkov case 0x00000413: 27921afaf18SBorislav Petkov return "dram"; 28021afaf18SBorislav Petkov 28121afaf18SBorislav Petkov case 0xc0000408: 28221afaf18SBorislav Petkov return "ht_links"; 28321afaf18SBorislav Petkov 28421afaf18SBorislav Petkov case 0xc0000409: 28521afaf18SBorislav Petkov return "l3_cache"; 28621afaf18SBorislav Petkov 28721afaf18SBorislav Petkov default: 28821afaf18SBorislav Petkov WARN(1, "Funny MSR: 0x%08x\n", b->address); 28921afaf18SBorislav Petkov return ""; 29021afaf18SBorislav Petkov } 29121afaf18SBorislav Petkov }; 29221afaf18SBorislav Petkov 29321afaf18SBorislav Petkov 29421afaf18SBorislav Petkov static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 29521afaf18SBorislav Petkov { 29621afaf18SBorislav Petkov /* 29721afaf18SBorislav Petkov * bank 4 supports APIC LVT interrupts implicitly since forever. 29821afaf18SBorislav Petkov */ 29921afaf18SBorislav Petkov if (bank == 4) 30021afaf18SBorislav Petkov return true; 30121afaf18SBorislav Petkov 30221afaf18SBorislav Petkov /* 30321afaf18SBorislav Petkov * IntP: interrupt present; if this bit is set, the thresholding 30421afaf18SBorislav Petkov * bank can generate APIC LVT interrupts 30521afaf18SBorislav Petkov */ 30621afaf18SBorislav Petkov return msr_high_bits & BIT(28); 30721afaf18SBorislav Petkov } 30821afaf18SBorislav Petkov 30921afaf18SBorislav Petkov static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 31021afaf18SBorislav Petkov { 31121afaf18SBorislav Petkov int msr = (hi & MASK_LVTOFF_HI) >> 20; 31221afaf18SBorislav Petkov 31321afaf18SBorislav Petkov if (apic < 0) { 31421afaf18SBorislav Petkov pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 31521afaf18SBorislav Petkov "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 31621afaf18SBorislav Petkov b->bank, b->block, b->address, hi, lo); 31721afaf18SBorislav Petkov return 0; 31821afaf18SBorislav Petkov } 31921afaf18SBorislav Petkov 32021afaf18SBorislav Petkov if (apic != msr) { 32121afaf18SBorislav Petkov /* 32221afaf18SBorislav Petkov * On SMCA CPUs, LVT offset is programmed at a different MSR, and 32321afaf18SBorislav Petkov * the BIOS provides the value. The original field where LVT offset 32421afaf18SBorislav Petkov * was set is reserved. Return early here: 32521afaf18SBorislav Petkov */ 32621afaf18SBorislav Petkov if (mce_flags.smca) 32721afaf18SBorislav Petkov return 0; 32821afaf18SBorislav Petkov 32921afaf18SBorislav Petkov pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 33021afaf18SBorislav Petkov "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 33121afaf18SBorislav Petkov b->cpu, apic, b->bank, b->block, b->address, hi, lo); 33221afaf18SBorislav Petkov return 0; 33321afaf18SBorislav Petkov } 33421afaf18SBorislav Petkov 33521afaf18SBorislav Petkov return 1; 33621afaf18SBorislav Petkov }; 33721afaf18SBorislav Petkov 33821afaf18SBorislav Petkov /* Reprogram MCx_MISC MSR behind this threshold bank. */ 33921afaf18SBorislav Petkov static void threshold_restart_bank(void *_tr) 34021afaf18SBorislav Petkov { 34121afaf18SBorislav Petkov struct thresh_restart *tr = _tr; 34221afaf18SBorislav Petkov u32 hi, lo; 34321afaf18SBorislav Petkov 34421afaf18SBorislav Petkov rdmsr(tr->b->address, lo, hi); 34521afaf18SBorislav Petkov 34621afaf18SBorislav Petkov if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 34721afaf18SBorislav Petkov tr->reset = 1; /* limit cannot be lower than err count */ 34821afaf18SBorislav Petkov 34921afaf18SBorislav Petkov if (tr->reset) { /* reset err count and overflow bit */ 35021afaf18SBorislav Petkov hi = 35121afaf18SBorislav Petkov (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 35221afaf18SBorislav Petkov (THRESHOLD_MAX - tr->b->threshold_limit); 35321afaf18SBorislav Petkov } else if (tr->old_limit) { /* change limit w/o reset */ 35421afaf18SBorislav Petkov int new_count = (hi & THRESHOLD_MAX) + 35521afaf18SBorislav Petkov (tr->old_limit - tr->b->threshold_limit); 35621afaf18SBorislav Petkov 35721afaf18SBorislav Petkov hi = (hi & ~MASK_ERR_COUNT_HI) | 35821afaf18SBorislav Petkov (new_count & THRESHOLD_MAX); 35921afaf18SBorislav Petkov } 36021afaf18SBorislav Petkov 36121afaf18SBorislav Petkov /* clear IntType */ 36221afaf18SBorislav Petkov hi &= ~MASK_INT_TYPE_HI; 36321afaf18SBorislav Petkov 36421afaf18SBorislav Petkov if (!tr->b->interrupt_capable) 36521afaf18SBorislav Petkov goto done; 36621afaf18SBorislav Petkov 36721afaf18SBorislav Petkov if (tr->set_lvt_off) { 36821afaf18SBorislav Petkov if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 36921afaf18SBorislav Petkov /* set new lvt offset */ 37021afaf18SBorislav Petkov hi &= ~MASK_LVTOFF_HI; 37121afaf18SBorislav Petkov hi |= tr->lvt_off << 20; 37221afaf18SBorislav Petkov } 37321afaf18SBorislav Petkov } 37421afaf18SBorislav Petkov 37521afaf18SBorislav Petkov if (tr->b->interrupt_enable) 37621afaf18SBorislav Petkov hi |= INT_TYPE_APIC; 37721afaf18SBorislav Petkov 37821afaf18SBorislav Petkov done: 37921afaf18SBorislav Petkov 38021afaf18SBorislav Petkov hi |= MASK_COUNT_EN_HI; 38121afaf18SBorislav Petkov wrmsr(tr->b->address, lo, hi); 38221afaf18SBorislav Petkov } 38321afaf18SBorislav Petkov 38421afaf18SBorislav Petkov static void mce_threshold_block_init(struct threshold_block *b, int offset) 38521afaf18SBorislav Petkov { 38621afaf18SBorislav Petkov struct thresh_restart tr = { 38721afaf18SBorislav Petkov .b = b, 38821afaf18SBorislav Petkov .set_lvt_off = 1, 38921afaf18SBorislav Petkov .lvt_off = offset, 39021afaf18SBorislav Petkov }; 39121afaf18SBorislav Petkov 39221afaf18SBorislav Petkov b->threshold_limit = THRESHOLD_MAX; 39321afaf18SBorislav Petkov threshold_restart_bank(&tr); 39421afaf18SBorislav Petkov }; 39521afaf18SBorislav Petkov 39621afaf18SBorislav Petkov static int setup_APIC_mce_threshold(int reserved, int new) 39721afaf18SBorislav Petkov { 39821afaf18SBorislav Petkov if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 39921afaf18SBorislav Petkov APIC_EILVT_MSG_FIX, 0)) 40021afaf18SBorislav Petkov return new; 40121afaf18SBorislav Petkov 40221afaf18SBorislav Petkov return reserved; 40321afaf18SBorislav Petkov } 40421afaf18SBorislav Petkov 40521afaf18SBorislav Petkov static int setup_APIC_deferred_error(int reserved, int new) 40621afaf18SBorislav Petkov { 40721afaf18SBorislav Petkov if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 40821afaf18SBorislav Petkov APIC_EILVT_MSG_FIX, 0)) 40921afaf18SBorislav Petkov return new; 41021afaf18SBorislav Petkov 41121afaf18SBorislav Petkov return reserved; 41221afaf18SBorislav Petkov } 41321afaf18SBorislav Petkov 41421afaf18SBorislav Petkov static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 41521afaf18SBorislav Petkov { 41621afaf18SBorislav Petkov u32 low = 0, high = 0; 41721afaf18SBorislav Petkov int def_offset = -1, def_new; 41821afaf18SBorislav Petkov 41921afaf18SBorislav Petkov if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 42021afaf18SBorislav Petkov return; 42121afaf18SBorislav Petkov 42221afaf18SBorislav Petkov def_new = (low & MASK_DEF_LVTOFF) >> 4; 42321afaf18SBorislav Petkov if (!(low & MASK_DEF_LVTOFF)) { 42421afaf18SBorislav Petkov pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 42521afaf18SBorislav Petkov def_new = DEF_LVT_OFF; 42621afaf18SBorislav Petkov low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 42721afaf18SBorislav Petkov } 42821afaf18SBorislav Petkov 42921afaf18SBorislav Petkov def_offset = setup_APIC_deferred_error(def_offset, def_new); 43021afaf18SBorislav Petkov if ((def_offset == def_new) && 43121afaf18SBorislav Petkov (deferred_error_int_vector != amd_deferred_error_interrupt)) 43221afaf18SBorislav Petkov deferred_error_int_vector = amd_deferred_error_interrupt; 43321afaf18SBorislav Petkov 43421afaf18SBorislav Petkov if (!mce_flags.smca) 43521afaf18SBorislav Petkov low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 43621afaf18SBorislav Petkov 43721afaf18SBorislav Petkov wrmsr(MSR_CU_DEF_ERR, low, high); 43821afaf18SBorislav Petkov } 43921afaf18SBorislav Petkov 44021afaf18SBorislav Petkov static u32 smca_get_block_address(unsigned int bank, unsigned int block) 44121afaf18SBorislav Petkov { 44221afaf18SBorislav Petkov u32 low, high; 44321afaf18SBorislav Petkov u32 addr = 0; 44421afaf18SBorislav Petkov 44521afaf18SBorislav Petkov if (smca_get_bank_type(bank) == SMCA_RESERVED) 44621afaf18SBorislav Petkov return addr; 44721afaf18SBorislav Petkov 44821afaf18SBorislav Petkov if (!block) 44921afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_MISC(bank); 45021afaf18SBorislav Petkov 45121afaf18SBorislav Petkov /* Check our cache first: */ 45221afaf18SBorislav Petkov if (smca_bank_addrs[bank][block] != -1) 45321afaf18SBorislav Petkov return smca_bank_addrs[bank][block]; 45421afaf18SBorislav Petkov 45521afaf18SBorislav Petkov /* 45621afaf18SBorislav Petkov * For SMCA enabled processors, BLKPTR field of the first MISC register 45721afaf18SBorislav Petkov * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 45821afaf18SBorislav Petkov */ 45921afaf18SBorislav Petkov if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 46021afaf18SBorislav Petkov goto out; 46121afaf18SBorislav Petkov 46221afaf18SBorislav Petkov if (!(low & MCI_CONFIG_MCAX)) 46321afaf18SBorislav Petkov goto out; 46421afaf18SBorislav Petkov 46521afaf18SBorislav Petkov if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && 46621afaf18SBorislav Petkov (low & MASK_BLKPTR_LO)) 46721afaf18SBorislav Petkov addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 46821afaf18SBorislav Petkov 46921afaf18SBorislav Petkov out: 47021afaf18SBorislav Petkov smca_bank_addrs[bank][block] = addr; 47121afaf18SBorislav Petkov return addr; 47221afaf18SBorislav Petkov } 47321afaf18SBorislav Petkov 47421afaf18SBorislav Petkov static u32 get_block_address(u32 current_addr, u32 low, u32 high, 47521afaf18SBorislav Petkov unsigned int bank, unsigned int block) 47621afaf18SBorislav Petkov { 47721afaf18SBorislav Petkov u32 addr = 0, offset = 0; 47821afaf18SBorislav Petkov 47921afaf18SBorislav Petkov if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) 48021afaf18SBorislav Petkov return addr; 48121afaf18SBorislav Petkov 48221afaf18SBorislav Petkov if (mce_flags.smca) 48321afaf18SBorislav Petkov return smca_get_block_address(bank, block); 48421afaf18SBorislav Petkov 48521afaf18SBorislav Petkov /* Fall back to method we used for older processors: */ 48621afaf18SBorislav Petkov switch (block) { 48721afaf18SBorislav Petkov case 0: 48821afaf18SBorislav Petkov addr = msr_ops.misc(bank); 48921afaf18SBorislav Petkov break; 49021afaf18SBorislav Petkov case 1: 49121afaf18SBorislav Petkov offset = ((low & MASK_BLKPTR_LO) >> 21); 49221afaf18SBorislav Petkov if (offset) 49321afaf18SBorislav Petkov addr = MCG_XBLK_ADDR + offset; 49421afaf18SBorislav Petkov break; 49521afaf18SBorislav Petkov default: 49621afaf18SBorislav Petkov addr = ++current_addr; 49721afaf18SBorislav Petkov } 49821afaf18SBorislav Petkov return addr; 49921afaf18SBorislav Petkov } 50021afaf18SBorislav Petkov 50121afaf18SBorislav Petkov static int 50221afaf18SBorislav Petkov prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 50321afaf18SBorislav Petkov int offset, u32 misc_high) 50421afaf18SBorislav Petkov { 50521afaf18SBorislav Petkov unsigned int cpu = smp_processor_id(); 50621afaf18SBorislav Petkov u32 smca_low, smca_high; 50721afaf18SBorislav Petkov struct threshold_block b; 50821afaf18SBorislav Petkov int new; 50921afaf18SBorislav Petkov 51021afaf18SBorislav Petkov if (!block) 51121afaf18SBorislav Petkov per_cpu(bank_map, cpu) |= (1 << bank); 51221afaf18SBorislav Petkov 51321afaf18SBorislav Petkov memset(&b, 0, sizeof(b)); 51421afaf18SBorislav Petkov b.cpu = cpu; 51521afaf18SBorislav Petkov b.bank = bank; 51621afaf18SBorislav Petkov b.block = block; 51721afaf18SBorislav Petkov b.address = addr; 51821afaf18SBorislav Petkov b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 51921afaf18SBorislav Petkov 52021afaf18SBorislav Petkov if (!b.interrupt_capable) 52121afaf18SBorislav Petkov goto done; 52221afaf18SBorislav Petkov 52321afaf18SBorislav Petkov b.interrupt_enable = 1; 52421afaf18SBorislav Petkov 52521afaf18SBorislav Petkov if (!mce_flags.smca) { 52621afaf18SBorislav Petkov new = (misc_high & MASK_LVTOFF_HI) >> 20; 52721afaf18SBorislav Petkov goto set_offset; 52821afaf18SBorislav Petkov } 52921afaf18SBorislav Petkov 53021afaf18SBorislav Petkov /* Gather LVT offset for thresholding: */ 53121afaf18SBorislav Petkov if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 53221afaf18SBorislav Petkov goto out; 53321afaf18SBorislav Petkov 53421afaf18SBorislav Petkov new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 53521afaf18SBorislav Petkov 53621afaf18SBorislav Petkov set_offset: 53721afaf18SBorislav Petkov offset = setup_APIC_mce_threshold(offset, new); 53821afaf18SBorislav Petkov if (offset == new) 53921afaf18SBorislav Petkov thresholding_irq_en = true; 54021afaf18SBorislav Petkov 54121afaf18SBorislav Petkov done: 54221afaf18SBorislav Petkov mce_threshold_block_init(&b, offset); 54321afaf18SBorislav Petkov 54421afaf18SBorislav Petkov out: 54521afaf18SBorislav Petkov return offset; 54621afaf18SBorislav Petkov } 54721afaf18SBorislav Petkov 54821afaf18SBorislav Petkov /* cpu init entry point, called from mce.c with preempt off */ 54921afaf18SBorislav Petkov void mce_amd_feature_init(struct cpuinfo_x86 *c) 55021afaf18SBorislav Petkov { 55121afaf18SBorislav Petkov u32 low = 0, high = 0, address = 0; 55221afaf18SBorislav Petkov unsigned int bank, block, cpu = smp_processor_id(); 55321afaf18SBorislav Petkov int offset = -1; 55421afaf18SBorislav Petkov 55521afaf18SBorislav Petkov for (bank = 0; bank < mca_cfg.banks; ++bank) { 55621afaf18SBorislav Petkov if (mce_flags.smca) 55721afaf18SBorislav Petkov smca_configure(bank, cpu); 55821afaf18SBorislav Petkov 55921afaf18SBorislav Petkov for (block = 0; block < NR_BLOCKS; ++block) { 56021afaf18SBorislav Petkov address = get_block_address(address, low, high, bank, block); 56121afaf18SBorislav Petkov if (!address) 56221afaf18SBorislav Petkov break; 56321afaf18SBorislav Petkov 56421afaf18SBorislav Petkov if (rdmsr_safe(address, &low, &high)) 56521afaf18SBorislav Petkov break; 56621afaf18SBorislav Petkov 56721afaf18SBorislav Petkov if (!(high & MASK_VALID_HI)) 56821afaf18SBorislav Petkov continue; 56921afaf18SBorislav Petkov 57021afaf18SBorislav Petkov if (!(high & MASK_CNTP_HI) || 57121afaf18SBorislav Petkov (high & MASK_LOCKED_HI)) 57221afaf18SBorislav Petkov continue; 57321afaf18SBorislav Petkov 57421afaf18SBorislav Petkov offset = prepare_threshold_block(bank, block, address, offset, high); 57521afaf18SBorislav Petkov } 57621afaf18SBorislav Petkov } 57721afaf18SBorislav Petkov 57821afaf18SBorislav Petkov if (mce_flags.succor) 57921afaf18SBorislav Petkov deferred_error_interrupt_enable(c); 58021afaf18SBorislav Petkov } 58121afaf18SBorislav Petkov 58221afaf18SBorislav Petkov int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) 58321afaf18SBorislav Petkov { 58421afaf18SBorislav Petkov u64 dram_base_addr, dram_limit_addr, dram_hole_base; 58521afaf18SBorislav Petkov /* We start from the normalized address */ 58621afaf18SBorislav Petkov u64 ret_addr = norm_addr; 58721afaf18SBorislav Petkov 58821afaf18SBorislav Petkov u32 tmp; 58921afaf18SBorislav Petkov 59021afaf18SBorislav Petkov u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; 59121afaf18SBorislav Petkov u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; 59221afaf18SBorislav Petkov u8 intlv_addr_sel, intlv_addr_bit; 59321afaf18SBorislav Petkov u8 num_intlv_bits, hashed_bit; 59421afaf18SBorislav Petkov u8 lgcy_mmio_hole_en, base = 0; 59521afaf18SBorislav Petkov u8 cs_mask, cs_id = 0; 59621afaf18SBorislav Petkov bool hash_enabled = false; 59721afaf18SBorislav Petkov 59821afaf18SBorislav Petkov /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ 59921afaf18SBorislav Petkov if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) 60021afaf18SBorislav Petkov goto out_err; 60121afaf18SBorislav Petkov 60221afaf18SBorislav Petkov /* Remove HiAddrOffset from normalized address, if enabled: */ 60321afaf18SBorislav Petkov if (tmp & BIT(0)) { 60421afaf18SBorislav Petkov u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; 60521afaf18SBorislav Petkov 60621afaf18SBorislav Petkov if (norm_addr >= hi_addr_offset) { 60721afaf18SBorislav Petkov ret_addr -= hi_addr_offset; 60821afaf18SBorislav Petkov base = 1; 60921afaf18SBorislav Petkov } 61021afaf18SBorislav Petkov } 61121afaf18SBorislav Petkov 61221afaf18SBorislav Petkov /* Read D18F0x110 (DramBaseAddress). */ 61321afaf18SBorislav Petkov if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) 61421afaf18SBorislav Petkov goto out_err; 61521afaf18SBorislav Petkov 61621afaf18SBorislav Petkov /* Check if address range is valid. */ 61721afaf18SBorislav Petkov if (!(tmp & BIT(0))) { 61821afaf18SBorislav Petkov pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", 61921afaf18SBorislav Petkov __func__, tmp); 62021afaf18SBorislav Petkov goto out_err; 62121afaf18SBorislav Petkov } 62221afaf18SBorislav Petkov 62321afaf18SBorislav Petkov lgcy_mmio_hole_en = tmp & BIT(1); 62421afaf18SBorislav Petkov intlv_num_chan = (tmp >> 4) & 0xF; 62521afaf18SBorislav Petkov intlv_addr_sel = (tmp >> 8) & 0x7; 62621afaf18SBorislav Petkov dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; 62721afaf18SBorislav Petkov 62821afaf18SBorislav Petkov /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ 62921afaf18SBorislav Petkov if (intlv_addr_sel > 3) { 63021afaf18SBorislav Petkov pr_err("%s: Invalid interleave address select %d.\n", 63121afaf18SBorislav Petkov __func__, intlv_addr_sel); 63221afaf18SBorislav Petkov goto out_err; 63321afaf18SBorislav Petkov } 63421afaf18SBorislav Petkov 63521afaf18SBorislav Petkov /* Read D18F0x114 (DramLimitAddress). */ 63621afaf18SBorislav Petkov if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) 63721afaf18SBorislav Petkov goto out_err; 63821afaf18SBorislav Petkov 63921afaf18SBorislav Petkov intlv_num_sockets = (tmp >> 8) & 0x1; 64021afaf18SBorislav Petkov intlv_num_dies = (tmp >> 10) & 0x3; 64121afaf18SBorislav Petkov dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); 64221afaf18SBorislav Petkov 64321afaf18SBorislav Petkov intlv_addr_bit = intlv_addr_sel + 8; 64421afaf18SBorislav Petkov 64521afaf18SBorislav Petkov /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ 64621afaf18SBorislav Petkov switch (intlv_num_chan) { 64721afaf18SBorislav Petkov case 0: intlv_num_chan = 0; break; 64821afaf18SBorislav Petkov case 1: intlv_num_chan = 1; break; 64921afaf18SBorislav Petkov case 3: intlv_num_chan = 2; break; 65021afaf18SBorislav Petkov case 5: intlv_num_chan = 3; break; 65121afaf18SBorislav Petkov case 7: intlv_num_chan = 4; break; 65221afaf18SBorislav Petkov 65321afaf18SBorislav Petkov case 8: intlv_num_chan = 1; 65421afaf18SBorislav Petkov hash_enabled = true; 65521afaf18SBorislav Petkov break; 65621afaf18SBorislav Petkov default: 65721afaf18SBorislav Petkov pr_err("%s: Invalid number of interleaved channels %d.\n", 65821afaf18SBorislav Petkov __func__, intlv_num_chan); 65921afaf18SBorislav Petkov goto out_err; 66021afaf18SBorislav Petkov } 66121afaf18SBorislav Petkov 66221afaf18SBorislav Petkov num_intlv_bits = intlv_num_chan; 66321afaf18SBorislav Petkov 66421afaf18SBorislav Petkov if (intlv_num_dies > 2) { 66521afaf18SBorislav Petkov pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", 66621afaf18SBorislav Petkov __func__, intlv_num_dies); 66721afaf18SBorislav Petkov goto out_err; 66821afaf18SBorislav Petkov } 66921afaf18SBorislav Petkov 67021afaf18SBorislav Petkov num_intlv_bits += intlv_num_dies; 67121afaf18SBorislav Petkov 67221afaf18SBorislav Petkov /* Add a bit if sockets are interleaved. */ 67321afaf18SBorislav Petkov num_intlv_bits += intlv_num_sockets; 67421afaf18SBorislav Petkov 67521afaf18SBorislav Petkov /* Assert num_intlv_bits <= 4 */ 67621afaf18SBorislav Petkov if (num_intlv_bits > 4) { 67721afaf18SBorislav Petkov pr_err("%s: Invalid interleave bits %d.\n", 67821afaf18SBorislav Petkov __func__, num_intlv_bits); 67921afaf18SBorislav Petkov goto out_err; 68021afaf18SBorislav Petkov } 68121afaf18SBorislav Petkov 68221afaf18SBorislav Petkov if (num_intlv_bits > 0) { 68321afaf18SBorislav Petkov u64 temp_addr_x, temp_addr_i, temp_addr_y; 68421afaf18SBorislav Petkov u8 die_id_bit, sock_id_bit, cs_fabric_id; 68521afaf18SBorislav Petkov 68621afaf18SBorislav Petkov /* 68721afaf18SBorislav Petkov * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. 68821afaf18SBorislav Petkov * This is the fabric id for this coherent slave. Use 68921afaf18SBorislav Petkov * umc/channel# as instance id of the coherent slave 69021afaf18SBorislav Petkov * for FICAA. 69121afaf18SBorislav Petkov */ 69221afaf18SBorislav Petkov if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) 69321afaf18SBorislav Petkov goto out_err; 69421afaf18SBorislav Petkov 69521afaf18SBorislav Petkov cs_fabric_id = (tmp >> 8) & 0xFF; 69621afaf18SBorislav Petkov die_id_bit = 0; 69721afaf18SBorislav Petkov 69821afaf18SBorislav Petkov /* If interleaved over more than 1 channel: */ 69921afaf18SBorislav Petkov if (intlv_num_chan) { 70021afaf18SBorislav Petkov die_id_bit = intlv_num_chan; 70121afaf18SBorislav Petkov cs_mask = (1 << die_id_bit) - 1; 70221afaf18SBorislav Petkov cs_id = cs_fabric_id & cs_mask; 70321afaf18SBorislav Petkov } 70421afaf18SBorislav Petkov 70521afaf18SBorislav Petkov sock_id_bit = die_id_bit; 70621afaf18SBorislav Petkov 70721afaf18SBorislav Petkov /* Read D18F1x208 (SystemFabricIdMask). */ 70821afaf18SBorislav Petkov if (intlv_num_dies || intlv_num_sockets) 70921afaf18SBorislav Petkov if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) 71021afaf18SBorislav Petkov goto out_err; 71121afaf18SBorislav Petkov 71221afaf18SBorislav Petkov /* If interleaved over more than 1 die. */ 71321afaf18SBorislav Petkov if (intlv_num_dies) { 71421afaf18SBorislav Petkov sock_id_bit = die_id_bit + intlv_num_dies; 71521afaf18SBorislav Petkov die_id_shift = (tmp >> 24) & 0xF; 71621afaf18SBorislav Petkov die_id_mask = (tmp >> 8) & 0xFF; 71721afaf18SBorislav Petkov 71821afaf18SBorislav Petkov cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; 71921afaf18SBorislav Petkov } 72021afaf18SBorislav Petkov 72121afaf18SBorislav Petkov /* If interleaved over more than 1 socket. */ 72221afaf18SBorislav Petkov if (intlv_num_sockets) { 72321afaf18SBorislav Petkov socket_id_shift = (tmp >> 28) & 0xF; 72421afaf18SBorislav Petkov socket_id_mask = (tmp >> 16) & 0xFF; 72521afaf18SBorislav Petkov 72621afaf18SBorislav Petkov cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; 72721afaf18SBorislav Petkov } 72821afaf18SBorislav Petkov 72921afaf18SBorislav Petkov /* 73021afaf18SBorislav Petkov * The pre-interleaved address consists of XXXXXXIIIYYYYY 73121afaf18SBorislav Petkov * where III is the ID for this CS, and XXXXXXYYYYY are the 73221afaf18SBorislav Petkov * address bits from the post-interleaved address. 73321afaf18SBorislav Petkov * "num_intlv_bits" has been calculated to tell us how many "I" 73421afaf18SBorislav Petkov * bits there are. "intlv_addr_bit" tells us how many "Y" bits 73521afaf18SBorislav Petkov * there are (where "I" starts). 73621afaf18SBorislav Petkov */ 73721afaf18SBorislav Petkov temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); 73821afaf18SBorislav Petkov temp_addr_i = (cs_id << intlv_addr_bit); 73921afaf18SBorislav Petkov temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; 74021afaf18SBorislav Petkov ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; 74121afaf18SBorislav Petkov } 74221afaf18SBorislav Petkov 74321afaf18SBorislav Petkov /* Add dram base address */ 74421afaf18SBorislav Petkov ret_addr += dram_base_addr; 74521afaf18SBorislav Petkov 74621afaf18SBorislav Petkov /* If legacy MMIO hole enabled */ 74721afaf18SBorislav Petkov if (lgcy_mmio_hole_en) { 74821afaf18SBorislav Petkov if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) 74921afaf18SBorislav Petkov goto out_err; 75021afaf18SBorislav Petkov 75121afaf18SBorislav Petkov dram_hole_base = tmp & GENMASK(31, 24); 75221afaf18SBorislav Petkov if (ret_addr >= dram_hole_base) 75321afaf18SBorislav Petkov ret_addr += (BIT_ULL(32) - dram_hole_base); 75421afaf18SBorislav Petkov } 75521afaf18SBorislav Petkov 75621afaf18SBorislav Petkov if (hash_enabled) { 75721afaf18SBorislav Petkov /* Save some parentheses and grab ls-bit at the end. */ 75821afaf18SBorislav Petkov hashed_bit = (ret_addr >> 12) ^ 75921afaf18SBorislav Petkov (ret_addr >> 18) ^ 76021afaf18SBorislav Petkov (ret_addr >> 21) ^ 76121afaf18SBorislav Petkov (ret_addr >> 30) ^ 76221afaf18SBorislav Petkov cs_id; 76321afaf18SBorislav Petkov 76421afaf18SBorislav Petkov hashed_bit &= BIT(0); 76521afaf18SBorislav Petkov 76621afaf18SBorislav Petkov if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) 76721afaf18SBorislav Petkov ret_addr ^= BIT(intlv_addr_bit); 76821afaf18SBorislav Petkov } 76921afaf18SBorislav Petkov 77021afaf18SBorislav Petkov /* Is calculated system address is above DRAM limit address? */ 77121afaf18SBorislav Petkov if (ret_addr > dram_limit_addr) 77221afaf18SBorislav Petkov goto out_err; 77321afaf18SBorislav Petkov 77421afaf18SBorislav Petkov *sys_addr = ret_addr; 77521afaf18SBorislav Petkov return 0; 77621afaf18SBorislav Petkov 77721afaf18SBorislav Petkov out_err: 77821afaf18SBorislav Petkov return -EINVAL; 77921afaf18SBorislav Petkov } 78021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); 78121afaf18SBorislav Petkov 78221afaf18SBorislav Petkov bool amd_mce_is_memory_error(struct mce *m) 78321afaf18SBorislav Petkov { 78421afaf18SBorislav Petkov /* ErrCodeExt[20:16] */ 78521afaf18SBorislav Petkov u8 xec = (m->status >> 16) & 0x1f; 78621afaf18SBorislav Petkov 78721afaf18SBorislav Petkov if (mce_flags.smca) 78821afaf18SBorislav Petkov return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; 78921afaf18SBorislav Petkov 79021afaf18SBorislav Petkov return m->bank == 4 && xec == 0x8; 79121afaf18SBorislav Petkov } 79221afaf18SBorislav Petkov 79321afaf18SBorislav Petkov static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 79421afaf18SBorislav Petkov { 79521afaf18SBorislav Petkov struct mce m; 79621afaf18SBorislav Petkov 79721afaf18SBorislav Petkov mce_setup(&m); 79821afaf18SBorislav Petkov 79921afaf18SBorislav Petkov m.status = status; 80021afaf18SBorislav Petkov m.misc = misc; 80121afaf18SBorislav Petkov m.bank = bank; 80221afaf18SBorislav Petkov m.tsc = rdtsc(); 80321afaf18SBorislav Petkov 80421afaf18SBorislav Petkov if (m.status & MCI_STATUS_ADDRV) { 80521afaf18SBorislav Petkov m.addr = addr; 80621afaf18SBorislav Petkov 80721afaf18SBorislav Petkov /* 80821afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 80921afaf18SBorislav Petkov * *valid* bit of the address bits. 81021afaf18SBorislav Petkov */ 81121afaf18SBorislav Petkov if (mce_flags.smca) { 81221afaf18SBorislav Petkov u8 lsb = (m.addr >> 56) & 0x3f; 81321afaf18SBorislav Petkov 81421afaf18SBorislav Petkov m.addr &= GENMASK_ULL(55, lsb); 81521afaf18SBorislav Petkov } 81621afaf18SBorislav Petkov } 81721afaf18SBorislav Petkov 81821afaf18SBorislav Petkov if (mce_flags.smca) { 81921afaf18SBorislav Petkov rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 82021afaf18SBorislav Petkov 82121afaf18SBorislav Petkov if (m.status & MCI_STATUS_SYNDV) 82221afaf18SBorislav Petkov rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 82321afaf18SBorislav Petkov } 82421afaf18SBorislav Petkov 82521afaf18SBorislav Petkov mce_log(&m); 82621afaf18SBorislav Petkov } 82721afaf18SBorislav Petkov 828312a4661SLinus Torvalds asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(struct pt_regs *regs) 82921afaf18SBorislav Petkov { 83021afaf18SBorislav Petkov entering_irq(); 83121afaf18SBorislav Petkov trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 83221afaf18SBorislav Petkov inc_irq_stat(irq_deferred_error_count); 83321afaf18SBorislav Petkov deferred_error_int_vector(); 83421afaf18SBorislav Petkov trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 83521afaf18SBorislav Petkov exiting_ack_irq(); 83621afaf18SBorislav Petkov } 83721afaf18SBorislav Petkov 83821afaf18SBorislav Petkov /* 83921afaf18SBorislav Petkov * Returns true if the logged error is deferred. False, otherwise. 84021afaf18SBorislav Petkov */ 84121afaf18SBorislav Petkov static inline bool 84221afaf18SBorislav Petkov _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 84321afaf18SBorislav Petkov { 84421afaf18SBorislav Petkov u64 status, addr = 0; 84521afaf18SBorislav Petkov 84621afaf18SBorislav Petkov rdmsrl(msr_stat, status); 84721afaf18SBorislav Petkov if (!(status & MCI_STATUS_VAL)) 84821afaf18SBorislav Petkov return false; 84921afaf18SBorislav Petkov 85021afaf18SBorislav Petkov if (status & MCI_STATUS_ADDRV) 85121afaf18SBorislav Petkov rdmsrl(msr_addr, addr); 85221afaf18SBorislav Petkov 85321afaf18SBorislav Petkov __log_error(bank, status, addr, misc); 85421afaf18SBorislav Petkov 85521afaf18SBorislav Petkov wrmsrl(msr_stat, 0); 85621afaf18SBorislav Petkov 85721afaf18SBorislav Petkov return status & MCI_STATUS_DEFERRED; 85821afaf18SBorislav Petkov } 85921afaf18SBorislav Petkov 86021afaf18SBorislav Petkov /* 86121afaf18SBorislav Petkov * We have three scenarios for checking for Deferred errors: 86221afaf18SBorislav Petkov * 86321afaf18SBorislav Petkov * 1) Non-SMCA systems check MCA_STATUS and log error if found. 86421afaf18SBorislav Petkov * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 86521afaf18SBorislav Petkov * clear MCA_DESTAT. 86621afaf18SBorislav Petkov * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 86721afaf18SBorislav Petkov * log it. 86821afaf18SBorislav Petkov */ 86921afaf18SBorislav Petkov static void log_error_deferred(unsigned int bank) 87021afaf18SBorislav Petkov { 87121afaf18SBorislav Petkov bool defrd; 87221afaf18SBorislav Petkov 87321afaf18SBorislav Petkov defrd = _log_error_bank(bank, msr_ops.status(bank), 87421afaf18SBorislav Petkov msr_ops.addr(bank), 0); 87521afaf18SBorislav Petkov 87621afaf18SBorislav Petkov if (!mce_flags.smca) 87721afaf18SBorislav Petkov return; 87821afaf18SBorislav Petkov 87921afaf18SBorislav Petkov /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 88021afaf18SBorislav Petkov if (defrd) { 88121afaf18SBorislav Petkov wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 88221afaf18SBorislav Petkov return; 88321afaf18SBorislav Petkov } 88421afaf18SBorislav Petkov 88521afaf18SBorislav Petkov /* 88621afaf18SBorislav Petkov * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 88721afaf18SBorislav Petkov * for a valid error. 88821afaf18SBorislav Petkov */ 88921afaf18SBorislav Petkov _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 89021afaf18SBorislav Petkov MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 89121afaf18SBorislav Petkov } 89221afaf18SBorislav Petkov 89321afaf18SBorislav Petkov /* APIC interrupt handler for deferred errors */ 89421afaf18SBorislav Petkov static void amd_deferred_error_interrupt(void) 89521afaf18SBorislav Petkov { 89621afaf18SBorislav Petkov unsigned int bank; 89721afaf18SBorislav Petkov 89821afaf18SBorislav Petkov for (bank = 0; bank < mca_cfg.banks; ++bank) 89921afaf18SBorislav Petkov log_error_deferred(bank); 90021afaf18SBorislav Petkov } 90121afaf18SBorislav Petkov 90221afaf18SBorislav Petkov static void log_error_thresholding(unsigned int bank, u64 misc) 90321afaf18SBorislav Petkov { 90421afaf18SBorislav Petkov _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); 90521afaf18SBorislav Petkov } 90621afaf18SBorislav Petkov 90721afaf18SBorislav Petkov static void log_and_reset_block(struct threshold_block *block) 90821afaf18SBorislav Petkov { 90921afaf18SBorislav Petkov struct thresh_restart tr; 91021afaf18SBorislav Petkov u32 low = 0, high = 0; 91121afaf18SBorislav Petkov 91221afaf18SBorislav Petkov if (!block) 91321afaf18SBorislav Petkov return; 91421afaf18SBorislav Petkov 91521afaf18SBorislav Petkov if (rdmsr_safe(block->address, &low, &high)) 91621afaf18SBorislav Petkov return; 91721afaf18SBorislav Petkov 91821afaf18SBorislav Petkov if (!(high & MASK_OVERFLOW_HI)) 91921afaf18SBorislav Petkov return; 92021afaf18SBorislav Petkov 92121afaf18SBorislav Petkov /* Log the MCE which caused the threshold event. */ 92221afaf18SBorislav Petkov log_error_thresholding(block->bank, ((u64)high << 32) | low); 92321afaf18SBorislav Petkov 92421afaf18SBorislav Petkov /* Reset threshold block after logging error. */ 92521afaf18SBorislav Petkov memset(&tr, 0, sizeof(tr)); 92621afaf18SBorislav Petkov tr.b = block; 92721afaf18SBorislav Petkov threshold_restart_bank(&tr); 92821afaf18SBorislav Petkov } 92921afaf18SBorislav Petkov 93021afaf18SBorislav Petkov /* 93121afaf18SBorislav Petkov * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 93221afaf18SBorislav Petkov * goes off when error_count reaches threshold_limit. 93321afaf18SBorislav Petkov */ 93421afaf18SBorislav Petkov static void amd_threshold_interrupt(void) 93521afaf18SBorislav Petkov { 93621afaf18SBorislav Petkov struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 93721afaf18SBorislav Petkov unsigned int bank, cpu = smp_processor_id(); 93821afaf18SBorislav Petkov 93921afaf18SBorislav Petkov for (bank = 0; bank < mca_cfg.banks; ++bank) { 94021afaf18SBorislav Petkov if (!(per_cpu(bank_map, cpu) & (1 << bank))) 94121afaf18SBorislav Petkov continue; 94221afaf18SBorislav Petkov 94321afaf18SBorislav Petkov first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; 94421afaf18SBorislav Petkov if (!first_block) 94521afaf18SBorislav Petkov continue; 94621afaf18SBorislav Petkov 94721afaf18SBorislav Petkov /* 94821afaf18SBorislav Petkov * The first block is also the head of the list. Check it first 94921afaf18SBorislav Petkov * before iterating over the rest. 95021afaf18SBorislav Petkov */ 95121afaf18SBorislav Petkov log_and_reset_block(first_block); 95221afaf18SBorislav Petkov list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 95321afaf18SBorislav Petkov log_and_reset_block(block); 95421afaf18SBorislav Petkov } 95521afaf18SBorislav Petkov } 95621afaf18SBorislav Petkov 95721afaf18SBorislav Petkov /* 95821afaf18SBorislav Petkov * Sysfs Interface 95921afaf18SBorislav Petkov */ 96021afaf18SBorislav Petkov 96121afaf18SBorislav Petkov struct threshold_attr { 96221afaf18SBorislav Petkov struct attribute attr; 96321afaf18SBorislav Petkov ssize_t (*show) (struct threshold_block *, char *); 96421afaf18SBorislav Petkov ssize_t (*store) (struct threshold_block *, const char *, size_t count); 96521afaf18SBorislav Petkov }; 96621afaf18SBorislav Petkov 96721afaf18SBorislav Petkov #define SHOW_FIELDS(name) \ 96821afaf18SBorislav Petkov static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 96921afaf18SBorislav Petkov { \ 97021afaf18SBorislav Petkov return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 97121afaf18SBorislav Petkov } 97221afaf18SBorislav Petkov SHOW_FIELDS(interrupt_enable) 97321afaf18SBorislav Petkov SHOW_FIELDS(threshold_limit) 97421afaf18SBorislav Petkov 97521afaf18SBorislav Petkov static ssize_t 97621afaf18SBorislav Petkov store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 97721afaf18SBorislav Petkov { 97821afaf18SBorislav Petkov struct thresh_restart tr; 97921afaf18SBorislav Petkov unsigned long new; 98021afaf18SBorislav Petkov 98121afaf18SBorislav Petkov if (!b->interrupt_capable) 98221afaf18SBorislav Petkov return -EINVAL; 98321afaf18SBorislav Petkov 98421afaf18SBorislav Petkov if (kstrtoul(buf, 0, &new) < 0) 98521afaf18SBorislav Petkov return -EINVAL; 98621afaf18SBorislav Petkov 98721afaf18SBorislav Petkov b->interrupt_enable = !!new; 98821afaf18SBorislav Petkov 98921afaf18SBorislav Petkov memset(&tr, 0, sizeof(tr)); 99021afaf18SBorislav Petkov tr.b = b; 99121afaf18SBorislav Petkov 99221afaf18SBorislav Petkov smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); 99321afaf18SBorislav Petkov 99421afaf18SBorislav Petkov return size; 99521afaf18SBorislav Petkov } 99621afaf18SBorislav Petkov 99721afaf18SBorislav Petkov static ssize_t 99821afaf18SBorislav Petkov store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 99921afaf18SBorislav Petkov { 100021afaf18SBorislav Petkov struct thresh_restart tr; 100121afaf18SBorislav Petkov unsigned long new; 100221afaf18SBorislav Petkov 100321afaf18SBorislav Petkov if (kstrtoul(buf, 0, &new) < 0) 100421afaf18SBorislav Petkov return -EINVAL; 100521afaf18SBorislav Petkov 100621afaf18SBorislav Petkov if (new > THRESHOLD_MAX) 100721afaf18SBorislav Petkov new = THRESHOLD_MAX; 100821afaf18SBorislav Petkov if (new < 1) 100921afaf18SBorislav Petkov new = 1; 101021afaf18SBorislav Petkov 101121afaf18SBorislav Petkov memset(&tr, 0, sizeof(tr)); 101221afaf18SBorislav Petkov tr.old_limit = b->threshold_limit; 101321afaf18SBorislav Petkov b->threshold_limit = new; 101421afaf18SBorislav Petkov tr.b = b; 101521afaf18SBorislav Petkov 101621afaf18SBorislav Petkov smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); 101721afaf18SBorislav Petkov 101821afaf18SBorislav Petkov return size; 101921afaf18SBorislav Petkov } 102021afaf18SBorislav Petkov 102121afaf18SBorislav Petkov static ssize_t show_error_count(struct threshold_block *b, char *buf) 102221afaf18SBorislav Petkov { 102321afaf18SBorislav Petkov u32 lo, hi; 102421afaf18SBorislav Petkov 102521afaf18SBorislav Petkov rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); 102621afaf18SBorislav Petkov 102721afaf18SBorislav Petkov return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 102821afaf18SBorislav Petkov (THRESHOLD_MAX - b->threshold_limit))); 102921afaf18SBorislav Petkov } 103021afaf18SBorislav Petkov 103121afaf18SBorislav Petkov static struct threshold_attr error_count = { 103221afaf18SBorislav Petkov .attr = {.name = __stringify(error_count), .mode = 0444 }, 103321afaf18SBorislav Petkov .show = show_error_count, 103421afaf18SBorislav Petkov }; 103521afaf18SBorislav Petkov 103621afaf18SBorislav Petkov #define RW_ATTR(val) \ 103721afaf18SBorislav Petkov static struct threshold_attr val = { \ 103821afaf18SBorislav Petkov .attr = {.name = __stringify(val), .mode = 0644 }, \ 103921afaf18SBorislav Petkov .show = show_## val, \ 104021afaf18SBorislav Petkov .store = store_## val, \ 104121afaf18SBorislav Petkov }; 104221afaf18SBorislav Petkov 104321afaf18SBorislav Petkov RW_ATTR(interrupt_enable); 104421afaf18SBorislav Petkov RW_ATTR(threshold_limit); 104521afaf18SBorislav Petkov 104621afaf18SBorislav Petkov static struct attribute *default_attrs[] = { 104721afaf18SBorislav Petkov &threshold_limit.attr, 104821afaf18SBorislav Petkov &error_count.attr, 104921afaf18SBorislav Petkov NULL, /* possibly interrupt_enable if supported, see below */ 105021afaf18SBorislav Petkov NULL, 105121afaf18SBorislav Petkov }; 105221afaf18SBorislav Petkov 105321afaf18SBorislav Petkov #define to_block(k) container_of(k, struct threshold_block, kobj) 105421afaf18SBorislav Petkov #define to_attr(a) container_of(a, struct threshold_attr, attr) 105521afaf18SBorislav Petkov 105621afaf18SBorislav Petkov static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 105721afaf18SBorislav Petkov { 105821afaf18SBorislav Petkov struct threshold_block *b = to_block(kobj); 105921afaf18SBorislav Petkov struct threshold_attr *a = to_attr(attr); 106021afaf18SBorislav Petkov ssize_t ret; 106121afaf18SBorislav Petkov 106221afaf18SBorislav Petkov ret = a->show ? a->show(b, buf) : -EIO; 106321afaf18SBorislav Petkov 106421afaf18SBorislav Petkov return ret; 106521afaf18SBorislav Petkov } 106621afaf18SBorislav Petkov 106721afaf18SBorislav Petkov static ssize_t store(struct kobject *kobj, struct attribute *attr, 106821afaf18SBorislav Petkov const char *buf, size_t count) 106921afaf18SBorislav Petkov { 107021afaf18SBorislav Petkov struct threshold_block *b = to_block(kobj); 107121afaf18SBorislav Petkov struct threshold_attr *a = to_attr(attr); 107221afaf18SBorislav Petkov ssize_t ret; 107321afaf18SBorislav Petkov 107421afaf18SBorislav Petkov ret = a->store ? a->store(b, buf, count) : -EIO; 107521afaf18SBorislav Petkov 107621afaf18SBorislav Petkov return ret; 107721afaf18SBorislav Petkov } 107821afaf18SBorislav Petkov 107921afaf18SBorislav Petkov static const struct sysfs_ops threshold_ops = { 108021afaf18SBorislav Petkov .show = show, 108121afaf18SBorislav Petkov .store = store, 108221afaf18SBorislav Petkov }; 108321afaf18SBorislav Petkov 108421afaf18SBorislav Petkov static struct kobj_type threshold_ktype = { 108521afaf18SBorislav Petkov .sysfs_ops = &threshold_ops, 108621afaf18SBorislav Petkov .default_attrs = default_attrs, 108721afaf18SBorislav Petkov }; 108821afaf18SBorislav Petkov 108921afaf18SBorislav Petkov static const char *get_name(unsigned int bank, struct threshold_block *b) 109021afaf18SBorislav Petkov { 109121afaf18SBorislav Petkov enum smca_bank_types bank_type; 109221afaf18SBorislav Petkov 109321afaf18SBorislav Petkov if (!mce_flags.smca) { 109421afaf18SBorislav Petkov if (b && bank == 4) 109521afaf18SBorislav Petkov return bank4_names(b); 109621afaf18SBorislav Petkov 109721afaf18SBorislav Petkov return th_names[bank]; 109821afaf18SBorislav Petkov } 109921afaf18SBorislav Petkov 110021afaf18SBorislav Petkov bank_type = smca_get_bank_type(bank); 110121afaf18SBorislav Petkov if (bank_type >= N_SMCA_BANK_TYPES) 110221afaf18SBorislav Petkov return NULL; 110321afaf18SBorislav Petkov 110421afaf18SBorislav Petkov if (b && bank_type == SMCA_UMC) { 110521afaf18SBorislav Petkov if (b->block < ARRAY_SIZE(smca_umc_block_names)) 110621afaf18SBorislav Petkov return smca_umc_block_names[b->block]; 110721afaf18SBorislav Petkov return NULL; 110821afaf18SBorislav Petkov } 110921afaf18SBorislav Petkov 111021afaf18SBorislav Petkov if (smca_banks[bank].hwid->count == 1) 111121afaf18SBorislav Petkov return smca_get_name(bank_type); 111221afaf18SBorislav Petkov 111321afaf18SBorislav Petkov snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 111421afaf18SBorislav Petkov "%s_%x", smca_get_name(bank_type), 111521afaf18SBorislav Petkov smca_banks[bank].sysfs_id); 111621afaf18SBorislav Petkov return buf_mcatype; 111721afaf18SBorislav Petkov } 111821afaf18SBorislav Petkov 111921afaf18SBorislav Petkov static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, 112021afaf18SBorislav Petkov unsigned int block, u32 address) 112121afaf18SBorislav Petkov { 112221afaf18SBorislav Petkov struct threshold_block *b = NULL; 112321afaf18SBorislav Petkov u32 low, high; 112421afaf18SBorislav Petkov int err; 112521afaf18SBorislav Petkov 112621afaf18SBorislav Petkov if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) 112721afaf18SBorislav Petkov return 0; 112821afaf18SBorislav Petkov 112921afaf18SBorislav Petkov if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) 113021afaf18SBorislav Petkov return 0; 113121afaf18SBorislav Petkov 113221afaf18SBorislav Petkov if (!(high & MASK_VALID_HI)) { 113321afaf18SBorislav Petkov if (block) 113421afaf18SBorislav Petkov goto recurse; 113521afaf18SBorislav Petkov else 113621afaf18SBorislav Petkov return 0; 113721afaf18SBorislav Petkov } 113821afaf18SBorislav Petkov 113921afaf18SBorislav Petkov if (!(high & MASK_CNTP_HI) || 114021afaf18SBorislav Petkov (high & MASK_LOCKED_HI)) 114121afaf18SBorislav Petkov goto recurse; 114221afaf18SBorislav Petkov 114321afaf18SBorislav Petkov b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 114421afaf18SBorislav Petkov if (!b) 114521afaf18SBorislav Petkov return -ENOMEM; 114621afaf18SBorislav Petkov 114721afaf18SBorislav Petkov b->block = block; 114821afaf18SBorislav Petkov b->bank = bank; 114921afaf18SBorislav Petkov b->cpu = cpu; 115021afaf18SBorislav Petkov b->address = address; 115121afaf18SBorislav Petkov b->interrupt_enable = 0; 115221afaf18SBorislav Petkov b->interrupt_capable = lvt_interrupt_supported(bank, high); 115321afaf18SBorislav Petkov b->threshold_limit = THRESHOLD_MAX; 115421afaf18SBorislav Petkov 115521afaf18SBorislav Petkov if (b->interrupt_capable) { 115621afaf18SBorislav Petkov threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 115721afaf18SBorislav Petkov b->interrupt_enable = 1; 115821afaf18SBorislav Petkov } else { 115921afaf18SBorislav Petkov threshold_ktype.default_attrs[2] = NULL; 116021afaf18SBorislav Petkov } 116121afaf18SBorislav Petkov 116221afaf18SBorislav Petkov INIT_LIST_HEAD(&b->miscj); 116321afaf18SBorislav Petkov 116421afaf18SBorislav Petkov if (per_cpu(threshold_banks, cpu)[bank]->blocks) { 116521afaf18SBorislav Petkov list_add(&b->miscj, 116621afaf18SBorislav Petkov &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); 116721afaf18SBorislav Petkov } else { 116821afaf18SBorislav Petkov per_cpu(threshold_banks, cpu)[bank]->blocks = b; 116921afaf18SBorislav Petkov } 117021afaf18SBorislav Petkov 117121afaf18SBorislav Petkov err = kobject_init_and_add(&b->kobj, &threshold_ktype, 117221afaf18SBorislav Petkov per_cpu(threshold_banks, cpu)[bank]->kobj, 117321afaf18SBorislav Petkov get_name(bank, b)); 117421afaf18SBorislav Petkov if (err) 117521afaf18SBorislav Petkov goto out_free; 117621afaf18SBorislav Petkov recurse: 117721afaf18SBorislav Petkov address = get_block_address(address, low, high, bank, ++block); 117821afaf18SBorislav Petkov if (!address) 117921afaf18SBorislav Petkov return 0; 118021afaf18SBorislav Petkov 118121afaf18SBorislav Petkov err = allocate_threshold_blocks(cpu, bank, block, address); 118221afaf18SBorislav Petkov if (err) 118321afaf18SBorislav Petkov goto out_free; 118421afaf18SBorislav Petkov 118521afaf18SBorislav Petkov if (b) 118621afaf18SBorislav Petkov kobject_uevent(&b->kobj, KOBJ_ADD); 118721afaf18SBorislav Petkov 118821afaf18SBorislav Petkov return err; 118921afaf18SBorislav Petkov 119021afaf18SBorislav Petkov out_free: 119121afaf18SBorislav Petkov if (b) { 119221afaf18SBorislav Petkov kobject_put(&b->kobj); 119321afaf18SBorislav Petkov list_del(&b->miscj); 119421afaf18SBorislav Petkov kfree(b); 119521afaf18SBorislav Petkov } 119621afaf18SBorislav Petkov return err; 119721afaf18SBorislav Petkov } 119821afaf18SBorislav Petkov 119921afaf18SBorislav Petkov static int __threshold_add_blocks(struct threshold_bank *b) 120021afaf18SBorislav Petkov { 120121afaf18SBorislav Petkov struct list_head *head = &b->blocks->miscj; 120221afaf18SBorislav Petkov struct threshold_block *pos = NULL; 120321afaf18SBorislav Petkov struct threshold_block *tmp = NULL; 120421afaf18SBorislav Petkov int err = 0; 120521afaf18SBorislav Petkov 120621afaf18SBorislav Petkov err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 120721afaf18SBorislav Petkov if (err) 120821afaf18SBorislav Petkov return err; 120921afaf18SBorislav Petkov 121021afaf18SBorislav Petkov list_for_each_entry_safe(pos, tmp, head, miscj) { 121121afaf18SBorislav Petkov 121221afaf18SBorislav Petkov err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 121321afaf18SBorislav Petkov if (err) { 121421afaf18SBorislav Petkov list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 121521afaf18SBorislav Petkov kobject_del(&pos->kobj); 121621afaf18SBorislav Petkov 121721afaf18SBorislav Petkov return err; 121821afaf18SBorislav Petkov } 121921afaf18SBorislav Petkov } 122021afaf18SBorislav Petkov return err; 122121afaf18SBorislav Petkov } 122221afaf18SBorislav Petkov 122321afaf18SBorislav Petkov static int threshold_create_bank(unsigned int cpu, unsigned int bank) 122421afaf18SBorislav Petkov { 122521afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 122621afaf18SBorislav Petkov struct amd_northbridge *nb = NULL; 122721afaf18SBorislav Petkov struct threshold_bank *b = NULL; 122821afaf18SBorislav Petkov const char *name = get_name(bank, NULL); 122921afaf18SBorislav Petkov int err = 0; 123021afaf18SBorislav Petkov 123121afaf18SBorislav Petkov if (!dev) 123221afaf18SBorislav Petkov return -ENODEV; 123321afaf18SBorislav Petkov 123421afaf18SBorislav Petkov if (is_shared_bank(bank)) { 123521afaf18SBorislav Petkov nb = node_to_amd_nb(amd_get_nb_id(cpu)); 123621afaf18SBorislav Petkov 123721afaf18SBorislav Petkov /* threshold descriptor already initialized on this node? */ 123821afaf18SBorislav Petkov if (nb && nb->bank4) { 123921afaf18SBorislav Petkov /* yes, use it */ 124021afaf18SBorislav Petkov b = nb->bank4; 124121afaf18SBorislav Petkov err = kobject_add(b->kobj, &dev->kobj, name); 124221afaf18SBorislav Petkov if (err) 124321afaf18SBorislav Petkov goto out; 124421afaf18SBorislav Petkov 124521afaf18SBorislav Petkov per_cpu(threshold_banks, cpu)[bank] = b; 124621afaf18SBorislav Petkov refcount_inc(&b->cpus); 124721afaf18SBorislav Petkov 124821afaf18SBorislav Petkov err = __threshold_add_blocks(b); 124921afaf18SBorislav Petkov 125021afaf18SBorislav Petkov goto out; 125121afaf18SBorislav Petkov } 125221afaf18SBorislav Petkov } 125321afaf18SBorislav Petkov 125421afaf18SBorislav Petkov b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 125521afaf18SBorislav Petkov if (!b) { 125621afaf18SBorislav Petkov err = -ENOMEM; 125721afaf18SBorislav Petkov goto out; 125821afaf18SBorislav Petkov } 125921afaf18SBorislav Petkov 126021afaf18SBorislav Petkov b->kobj = kobject_create_and_add(name, &dev->kobj); 126121afaf18SBorislav Petkov if (!b->kobj) { 126221afaf18SBorislav Petkov err = -EINVAL; 126321afaf18SBorislav Petkov goto out_free; 126421afaf18SBorislav Petkov } 126521afaf18SBorislav Petkov 126621afaf18SBorislav Petkov per_cpu(threshold_banks, cpu)[bank] = b; 126721afaf18SBorislav Petkov 126821afaf18SBorislav Petkov if (is_shared_bank(bank)) { 126921afaf18SBorislav Petkov refcount_set(&b->cpus, 1); 127021afaf18SBorislav Petkov 127121afaf18SBorislav Petkov /* nb is already initialized, see above */ 127221afaf18SBorislav Petkov if (nb) { 127321afaf18SBorislav Petkov WARN_ON(nb->bank4); 127421afaf18SBorislav Petkov nb->bank4 = b; 127521afaf18SBorislav Petkov } 127621afaf18SBorislav Petkov } 127721afaf18SBorislav Petkov 127821afaf18SBorislav Petkov err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); 127921afaf18SBorislav Petkov if (!err) 128021afaf18SBorislav Petkov goto out; 128121afaf18SBorislav Petkov 128221afaf18SBorislav Petkov out_free: 128321afaf18SBorislav Petkov kfree(b); 128421afaf18SBorislav Petkov 128521afaf18SBorislav Petkov out: 128621afaf18SBorislav Petkov return err; 128721afaf18SBorislav Petkov } 128821afaf18SBorislav Petkov 128921afaf18SBorislav Petkov static void deallocate_threshold_block(unsigned int cpu, 129021afaf18SBorislav Petkov unsigned int bank) 129121afaf18SBorislav Petkov { 129221afaf18SBorislav Petkov struct threshold_block *pos = NULL; 129321afaf18SBorislav Petkov struct threshold_block *tmp = NULL; 129421afaf18SBorislav Petkov struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; 129521afaf18SBorislav Petkov 129621afaf18SBorislav Petkov if (!head) 129721afaf18SBorislav Petkov return; 129821afaf18SBorislav Petkov 129921afaf18SBorislav Petkov list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { 130021afaf18SBorislav Petkov kobject_put(&pos->kobj); 130121afaf18SBorislav Petkov list_del(&pos->miscj); 130221afaf18SBorislav Petkov kfree(pos); 130321afaf18SBorislav Petkov } 130421afaf18SBorislav Petkov 130521afaf18SBorislav Petkov kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); 130621afaf18SBorislav Petkov per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; 130721afaf18SBorislav Petkov } 130821afaf18SBorislav Petkov 130921afaf18SBorislav Petkov static void __threshold_remove_blocks(struct threshold_bank *b) 131021afaf18SBorislav Petkov { 131121afaf18SBorislav Petkov struct threshold_block *pos = NULL; 131221afaf18SBorislav Petkov struct threshold_block *tmp = NULL; 131321afaf18SBorislav Petkov 131421afaf18SBorislav Petkov kobject_del(b->kobj); 131521afaf18SBorislav Petkov 131621afaf18SBorislav Petkov list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 131721afaf18SBorislav Petkov kobject_del(&pos->kobj); 131821afaf18SBorislav Petkov } 131921afaf18SBorislav Petkov 132021afaf18SBorislav Petkov static void threshold_remove_bank(unsigned int cpu, int bank) 132121afaf18SBorislav Petkov { 132221afaf18SBorislav Petkov struct amd_northbridge *nb; 132321afaf18SBorislav Petkov struct threshold_bank *b; 132421afaf18SBorislav Petkov 132521afaf18SBorislav Petkov b = per_cpu(threshold_banks, cpu)[bank]; 132621afaf18SBorislav Petkov if (!b) 132721afaf18SBorislav Petkov return; 132821afaf18SBorislav Petkov 132921afaf18SBorislav Petkov if (!b->blocks) 133021afaf18SBorislav Petkov goto free_out; 133121afaf18SBorislav Petkov 133221afaf18SBorislav Petkov if (is_shared_bank(bank)) { 133321afaf18SBorislav Petkov if (!refcount_dec_and_test(&b->cpus)) { 133421afaf18SBorislav Petkov __threshold_remove_blocks(b); 133521afaf18SBorislav Petkov per_cpu(threshold_banks, cpu)[bank] = NULL; 133621afaf18SBorislav Petkov return; 133721afaf18SBorislav Petkov } else { 133821afaf18SBorislav Petkov /* 133921afaf18SBorislav Petkov * the last CPU on this node using the shared bank is 134021afaf18SBorislav Petkov * going away, remove that bank now. 134121afaf18SBorislav Petkov */ 134221afaf18SBorislav Petkov nb = node_to_amd_nb(amd_get_nb_id(cpu)); 134321afaf18SBorislav Petkov nb->bank4 = NULL; 134421afaf18SBorislav Petkov } 134521afaf18SBorislav Petkov } 134621afaf18SBorislav Petkov 134721afaf18SBorislav Petkov deallocate_threshold_block(cpu, bank); 134821afaf18SBorislav Petkov 134921afaf18SBorislav Petkov free_out: 135021afaf18SBorislav Petkov kobject_del(b->kobj); 135121afaf18SBorislav Petkov kobject_put(b->kobj); 135221afaf18SBorislav Petkov kfree(b); 135321afaf18SBorislav Petkov per_cpu(threshold_banks, cpu)[bank] = NULL; 135421afaf18SBorislav Petkov } 135521afaf18SBorislav Petkov 135621afaf18SBorislav Petkov int mce_threshold_remove_device(unsigned int cpu) 135721afaf18SBorislav Petkov { 135821afaf18SBorislav Petkov unsigned int bank; 135921afaf18SBorislav Petkov 136021afaf18SBorislav Petkov for (bank = 0; bank < mca_cfg.banks; ++bank) { 136121afaf18SBorislav Petkov if (!(per_cpu(bank_map, cpu) & (1 << bank))) 136221afaf18SBorislav Petkov continue; 136321afaf18SBorislav Petkov threshold_remove_bank(cpu, bank); 136421afaf18SBorislav Petkov } 136521afaf18SBorislav Petkov kfree(per_cpu(threshold_banks, cpu)); 136621afaf18SBorislav Petkov per_cpu(threshold_banks, cpu) = NULL; 136721afaf18SBorislav Petkov return 0; 136821afaf18SBorislav Petkov } 136921afaf18SBorislav Petkov 137021afaf18SBorislav Petkov /* create dir/files for all valid threshold banks */ 137121afaf18SBorislav Petkov int mce_threshold_create_device(unsigned int cpu) 137221afaf18SBorislav Petkov { 137321afaf18SBorislav Petkov unsigned int bank; 137421afaf18SBorislav Petkov struct threshold_bank **bp; 137521afaf18SBorislav Petkov int err = 0; 137621afaf18SBorislav Petkov 137721afaf18SBorislav Petkov bp = per_cpu(threshold_banks, cpu); 137821afaf18SBorislav Petkov if (bp) 137921afaf18SBorislav Petkov return 0; 138021afaf18SBorislav Petkov 138121afaf18SBorislav Petkov bp = kcalloc(mca_cfg.banks, sizeof(struct threshold_bank *), 138221afaf18SBorislav Petkov GFP_KERNEL); 138321afaf18SBorislav Petkov if (!bp) 138421afaf18SBorislav Petkov return -ENOMEM; 138521afaf18SBorislav Petkov 138621afaf18SBorislav Petkov per_cpu(threshold_banks, cpu) = bp; 138721afaf18SBorislav Petkov 138821afaf18SBorislav Petkov for (bank = 0; bank < mca_cfg.banks; ++bank) { 138921afaf18SBorislav Petkov if (!(per_cpu(bank_map, cpu) & (1 << bank))) 139021afaf18SBorislav Petkov continue; 139121afaf18SBorislav Petkov err = threshold_create_bank(cpu, bank); 139221afaf18SBorislav Petkov if (err) 139321afaf18SBorislav Petkov goto err; 139421afaf18SBorislav Petkov } 139521afaf18SBorislav Petkov return err; 139621afaf18SBorislav Petkov err: 139721afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 139821afaf18SBorislav Petkov return err; 139921afaf18SBorislav Petkov } 140021afaf18SBorislav Petkov 140121afaf18SBorislav Petkov static __init int threshold_init_device(void) 140221afaf18SBorislav Petkov { 140321afaf18SBorislav Petkov unsigned lcpu = 0; 140421afaf18SBorislav Petkov 140521afaf18SBorislav Petkov /* to hit CPUs online before the notifier is up */ 140621afaf18SBorislav Petkov for_each_online_cpu(lcpu) { 140721afaf18SBorislav Petkov int err = mce_threshold_create_device(lcpu); 140821afaf18SBorislav Petkov 140921afaf18SBorislav Petkov if (err) 141021afaf18SBorislav Petkov return err; 141121afaf18SBorislav Petkov } 141221afaf18SBorislav Petkov 141321afaf18SBorislav Petkov if (thresholding_irq_en) 141421afaf18SBorislav Petkov mce_threshold_vector = amd_threshold_interrupt; 141521afaf18SBorislav Petkov 141621afaf18SBorislav Petkov return 0; 141721afaf18SBorislav Petkov } 141821afaf18SBorislav Petkov /* 141921afaf18SBorislav Petkov * there are 3 funcs which need to be _initcalled in a logic sequence: 142021afaf18SBorislav Petkov * 1. xen_late_init_mcelog 142121afaf18SBorislav Petkov * 2. mcheck_init_device 142221afaf18SBorislav Petkov * 3. threshold_init_device 142321afaf18SBorislav Petkov * 142421afaf18SBorislav Petkov * xen_late_init_mcelog must register xen_mce_chrdev_device before 142521afaf18SBorislav Petkov * native mce_chrdev_device registration if running under xen platform; 142621afaf18SBorislav Petkov * 142721afaf18SBorislav Petkov * mcheck_init_device should be inited before threshold_init_device to 142821afaf18SBorislav Petkov * initialize mce_device, otherwise a NULL ptr dereference will cause panic. 142921afaf18SBorislav Petkov * 143021afaf18SBorislav Petkov * so we use following _initcalls 143121afaf18SBorislav Petkov * 1. device_initcall(xen_late_init_mcelog); 143221afaf18SBorislav Petkov * 2. device_initcall_sync(mcheck_init_device); 143321afaf18SBorislav Petkov * 3. late_initcall(threshold_init_device); 143421afaf18SBorislav Petkov * 143521afaf18SBorislav Petkov * when running under xen, the initcall order is 1,2,3; 143621afaf18SBorislav Petkov * on baremetal, we skip 1 and we do only 2 and 3. 143721afaf18SBorislav Petkov */ 143821afaf18SBorislav Petkov late_initcall(threshold_init_device); 1439