1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/kernel.h> 3 4 #include <linux/string.h> 5 #include <linux/bitops.h> 6 #include <linux/smp.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/thread_info.h> 10 #include <linux/init.h> 11 #include <linux/uaccess.h> 12 13 #include <asm/cpufeature.h> 14 #include <asm/pgtable.h> 15 #include <asm/msr.h> 16 #include <asm/bugs.h> 17 #include <asm/cpu.h> 18 #include <asm/intel-family.h> 19 #include <asm/microcode_intel.h> 20 #include <asm/hwcap2.h> 21 #include <asm/elf.h> 22 23 #ifdef CONFIG_X86_64 24 #include <linux/topology.h> 25 #endif 26 27 #include "cpu.h" 28 29 #ifdef CONFIG_X86_LOCAL_APIC 30 #include <asm/mpspec.h> 31 #include <asm/apic.h> 32 #endif 33 34 /* 35 * Just in case our CPU detection goes bad, or you have a weird system, 36 * allow a way to override the automatic disabling of MPX. 37 */ 38 static int forcempx; 39 40 static int __init forcempx_setup(char *__unused) 41 { 42 forcempx = 1; 43 44 return 1; 45 } 46 __setup("intel-skd-046-workaround=disable", forcempx_setup); 47 48 void check_mpx_erratum(struct cpuinfo_x86 *c) 49 { 50 if (forcempx) 51 return; 52 /* 53 * Turn off the MPX feature on CPUs where SMEP is not 54 * available or disabled. 55 * 56 * Works around Intel Erratum SKD046: "Branch Instructions 57 * May Initialize MPX Bound Registers Incorrectly". 58 * 59 * This might falsely disable MPX on systems without 60 * SMEP, like Atom processors without SMEP. But there 61 * is no such hardware known at the moment. 62 */ 63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { 64 setup_clear_cpu_cap(X86_FEATURE_MPX); 65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); 66 } 67 } 68 69 static bool ring3mwait_disabled __read_mostly; 70 71 static int __init ring3mwait_disable(char *__unused) 72 { 73 ring3mwait_disabled = true; 74 return 0; 75 } 76 __setup("ring3mwait=disable", ring3mwait_disable); 77 78 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 79 { 80 /* 81 * Ring 3 MONITOR/MWAIT feature cannot be detected without 82 * cpu model and family comparison. 83 */ 84 if (c->x86 != 6) 85 return; 86 switch (c->x86_model) { 87 case INTEL_FAM6_XEON_PHI_KNL: 88 case INTEL_FAM6_XEON_PHI_KNM: 89 break; 90 default: 91 return; 92 } 93 94 if (ring3mwait_disabled) 95 return; 96 97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 98 this_cpu_or(msr_misc_features_shadow, 99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 100 101 if (c == &boot_cpu_data) 102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 103 } 104 105 static void early_init_intel(struct cpuinfo_x86 *c) 106 { 107 u64 misc_enable; 108 109 /* Unmask CPUID levels if masked: */ 110 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 111 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 112 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 113 c->cpuid_level = cpuid_eax(0); 114 get_cpu_cap(c); 115 } 116 } 117 118 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 119 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 120 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 121 122 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 123 c->microcode = intel_get_microcode_revision(); 124 125 /* 126 * Atom erratum AAE44/AAF40/AAG38/AAH41: 127 * 128 * A race condition between speculative fetches and invalidating 129 * a large page. This is worked around in microcode, but we 130 * need the microcode to have already been loaded... so if it is 131 * not, recommend a BIOS update and disable large pages. 132 */ 133 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && 134 c->microcode < 0x20e) { 135 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 136 clear_cpu_cap(c, X86_FEATURE_PSE); 137 } 138 139 #ifdef CONFIG_X86_64 140 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 141 #else 142 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 143 if (c->x86 == 15 && c->x86_cache_alignment == 64) 144 c->x86_cache_alignment = 128; 145 #endif 146 147 /* CPUID workaround for 0F33/0F34 CPU */ 148 if (c->x86 == 0xF && c->x86_model == 0x3 149 && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) 150 c->x86_phys_bits = 36; 151 152 /* 153 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 154 * with P/T states and does not stop in deep C-states. 155 * 156 * It is also reliable across cores and sockets. (but not across 157 * cabinets - we turn it off in that case explicitly.) 158 */ 159 if (c->x86_power & (1 << 8)) { 160 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 161 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 162 } 163 164 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 165 if (c->x86 == 6) { 166 switch (c->x86_model) { 167 case 0x27: /* Penwell */ 168 case 0x35: /* Cloverview */ 169 case 0x4a: /* Merrifield */ 170 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 171 break; 172 default: 173 break; 174 } 175 } 176 177 /* 178 * There is a known erratum on Pentium III and Core Solo 179 * and Core Duo CPUs. 180 * " Page with PAT set to WC while associated MTRR is UC 181 * may consolidate to UC " 182 * Because of this erratum, it is better to stick with 183 * setting WC in MTRR rather than using PAT on these CPUs. 184 * 185 * Enable PAT WC only on P4, Core 2 or later CPUs. 186 */ 187 if (c->x86 == 6 && c->x86_model < 15) 188 clear_cpu_cap(c, X86_FEATURE_PAT); 189 190 #ifdef CONFIG_KMEMCHECK 191 /* 192 * P4s have a "fast strings" feature which causes single- 193 * stepping REP instructions to only generate a #DB on 194 * cache-line boundaries. 195 * 196 * Ingo Molnar reported a Pentium D (model 6) and a Xeon 197 * (model 2) with the same problem. 198 */ 199 if (c->x86 == 15) 200 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 201 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) 202 pr_info("kmemcheck: Disabling fast string operations\n"); 203 #endif 204 205 /* 206 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 207 * clear the fast string and enhanced fast string CPU capabilities. 208 */ 209 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 210 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 211 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 212 pr_info("Disabled fast string operations\n"); 213 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 214 setup_clear_cpu_cap(X86_FEATURE_ERMS); 215 } 216 } 217 218 /* 219 * Intel Quark Core DevMan_001.pdf section 6.4.11 220 * "The operating system also is required to invalidate (i.e., flush) 221 * the TLB when any changes are made to any of the page table entries. 222 * The operating system must reload CR3 to cause the TLB to be flushed" 223 * 224 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 225 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 226 * to be modified. 227 */ 228 if (c->x86 == 5 && c->x86_model == 9) { 229 pr_info("Disabling PGE capability bit\n"); 230 setup_clear_cpu_cap(X86_FEATURE_PGE); 231 } 232 233 if (c->cpuid_level >= 0x00000001) { 234 u32 eax, ebx, ecx, edx; 235 236 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 237 /* 238 * If HTT (EDX[28]) is set EBX[16:23] contain the number of 239 * apicids which are reserved per package. Store the resulting 240 * shift value for the package management code. 241 */ 242 if (edx & (1U << 28)) 243 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); 244 } 245 246 check_mpx_erratum(c); 247 } 248 249 #ifdef CONFIG_X86_32 250 /* 251 * Early probe support logic for ppro memory erratum #50 252 * 253 * This is called before we do cpu ident work 254 */ 255 256 int ppro_with_ram_bug(void) 257 { 258 /* Uses data from early_cpu_detect now */ 259 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 260 boot_cpu_data.x86 == 6 && 261 boot_cpu_data.x86_model == 1 && 262 boot_cpu_data.x86_mask < 8) { 263 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 264 return 1; 265 } 266 return 0; 267 } 268 269 static void intel_smp_check(struct cpuinfo_x86 *c) 270 { 271 /* calling is from identify_secondary_cpu() ? */ 272 if (!c->cpu_index) 273 return; 274 275 /* 276 * Mask B, Pentium, but not Pentium MMX 277 */ 278 if (c->x86 == 5 && 279 c->x86_mask >= 1 && c->x86_mask <= 4 && 280 c->x86_model <= 3) { 281 /* 282 * Remember we have B step Pentia with bugs 283 */ 284 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 285 "with B stepping processors.\n"); 286 } 287 } 288 289 static int forcepae; 290 static int __init forcepae_setup(char *__unused) 291 { 292 forcepae = 1; 293 return 1; 294 } 295 __setup("forcepae", forcepae_setup); 296 297 static void intel_workarounds(struct cpuinfo_x86 *c) 298 { 299 #ifdef CONFIG_X86_F00F_BUG 300 /* 301 * All models of Pentium and Pentium with MMX technology CPUs 302 * have the F0 0F bug, which lets nonprivileged users lock up the 303 * system. Announce that the fault handler will be checking for it. 304 * The Quark is also family 5, but does not have the same bug. 305 */ 306 clear_cpu_bug(c, X86_BUG_F00F); 307 if (c->x86 == 5 && c->x86_model < 9) { 308 static int f00f_workaround_enabled; 309 310 set_cpu_bug(c, X86_BUG_F00F); 311 if (!f00f_workaround_enabled) { 312 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 313 f00f_workaround_enabled = 1; 314 } 315 } 316 #endif 317 318 /* 319 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 320 * model 3 mask 3 321 */ 322 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 323 clear_cpu_cap(c, X86_FEATURE_SEP); 324 325 /* 326 * PAE CPUID issue: many Pentium M report no PAE but may have a 327 * functionally usable PAE implementation. 328 * Forcefully enable PAE if kernel parameter "forcepae" is present. 329 */ 330 if (forcepae) { 331 pr_warn("PAE forced!\n"); 332 set_cpu_cap(c, X86_FEATURE_PAE); 333 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 334 } 335 336 /* 337 * P4 Xeon erratum 037 workaround. 338 * Hardware prefetcher may cause stale data to be loaded into the cache. 339 */ 340 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 341 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 342 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 343 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 344 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 345 } 346 } 347 348 /* 349 * See if we have a good local APIC by checking for buggy Pentia, 350 * i.e. all B steppings and the C2 stepping of P54C when using their 351 * integrated APIC (see 11AP erratum in "Pentium Processor 352 * Specification Update"). 353 */ 354 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 355 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 356 set_cpu_bug(c, X86_BUG_11AP); 357 358 359 #ifdef CONFIG_X86_INTEL_USERCOPY 360 /* 361 * Set up the preferred alignment for movsl bulk memory moves 362 */ 363 switch (c->x86) { 364 case 4: /* 486: untested */ 365 break; 366 case 5: /* Old Pentia: untested */ 367 break; 368 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 369 movsl_mask.mask = 7; 370 break; 371 case 15: /* P4 is OK down to 8-byte alignment */ 372 movsl_mask.mask = 7; 373 break; 374 } 375 #endif 376 377 intel_smp_check(c); 378 } 379 #else 380 static void intel_workarounds(struct cpuinfo_x86 *c) 381 { 382 } 383 #endif 384 385 static void srat_detect_node(struct cpuinfo_x86 *c) 386 { 387 #ifdef CONFIG_NUMA 388 unsigned node; 389 int cpu = smp_processor_id(); 390 391 /* Don't do the funky fallback heuristics the AMD version employs 392 for now. */ 393 node = numa_cpu_node(cpu); 394 if (node == NUMA_NO_NODE || !node_online(node)) { 395 /* reuse the value from init_cpu_to_node() */ 396 node = cpu_to_node(cpu); 397 } 398 numa_set_node(cpu, node); 399 #endif 400 } 401 402 /* 403 * find out the number of processor cores on the die 404 */ 405 static int intel_num_cpu_cores(struct cpuinfo_x86 *c) 406 { 407 unsigned int eax, ebx, ecx, edx; 408 409 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 410 return 1; 411 412 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 413 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 414 if (eax & 0x1f) 415 return (eax >> 26) + 1; 416 else 417 return 1; 418 } 419 420 static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 421 { 422 /* Intel VMX MSR indicated features */ 423 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 424 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 425 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 426 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 427 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 428 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 429 430 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 431 432 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 433 clear_cpu_cap(c, X86_FEATURE_VNMI); 434 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 435 clear_cpu_cap(c, X86_FEATURE_EPT); 436 clear_cpu_cap(c, X86_FEATURE_VPID); 437 438 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 439 msr_ctl = vmx_msr_high | vmx_msr_low; 440 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 441 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 442 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 443 set_cpu_cap(c, X86_FEATURE_VNMI); 444 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 445 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 446 vmx_msr_low, vmx_msr_high); 447 msr_ctl2 = vmx_msr_high | vmx_msr_low; 448 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 449 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 450 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 451 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 452 set_cpu_cap(c, X86_FEATURE_EPT); 453 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 454 set_cpu_cap(c, X86_FEATURE_VPID); 455 } 456 } 457 458 static void init_intel_energy_perf(struct cpuinfo_x86 *c) 459 { 460 u64 epb; 461 462 /* 463 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. 464 * (x86_energy_perf_policy(8) is available to change it at run-time.) 465 */ 466 if (!cpu_has(c, X86_FEATURE_EPB)) 467 return; 468 469 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 470 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) 471 return; 472 473 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); 474 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); 475 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; 476 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 477 } 478 479 static void intel_bsp_resume(struct cpuinfo_x86 *c) 480 { 481 /* 482 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, 483 * so reinitialize it properly like during bootup: 484 */ 485 init_intel_energy_perf(c); 486 } 487 488 static void init_cpuid_fault(struct cpuinfo_x86 *c) 489 { 490 u64 msr; 491 492 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 493 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 494 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 495 } 496 } 497 498 static void init_intel_misc_features(struct cpuinfo_x86 *c) 499 { 500 u64 msr; 501 502 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 503 return; 504 505 /* Clear all MISC features */ 506 this_cpu_write(msr_misc_features_shadow, 0); 507 508 /* Check features and update capabilities and shadow control bits */ 509 init_cpuid_fault(c); 510 probe_xeon_phi_r3mwait(c); 511 512 msr = this_cpu_read(msr_misc_features_shadow); 513 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 514 } 515 516 static void init_intel(struct cpuinfo_x86 *c) 517 { 518 unsigned int l2 = 0; 519 520 early_init_intel(c); 521 522 intel_workarounds(c); 523 524 /* 525 * Detect the extended topology information if available. This 526 * will reinitialise the initial_apicid which will be used 527 * in init_intel_cacheinfo() 528 */ 529 detect_extended_topology(c); 530 531 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 532 /* 533 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 534 * detection. 535 */ 536 c->x86_max_cores = intel_num_cpu_cores(c); 537 #ifdef CONFIG_X86_32 538 detect_ht(c); 539 #endif 540 } 541 542 l2 = init_intel_cacheinfo(c); 543 544 /* Detect legacy cache sizes if init_intel_cacheinfo did not */ 545 if (l2 == 0) { 546 cpu_detect_cache_sizes(c); 547 l2 = c->x86_cache_size; 548 } 549 550 if (c->cpuid_level > 9) { 551 unsigned eax = cpuid_eax(10); 552 /* Check for version and the number of counters */ 553 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 554 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 555 } 556 557 if (cpu_has(c, X86_FEATURE_XMM2)) 558 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 559 560 if (boot_cpu_has(X86_FEATURE_DS)) { 561 unsigned int l1; 562 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 563 if (!(l1 & (1<<11))) 564 set_cpu_cap(c, X86_FEATURE_BTS); 565 if (!(l1 & (1<<12))) 566 set_cpu_cap(c, X86_FEATURE_PEBS); 567 } 568 569 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 570 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 571 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 572 573 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 574 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 575 set_cpu_bug(c, X86_BUG_MONITOR); 576 577 #ifdef CONFIG_X86_64 578 if (c->x86 == 15) 579 c->x86_cache_alignment = c->x86_clflush_size * 2; 580 if (c->x86 == 6) 581 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 582 #else 583 /* 584 * Names for the Pentium II/Celeron processors 585 * detectable only by also checking the cache size. 586 * Dixon is NOT a Celeron. 587 */ 588 if (c->x86 == 6) { 589 char *p = NULL; 590 591 switch (c->x86_model) { 592 case 5: 593 if (l2 == 0) 594 p = "Celeron (Covington)"; 595 else if (l2 == 256) 596 p = "Mobile Pentium II (Dixon)"; 597 break; 598 599 case 6: 600 if (l2 == 128) 601 p = "Celeron (Mendocino)"; 602 else if (c->x86_mask == 0 || c->x86_mask == 5) 603 p = "Celeron-A"; 604 break; 605 606 case 8: 607 if (l2 == 128) 608 p = "Celeron (Coppermine)"; 609 break; 610 } 611 612 if (p) 613 strcpy(c->x86_model_id, p); 614 } 615 616 if (c->x86 == 15) 617 set_cpu_cap(c, X86_FEATURE_P4); 618 if (c->x86 == 6) 619 set_cpu_cap(c, X86_FEATURE_P3); 620 #endif 621 622 /* Work around errata */ 623 srat_detect_node(c); 624 625 if (cpu_has(c, X86_FEATURE_VMX)) 626 detect_vmx_virtcap(c); 627 628 init_intel_energy_perf(c); 629 630 init_intel_misc_features(c); 631 } 632 633 #ifdef CONFIG_X86_32 634 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 635 { 636 /* 637 * Intel PIII Tualatin. This comes in two flavours. 638 * One has 256kb of cache, the other 512. We have no way 639 * to determine which, so we use a boottime override 640 * for the 512kb model, and assume 256 otherwise. 641 */ 642 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 643 size = 256; 644 645 /* 646 * Intel Quark SoC X1000 contains a 4-way set associative 647 * 16K cache with a 16 byte cache line and 256 lines per tag 648 */ 649 if ((c->x86 == 5) && (c->x86_model == 9)) 650 size = 16; 651 return size; 652 } 653 #endif 654 655 #define TLB_INST_4K 0x01 656 #define TLB_INST_4M 0x02 657 #define TLB_INST_2M_4M 0x03 658 659 #define TLB_INST_ALL 0x05 660 #define TLB_INST_1G 0x06 661 662 #define TLB_DATA_4K 0x11 663 #define TLB_DATA_4M 0x12 664 #define TLB_DATA_2M_4M 0x13 665 #define TLB_DATA_4K_4M 0x14 666 667 #define TLB_DATA_1G 0x16 668 669 #define TLB_DATA0_4K 0x21 670 #define TLB_DATA0_4M 0x22 671 #define TLB_DATA0_2M_4M 0x23 672 673 #define STLB_4K 0x41 674 #define STLB_4K_2M 0x42 675 676 static const struct _tlb_table intel_tlb_table[] = { 677 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 678 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 679 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 680 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 681 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 682 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 683 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 684 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 685 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 686 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 687 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 688 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 689 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 690 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 691 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 692 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 693 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 694 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 695 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 696 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 697 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 698 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 699 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 700 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 701 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 702 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 703 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 704 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 705 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 706 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 707 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 708 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 709 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 710 { 0x00, 0, 0 } 711 }; 712 713 static void intel_tlb_lookup(const unsigned char desc) 714 { 715 unsigned char k; 716 if (desc == 0) 717 return; 718 719 /* look up this descriptor in the table */ 720 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 721 intel_tlb_table[k].descriptor != 0; k++) 722 ; 723 724 if (intel_tlb_table[k].tlb_type == 0) 725 return; 726 727 switch (intel_tlb_table[k].tlb_type) { 728 case STLB_4K: 729 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 730 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 731 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 732 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 733 break; 734 case STLB_4K_2M: 735 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 736 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 737 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 738 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 739 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 740 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 741 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 742 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 743 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 744 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 745 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 746 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 747 break; 748 case TLB_INST_ALL: 749 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 750 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 751 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 752 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 753 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 754 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 755 break; 756 case TLB_INST_4K: 757 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 758 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 759 break; 760 case TLB_INST_4M: 761 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 762 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 763 break; 764 case TLB_INST_2M_4M: 765 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 766 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 767 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 768 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 769 break; 770 case TLB_DATA_4K: 771 case TLB_DATA0_4K: 772 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 773 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 774 break; 775 case TLB_DATA_4M: 776 case TLB_DATA0_4M: 777 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 778 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 779 break; 780 case TLB_DATA_2M_4M: 781 case TLB_DATA0_2M_4M: 782 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 783 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 784 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 785 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 786 break; 787 case TLB_DATA_4K_4M: 788 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 789 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 790 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 791 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 792 break; 793 case TLB_DATA_1G: 794 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 795 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 796 break; 797 } 798 } 799 800 static void intel_detect_tlb(struct cpuinfo_x86 *c) 801 { 802 int i, j, n; 803 unsigned int regs[4]; 804 unsigned char *desc = (unsigned char *)regs; 805 806 if (c->cpuid_level < 2) 807 return; 808 809 /* Number of times to iterate */ 810 n = cpuid_eax(2) & 0xFF; 811 812 for (i = 0 ; i < n ; i++) { 813 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 814 815 /* If bit 31 is set, this is an unknown format */ 816 for (j = 0 ; j < 3 ; j++) 817 if (regs[j] & (1 << 31)) 818 regs[j] = 0; 819 820 /* Byte 0 is level count, not a descriptor */ 821 for (j = 1 ; j < 16 ; j++) 822 intel_tlb_lookup(desc[j]); 823 } 824 } 825 826 static const struct cpu_dev intel_cpu_dev = { 827 .c_vendor = "Intel", 828 .c_ident = { "GenuineIntel" }, 829 #ifdef CONFIG_X86_32 830 .legacy_models = { 831 { .family = 4, .model_names = 832 { 833 [0] = "486 DX-25/33", 834 [1] = "486 DX-50", 835 [2] = "486 SX", 836 [3] = "486 DX/2", 837 [4] = "486 SL", 838 [5] = "486 SX/2", 839 [7] = "486 DX/2-WB", 840 [8] = "486 DX/4", 841 [9] = "486 DX/4-WB" 842 } 843 }, 844 { .family = 5, .model_names = 845 { 846 [0] = "Pentium 60/66 A-step", 847 [1] = "Pentium 60/66", 848 [2] = "Pentium 75 - 200", 849 [3] = "OverDrive PODP5V83", 850 [4] = "Pentium MMX", 851 [7] = "Mobile Pentium 75 - 200", 852 [8] = "Mobile Pentium MMX", 853 [9] = "Quark SoC X1000", 854 } 855 }, 856 { .family = 6, .model_names = 857 { 858 [0] = "Pentium Pro A-step", 859 [1] = "Pentium Pro", 860 [3] = "Pentium II (Klamath)", 861 [4] = "Pentium II (Deschutes)", 862 [5] = "Pentium II (Deschutes)", 863 [6] = "Mobile Pentium II", 864 [7] = "Pentium III (Katmai)", 865 [8] = "Pentium III (Coppermine)", 866 [10] = "Pentium III (Cascades)", 867 [11] = "Pentium III (Tualatin)", 868 } 869 }, 870 { .family = 15, .model_names = 871 { 872 [0] = "Pentium 4 (Unknown)", 873 [1] = "Pentium 4 (Willamette)", 874 [2] = "Pentium 4 (Northwood)", 875 [4] = "Pentium 4 (Foster)", 876 [5] = "Pentium 4 (Foster)", 877 } 878 }, 879 }, 880 .legacy_cache_size = intel_size_cache, 881 #endif 882 .c_detect_tlb = intel_detect_tlb, 883 .c_early_init = early_init_intel, 884 .c_init = init_intel, 885 .c_bsp_resume = intel_bsp_resume, 886 .c_x86_vendor = X86_VENDOR_INTEL, 887 }; 888 889 cpu_dev_register(intel_cpu_dev); 890 891