1 #include <linux/kernel.h> 2 3 #include <linux/string.h> 4 #include <linux/bitops.h> 5 #include <linux/smp.h> 6 #include <linux/sched.h> 7 #include <linux/sched/clock.h> 8 #include <linux/thread_info.h> 9 #include <linux/init.h> 10 #include <linux/uaccess.h> 11 12 #include <asm/cpufeature.h> 13 #include <asm/pgtable.h> 14 #include <asm/msr.h> 15 #include <asm/bugs.h> 16 #include <asm/cpu.h> 17 #include <asm/intel-family.h> 18 #include <asm/microcode_intel.h> 19 #include <asm/hwcap2.h> 20 #include <asm/elf.h> 21 22 #ifdef CONFIG_X86_64 23 #include <linux/topology.h> 24 #endif 25 26 #include "cpu.h" 27 28 #ifdef CONFIG_X86_LOCAL_APIC 29 #include <asm/mpspec.h> 30 #include <asm/apic.h> 31 #endif 32 33 /* 34 * Just in case our CPU detection goes bad, or you have a weird system, 35 * allow a way to override the automatic disabling of MPX. 36 */ 37 static int forcempx; 38 39 static int __init forcempx_setup(char *__unused) 40 { 41 forcempx = 1; 42 43 return 1; 44 } 45 __setup("intel-skd-046-workaround=disable", forcempx_setup); 46 47 void check_mpx_erratum(struct cpuinfo_x86 *c) 48 { 49 if (forcempx) 50 return; 51 /* 52 * Turn off the MPX feature on CPUs where SMEP is not 53 * available or disabled. 54 * 55 * Works around Intel Erratum SKD046: "Branch Instructions 56 * May Initialize MPX Bound Registers Incorrectly". 57 * 58 * This might falsely disable MPX on systems without 59 * SMEP, like Atom processors without SMEP. But there 60 * is no such hardware known at the moment. 61 */ 62 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { 63 setup_clear_cpu_cap(X86_FEATURE_MPX); 64 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); 65 } 66 } 67 68 static bool ring3mwait_disabled __read_mostly; 69 70 static int __init ring3mwait_disable(char *__unused) 71 { 72 ring3mwait_disabled = true; 73 return 0; 74 } 75 __setup("ring3mwait=disable", ring3mwait_disable); 76 77 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 78 { 79 /* 80 * Ring 3 MONITOR/MWAIT feature cannot be detected without 81 * cpu model and family comparison. 82 */ 83 if (c->x86 != 6) 84 return; 85 switch (c->x86_model) { 86 case INTEL_FAM6_XEON_PHI_KNL: 87 case INTEL_FAM6_XEON_PHI_KNM: 88 break; 89 default: 90 return; 91 } 92 93 if (ring3mwait_disabled) { 94 msr_clear_bit(MSR_MISC_FEATURE_ENABLES, 95 MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); 96 return; 97 } 98 99 msr_set_bit(MSR_MISC_FEATURE_ENABLES, 100 MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); 101 102 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 103 104 if (c == &boot_cpu_data) 105 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 106 } 107 108 static void early_init_intel(struct cpuinfo_x86 *c) 109 { 110 u64 misc_enable; 111 112 /* Unmask CPUID levels if masked: */ 113 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 114 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 115 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 116 c->cpuid_level = cpuid_eax(0); 117 get_cpu_cap(c); 118 } 119 } 120 121 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 122 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 123 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 124 125 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 126 c->microcode = intel_get_microcode_revision(); 127 128 /* 129 * Atom erratum AAE44/AAF40/AAG38/AAH41: 130 * 131 * A race condition between speculative fetches and invalidating 132 * a large page. This is worked around in microcode, but we 133 * need the microcode to have already been loaded... so if it is 134 * not, recommend a BIOS update and disable large pages. 135 */ 136 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && 137 c->microcode < 0x20e) { 138 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 139 clear_cpu_cap(c, X86_FEATURE_PSE); 140 } 141 142 #ifdef CONFIG_X86_64 143 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 144 #else 145 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 146 if (c->x86 == 15 && c->x86_cache_alignment == 64) 147 c->x86_cache_alignment = 128; 148 #endif 149 150 /* CPUID workaround for 0F33/0F34 CPU */ 151 if (c->x86 == 0xF && c->x86_model == 0x3 152 && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) 153 c->x86_phys_bits = 36; 154 155 /* 156 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 157 * with P/T states and does not stop in deep C-states. 158 * 159 * It is also reliable across cores and sockets. (but not across 160 * cabinets - we turn it off in that case explicitly.) 161 */ 162 if (c->x86_power & (1 << 8)) { 163 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 164 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 165 if (check_tsc_unstable()) 166 clear_sched_clock_stable(); 167 } else { 168 clear_sched_clock_stable(); 169 } 170 171 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 172 if (c->x86 == 6) { 173 switch (c->x86_model) { 174 case 0x27: /* Penwell */ 175 case 0x35: /* Cloverview */ 176 case 0x4a: /* Merrifield */ 177 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 178 break; 179 default: 180 break; 181 } 182 } 183 184 /* 185 * There is a known erratum on Pentium III and Core Solo 186 * and Core Duo CPUs. 187 * " Page with PAT set to WC while associated MTRR is UC 188 * may consolidate to UC " 189 * Because of this erratum, it is better to stick with 190 * setting WC in MTRR rather than using PAT on these CPUs. 191 * 192 * Enable PAT WC only on P4, Core 2 or later CPUs. 193 */ 194 if (c->x86 == 6 && c->x86_model < 15) 195 clear_cpu_cap(c, X86_FEATURE_PAT); 196 197 #ifdef CONFIG_KMEMCHECK 198 /* 199 * P4s have a "fast strings" feature which causes single- 200 * stepping REP instructions to only generate a #DB on 201 * cache-line boundaries. 202 * 203 * Ingo Molnar reported a Pentium D (model 6) and a Xeon 204 * (model 2) with the same problem. 205 */ 206 if (c->x86 == 15) 207 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 208 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) 209 pr_info("kmemcheck: Disabling fast string operations\n"); 210 #endif 211 212 /* 213 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 214 * clear the fast string and enhanced fast string CPU capabilities. 215 */ 216 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 217 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 218 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 219 pr_info("Disabled fast string operations\n"); 220 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 221 setup_clear_cpu_cap(X86_FEATURE_ERMS); 222 } 223 } 224 225 /* 226 * Intel Quark Core DevMan_001.pdf section 6.4.11 227 * "The operating system also is required to invalidate (i.e., flush) 228 * the TLB when any changes are made to any of the page table entries. 229 * The operating system must reload CR3 to cause the TLB to be flushed" 230 * 231 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 232 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 233 * to be modified. 234 */ 235 if (c->x86 == 5 && c->x86_model == 9) { 236 pr_info("Disabling PGE capability bit\n"); 237 setup_clear_cpu_cap(X86_FEATURE_PGE); 238 } 239 240 if (c->cpuid_level >= 0x00000001) { 241 u32 eax, ebx, ecx, edx; 242 243 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 244 /* 245 * If HTT (EDX[28]) is set EBX[16:23] contain the number of 246 * apicids which are reserved per package. Store the resulting 247 * shift value for the package management code. 248 */ 249 if (edx & (1U << 28)) 250 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); 251 } 252 253 check_mpx_erratum(c); 254 } 255 256 #ifdef CONFIG_X86_32 257 /* 258 * Early probe support logic for ppro memory erratum #50 259 * 260 * This is called before we do cpu ident work 261 */ 262 263 int ppro_with_ram_bug(void) 264 { 265 /* Uses data from early_cpu_detect now */ 266 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 267 boot_cpu_data.x86 == 6 && 268 boot_cpu_data.x86_model == 1 && 269 boot_cpu_data.x86_mask < 8) { 270 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 271 return 1; 272 } 273 return 0; 274 } 275 276 static void intel_smp_check(struct cpuinfo_x86 *c) 277 { 278 /* calling is from identify_secondary_cpu() ? */ 279 if (!c->cpu_index) 280 return; 281 282 /* 283 * Mask B, Pentium, but not Pentium MMX 284 */ 285 if (c->x86 == 5 && 286 c->x86_mask >= 1 && c->x86_mask <= 4 && 287 c->x86_model <= 3) { 288 /* 289 * Remember we have B step Pentia with bugs 290 */ 291 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 292 "with B stepping processors.\n"); 293 } 294 } 295 296 static int forcepae; 297 static int __init forcepae_setup(char *__unused) 298 { 299 forcepae = 1; 300 return 1; 301 } 302 __setup("forcepae", forcepae_setup); 303 304 static void intel_workarounds(struct cpuinfo_x86 *c) 305 { 306 #ifdef CONFIG_X86_F00F_BUG 307 /* 308 * All models of Pentium and Pentium with MMX technology CPUs 309 * have the F0 0F bug, which lets nonprivileged users lock up the 310 * system. Announce that the fault handler will be checking for it. 311 * The Quark is also family 5, but does not have the same bug. 312 */ 313 clear_cpu_bug(c, X86_BUG_F00F); 314 if (c->x86 == 5 && c->x86_model < 9) { 315 static int f00f_workaround_enabled; 316 317 set_cpu_bug(c, X86_BUG_F00F); 318 if (!f00f_workaround_enabled) { 319 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 320 f00f_workaround_enabled = 1; 321 } 322 } 323 #endif 324 325 /* 326 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 327 * model 3 mask 3 328 */ 329 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 330 clear_cpu_cap(c, X86_FEATURE_SEP); 331 332 /* 333 * PAE CPUID issue: many Pentium M report no PAE but may have a 334 * functionally usable PAE implementation. 335 * Forcefully enable PAE if kernel parameter "forcepae" is present. 336 */ 337 if (forcepae) { 338 pr_warn("PAE forced!\n"); 339 set_cpu_cap(c, X86_FEATURE_PAE); 340 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 341 } 342 343 /* 344 * P4 Xeon erratum 037 workaround. 345 * Hardware prefetcher may cause stale data to be loaded into the cache. 346 */ 347 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 348 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 349 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 350 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 351 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 352 } 353 } 354 355 /* 356 * See if we have a good local APIC by checking for buggy Pentia, 357 * i.e. all B steppings and the C2 stepping of P54C when using their 358 * integrated APIC (see 11AP erratum in "Pentium Processor 359 * Specification Update"). 360 */ 361 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 362 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 363 set_cpu_bug(c, X86_BUG_11AP); 364 365 366 #ifdef CONFIG_X86_INTEL_USERCOPY 367 /* 368 * Set up the preferred alignment for movsl bulk memory moves 369 */ 370 switch (c->x86) { 371 case 4: /* 486: untested */ 372 break; 373 case 5: /* Old Pentia: untested */ 374 break; 375 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 376 movsl_mask.mask = 7; 377 break; 378 case 15: /* P4 is OK down to 8-byte alignment */ 379 movsl_mask.mask = 7; 380 break; 381 } 382 #endif 383 384 intel_smp_check(c); 385 } 386 #else 387 static void intel_workarounds(struct cpuinfo_x86 *c) 388 { 389 } 390 #endif 391 392 static void srat_detect_node(struct cpuinfo_x86 *c) 393 { 394 #ifdef CONFIG_NUMA 395 unsigned node; 396 int cpu = smp_processor_id(); 397 398 /* Don't do the funky fallback heuristics the AMD version employs 399 for now. */ 400 node = numa_cpu_node(cpu); 401 if (node == NUMA_NO_NODE || !node_online(node)) { 402 /* reuse the value from init_cpu_to_node() */ 403 node = cpu_to_node(cpu); 404 } 405 numa_set_node(cpu, node); 406 #endif 407 } 408 409 /* 410 * find out the number of processor cores on the die 411 */ 412 static int intel_num_cpu_cores(struct cpuinfo_x86 *c) 413 { 414 unsigned int eax, ebx, ecx, edx; 415 416 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 417 return 1; 418 419 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 420 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 421 if (eax & 0x1f) 422 return (eax >> 26) + 1; 423 else 424 return 1; 425 } 426 427 static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 428 { 429 /* Intel VMX MSR indicated features */ 430 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 431 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 432 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 433 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 434 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 435 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 436 437 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 438 439 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 440 clear_cpu_cap(c, X86_FEATURE_VNMI); 441 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 442 clear_cpu_cap(c, X86_FEATURE_EPT); 443 clear_cpu_cap(c, X86_FEATURE_VPID); 444 445 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 446 msr_ctl = vmx_msr_high | vmx_msr_low; 447 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 448 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 449 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 450 set_cpu_cap(c, X86_FEATURE_VNMI); 451 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 452 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 453 vmx_msr_low, vmx_msr_high); 454 msr_ctl2 = vmx_msr_high | vmx_msr_low; 455 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 456 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 457 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 458 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 459 set_cpu_cap(c, X86_FEATURE_EPT); 460 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 461 set_cpu_cap(c, X86_FEATURE_VPID); 462 } 463 } 464 465 static void init_intel_energy_perf(struct cpuinfo_x86 *c) 466 { 467 u64 epb; 468 469 /* 470 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. 471 * (x86_energy_perf_policy(8) is available to change it at run-time.) 472 */ 473 if (!cpu_has(c, X86_FEATURE_EPB)) 474 return; 475 476 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 477 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) 478 return; 479 480 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); 481 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); 482 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; 483 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 484 } 485 486 static void intel_bsp_resume(struct cpuinfo_x86 *c) 487 { 488 /* 489 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, 490 * so reinitialize it properly like during bootup: 491 */ 492 init_intel_energy_perf(c); 493 } 494 495 static void init_intel(struct cpuinfo_x86 *c) 496 { 497 unsigned int l2 = 0; 498 499 early_init_intel(c); 500 501 intel_workarounds(c); 502 503 /* 504 * Detect the extended topology information if available. This 505 * will reinitialise the initial_apicid which will be used 506 * in init_intel_cacheinfo() 507 */ 508 detect_extended_topology(c); 509 510 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 511 /* 512 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 513 * detection. 514 */ 515 c->x86_max_cores = intel_num_cpu_cores(c); 516 #ifdef CONFIG_X86_32 517 detect_ht(c); 518 #endif 519 } 520 521 l2 = init_intel_cacheinfo(c); 522 523 /* Detect legacy cache sizes if init_intel_cacheinfo did not */ 524 if (l2 == 0) { 525 cpu_detect_cache_sizes(c); 526 l2 = c->x86_cache_size; 527 } 528 529 if (c->cpuid_level > 9) { 530 unsigned eax = cpuid_eax(10); 531 /* Check for version and the number of counters */ 532 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 533 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 534 } 535 536 if (cpu_has(c, X86_FEATURE_XMM2)) 537 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 538 539 if (boot_cpu_has(X86_FEATURE_DS)) { 540 unsigned int l1; 541 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 542 if (!(l1 & (1<<11))) 543 set_cpu_cap(c, X86_FEATURE_BTS); 544 if (!(l1 & (1<<12))) 545 set_cpu_cap(c, X86_FEATURE_PEBS); 546 } 547 548 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 549 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 550 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 551 552 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 553 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 554 set_cpu_bug(c, X86_BUG_MONITOR); 555 556 #ifdef CONFIG_X86_64 557 if (c->x86 == 15) 558 c->x86_cache_alignment = c->x86_clflush_size * 2; 559 if (c->x86 == 6) 560 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 561 #else 562 /* 563 * Names for the Pentium II/Celeron processors 564 * detectable only by also checking the cache size. 565 * Dixon is NOT a Celeron. 566 */ 567 if (c->x86 == 6) { 568 char *p = NULL; 569 570 switch (c->x86_model) { 571 case 5: 572 if (l2 == 0) 573 p = "Celeron (Covington)"; 574 else if (l2 == 256) 575 p = "Mobile Pentium II (Dixon)"; 576 break; 577 578 case 6: 579 if (l2 == 128) 580 p = "Celeron (Mendocino)"; 581 else if (c->x86_mask == 0 || c->x86_mask == 5) 582 p = "Celeron-A"; 583 break; 584 585 case 8: 586 if (l2 == 128) 587 p = "Celeron (Coppermine)"; 588 break; 589 } 590 591 if (p) 592 strcpy(c->x86_model_id, p); 593 } 594 595 if (c->x86 == 15) 596 set_cpu_cap(c, X86_FEATURE_P4); 597 if (c->x86 == 6) 598 set_cpu_cap(c, X86_FEATURE_P3); 599 #endif 600 601 /* Work around errata */ 602 srat_detect_node(c); 603 604 if (cpu_has(c, X86_FEATURE_VMX)) 605 detect_vmx_virtcap(c); 606 607 init_intel_energy_perf(c); 608 609 probe_xeon_phi_r3mwait(c); 610 } 611 612 #ifdef CONFIG_X86_32 613 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 614 { 615 /* 616 * Intel PIII Tualatin. This comes in two flavours. 617 * One has 256kb of cache, the other 512. We have no way 618 * to determine which, so we use a boottime override 619 * for the 512kb model, and assume 256 otherwise. 620 */ 621 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 622 size = 256; 623 624 /* 625 * Intel Quark SoC X1000 contains a 4-way set associative 626 * 16K cache with a 16 byte cache line and 256 lines per tag 627 */ 628 if ((c->x86 == 5) && (c->x86_model == 9)) 629 size = 16; 630 return size; 631 } 632 #endif 633 634 #define TLB_INST_4K 0x01 635 #define TLB_INST_4M 0x02 636 #define TLB_INST_2M_4M 0x03 637 638 #define TLB_INST_ALL 0x05 639 #define TLB_INST_1G 0x06 640 641 #define TLB_DATA_4K 0x11 642 #define TLB_DATA_4M 0x12 643 #define TLB_DATA_2M_4M 0x13 644 #define TLB_DATA_4K_4M 0x14 645 646 #define TLB_DATA_1G 0x16 647 648 #define TLB_DATA0_4K 0x21 649 #define TLB_DATA0_4M 0x22 650 #define TLB_DATA0_2M_4M 0x23 651 652 #define STLB_4K 0x41 653 #define STLB_4K_2M 0x42 654 655 static const struct _tlb_table intel_tlb_table[] = { 656 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 657 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 658 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 659 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 660 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 661 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 662 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 663 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 664 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 665 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 666 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 667 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 668 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 669 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 670 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 671 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 672 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 673 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 674 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 675 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 676 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 677 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 678 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 679 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 680 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 681 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 682 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 683 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 684 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 685 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 686 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 687 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 688 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 689 { 0x00, 0, 0 } 690 }; 691 692 static void intel_tlb_lookup(const unsigned char desc) 693 { 694 unsigned char k; 695 if (desc == 0) 696 return; 697 698 /* look up this descriptor in the table */ 699 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 700 intel_tlb_table[k].descriptor != 0; k++) 701 ; 702 703 if (intel_tlb_table[k].tlb_type == 0) 704 return; 705 706 switch (intel_tlb_table[k].tlb_type) { 707 case STLB_4K: 708 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 709 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 710 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 711 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 712 break; 713 case STLB_4K_2M: 714 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 715 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 716 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 717 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 718 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 719 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 720 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 721 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 722 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 723 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 724 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 725 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 726 break; 727 case TLB_INST_ALL: 728 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 729 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 730 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 731 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 732 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 733 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 734 break; 735 case TLB_INST_4K: 736 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 737 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 738 break; 739 case TLB_INST_4M: 740 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 741 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 742 break; 743 case TLB_INST_2M_4M: 744 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 745 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 746 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 747 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 748 break; 749 case TLB_DATA_4K: 750 case TLB_DATA0_4K: 751 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 752 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 753 break; 754 case TLB_DATA_4M: 755 case TLB_DATA0_4M: 756 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 757 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 758 break; 759 case TLB_DATA_2M_4M: 760 case TLB_DATA0_2M_4M: 761 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 762 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 763 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 764 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 765 break; 766 case TLB_DATA_4K_4M: 767 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 768 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 769 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 770 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 771 break; 772 case TLB_DATA_1G: 773 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 774 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 775 break; 776 } 777 } 778 779 static void intel_detect_tlb(struct cpuinfo_x86 *c) 780 { 781 int i, j, n; 782 unsigned int regs[4]; 783 unsigned char *desc = (unsigned char *)regs; 784 785 if (c->cpuid_level < 2) 786 return; 787 788 /* Number of times to iterate */ 789 n = cpuid_eax(2) & 0xFF; 790 791 for (i = 0 ; i < n ; i++) { 792 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 793 794 /* If bit 31 is set, this is an unknown format */ 795 for (j = 0 ; j < 3 ; j++) 796 if (regs[j] & (1 << 31)) 797 regs[j] = 0; 798 799 /* Byte 0 is level count, not a descriptor */ 800 for (j = 1 ; j < 16 ; j++) 801 intel_tlb_lookup(desc[j]); 802 } 803 } 804 805 static const struct cpu_dev intel_cpu_dev = { 806 .c_vendor = "Intel", 807 .c_ident = { "GenuineIntel" }, 808 #ifdef CONFIG_X86_32 809 .legacy_models = { 810 { .family = 4, .model_names = 811 { 812 [0] = "486 DX-25/33", 813 [1] = "486 DX-50", 814 [2] = "486 SX", 815 [3] = "486 DX/2", 816 [4] = "486 SL", 817 [5] = "486 SX/2", 818 [7] = "486 DX/2-WB", 819 [8] = "486 DX/4", 820 [9] = "486 DX/4-WB" 821 } 822 }, 823 { .family = 5, .model_names = 824 { 825 [0] = "Pentium 60/66 A-step", 826 [1] = "Pentium 60/66", 827 [2] = "Pentium 75 - 200", 828 [3] = "OverDrive PODP5V83", 829 [4] = "Pentium MMX", 830 [7] = "Mobile Pentium 75 - 200", 831 [8] = "Mobile Pentium MMX", 832 [9] = "Quark SoC X1000", 833 } 834 }, 835 { .family = 6, .model_names = 836 { 837 [0] = "Pentium Pro A-step", 838 [1] = "Pentium Pro", 839 [3] = "Pentium II (Klamath)", 840 [4] = "Pentium II (Deschutes)", 841 [5] = "Pentium II (Deschutes)", 842 [6] = "Mobile Pentium II", 843 [7] = "Pentium III (Katmai)", 844 [8] = "Pentium III (Coppermine)", 845 [10] = "Pentium III (Cascades)", 846 [11] = "Pentium III (Tualatin)", 847 } 848 }, 849 { .family = 15, .model_names = 850 { 851 [0] = "Pentium 4 (Unknown)", 852 [1] = "Pentium 4 (Willamette)", 853 [2] = "Pentium 4 (Northwood)", 854 [4] = "Pentium 4 (Foster)", 855 [5] = "Pentium 4 (Foster)", 856 } 857 }, 858 }, 859 .legacy_cache_size = intel_size_cache, 860 #endif 861 .c_detect_tlb = intel_detect_tlb, 862 .c_early_init = early_init_intel, 863 .c_init = init_intel, 864 .c_bsp_resume = intel_bsp_resume, 865 .c_x86_vendor = X86_VENDOR_INTEL, 866 }; 867 868 cpu_dev_register(intel_cpu_dev); 869 870