1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/kernel.h> 3 4 #include <linux/string.h> 5 #include <linux/bitops.h> 6 #include <linux/smp.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/thread_info.h> 10 #include <linux/init.h> 11 #include <linux/uaccess.h> 12 13 #include <asm/cpufeature.h> 14 #include <asm/pgtable.h> 15 #include <asm/msr.h> 16 #include <asm/bugs.h> 17 #include <asm/cpu.h> 18 #include <asm/intel-family.h> 19 #include <asm/microcode_intel.h> 20 #include <asm/hwcap2.h> 21 #include <asm/elf.h> 22 23 #ifdef CONFIG_X86_64 24 #include <linux/topology.h> 25 #endif 26 27 #include "cpu.h" 28 29 #ifdef CONFIG_X86_LOCAL_APIC 30 #include <asm/mpspec.h> 31 #include <asm/apic.h> 32 #endif 33 34 /* 35 * Just in case our CPU detection goes bad, or you have a weird system, 36 * allow a way to override the automatic disabling of MPX. 37 */ 38 static int forcempx; 39 40 static int __init forcempx_setup(char *__unused) 41 { 42 forcempx = 1; 43 44 return 1; 45 } 46 __setup("intel-skd-046-workaround=disable", forcempx_setup); 47 48 void check_mpx_erratum(struct cpuinfo_x86 *c) 49 { 50 if (forcempx) 51 return; 52 /* 53 * Turn off the MPX feature on CPUs where SMEP is not 54 * available or disabled. 55 * 56 * Works around Intel Erratum SKD046: "Branch Instructions 57 * May Initialize MPX Bound Registers Incorrectly". 58 * 59 * This might falsely disable MPX on systems without 60 * SMEP, like Atom processors without SMEP. But there 61 * is no such hardware known at the moment. 62 */ 63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { 64 setup_clear_cpu_cap(X86_FEATURE_MPX); 65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); 66 } 67 } 68 69 static bool ring3mwait_disabled __read_mostly; 70 71 static int __init ring3mwait_disable(char *__unused) 72 { 73 ring3mwait_disabled = true; 74 return 0; 75 } 76 __setup("ring3mwait=disable", ring3mwait_disable); 77 78 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 79 { 80 /* 81 * Ring 3 MONITOR/MWAIT feature cannot be detected without 82 * cpu model and family comparison. 83 */ 84 if (c->x86 != 6) 85 return; 86 switch (c->x86_model) { 87 case INTEL_FAM6_XEON_PHI_KNL: 88 case INTEL_FAM6_XEON_PHI_KNM: 89 break; 90 default: 91 return; 92 } 93 94 if (ring3mwait_disabled) 95 return; 96 97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 98 this_cpu_or(msr_misc_features_shadow, 99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 100 101 if (c == &boot_cpu_data) 102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 103 } 104 105 /* 106 * Early microcode releases for the Spectre v2 mitigation were broken. 107 * Information taken from; 108 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf 109 * - https://kb.vmware.com/s/article/52345 110 * - Microcode revisions observed in the wild 111 * - Release note from 20180108 microcode release 112 */ 113 struct sku_microcode { 114 u8 model; 115 u8 stepping; 116 u32 microcode; 117 }; 118 static const struct sku_microcode spectre_bad_microcodes[] = { 119 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 }, 120 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 }, 121 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 }, 122 { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 }, 123 { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 }, 124 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, 125 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, 126 { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 }, 127 { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b }, 128 { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 }, 129 { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 }, 130 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, 131 { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 }, 132 { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 }, 133 { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 }, 134 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, 135 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, 136 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, 137 /* Observed in the wild */ 138 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, 139 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, 140 }; 141 142 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 143 { 144 int i; 145 146 /* 147 * We know that the hypervisor lie to us on the microcode version so 148 * we may as well hope that it is running the correct version. 149 */ 150 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 151 return false; 152 153 if (c->x86 != 6) 154 return false; 155 156 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 157 if (c->x86_model == spectre_bad_microcodes[i].model && 158 c->x86_stepping == spectre_bad_microcodes[i].stepping) 159 return (c->microcode <= spectre_bad_microcodes[i].microcode); 160 } 161 return false; 162 } 163 164 static void early_init_intel(struct cpuinfo_x86 *c) 165 { 166 u64 misc_enable; 167 168 /* Unmask CPUID levels if masked: */ 169 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 170 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 171 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 172 c->cpuid_level = cpuid_eax(0); 173 get_cpu_cap(c); 174 } 175 } 176 177 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 178 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 179 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 180 181 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 182 c->microcode = intel_get_microcode_revision(); 183 184 /* Now if any of them are set, check the blacklist and clear the lot */ 185 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 186 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 187 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 188 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 189 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 190 setup_clear_cpu_cap(X86_FEATURE_IBRS); 191 setup_clear_cpu_cap(X86_FEATURE_IBPB); 192 setup_clear_cpu_cap(X86_FEATURE_STIBP); 193 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 194 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); 195 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 196 setup_clear_cpu_cap(X86_FEATURE_SSBD); 197 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); 198 } 199 200 /* 201 * Atom erratum AAE44/AAF40/AAG38/AAH41: 202 * 203 * A race condition between speculative fetches and invalidating 204 * a large page. This is worked around in microcode, but we 205 * need the microcode to have already been loaded... so if it is 206 * not, recommend a BIOS update and disable large pages. 207 */ 208 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && 209 c->microcode < 0x20e) { 210 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 211 clear_cpu_cap(c, X86_FEATURE_PSE); 212 } 213 214 #ifdef CONFIG_X86_64 215 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 216 #else 217 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 218 if (c->x86 == 15 && c->x86_cache_alignment == 64) 219 c->x86_cache_alignment = 128; 220 #endif 221 222 /* CPUID workaround for 0F33/0F34 CPU */ 223 if (c->x86 == 0xF && c->x86_model == 0x3 224 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 225 c->x86_phys_bits = 36; 226 227 /* 228 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 229 * with P/T states and does not stop in deep C-states. 230 * 231 * It is also reliable across cores and sockets. (but not across 232 * cabinets - we turn it off in that case explicitly.) 233 */ 234 if (c->x86_power & (1 << 8)) { 235 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 236 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 237 } 238 239 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 240 if (c->x86 == 6) { 241 switch (c->x86_model) { 242 case 0x27: /* Penwell */ 243 case 0x35: /* Cloverview */ 244 case 0x4a: /* Merrifield */ 245 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 246 break; 247 default: 248 break; 249 } 250 } 251 252 /* 253 * There is a known erratum on Pentium III and Core Solo 254 * and Core Duo CPUs. 255 * " Page with PAT set to WC while associated MTRR is UC 256 * may consolidate to UC " 257 * Because of this erratum, it is better to stick with 258 * setting WC in MTRR rather than using PAT on these CPUs. 259 * 260 * Enable PAT WC only on P4, Core 2 or later CPUs. 261 */ 262 if (c->x86 == 6 && c->x86_model < 15) 263 clear_cpu_cap(c, X86_FEATURE_PAT); 264 265 /* 266 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 267 * clear the fast string and enhanced fast string CPU capabilities. 268 */ 269 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 270 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 271 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 272 pr_info("Disabled fast string operations\n"); 273 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 274 setup_clear_cpu_cap(X86_FEATURE_ERMS); 275 } 276 } 277 278 /* 279 * Intel Quark Core DevMan_001.pdf section 6.4.11 280 * "The operating system also is required to invalidate (i.e., flush) 281 * the TLB when any changes are made to any of the page table entries. 282 * The operating system must reload CR3 to cause the TLB to be flushed" 283 * 284 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 285 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 286 * to be modified. 287 */ 288 if (c->x86 == 5 && c->x86_model == 9) { 289 pr_info("Disabling PGE capability bit\n"); 290 setup_clear_cpu_cap(X86_FEATURE_PGE); 291 } 292 293 if (c->cpuid_level >= 0x00000001) { 294 u32 eax, ebx, ecx, edx; 295 296 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 297 /* 298 * If HTT (EDX[28]) is set EBX[16:23] contain the number of 299 * apicids which are reserved per package. Store the resulting 300 * shift value for the package management code. 301 */ 302 if (edx & (1U << 28)) 303 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); 304 } 305 306 check_mpx_erratum(c); 307 308 /* 309 * Get the number of SMT siblings early from the extended topology 310 * leaf, if available. Otherwise try the legacy SMT detection. 311 */ 312 if (detect_extended_topology_early(c) < 0) 313 detect_ht_early(c); 314 } 315 316 #ifdef CONFIG_X86_32 317 /* 318 * Early probe support logic for ppro memory erratum #50 319 * 320 * This is called before we do cpu ident work 321 */ 322 323 int ppro_with_ram_bug(void) 324 { 325 /* Uses data from early_cpu_detect now */ 326 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 327 boot_cpu_data.x86 == 6 && 328 boot_cpu_data.x86_model == 1 && 329 boot_cpu_data.x86_stepping < 8) { 330 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 331 return 1; 332 } 333 return 0; 334 } 335 336 static void intel_smp_check(struct cpuinfo_x86 *c) 337 { 338 /* calling is from identify_secondary_cpu() ? */ 339 if (!c->cpu_index) 340 return; 341 342 /* 343 * Mask B, Pentium, but not Pentium MMX 344 */ 345 if (c->x86 == 5 && 346 c->x86_stepping >= 1 && c->x86_stepping <= 4 && 347 c->x86_model <= 3) { 348 /* 349 * Remember we have B step Pentia with bugs 350 */ 351 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 352 "with B stepping processors.\n"); 353 } 354 } 355 356 static int forcepae; 357 static int __init forcepae_setup(char *__unused) 358 { 359 forcepae = 1; 360 return 1; 361 } 362 __setup("forcepae", forcepae_setup); 363 364 static void intel_workarounds(struct cpuinfo_x86 *c) 365 { 366 #ifdef CONFIG_X86_F00F_BUG 367 /* 368 * All models of Pentium and Pentium with MMX technology CPUs 369 * have the F0 0F bug, which lets nonprivileged users lock up the 370 * system. Announce that the fault handler will be checking for it. 371 * The Quark is also family 5, but does not have the same bug. 372 */ 373 clear_cpu_bug(c, X86_BUG_F00F); 374 if (c->x86 == 5 && c->x86_model < 9) { 375 static int f00f_workaround_enabled; 376 377 set_cpu_bug(c, X86_BUG_F00F); 378 if (!f00f_workaround_enabled) { 379 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 380 f00f_workaround_enabled = 1; 381 } 382 } 383 #endif 384 385 /* 386 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 387 * model 3 mask 3 388 */ 389 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) 390 clear_cpu_cap(c, X86_FEATURE_SEP); 391 392 /* 393 * PAE CPUID issue: many Pentium M report no PAE but may have a 394 * functionally usable PAE implementation. 395 * Forcefully enable PAE if kernel parameter "forcepae" is present. 396 */ 397 if (forcepae) { 398 pr_warn("PAE forced!\n"); 399 set_cpu_cap(c, X86_FEATURE_PAE); 400 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 401 } 402 403 /* 404 * P4 Xeon erratum 037 workaround. 405 * Hardware prefetcher may cause stale data to be loaded into the cache. 406 */ 407 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { 408 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 409 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 410 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 411 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 412 } 413 } 414 415 /* 416 * See if we have a good local APIC by checking for buggy Pentia, 417 * i.e. all B steppings and the C2 stepping of P54C when using their 418 * integrated APIC (see 11AP erratum in "Pentium Processor 419 * Specification Update"). 420 */ 421 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 422 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 423 set_cpu_bug(c, X86_BUG_11AP); 424 425 426 #ifdef CONFIG_X86_INTEL_USERCOPY 427 /* 428 * Set up the preferred alignment for movsl bulk memory moves 429 */ 430 switch (c->x86) { 431 case 4: /* 486: untested */ 432 break; 433 case 5: /* Old Pentia: untested */ 434 break; 435 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 436 movsl_mask.mask = 7; 437 break; 438 case 15: /* P4 is OK down to 8-byte alignment */ 439 movsl_mask.mask = 7; 440 break; 441 } 442 #endif 443 444 intel_smp_check(c); 445 } 446 #else 447 static void intel_workarounds(struct cpuinfo_x86 *c) 448 { 449 } 450 #endif 451 452 static void srat_detect_node(struct cpuinfo_x86 *c) 453 { 454 #ifdef CONFIG_NUMA 455 unsigned node; 456 int cpu = smp_processor_id(); 457 458 /* Don't do the funky fallback heuristics the AMD version employs 459 for now. */ 460 node = numa_cpu_node(cpu); 461 if (node == NUMA_NO_NODE || !node_online(node)) { 462 /* reuse the value from init_cpu_to_node() */ 463 node = cpu_to_node(cpu); 464 } 465 numa_set_node(cpu, node); 466 #endif 467 } 468 469 static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 470 { 471 /* Intel VMX MSR indicated features */ 472 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 473 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 474 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 475 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 476 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 477 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 478 #define x86_VMX_FEATURE_EPT_CAP_AD 0x00200000 479 480 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 481 u32 msr_vpid_cap, msr_ept_cap; 482 483 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 484 clear_cpu_cap(c, X86_FEATURE_VNMI); 485 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 486 clear_cpu_cap(c, X86_FEATURE_EPT); 487 clear_cpu_cap(c, X86_FEATURE_VPID); 488 clear_cpu_cap(c, X86_FEATURE_EPT_AD); 489 490 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 491 msr_ctl = vmx_msr_high | vmx_msr_low; 492 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 493 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 494 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 495 set_cpu_cap(c, X86_FEATURE_VNMI); 496 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 497 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 498 vmx_msr_low, vmx_msr_high); 499 msr_ctl2 = vmx_msr_high | vmx_msr_low; 500 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 501 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 502 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 503 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) { 504 set_cpu_cap(c, X86_FEATURE_EPT); 505 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, 506 msr_ept_cap, msr_vpid_cap); 507 if (msr_ept_cap & x86_VMX_FEATURE_EPT_CAP_AD) 508 set_cpu_cap(c, X86_FEATURE_EPT_AD); 509 } 510 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 511 set_cpu_cap(c, X86_FEATURE_VPID); 512 } 513 } 514 515 #define MSR_IA32_TME_ACTIVATE 0x982 516 517 /* Helpers to access TME_ACTIVATE MSR */ 518 #define TME_ACTIVATE_LOCKED(x) (x & 0x1) 519 #define TME_ACTIVATE_ENABLED(x) (x & 0x2) 520 521 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ 522 #define TME_ACTIVATE_POLICY_AES_XTS_128 0 523 524 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ 525 526 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ 527 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 528 529 /* Values for mktme_status (SW only construct) */ 530 #define MKTME_ENABLED 0 531 #define MKTME_DISABLED 1 532 #define MKTME_UNINITIALIZED 2 533 static int mktme_status = MKTME_UNINITIALIZED; 534 535 static void detect_tme(struct cpuinfo_x86 *c) 536 { 537 u64 tme_activate, tme_policy, tme_crypto_algs; 538 int keyid_bits = 0, nr_keyids = 0; 539 static u64 tme_activate_cpu0 = 0; 540 541 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); 542 543 if (mktme_status != MKTME_UNINITIALIZED) { 544 if (tme_activate != tme_activate_cpu0) { 545 /* Broken BIOS? */ 546 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); 547 pr_err_once("x86/tme: MKTME is not usable\n"); 548 mktme_status = MKTME_DISABLED; 549 550 /* Proceed. We may need to exclude bits from x86_phys_bits. */ 551 } 552 } else { 553 tme_activate_cpu0 = tme_activate; 554 } 555 556 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 557 pr_info_once("x86/tme: not enabled by BIOS\n"); 558 mktme_status = MKTME_DISABLED; 559 return; 560 } 561 562 if (mktme_status != MKTME_UNINITIALIZED) 563 goto detect_keyid_bits; 564 565 pr_info("x86/tme: enabled by BIOS\n"); 566 567 tme_policy = TME_ACTIVATE_POLICY(tme_activate); 568 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128) 569 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); 570 571 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate); 572 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { 573 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", 574 tme_crypto_algs); 575 mktme_status = MKTME_DISABLED; 576 } 577 detect_keyid_bits: 578 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); 579 nr_keyids = (1UL << keyid_bits) - 1; 580 if (nr_keyids) { 581 pr_info_once("x86/mktme: enabled by BIOS\n"); 582 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); 583 } else { 584 pr_info_once("x86/mktme: disabled by BIOS\n"); 585 } 586 587 if (mktme_status == MKTME_UNINITIALIZED) { 588 /* MKTME is usable */ 589 mktme_status = MKTME_ENABLED; 590 } 591 592 /* 593 * KeyID bits effectively lower the number of physical address 594 * bits. Update cpuinfo_x86::x86_phys_bits accordingly. 595 */ 596 c->x86_phys_bits -= keyid_bits; 597 } 598 599 static void init_cpuid_fault(struct cpuinfo_x86 *c) 600 { 601 u64 msr; 602 603 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 604 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 605 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 606 } 607 } 608 609 static void init_intel_misc_features(struct cpuinfo_x86 *c) 610 { 611 u64 msr; 612 613 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 614 return; 615 616 /* Clear all MISC features */ 617 this_cpu_write(msr_misc_features_shadow, 0); 618 619 /* Check features and update capabilities and shadow control bits */ 620 init_cpuid_fault(c); 621 probe_xeon_phi_r3mwait(c); 622 623 msr = this_cpu_read(msr_misc_features_shadow); 624 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 625 } 626 627 static void init_intel(struct cpuinfo_x86 *c) 628 { 629 early_init_intel(c); 630 631 intel_workarounds(c); 632 633 /* 634 * Detect the extended topology information if available. This 635 * will reinitialise the initial_apicid which will be used 636 * in init_intel_cacheinfo() 637 */ 638 detect_extended_topology(c); 639 640 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 641 /* 642 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 643 * detection. 644 */ 645 detect_num_cpu_cores(c); 646 #ifdef CONFIG_X86_32 647 detect_ht(c); 648 #endif 649 } 650 651 init_intel_cacheinfo(c); 652 653 if (c->cpuid_level > 9) { 654 unsigned eax = cpuid_eax(10); 655 /* Check for version and the number of counters */ 656 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 657 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 658 } 659 660 if (cpu_has(c, X86_FEATURE_XMM2)) 661 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 662 663 if (boot_cpu_has(X86_FEATURE_DS)) { 664 unsigned int l1, l2; 665 666 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 667 if (!(l1 & (1<<11))) 668 set_cpu_cap(c, X86_FEATURE_BTS); 669 if (!(l1 & (1<<12))) 670 set_cpu_cap(c, X86_FEATURE_PEBS); 671 } 672 673 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 674 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 675 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 676 677 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 678 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 679 set_cpu_bug(c, X86_BUG_MONITOR); 680 681 #ifdef CONFIG_X86_64 682 if (c->x86 == 15) 683 c->x86_cache_alignment = c->x86_clflush_size * 2; 684 if (c->x86 == 6) 685 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 686 #else 687 /* 688 * Names for the Pentium II/Celeron processors 689 * detectable only by also checking the cache size. 690 * Dixon is NOT a Celeron. 691 */ 692 if (c->x86 == 6) { 693 unsigned int l2 = c->x86_cache_size; 694 char *p = NULL; 695 696 switch (c->x86_model) { 697 case 5: 698 if (l2 == 0) 699 p = "Celeron (Covington)"; 700 else if (l2 == 256) 701 p = "Mobile Pentium II (Dixon)"; 702 break; 703 704 case 6: 705 if (l2 == 128) 706 p = "Celeron (Mendocino)"; 707 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 708 p = "Celeron-A"; 709 break; 710 711 case 8: 712 if (l2 == 128) 713 p = "Celeron (Coppermine)"; 714 break; 715 } 716 717 if (p) 718 strcpy(c->x86_model_id, p); 719 } 720 721 if (c->x86 == 15) 722 set_cpu_cap(c, X86_FEATURE_P4); 723 if (c->x86 == 6) 724 set_cpu_cap(c, X86_FEATURE_P3); 725 #endif 726 727 /* Work around errata */ 728 srat_detect_node(c); 729 730 if (cpu_has(c, X86_FEATURE_VMX)) 731 detect_vmx_virtcap(c); 732 733 if (cpu_has(c, X86_FEATURE_TME)) 734 detect_tme(c); 735 736 init_intel_misc_features(c); 737 } 738 739 #ifdef CONFIG_X86_32 740 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 741 { 742 /* 743 * Intel PIII Tualatin. This comes in two flavours. 744 * One has 256kb of cache, the other 512. We have no way 745 * to determine which, so we use a boottime override 746 * for the 512kb model, and assume 256 otherwise. 747 */ 748 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 749 size = 256; 750 751 /* 752 * Intel Quark SoC X1000 contains a 4-way set associative 753 * 16K cache with a 16 byte cache line and 256 lines per tag 754 */ 755 if ((c->x86 == 5) && (c->x86_model == 9)) 756 size = 16; 757 return size; 758 } 759 #endif 760 761 #define TLB_INST_4K 0x01 762 #define TLB_INST_4M 0x02 763 #define TLB_INST_2M_4M 0x03 764 765 #define TLB_INST_ALL 0x05 766 #define TLB_INST_1G 0x06 767 768 #define TLB_DATA_4K 0x11 769 #define TLB_DATA_4M 0x12 770 #define TLB_DATA_2M_4M 0x13 771 #define TLB_DATA_4K_4M 0x14 772 773 #define TLB_DATA_1G 0x16 774 775 #define TLB_DATA0_4K 0x21 776 #define TLB_DATA0_4M 0x22 777 #define TLB_DATA0_2M_4M 0x23 778 779 #define STLB_4K 0x41 780 #define STLB_4K_2M 0x42 781 782 static const struct _tlb_table intel_tlb_table[] = { 783 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 784 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 785 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 786 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 787 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 788 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 789 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 790 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 791 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 792 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 793 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 794 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 795 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 796 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 797 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 798 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 799 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 800 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 801 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 802 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 803 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, 804 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, 805 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, 806 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 807 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 808 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 809 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 810 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 811 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 812 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 813 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 814 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 815 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 816 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 817 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 818 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 819 { 0x00, 0, 0 } 820 }; 821 822 static void intel_tlb_lookup(const unsigned char desc) 823 { 824 unsigned char k; 825 if (desc == 0) 826 return; 827 828 /* look up this descriptor in the table */ 829 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 830 intel_tlb_table[k].descriptor != 0; k++) 831 ; 832 833 if (intel_tlb_table[k].tlb_type == 0) 834 return; 835 836 switch (intel_tlb_table[k].tlb_type) { 837 case STLB_4K: 838 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 839 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 840 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 841 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 842 break; 843 case STLB_4K_2M: 844 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 845 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 846 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 847 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 848 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 849 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 850 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 851 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 852 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 853 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 854 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 855 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 856 break; 857 case TLB_INST_ALL: 858 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 859 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 860 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 861 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 862 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 863 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 864 break; 865 case TLB_INST_4K: 866 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 867 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 868 break; 869 case TLB_INST_4M: 870 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 871 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 872 break; 873 case TLB_INST_2M_4M: 874 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 875 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 876 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 877 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 878 break; 879 case TLB_DATA_4K: 880 case TLB_DATA0_4K: 881 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 882 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 883 break; 884 case TLB_DATA_4M: 885 case TLB_DATA0_4M: 886 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 887 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 888 break; 889 case TLB_DATA_2M_4M: 890 case TLB_DATA0_2M_4M: 891 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 892 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 893 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 894 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 895 break; 896 case TLB_DATA_4K_4M: 897 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 898 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 899 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 900 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 901 break; 902 case TLB_DATA_1G: 903 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 904 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 905 break; 906 } 907 } 908 909 static void intel_detect_tlb(struct cpuinfo_x86 *c) 910 { 911 int i, j, n; 912 unsigned int regs[4]; 913 unsigned char *desc = (unsigned char *)regs; 914 915 if (c->cpuid_level < 2) 916 return; 917 918 /* Number of times to iterate */ 919 n = cpuid_eax(2) & 0xFF; 920 921 for (i = 0 ; i < n ; i++) { 922 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 923 924 /* If bit 31 is set, this is an unknown format */ 925 for (j = 0 ; j < 3 ; j++) 926 if (regs[j] & (1 << 31)) 927 regs[j] = 0; 928 929 /* Byte 0 is level count, not a descriptor */ 930 for (j = 1 ; j < 16 ; j++) 931 intel_tlb_lookup(desc[j]); 932 } 933 } 934 935 static const struct cpu_dev intel_cpu_dev = { 936 .c_vendor = "Intel", 937 .c_ident = { "GenuineIntel" }, 938 #ifdef CONFIG_X86_32 939 .legacy_models = { 940 { .family = 4, .model_names = 941 { 942 [0] = "486 DX-25/33", 943 [1] = "486 DX-50", 944 [2] = "486 SX", 945 [3] = "486 DX/2", 946 [4] = "486 SL", 947 [5] = "486 SX/2", 948 [7] = "486 DX/2-WB", 949 [8] = "486 DX/4", 950 [9] = "486 DX/4-WB" 951 } 952 }, 953 { .family = 5, .model_names = 954 { 955 [0] = "Pentium 60/66 A-step", 956 [1] = "Pentium 60/66", 957 [2] = "Pentium 75 - 200", 958 [3] = "OverDrive PODP5V83", 959 [4] = "Pentium MMX", 960 [7] = "Mobile Pentium 75 - 200", 961 [8] = "Mobile Pentium MMX", 962 [9] = "Quark SoC X1000", 963 } 964 }, 965 { .family = 6, .model_names = 966 { 967 [0] = "Pentium Pro A-step", 968 [1] = "Pentium Pro", 969 [3] = "Pentium II (Klamath)", 970 [4] = "Pentium II (Deschutes)", 971 [5] = "Pentium II (Deschutes)", 972 [6] = "Mobile Pentium II", 973 [7] = "Pentium III (Katmai)", 974 [8] = "Pentium III (Coppermine)", 975 [10] = "Pentium III (Cascades)", 976 [11] = "Pentium III (Tualatin)", 977 } 978 }, 979 { .family = 15, .model_names = 980 { 981 [0] = "Pentium 4 (Unknown)", 982 [1] = "Pentium 4 (Willamette)", 983 [2] = "Pentium 4 (Northwood)", 984 [4] = "Pentium 4 (Foster)", 985 [5] = "Pentium 4 (Foster)", 986 } 987 }, 988 }, 989 .legacy_cache_size = intel_size_cache, 990 #endif 991 .c_detect_tlb = intel_detect_tlb, 992 .c_early_init = early_init_intel, 993 .c_init = init_intel, 994 .c_x86_vendor = X86_VENDOR_INTEL, 995 }; 996 997 cpu_dev_register(intel_cpu_dev); 998