1 #include <linux/kernel.h> 2 3 #include <linux/string.h> 4 #include <linux/bitops.h> 5 #include <linux/smp.h> 6 #include <linux/sched.h> 7 #include <linux/thread_info.h> 8 #include <linux/init.h> 9 #include <linux/uaccess.h> 10 11 #include <asm/cpufeature.h> 12 #include <asm/pgtable.h> 13 #include <asm/msr.h> 14 #include <asm/bugs.h> 15 #include <asm/cpu.h> 16 #include <asm/intel-family.h> 17 #include <asm/microcode_intel.h> 18 19 #ifdef CONFIG_X86_64 20 #include <linux/topology.h> 21 #endif 22 23 #include "cpu.h" 24 25 #ifdef CONFIG_X86_LOCAL_APIC 26 #include <asm/mpspec.h> 27 #include <asm/apic.h> 28 #endif 29 30 /* 31 * Just in case our CPU detection goes bad, or you have a weird system, 32 * allow a way to override the automatic disabling of MPX. 33 */ 34 static int forcempx; 35 36 static int __init forcempx_setup(char *__unused) 37 { 38 forcempx = 1; 39 40 return 1; 41 } 42 __setup("intel-skd-046-workaround=disable", forcempx_setup); 43 44 void check_mpx_erratum(struct cpuinfo_x86 *c) 45 { 46 if (forcempx) 47 return; 48 /* 49 * Turn off the MPX feature on CPUs where SMEP is not 50 * available or disabled. 51 * 52 * Works around Intel Erratum SKD046: "Branch Instructions 53 * May Initialize MPX Bound Registers Incorrectly". 54 * 55 * This might falsely disable MPX on systems without 56 * SMEP, like Atom processors without SMEP. But there 57 * is no such hardware known at the moment. 58 */ 59 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { 60 setup_clear_cpu_cap(X86_FEATURE_MPX); 61 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); 62 } 63 } 64 65 static void early_init_intel(struct cpuinfo_x86 *c) 66 { 67 u64 misc_enable; 68 69 /* Unmask CPUID levels if masked: */ 70 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 71 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 72 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 73 c->cpuid_level = cpuid_eax(0); 74 get_cpu_cap(c); 75 } 76 } 77 78 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 79 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 80 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 81 82 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 83 c->microcode = intel_get_microcode_revision(); 84 85 /* 86 * Atom erratum AAE44/AAF40/AAG38/AAH41: 87 * 88 * A race condition between speculative fetches and invalidating 89 * a large page. This is worked around in microcode, but we 90 * need the microcode to have already been loaded... so if it is 91 * not, recommend a BIOS update and disable large pages. 92 */ 93 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && 94 c->microcode < 0x20e) { 95 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 96 clear_cpu_cap(c, X86_FEATURE_PSE); 97 } 98 99 #ifdef CONFIG_X86_64 100 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 101 #else 102 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 103 if (c->x86 == 15 && c->x86_cache_alignment == 64) 104 c->x86_cache_alignment = 128; 105 #endif 106 107 /* CPUID workaround for 0F33/0F34 CPU */ 108 if (c->x86 == 0xF && c->x86_model == 0x3 109 && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) 110 c->x86_phys_bits = 36; 111 112 /* 113 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 114 * with P/T states and does not stop in deep C-states. 115 * 116 * It is also reliable across cores and sockets. (but not across 117 * cabinets - we turn it off in that case explicitly.) 118 */ 119 if (c->x86_power & (1 << 8)) { 120 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 121 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 122 if (!check_tsc_unstable()) 123 set_sched_clock_stable(); 124 } 125 126 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 127 if (c->x86 == 6) { 128 switch (c->x86_model) { 129 case 0x27: /* Penwell */ 130 case 0x35: /* Cloverview */ 131 case 0x4a: /* Merrifield */ 132 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 133 break; 134 default: 135 break; 136 } 137 } 138 139 /* 140 * There is a known erratum on Pentium III and Core Solo 141 * and Core Duo CPUs. 142 * " Page with PAT set to WC while associated MTRR is UC 143 * may consolidate to UC " 144 * Because of this erratum, it is better to stick with 145 * setting WC in MTRR rather than using PAT on these CPUs. 146 * 147 * Enable PAT WC only on P4, Core 2 or later CPUs. 148 */ 149 if (c->x86 == 6 && c->x86_model < 15) 150 clear_cpu_cap(c, X86_FEATURE_PAT); 151 152 #ifdef CONFIG_KMEMCHECK 153 /* 154 * P4s have a "fast strings" feature which causes single- 155 * stepping REP instructions to only generate a #DB on 156 * cache-line boundaries. 157 * 158 * Ingo Molnar reported a Pentium D (model 6) and a Xeon 159 * (model 2) with the same problem. 160 */ 161 if (c->x86 == 15) 162 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 163 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) 164 pr_info("kmemcheck: Disabling fast string operations\n"); 165 #endif 166 167 /* 168 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 169 * clear the fast string and enhanced fast string CPU capabilities. 170 */ 171 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 172 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 173 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 174 pr_info("Disabled fast string operations\n"); 175 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 176 setup_clear_cpu_cap(X86_FEATURE_ERMS); 177 } 178 } 179 180 /* 181 * Intel Quark Core DevMan_001.pdf section 6.4.11 182 * "The operating system also is required to invalidate (i.e., flush) 183 * the TLB when any changes are made to any of the page table entries. 184 * The operating system must reload CR3 to cause the TLB to be flushed" 185 * 186 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 187 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 188 * to be modified. 189 */ 190 if (c->x86 == 5 && c->x86_model == 9) { 191 pr_info("Disabling PGE capability bit\n"); 192 setup_clear_cpu_cap(X86_FEATURE_PGE); 193 } 194 195 if (c->cpuid_level >= 0x00000001) { 196 u32 eax, ebx, ecx, edx; 197 198 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 199 /* 200 * If HTT (EDX[28]) is set EBX[16:23] contain the number of 201 * apicids which are reserved per package. Store the resulting 202 * shift value for the package management code. 203 */ 204 if (edx & (1U << 28)) 205 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); 206 } 207 208 check_mpx_erratum(c); 209 } 210 211 #ifdef CONFIG_X86_32 212 /* 213 * Early probe support logic for ppro memory erratum #50 214 * 215 * This is called before we do cpu ident work 216 */ 217 218 int ppro_with_ram_bug(void) 219 { 220 /* Uses data from early_cpu_detect now */ 221 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 222 boot_cpu_data.x86 == 6 && 223 boot_cpu_data.x86_model == 1 && 224 boot_cpu_data.x86_mask < 8) { 225 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 226 return 1; 227 } 228 return 0; 229 } 230 231 static void intel_smp_check(struct cpuinfo_x86 *c) 232 { 233 /* calling is from identify_secondary_cpu() ? */ 234 if (!c->cpu_index) 235 return; 236 237 /* 238 * Mask B, Pentium, but not Pentium MMX 239 */ 240 if (c->x86 == 5 && 241 c->x86_mask >= 1 && c->x86_mask <= 4 && 242 c->x86_model <= 3) { 243 /* 244 * Remember we have B step Pentia with bugs 245 */ 246 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 247 "with B stepping processors.\n"); 248 } 249 } 250 251 static int forcepae; 252 static int __init forcepae_setup(char *__unused) 253 { 254 forcepae = 1; 255 return 1; 256 } 257 __setup("forcepae", forcepae_setup); 258 259 static void intel_workarounds(struct cpuinfo_x86 *c) 260 { 261 #ifdef CONFIG_X86_F00F_BUG 262 /* 263 * All models of Pentium and Pentium with MMX technology CPUs 264 * have the F0 0F bug, which lets nonprivileged users lock up the 265 * system. Announce that the fault handler will be checking for it. 266 * The Quark is also family 5, but does not have the same bug. 267 */ 268 clear_cpu_bug(c, X86_BUG_F00F); 269 if (c->x86 == 5 && c->x86_model < 9) { 270 static int f00f_workaround_enabled; 271 272 set_cpu_bug(c, X86_BUG_F00F); 273 if (!f00f_workaround_enabled) { 274 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 275 f00f_workaround_enabled = 1; 276 } 277 } 278 #endif 279 280 /* 281 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 282 * model 3 mask 3 283 */ 284 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 285 clear_cpu_cap(c, X86_FEATURE_SEP); 286 287 /* 288 * PAE CPUID issue: many Pentium M report no PAE but may have a 289 * functionally usable PAE implementation. 290 * Forcefully enable PAE if kernel parameter "forcepae" is present. 291 */ 292 if (forcepae) { 293 pr_warn("PAE forced!\n"); 294 set_cpu_cap(c, X86_FEATURE_PAE); 295 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 296 } 297 298 /* 299 * P4 Xeon erratum 037 workaround. 300 * Hardware prefetcher may cause stale data to be loaded into the cache. 301 */ 302 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 303 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 304 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 305 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 306 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 307 } 308 } 309 310 /* 311 * See if we have a good local APIC by checking for buggy Pentia, 312 * i.e. all B steppings and the C2 stepping of P54C when using their 313 * integrated APIC (see 11AP erratum in "Pentium Processor 314 * Specification Update"). 315 */ 316 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 317 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 318 set_cpu_bug(c, X86_BUG_11AP); 319 320 321 #ifdef CONFIG_X86_INTEL_USERCOPY 322 /* 323 * Set up the preferred alignment for movsl bulk memory moves 324 */ 325 switch (c->x86) { 326 case 4: /* 486: untested */ 327 break; 328 case 5: /* Old Pentia: untested */ 329 break; 330 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 331 movsl_mask.mask = 7; 332 break; 333 case 15: /* P4 is OK down to 8-byte alignment */ 334 movsl_mask.mask = 7; 335 break; 336 } 337 #endif 338 339 intel_smp_check(c); 340 } 341 #else 342 static void intel_workarounds(struct cpuinfo_x86 *c) 343 { 344 } 345 #endif 346 347 static void srat_detect_node(struct cpuinfo_x86 *c) 348 { 349 #ifdef CONFIG_NUMA 350 unsigned node; 351 int cpu = smp_processor_id(); 352 353 /* Don't do the funky fallback heuristics the AMD version employs 354 for now. */ 355 node = numa_cpu_node(cpu); 356 if (node == NUMA_NO_NODE || !node_online(node)) { 357 /* reuse the value from init_cpu_to_node() */ 358 node = cpu_to_node(cpu); 359 } 360 numa_set_node(cpu, node); 361 #endif 362 } 363 364 /* 365 * find out the number of processor cores on the die 366 */ 367 static int intel_num_cpu_cores(struct cpuinfo_x86 *c) 368 { 369 unsigned int eax, ebx, ecx, edx; 370 371 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 372 return 1; 373 374 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 375 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 376 if (eax & 0x1f) 377 return (eax >> 26) + 1; 378 else 379 return 1; 380 } 381 382 static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 383 { 384 /* Intel VMX MSR indicated features */ 385 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 386 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 387 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 388 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 389 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 390 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 391 392 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 393 394 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 395 clear_cpu_cap(c, X86_FEATURE_VNMI); 396 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 397 clear_cpu_cap(c, X86_FEATURE_EPT); 398 clear_cpu_cap(c, X86_FEATURE_VPID); 399 400 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 401 msr_ctl = vmx_msr_high | vmx_msr_low; 402 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 403 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 404 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 405 set_cpu_cap(c, X86_FEATURE_VNMI); 406 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 407 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 408 vmx_msr_low, vmx_msr_high); 409 msr_ctl2 = vmx_msr_high | vmx_msr_low; 410 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 411 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 412 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 413 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 414 set_cpu_cap(c, X86_FEATURE_EPT); 415 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 416 set_cpu_cap(c, X86_FEATURE_VPID); 417 } 418 } 419 420 static void init_intel_energy_perf(struct cpuinfo_x86 *c) 421 { 422 u64 epb; 423 424 /* 425 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. 426 * (x86_energy_perf_policy(8) is available to change it at run-time.) 427 */ 428 if (!cpu_has(c, X86_FEATURE_EPB)) 429 return; 430 431 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 432 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) 433 return; 434 435 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); 436 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); 437 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; 438 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 439 } 440 441 static void intel_bsp_resume(struct cpuinfo_x86 *c) 442 { 443 /* 444 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, 445 * so reinitialize it properly like during bootup: 446 */ 447 init_intel_energy_perf(c); 448 } 449 450 static void init_intel(struct cpuinfo_x86 *c) 451 { 452 unsigned int l2 = 0; 453 454 early_init_intel(c); 455 456 intel_workarounds(c); 457 458 /* 459 * Detect the extended topology information if available. This 460 * will reinitialise the initial_apicid which will be used 461 * in init_intel_cacheinfo() 462 */ 463 detect_extended_topology(c); 464 465 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 466 /* 467 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 468 * detection. 469 */ 470 c->x86_max_cores = intel_num_cpu_cores(c); 471 #ifdef CONFIG_X86_32 472 detect_ht(c); 473 #endif 474 } 475 476 l2 = init_intel_cacheinfo(c); 477 478 /* Detect legacy cache sizes if init_intel_cacheinfo did not */ 479 if (l2 == 0) { 480 cpu_detect_cache_sizes(c); 481 l2 = c->x86_cache_size; 482 } 483 484 if (c->cpuid_level > 9) { 485 unsigned eax = cpuid_eax(10); 486 /* Check for version and the number of counters */ 487 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 488 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 489 } 490 491 if (cpu_has(c, X86_FEATURE_XMM2)) 492 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 493 494 if (boot_cpu_has(X86_FEATURE_DS)) { 495 unsigned int l1; 496 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 497 if (!(l1 & (1<<11))) 498 set_cpu_cap(c, X86_FEATURE_BTS); 499 if (!(l1 & (1<<12))) 500 set_cpu_cap(c, X86_FEATURE_PEBS); 501 } 502 503 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 504 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 505 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 506 507 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 508 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 509 set_cpu_bug(c, X86_BUG_MONITOR); 510 511 #ifdef CONFIG_X86_64 512 if (c->x86 == 15) 513 c->x86_cache_alignment = c->x86_clflush_size * 2; 514 if (c->x86 == 6) 515 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 516 #else 517 /* 518 * Names for the Pentium II/Celeron processors 519 * detectable only by also checking the cache size. 520 * Dixon is NOT a Celeron. 521 */ 522 if (c->x86 == 6) { 523 char *p = NULL; 524 525 switch (c->x86_model) { 526 case 5: 527 if (l2 == 0) 528 p = "Celeron (Covington)"; 529 else if (l2 == 256) 530 p = "Mobile Pentium II (Dixon)"; 531 break; 532 533 case 6: 534 if (l2 == 128) 535 p = "Celeron (Mendocino)"; 536 else if (c->x86_mask == 0 || c->x86_mask == 5) 537 p = "Celeron-A"; 538 break; 539 540 case 8: 541 if (l2 == 128) 542 p = "Celeron (Coppermine)"; 543 break; 544 } 545 546 if (p) 547 strcpy(c->x86_model_id, p); 548 } 549 550 if (c->x86 == 15) 551 set_cpu_cap(c, X86_FEATURE_P4); 552 if (c->x86 == 6) 553 set_cpu_cap(c, X86_FEATURE_P3); 554 #endif 555 556 /* Work around errata */ 557 srat_detect_node(c); 558 559 if (cpu_has(c, X86_FEATURE_VMX)) 560 detect_vmx_virtcap(c); 561 562 init_intel_energy_perf(c); 563 } 564 565 #ifdef CONFIG_X86_32 566 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 567 { 568 /* 569 * Intel PIII Tualatin. This comes in two flavours. 570 * One has 256kb of cache, the other 512. We have no way 571 * to determine which, so we use a boottime override 572 * for the 512kb model, and assume 256 otherwise. 573 */ 574 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 575 size = 256; 576 577 /* 578 * Intel Quark SoC X1000 contains a 4-way set associative 579 * 16K cache with a 16 byte cache line and 256 lines per tag 580 */ 581 if ((c->x86 == 5) && (c->x86_model == 9)) 582 size = 16; 583 return size; 584 } 585 #endif 586 587 #define TLB_INST_4K 0x01 588 #define TLB_INST_4M 0x02 589 #define TLB_INST_2M_4M 0x03 590 591 #define TLB_INST_ALL 0x05 592 #define TLB_INST_1G 0x06 593 594 #define TLB_DATA_4K 0x11 595 #define TLB_DATA_4M 0x12 596 #define TLB_DATA_2M_4M 0x13 597 #define TLB_DATA_4K_4M 0x14 598 599 #define TLB_DATA_1G 0x16 600 601 #define TLB_DATA0_4K 0x21 602 #define TLB_DATA0_4M 0x22 603 #define TLB_DATA0_2M_4M 0x23 604 605 #define STLB_4K 0x41 606 #define STLB_4K_2M 0x42 607 608 static const struct _tlb_table intel_tlb_table[] = { 609 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 610 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 611 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 612 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 613 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 614 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 615 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 616 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 617 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 618 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 619 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 620 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 621 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 622 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 623 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 624 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 625 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 626 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 627 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 628 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 629 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 630 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 631 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 632 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 633 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 634 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 635 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 636 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 637 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 638 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 639 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 640 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 641 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 642 { 0x00, 0, 0 } 643 }; 644 645 static void intel_tlb_lookup(const unsigned char desc) 646 { 647 unsigned char k; 648 if (desc == 0) 649 return; 650 651 /* look up this descriptor in the table */ 652 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 653 intel_tlb_table[k].descriptor != 0; k++) 654 ; 655 656 if (intel_tlb_table[k].tlb_type == 0) 657 return; 658 659 switch (intel_tlb_table[k].tlb_type) { 660 case STLB_4K: 661 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 662 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 663 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 664 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 665 break; 666 case STLB_4K_2M: 667 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 668 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 669 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 670 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 671 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 672 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 673 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 674 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 675 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 676 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 677 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 678 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 679 break; 680 case TLB_INST_ALL: 681 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 682 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 683 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 684 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 685 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 686 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 687 break; 688 case TLB_INST_4K: 689 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 690 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 691 break; 692 case TLB_INST_4M: 693 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 694 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 695 break; 696 case TLB_INST_2M_4M: 697 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 698 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 699 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 700 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 701 break; 702 case TLB_DATA_4K: 703 case TLB_DATA0_4K: 704 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 705 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 706 break; 707 case TLB_DATA_4M: 708 case TLB_DATA0_4M: 709 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 710 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 711 break; 712 case TLB_DATA_2M_4M: 713 case TLB_DATA0_2M_4M: 714 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 715 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 716 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 717 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 718 break; 719 case TLB_DATA_4K_4M: 720 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 721 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 722 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 723 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 724 break; 725 case TLB_DATA_1G: 726 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 727 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 728 break; 729 } 730 } 731 732 static void intel_detect_tlb(struct cpuinfo_x86 *c) 733 { 734 int i, j, n; 735 unsigned int regs[4]; 736 unsigned char *desc = (unsigned char *)regs; 737 738 if (c->cpuid_level < 2) 739 return; 740 741 /* Number of times to iterate */ 742 n = cpuid_eax(2) & 0xFF; 743 744 for (i = 0 ; i < n ; i++) { 745 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 746 747 /* If bit 31 is set, this is an unknown format */ 748 for (j = 0 ; j < 3 ; j++) 749 if (regs[j] & (1 << 31)) 750 regs[j] = 0; 751 752 /* Byte 0 is level count, not a descriptor */ 753 for (j = 1 ; j < 16 ; j++) 754 intel_tlb_lookup(desc[j]); 755 } 756 } 757 758 static const struct cpu_dev intel_cpu_dev = { 759 .c_vendor = "Intel", 760 .c_ident = { "GenuineIntel" }, 761 #ifdef CONFIG_X86_32 762 .legacy_models = { 763 { .family = 4, .model_names = 764 { 765 [0] = "486 DX-25/33", 766 [1] = "486 DX-50", 767 [2] = "486 SX", 768 [3] = "486 DX/2", 769 [4] = "486 SL", 770 [5] = "486 SX/2", 771 [7] = "486 DX/2-WB", 772 [8] = "486 DX/4", 773 [9] = "486 DX/4-WB" 774 } 775 }, 776 { .family = 5, .model_names = 777 { 778 [0] = "Pentium 60/66 A-step", 779 [1] = "Pentium 60/66", 780 [2] = "Pentium 75 - 200", 781 [3] = "OverDrive PODP5V83", 782 [4] = "Pentium MMX", 783 [7] = "Mobile Pentium 75 - 200", 784 [8] = "Mobile Pentium MMX", 785 [9] = "Quark SoC X1000", 786 } 787 }, 788 { .family = 6, .model_names = 789 { 790 [0] = "Pentium Pro A-step", 791 [1] = "Pentium Pro", 792 [3] = "Pentium II (Klamath)", 793 [4] = "Pentium II (Deschutes)", 794 [5] = "Pentium II (Deschutes)", 795 [6] = "Mobile Pentium II", 796 [7] = "Pentium III (Katmai)", 797 [8] = "Pentium III (Coppermine)", 798 [10] = "Pentium III (Cascades)", 799 [11] = "Pentium III (Tualatin)", 800 } 801 }, 802 { .family = 15, .model_names = 803 { 804 [0] = "Pentium 4 (Unknown)", 805 [1] = "Pentium 4 (Willamette)", 806 [2] = "Pentium 4 (Northwood)", 807 [4] = "Pentium 4 (Foster)", 808 [5] = "Pentium 4 (Foster)", 809 } 810 }, 811 }, 812 .legacy_cache_size = intel_size_cache, 813 #endif 814 .c_detect_tlb = intel_detect_tlb, 815 .c_early_init = early_init_intel, 816 .c_init = init_intel, 817 .c_bsp_resume = intel_bsp_resume, 818 .c_x86_vendor = X86_VENDOR_INTEL, 819 }; 820 821 cpu_dev_register(intel_cpu_dev); 822 823