1 #include <linux/init.h> 2 #include <linux/kernel.h> 3 4 #include <linux/string.h> 5 #include <linux/bitops.h> 6 #include <linux/smp.h> 7 #include <linux/sched.h> 8 #include <linux/thread_info.h> 9 #include <linux/module.h> 10 #include <linux/uaccess.h> 11 12 #include <asm/processor.h> 13 #include <asm/pgtable.h> 14 #include <asm/msr.h> 15 #include <asm/ds.h> 16 #include <asm/bugs.h> 17 #include <asm/cpu.h> 18 19 #ifdef CONFIG_X86_64 20 #include <linux/topology.h> 21 #include <asm/numa_64.h> 22 #endif 23 24 #include "cpu.h" 25 26 #ifdef CONFIG_X86_LOCAL_APIC 27 #include <asm/mpspec.h> 28 #include <asm/apic.h> 29 #endif 30 31 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 32 { 33 /* Unmask CPUID levels if masked: */ 34 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 35 u64 misc_enable; 36 37 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 38 39 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { 40 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; 41 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 42 c->cpuid_level = cpuid_eax(0); 43 } 44 } 45 46 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 47 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 49 50 #ifdef CONFIG_X86_64 51 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 52 #else 53 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 54 if (c->x86 == 15 && c->x86_cache_alignment == 64) 55 c->x86_cache_alignment = 128; 56 #endif 57 58 /* CPUID workaround for 0F33/0F34 CPU */ 59 if (c->x86 == 0xF && c->x86_model == 0x3 60 && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) 61 c->x86_phys_bits = 36; 62 63 /* 64 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 65 * with P/T states and does not stop in deep C-states. 66 * 67 * It is also reliable across cores and sockets. (but not across 68 * cabinets - we turn it off in that case explicitly.) 69 */ 70 if (c->x86_power & (1 << 8)) { 71 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 72 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 73 sched_clock_stable = 1; 74 } 75 76 /* 77 * There is a known erratum on Pentium III and Core Solo 78 * and Core Duo CPUs. 79 * " Page with PAT set to WC while associated MTRR is UC 80 * may consolidate to UC " 81 * Because of this erratum, it is better to stick with 82 * setting WC in MTRR rather than using PAT on these CPUs. 83 * 84 * Enable PAT WC only on P4, Core 2 or later CPUs. 85 */ 86 if (c->x86 == 6 && c->x86_model < 15) 87 clear_cpu_cap(c, X86_FEATURE_PAT); 88 89 #ifdef CONFIG_KMEMCHECK 90 /* 91 * P4s have a "fast strings" feature which causes single- 92 * stepping REP instructions to only generate a #DB on 93 * cache-line boundaries. 94 * 95 * Ingo Molnar reported a Pentium D (model 6) and a Xeon 96 * (model 2) with the same problem. 97 */ 98 if (c->x86 == 15) { 99 u64 misc_enable; 100 101 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 102 103 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { 104 printk(KERN_INFO "kmemcheck: Disabling fast string operations\n"); 105 106 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING; 107 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 108 } 109 } 110 #endif 111 } 112 113 #ifdef CONFIG_X86_32 114 /* 115 * Early probe support logic for ppro memory erratum #50 116 * 117 * This is called before we do cpu ident work 118 */ 119 120 int __cpuinit ppro_with_ram_bug(void) 121 { 122 /* Uses data from early_cpu_detect now */ 123 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 124 boot_cpu_data.x86 == 6 && 125 boot_cpu_data.x86_model == 1 && 126 boot_cpu_data.x86_mask < 8) { 127 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 128 return 1; 129 } 130 return 0; 131 } 132 133 #ifdef CONFIG_X86_F00F_BUG 134 static void __cpuinit trap_init_f00f_bug(void) 135 { 136 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO); 137 138 /* 139 * Update the IDT descriptor and reload the IDT so that 140 * it uses the read-only mapped virtual address. 141 */ 142 idt_descr.address = fix_to_virt(FIX_F00F_IDT); 143 load_idt(&idt_descr); 144 } 145 #endif 146 147 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c) 148 { 149 #ifdef CONFIG_SMP 150 /* calling is from identify_secondary_cpu() ? */ 151 if (c->cpu_index == boot_cpu_id) 152 return; 153 154 /* 155 * Mask B, Pentium, but not Pentium MMX 156 */ 157 if (c->x86 == 5 && 158 c->x86_mask >= 1 && c->x86_mask <= 4 && 159 c->x86_model <= 3) { 160 /* 161 * Remember we have B step Pentia with bugs 162 */ 163 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 164 "with B stepping processors.\n"); 165 } 166 #endif 167 } 168 169 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 170 { 171 unsigned long lo, hi; 172 173 #ifdef CONFIG_X86_F00F_BUG 174 /* 175 * All current models of Pentium and Pentium with MMX technology CPUs 176 * have the F0 0F bug, which lets nonprivileged users lock up the 177 * system. 178 * Note that the workaround only should be initialized once... 179 */ 180 c->f00f_bug = 0; 181 if (!paravirt_enabled() && c->x86 == 5) { 182 static int f00f_workaround_enabled; 183 184 c->f00f_bug = 1; 185 if (!f00f_workaround_enabled) { 186 trap_init_f00f_bug(); 187 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); 188 f00f_workaround_enabled = 1; 189 } 190 } 191 #endif 192 193 /* 194 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 195 * model 3 mask 3 196 */ 197 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 198 clear_cpu_cap(c, X86_FEATURE_SEP); 199 200 /* 201 * P4 Xeon errata 037 workaround. 202 * Hardware prefetcher may cause stale data to be loaded into the cache. 203 */ 204 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 205 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi); 206 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) { 207 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); 208 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); 209 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE; 210 wrmsr(MSR_IA32_MISC_ENABLE, lo, hi); 211 } 212 } 213 214 /* 215 * See if we have a good local APIC by checking for buggy Pentia, 216 * i.e. all B steppings and the C2 stepping of P54C when using their 217 * integrated APIC (see 11AP erratum in "Pentium Processor 218 * Specification Update"). 219 */ 220 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && 221 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 222 set_cpu_cap(c, X86_FEATURE_11AP); 223 224 225 #ifdef CONFIG_X86_INTEL_USERCOPY 226 /* 227 * Set up the preferred alignment for movsl bulk memory moves 228 */ 229 switch (c->x86) { 230 case 4: /* 486: untested */ 231 break; 232 case 5: /* Old Pentia: untested */ 233 break; 234 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 235 movsl_mask.mask = 7; 236 break; 237 case 15: /* P4 is OK down to 8-byte alignment */ 238 movsl_mask.mask = 7; 239 break; 240 } 241 #endif 242 243 #ifdef CONFIG_X86_NUMAQ 244 numaq_tsc_disable(); 245 #endif 246 247 intel_smp_check(c); 248 } 249 #else 250 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 251 { 252 } 253 #endif 254 255 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 256 { 257 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 258 unsigned node; 259 int cpu = smp_processor_id(); 260 int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid; 261 262 /* Don't do the funky fallback heuristics the AMD version employs 263 for now. */ 264 node = apicid_to_node[apicid]; 265 if (node == NUMA_NO_NODE) 266 node = first_node(node_online_map); 267 else if (!node_online(node)) { 268 /* reuse the value from init_cpu_to_node() */ 269 node = cpu_to_node(cpu); 270 } 271 numa_set_node(cpu, node); 272 #endif 273 } 274 275 /* 276 * find out the number of processor cores on the die 277 */ 278 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) 279 { 280 unsigned int eax, ebx, ecx, edx; 281 282 if (c->cpuid_level < 4) 283 return 1; 284 285 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 286 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 287 if (eax & 0x1f) 288 return (eax >> 26) + 1; 289 else 290 return 1; 291 } 292 293 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c) 294 { 295 /* Intel VMX MSR indicated features */ 296 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 297 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 298 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 299 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 300 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 301 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 302 303 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 304 305 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 306 clear_cpu_cap(c, X86_FEATURE_VNMI); 307 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 308 clear_cpu_cap(c, X86_FEATURE_EPT); 309 clear_cpu_cap(c, X86_FEATURE_VPID); 310 311 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 312 msr_ctl = vmx_msr_high | vmx_msr_low; 313 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 314 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 315 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 316 set_cpu_cap(c, X86_FEATURE_VNMI); 317 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 318 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 319 vmx_msr_low, vmx_msr_high); 320 msr_ctl2 = vmx_msr_high | vmx_msr_low; 321 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 322 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 323 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 324 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 325 set_cpu_cap(c, X86_FEATURE_EPT); 326 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 327 set_cpu_cap(c, X86_FEATURE_VPID); 328 } 329 } 330 331 static void __cpuinit init_intel(struct cpuinfo_x86 *c) 332 { 333 unsigned int l2 = 0; 334 335 early_init_intel(c); 336 337 intel_workarounds(c); 338 339 /* 340 * Detect the extended topology information if available. This 341 * will reinitialise the initial_apicid which will be used 342 * in init_intel_cacheinfo() 343 */ 344 detect_extended_topology(c); 345 346 l2 = init_intel_cacheinfo(c); 347 if (c->cpuid_level > 9) { 348 unsigned eax = cpuid_eax(10); 349 /* Check for version and the number of counters */ 350 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 351 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 352 } 353 354 if (c->cpuid_level > 6) { 355 unsigned ecx = cpuid_ecx(6); 356 if (ecx & 0x01) 357 set_cpu_cap(c, X86_FEATURE_APERFMPERF); 358 } 359 360 if (cpu_has_xmm2) 361 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 362 if (cpu_has_ds) { 363 unsigned int l1; 364 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 365 if (!(l1 & (1<<11))) 366 set_cpu_cap(c, X86_FEATURE_BTS); 367 if (!(l1 & (1<<12))) 368 set_cpu_cap(c, X86_FEATURE_PEBS); 369 ds_init_intel(c); 370 } 371 372 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush) 373 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR); 374 375 #ifdef CONFIG_X86_64 376 if (c->x86 == 15) 377 c->x86_cache_alignment = c->x86_clflush_size * 2; 378 if (c->x86 == 6) 379 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 380 #else 381 /* 382 * Names for the Pentium II/Celeron processors 383 * detectable only by also checking the cache size. 384 * Dixon is NOT a Celeron. 385 */ 386 if (c->x86 == 6) { 387 char *p = NULL; 388 389 switch (c->x86_model) { 390 case 5: 391 if (c->x86_mask == 0) { 392 if (l2 == 0) 393 p = "Celeron (Covington)"; 394 else if (l2 == 256) 395 p = "Mobile Pentium II (Dixon)"; 396 } 397 break; 398 399 case 6: 400 if (l2 == 128) 401 p = "Celeron (Mendocino)"; 402 else if (c->x86_mask == 0 || c->x86_mask == 5) 403 p = "Celeron-A"; 404 break; 405 406 case 8: 407 if (l2 == 128) 408 p = "Celeron (Coppermine)"; 409 break; 410 } 411 412 if (p) 413 strcpy(c->x86_model_id, p); 414 } 415 416 if (c->x86 == 15) 417 set_cpu_cap(c, X86_FEATURE_P4); 418 if (c->x86 == 6) 419 set_cpu_cap(c, X86_FEATURE_P3); 420 #endif 421 422 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 423 /* 424 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 425 * detection. 426 */ 427 c->x86_max_cores = intel_num_cpu_cores(c); 428 #ifdef CONFIG_X86_32 429 detect_ht(c); 430 #endif 431 } 432 433 /* Work around errata */ 434 srat_detect_node(c); 435 436 if (cpu_has(c, X86_FEATURE_VMX)) 437 detect_vmx_virtcap(c); 438 } 439 440 #ifdef CONFIG_X86_32 441 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 442 { 443 /* 444 * Intel PIII Tualatin. This comes in two flavours. 445 * One has 256kb of cache, the other 512. We have no way 446 * to determine which, so we use a boottime override 447 * for the 512kb model, and assume 256 otherwise. 448 */ 449 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 450 size = 256; 451 return size; 452 } 453 #endif 454 455 static const struct cpu_dev __cpuinitconst intel_cpu_dev = { 456 .c_vendor = "Intel", 457 .c_ident = { "GenuineIntel" }, 458 #ifdef CONFIG_X86_32 459 .c_models = { 460 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = 461 { 462 [0] = "486 DX-25/33", 463 [1] = "486 DX-50", 464 [2] = "486 SX", 465 [3] = "486 DX/2", 466 [4] = "486 SL", 467 [5] = "486 SX/2", 468 [7] = "486 DX/2-WB", 469 [8] = "486 DX/4", 470 [9] = "486 DX/4-WB" 471 } 472 }, 473 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = 474 { 475 [0] = "Pentium 60/66 A-step", 476 [1] = "Pentium 60/66", 477 [2] = "Pentium 75 - 200", 478 [3] = "OverDrive PODP5V83", 479 [4] = "Pentium MMX", 480 [7] = "Mobile Pentium 75 - 200", 481 [8] = "Mobile Pentium MMX" 482 } 483 }, 484 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = 485 { 486 [0] = "Pentium Pro A-step", 487 [1] = "Pentium Pro", 488 [3] = "Pentium II (Klamath)", 489 [4] = "Pentium II (Deschutes)", 490 [5] = "Pentium II (Deschutes)", 491 [6] = "Mobile Pentium II", 492 [7] = "Pentium III (Katmai)", 493 [8] = "Pentium III (Coppermine)", 494 [10] = "Pentium III (Cascades)", 495 [11] = "Pentium III (Tualatin)", 496 } 497 }, 498 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = 499 { 500 [0] = "Pentium 4 (Unknown)", 501 [1] = "Pentium 4 (Willamette)", 502 [2] = "Pentium 4 (Northwood)", 503 [4] = "Pentium 4 (Foster)", 504 [5] = "Pentium 4 (Foster)", 505 } 506 }, 507 }, 508 .c_size_cache = intel_size_cache, 509 #endif 510 .c_early_init = early_init_intel, 511 .c_init = init_intel, 512 .c_x86_vendor = X86_VENDOR_INTEL, 513 }; 514 515 cpu_dev_register(intel_cpu_dev); 516 517