1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/kernel.h> 3 #include <linux/pgtable.h> 4 5 #include <linux/string.h> 6 #include <linux/bitops.h> 7 #include <linux/smp.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/thread_info.h> 11 #include <linux/init.h> 12 #include <linux/uaccess.h> 13 14 #include <asm/cpufeature.h> 15 #include <asm/msr.h> 16 #include <asm/bugs.h> 17 #include <asm/cpu.h> 18 #include <asm/intel-family.h> 19 #include <asm/microcode_intel.h> 20 #include <asm/hwcap2.h> 21 #include <asm/elf.h> 22 #include <asm/cpu_device_id.h> 23 #include <asm/cmdline.h> 24 #include <asm/traps.h> 25 #include <asm/resctrl.h> 26 27 #ifdef CONFIG_X86_64 28 #include <linux/topology.h> 29 #endif 30 31 #include "cpu.h" 32 33 #ifdef CONFIG_X86_LOCAL_APIC 34 #include <asm/mpspec.h> 35 #include <asm/apic.h> 36 #endif 37 38 enum split_lock_detect_state { 39 sld_off = 0, 40 sld_warn, 41 sld_fatal, 42 }; 43 44 /* 45 * Default to sld_off because most systems do not support split lock detection 46 * split_lock_setup() will switch this to sld_warn on systems that support 47 * split lock detect, unless there is a command line override. 48 */ 49 static enum split_lock_detect_state sld_state __ro_after_init = sld_off; 50 static u64 msr_test_ctrl_cache __ro_after_init; 51 52 /* 53 * With a name like MSR_TEST_CTL it should go without saying, but don't touch 54 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it 55 * on CPUs that do not support SLD can cause fireworks, even when writing '0'. 56 */ 57 static bool cpu_model_supports_sld __ro_after_init; 58 59 /* 60 * Processors which have self-snooping capability can handle conflicting 61 * memory type across CPUs by snooping its own cache. However, there exists 62 * CPU models in which having conflicting memory types still leads to 63 * unpredictable behavior, machine check errors, or hangs. Clear this 64 * feature to prevent its use on machines with known erratas. 65 */ 66 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) 67 { 68 switch (c->x86_model) { 69 case INTEL_FAM6_CORE_YONAH: 70 case INTEL_FAM6_CORE2_MEROM: 71 case INTEL_FAM6_CORE2_MEROM_L: 72 case INTEL_FAM6_CORE2_PENRYN: 73 case INTEL_FAM6_CORE2_DUNNINGTON: 74 case INTEL_FAM6_NEHALEM: 75 case INTEL_FAM6_NEHALEM_G: 76 case INTEL_FAM6_NEHALEM_EP: 77 case INTEL_FAM6_NEHALEM_EX: 78 case INTEL_FAM6_WESTMERE: 79 case INTEL_FAM6_WESTMERE_EP: 80 case INTEL_FAM6_SANDYBRIDGE: 81 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); 82 } 83 } 84 85 static bool ring3mwait_disabled __read_mostly; 86 87 static int __init ring3mwait_disable(char *__unused) 88 { 89 ring3mwait_disabled = true; 90 return 0; 91 } 92 __setup("ring3mwait=disable", ring3mwait_disable); 93 94 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 95 { 96 /* 97 * Ring 3 MONITOR/MWAIT feature cannot be detected without 98 * cpu model and family comparison. 99 */ 100 if (c->x86 != 6) 101 return; 102 switch (c->x86_model) { 103 case INTEL_FAM6_XEON_PHI_KNL: 104 case INTEL_FAM6_XEON_PHI_KNM: 105 break; 106 default: 107 return; 108 } 109 110 if (ring3mwait_disabled) 111 return; 112 113 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 114 this_cpu_or(msr_misc_features_shadow, 115 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 116 117 if (c == &boot_cpu_data) 118 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 119 } 120 121 /* 122 * Early microcode releases for the Spectre v2 mitigation were broken. 123 * Information taken from; 124 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf 125 * - https://kb.vmware.com/s/article/52345 126 * - Microcode revisions observed in the wild 127 * - Release note from 20180108 microcode release 128 */ 129 struct sku_microcode { 130 u8 model; 131 u8 stepping; 132 u32 microcode; 133 }; 134 static const struct sku_microcode spectre_bad_microcodes[] = { 135 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 }, 136 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 }, 137 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 }, 138 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 }, 139 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 }, 140 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, 141 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, 142 { INTEL_FAM6_BROADWELL, 0x04, 0x28 }, 143 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b }, 144 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 }, 145 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 }, 146 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, 147 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 }, 148 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 }, 149 { INTEL_FAM6_HASWELL, 0x03, 0x23 }, 150 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, 151 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, 152 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, 153 /* Observed in the wild */ 154 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, 155 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, 156 }; 157 158 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) 159 { 160 int i; 161 162 /* 163 * We know that the hypervisor lie to us on the microcode version so 164 * we may as well hope that it is running the correct version. 165 */ 166 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 167 return false; 168 169 if (c->x86 != 6) 170 return false; 171 172 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { 173 if (c->x86_model == spectre_bad_microcodes[i].model && 174 c->x86_stepping == spectre_bad_microcodes[i].stepping) 175 return (c->microcode <= spectre_bad_microcodes[i].microcode); 176 } 177 return false; 178 } 179 180 static void early_init_intel(struct cpuinfo_x86 *c) 181 { 182 u64 misc_enable; 183 184 /* Unmask CPUID levels if masked: */ 185 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 186 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 187 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 188 c->cpuid_level = cpuid_eax(0); 189 get_cpu_cap(c); 190 } 191 } 192 193 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 194 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 195 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 196 197 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 198 c->microcode = intel_get_microcode_revision(); 199 200 /* Now if any of them are set, check the blacklist and clear the lot */ 201 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || 202 cpu_has(c, X86_FEATURE_INTEL_STIBP) || 203 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || 204 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { 205 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); 206 setup_clear_cpu_cap(X86_FEATURE_IBRS); 207 setup_clear_cpu_cap(X86_FEATURE_IBPB); 208 setup_clear_cpu_cap(X86_FEATURE_STIBP); 209 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); 210 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); 211 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); 212 setup_clear_cpu_cap(X86_FEATURE_SSBD); 213 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); 214 } 215 216 /* 217 * Atom erratum AAE44/AAF40/AAG38/AAH41: 218 * 219 * A race condition between speculative fetches and invalidating 220 * a large page. This is worked around in microcode, but we 221 * need the microcode to have already been loaded... so if it is 222 * not, recommend a BIOS update and disable large pages. 223 */ 224 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && 225 c->microcode < 0x20e) { 226 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 227 clear_cpu_cap(c, X86_FEATURE_PSE); 228 } 229 230 #ifdef CONFIG_X86_64 231 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 232 #else 233 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 234 if (c->x86 == 15 && c->x86_cache_alignment == 64) 235 c->x86_cache_alignment = 128; 236 #endif 237 238 /* CPUID workaround for 0F33/0F34 CPU */ 239 if (c->x86 == 0xF && c->x86_model == 0x3 240 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) 241 c->x86_phys_bits = 36; 242 243 /* 244 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 245 * with P/T states and does not stop in deep C-states. 246 * 247 * It is also reliable across cores and sockets. (but not across 248 * cabinets - we turn it off in that case explicitly.) 249 */ 250 if (c->x86_power & (1 << 8)) { 251 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 252 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 253 } 254 255 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 256 if (c->x86 == 6) { 257 switch (c->x86_model) { 258 case INTEL_FAM6_ATOM_SALTWELL_MID: 259 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 260 case INTEL_FAM6_ATOM_SILVERMONT_MID: 261 case INTEL_FAM6_ATOM_AIRMONT_NP: 262 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 263 break; 264 default: 265 break; 266 } 267 } 268 269 /* 270 * There is a known erratum on Pentium III and Core Solo 271 * and Core Duo CPUs. 272 * " Page with PAT set to WC while associated MTRR is UC 273 * may consolidate to UC " 274 * Because of this erratum, it is better to stick with 275 * setting WC in MTRR rather than using PAT on these CPUs. 276 * 277 * Enable PAT WC only on P4, Core 2 or later CPUs. 278 */ 279 if (c->x86 == 6 && c->x86_model < 15) 280 clear_cpu_cap(c, X86_FEATURE_PAT); 281 282 /* 283 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 284 * clear the fast string and enhanced fast string CPU capabilities. 285 */ 286 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 287 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 288 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 289 pr_info("Disabled fast string operations\n"); 290 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 291 setup_clear_cpu_cap(X86_FEATURE_ERMS); 292 } 293 } 294 295 /* 296 * Intel Quark Core DevMan_001.pdf section 6.4.11 297 * "The operating system also is required to invalidate (i.e., flush) 298 * the TLB when any changes are made to any of the page table entries. 299 * The operating system must reload CR3 to cause the TLB to be flushed" 300 * 301 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 302 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 303 * to be modified. 304 */ 305 if (c->x86 == 5 && c->x86_model == 9) { 306 pr_info("Disabling PGE capability bit\n"); 307 setup_clear_cpu_cap(X86_FEATURE_PGE); 308 } 309 310 if (c->cpuid_level >= 0x00000001) { 311 u32 eax, ebx, ecx, edx; 312 313 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 314 /* 315 * If HTT (EDX[28]) is set EBX[16:23] contain the number of 316 * apicids which are reserved per package. Store the resulting 317 * shift value for the package management code. 318 */ 319 if (edx & (1U << 28)) 320 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); 321 } 322 323 check_memory_type_self_snoop_errata(c); 324 325 /* 326 * Get the number of SMT siblings early from the extended topology 327 * leaf, if available. Otherwise try the legacy SMT detection. 328 */ 329 if (detect_extended_topology_early(c) < 0) 330 detect_ht_early(c); 331 } 332 333 static void bsp_init_intel(struct cpuinfo_x86 *c) 334 { 335 resctrl_cpu_detect(c); 336 } 337 338 #ifdef CONFIG_X86_32 339 /* 340 * Early probe support logic for ppro memory erratum #50 341 * 342 * This is called before we do cpu ident work 343 */ 344 345 int ppro_with_ram_bug(void) 346 { 347 /* Uses data from early_cpu_detect now */ 348 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 349 boot_cpu_data.x86 == 6 && 350 boot_cpu_data.x86_model == 1 && 351 boot_cpu_data.x86_stepping < 8) { 352 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 353 return 1; 354 } 355 return 0; 356 } 357 358 static void intel_smp_check(struct cpuinfo_x86 *c) 359 { 360 /* calling is from identify_secondary_cpu() ? */ 361 if (!c->cpu_index) 362 return; 363 364 /* 365 * Mask B, Pentium, but not Pentium MMX 366 */ 367 if (c->x86 == 5 && 368 c->x86_stepping >= 1 && c->x86_stepping <= 4 && 369 c->x86_model <= 3) { 370 /* 371 * Remember we have B step Pentia with bugs 372 */ 373 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 374 "with B stepping processors.\n"); 375 } 376 } 377 378 static int forcepae; 379 static int __init forcepae_setup(char *__unused) 380 { 381 forcepae = 1; 382 return 1; 383 } 384 __setup("forcepae", forcepae_setup); 385 386 static void intel_workarounds(struct cpuinfo_x86 *c) 387 { 388 #ifdef CONFIG_X86_F00F_BUG 389 /* 390 * All models of Pentium and Pentium with MMX technology CPUs 391 * have the F0 0F bug, which lets nonprivileged users lock up the 392 * system. Announce that the fault handler will be checking for it. 393 * The Quark is also family 5, but does not have the same bug. 394 */ 395 clear_cpu_bug(c, X86_BUG_F00F); 396 if (c->x86 == 5 && c->x86_model < 9) { 397 static int f00f_workaround_enabled; 398 399 set_cpu_bug(c, X86_BUG_F00F); 400 if (!f00f_workaround_enabled) { 401 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 402 f00f_workaround_enabled = 1; 403 } 404 } 405 #endif 406 407 /* 408 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 409 * model 3 mask 3 410 */ 411 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) 412 clear_cpu_cap(c, X86_FEATURE_SEP); 413 414 /* 415 * PAE CPUID issue: many Pentium M report no PAE but may have a 416 * functionally usable PAE implementation. 417 * Forcefully enable PAE if kernel parameter "forcepae" is present. 418 */ 419 if (forcepae) { 420 pr_warn("PAE forced!\n"); 421 set_cpu_cap(c, X86_FEATURE_PAE); 422 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 423 } 424 425 /* 426 * P4 Xeon erratum 037 workaround. 427 * Hardware prefetcher may cause stale data to be loaded into the cache. 428 */ 429 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { 430 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 431 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 432 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 433 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 434 } 435 } 436 437 /* 438 * See if we have a good local APIC by checking for buggy Pentia, 439 * i.e. all B steppings and the C2 stepping of P54C when using their 440 * integrated APIC (see 11AP erratum in "Pentium Processor 441 * Specification Update"). 442 */ 443 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 444 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) 445 set_cpu_bug(c, X86_BUG_11AP); 446 447 448 #ifdef CONFIG_X86_INTEL_USERCOPY 449 /* 450 * Set up the preferred alignment for movsl bulk memory moves 451 */ 452 switch (c->x86) { 453 case 4: /* 486: untested */ 454 break; 455 case 5: /* Old Pentia: untested */ 456 break; 457 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 458 movsl_mask.mask = 7; 459 break; 460 case 15: /* P4 is OK down to 8-byte alignment */ 461 movsl_mask.mask = 7; 462 break; 463 } 464 #endif 465 466 intel_smp_check(c); 467 } 468 #else 469 static void intel_workarounds(struct cpuinfo_x86 *c) 470 { 471 } 472 #endif 473 474 static void srat_detect_node(struct cpuinfo_x86 *c) 475 { 476 #ifdef CONFIG_NUMA 477 unsigned node; 478 int cpu = smp_processor_id(); 479 480 /* Don't do the funky fallback heuristics the AMD version employs 481 for now. */ 482 node = numa_cpu_node(cpu); 483 if (node == NUMA_NO_NODE || !node_online(node)) { 484 /* reuse the value from init_cpu_to_node() */ 485 node = cpu_to_node(cpu); 486 } 487 numa_set_node(cpu, node); 488 #endif 489 } 490 491 #define MSR_IA32_TME_ACTIVATE 0x982 492 493 /* Helpers to access TME_ACTIVATE MSR */ 494 #define TME_ACTIVATE_LOCKED(x) (x & 0x1) 495 #define TME_ACTIVATE_ENABLED(x) (x & 0x2) 496 497 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ 498 #define TME_ACTIVATE_POLICY_AES_XTS_128 0 499 500 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ 501 502 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ 503 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 504 505 /* Values for mktme_status (SW only construct) */ 506 #define MKTME_ENABLED 0 507 #define MKTME_DISABLED 1 508 #define MKTME_UNINITIALIZED 2 509 static int mktme_status = MKTME_UNINITIALIZED; 510 511 static void detect_tme(struct cpuinfo_x86 *c) 512 { 513 u64 tme_activate, tme_policy, tme_crypto_algs; 514 int keyid_bits = 0, nr_keyids = 0; 515 static u64 tme_activate_cpu0 = 0; 516 517 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); 518 519 if (mktme_status != MKTME_UNINITIALIZED) { 520 if (tme_activate != tme_activate_cpu0) { 521 /* Broken BIOS? */ 522 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); 523 pr_err_once("x86/tme: MKTME is not usable\n"); 524 mktme_status = MKTME_DISABLED; 525 526 /* Proceed. We may need to exclude bits from x86_phys_bits. */ 527 } 528 } else { 529 tme_activate_cpu0 = tme_activate; 530 } 531 532 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 533 pr_info_once("x86/tme: not enabled by BIOS\n"); 534 mktme_status = MKTME_DISABLED; 535 return; 536 } 537 538 if (mktme_status != MKTME_UNINITIALIZED) 539 goto detect_keyid_bits; 540 541 pr_info("x86/tme: enabled by BIOS\n"); 542 543 tme_policy = TME_ACTIVATE_POLICY(tme_activate); 544 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128) 545 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); 546 547 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate); 548 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { 549 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", 550 tme_crypto_algs); 551 mktme_status = MKTME_DISABLED; 552 } 553 detect_keyid_bits: 554 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); 555 nr_keyids = (1UL << keyid_bits) - 1; 556 if (nr_keyids) { 557 pr_info_once("x86/mktme: enabled by BIOS\n"); 558 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); 559 } else { 560 pr_info_once("x86/mktme: disabled by BIOS\n"); 561 } 562 563 if (mktme_status == MKTME_UNINITIALIZED) { 564 /* MKTME is usable */ 565 mktme_status = MKTME_ENABLED; 566 } 567 568 /* 569 * KeyID bits effectively lower the number of physical address 570 * bits. Update cpuinfo_x86::x86_phys_bits accordingly. 571 */ 572 c->x86_phys_bits -= keyid_bits; 573 } 574 575 static void init_cpuid_fault(struct cpuinfo_x86 *c) 576 { 577 u64 msr; 578 579 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 580 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 581 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 582 } 583 } 584 585 static void init_intel_misc_features(struct cpuinfo_x86 *c) 586 { 587 u64 msr; 588 589 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 590 return; 591 592 /* Clear all MISC features */ 593 this_cpu_write(msr_misc_features_shadow, 0); 594 595 /* Check features and update capabilities and shadow control bits */ 596 init_cpuid_fault(c); 597 probe_xeon_phi_r3mwait(c); 598 599 msr = this_cpu_read(msr_misc_features_shadow); 600 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 601 } 602 603 static void split_lock_init(void); 604 605 static void init_intel(struct cpuinfo_x86 *c) 606 { 607 early_init_intel(c); 608 609 intel_workarounds(c); 610 611 /* 612 * Detect the extended topology information if available. This 613 * will reinitialise the initial_apicid which will be used 614 * in init_intel_cacheinfo() 615 */ 616 detect_extended_topology(c); 617 618 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 619 /* 620 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 621 * detection. 622 */ 623 detect_num_cpu_cores(c); 624 #ifdef CONFIG_X86_32 625 detect_ht(c); 626 #endif 627 } 628 629 init_intel_cacheinfo(c); 630 631 if (c->cpuid_level > 9) { 632 unsigned eax = cpuid_eax(10); 633 /* Check for version and the number of counters */ 634 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 635 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 636 } 637 638 if (cpu_has(c, X86_FEATURE_XMM2)) 639 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 640 641 if (boot_cpu_has(X86_FEATURE_DS)) { 642 unsigned int l1, l2; 643 644 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 645 if (!(l1 & (1<<11))) 646 set_cpu_cap(c, X86_FEATURE_BTS); 647 if (!(l1 & (1<<12))) 648 set_cpu_cap(c, X86_FEATURE_PEBS); 649 } 650 651 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 652 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 653 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 654 655 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 656 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 657 set_cpu_bug(c, X86_BUG_MONITOR); 658 659 #ifdef CONFIG_X86_64 660 if (c->x86 == 15) 661 c->x86_cache_alignment = c->x86_clflush_size * 2; 662 if (c->x86 == 6) 663 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 664 #else 665 /* 666 * Names for the Pentium II/Celeron processors 667 * detectable only by also checking the cache size. 668 * Dixon is NOT a Celeron. 669 */ 670 if (c->x86 == 6) { 671 unsigned int l2 = c->x86_cache_size; 672 char *p = NULL; 673 674 switch (c->x86_model) { 675 case 5: 676 if (l2 == 0) 677 p = "Celeron (Covington)"; 678 else if (l2 == 256) 679 p = "Mobile Pentium II (Dixon)"; 680 break; 681 682 case 6: 683 if (l2 == 128) 684 p = "Celeron (Mendocino)"; 685 else if (c->x86_stepping == 0 || c->x86_stepping == 5) 686 p = "Celeron-A"; 687 break; 688 689 case 8: 690 if (l2 == 128) 691 p = "Celeron (Coppermine)"; 692 break; 693 } 694 695 if (p) 696 strcpy(c->x86_model_id, p); 697 } 698 699 if (c->x86 == 15) 700 set_cpu_cap(c, X86_FEATURE_P4); 701 if (c->x86 == 6) 702 set_cpu_cap(c, X86_FEATURE_P3); 703 #endif 704 705 /* Work around errata */ 706 srat_detect_node(c); 707 708 init_ia32_feat_ctl(c); 709 710 if (cpu_has(c, X86_FEATURE_TME)) 711 detect_tme(c); 712 713 init_intel_misc_features(c); 714 715 if (tsx_ctrl_state == TSX_CTRL_ENABLE) 716 tsx_enable(); 717 if (tsx_ctrl_state == TSX_CTRL_DISABLE) 718 tsx_disable(); 719 720 split_lock_init(); 721 } 722 723 #ifdef CONFIG_X86_32 724 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 725 { 726 /* 727 * Intel PIII Tualatin. This comes in two flavours. 728 * One has 256kb of cache, the other 512. We have no way 729 * to determine which, so we use a boottime override 730 * for the 512kb model, and assume 256 otherwise. 731 */ 732 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 733 size = 256; 734 735 /* 736 * Intel Quark SoC X1000 contains a 4-way set associative 737 * 16K cache with a 16 byte cache line and 256 lines per tag 738 */ 739 if ((c->x86 == 5) && (c->x86_model == 9)) 740 size = 16; 741 return size; 742 } 743 #endif 744 745 #define TLB_INST_4K 0x01 746 #define TLB_INST_4M 0x02 747 #define TLB_INST_2M_4M 0x03 748 749 #define TLB_INST_ALL 0x05 750 #define TLB_INST_1G 0x06 751 752 #define TLB_DATA_4K 0x11 753 #define TLB_DATA_4M 0x12 754 #define TLB_DATA_2M_4M 0x13 755 #define TLB_DATA_4K_4M 0x14 756 757 #define TLB_DATA_1G 0x16 758 759 #define TLB_DATA0_4K 0x21 760 #define TLB_DATA0_4M 0x22 761 #define TLB_DATA0_2M_4M 0x23 762 763 #define STLB_4K 0x41 764 #define STLB_4K_2M 0x42 765 766 static const struct _tlb_table intel_tlb_table[] = { 767 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 768 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 769 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 770 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 771 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 772 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 773 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" }, 774 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 775 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 776 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 777 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 778 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 779 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 780 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 781 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 782 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 783 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 784 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 785 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 786 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 787 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, 788 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, 789 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, 790 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 791 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 792 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 793 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 794 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 795 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 796 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 797 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 798 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 799 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 800 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 801 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" }, 802 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 803 { 0x00, 0, 0 } 804 }; 805 806 static void intel_tlb_lookup(const unsigned char desc) 807 { 808 unsigned char k; 809 if (desc == 0) 810 return; 811 812 /* look up this descriptor in the table */ 813 for (k = 0; intel_tlb_table[k].descriptor != desc && 814 intel_tlb_table[k].descriptor != 0; k++) 815 ; 816 817 if (intel_tlb_table[k].tlb_type == 0) 818 return; 819 820 switch (intel_tlb_table[k].tlb_type) { 821 case STLB_4K: 822 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 823 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 824 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 825 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 826 break; 827 case STLB_4K_2M: 828 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 829 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 830 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 831 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 832 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 833 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 834 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 835 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 836 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 837 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 838 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 839 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 840 break; 841 case TLB_INST_ALL: 842 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 843 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 844 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 845 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 846 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 847 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 848 break; 849 case TLB_INST_4K: 850 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 851 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 852 break; 853 case TLB_INST_4M: 854 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 855 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 856 break; 857 case TLB_INST_2M_4M: 858 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 859 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 860 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 861 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 862 break; 863 case TLB_DATA_4K: 864 case TLB_DATA0_4K: 865 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 866 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 867 break; 868 case TLB_DATA_4M: 869 case TLB_DATA0_4M: 870 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 871 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 872 break; 873 case TLB_DATA_2M_4M: 874 case TLB_DATA0_2M_4M: 875 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 876 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 877 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 878 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 879 break; 880 case TLB_DATA_4K_4M: 881 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 882 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 883 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 884 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 885 break; 886 case TLB_DATA_1G: 887 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 888 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 889 break; 890 } 891 } 892 893 static void intel_detect_tlb(struct cpuinfo_x86 *c) 894 { 895 int i, j, n; 896 unsigned int regs[4]; 897 unsigned char *desc = (unsigned char *)regs; 898 899 if (c->cpuid_level < 2) 900 return; 901 902 /* Number of times to iterate */ 903 n = cpuid_eax(2) & 0xFF; 904 905 for (i = 0 ; i < n ; i++) { 906 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 907 908 /* If bit 31 is set, this is an unknown format */ 909 for (j = 0 ; j < 3 ; j++) 910 if (regs[j] & (1 << 31)) 911 regs[j] = 0; 912 913 /* Byte 0 is level count, not a descriptor */ 914 for (j = 1 ; j < 16 ; j++) 915 intel_tlb_lookup(desc[j]); 916 } 917 } 918 919 static const struct cpu_dev intel_cpu_dev = { 920 .c_vendor = "Intel", 921 .c_ident = { "GenuineIntel" }, 922 #ifdef CONFIG_X86_32 923 .legacy_models = { 924 { .family = 4, .model_names = 925 { 926 [0] = "486 DX-25/33", 927 [1] = "486 DX-50", 928 [2] = "486 SX", 929 [3] = "486 DX/2", 930 [4] = "486 SL", 931 [5] = "486 SX/2", 932 [7] = "486 DX/2-WB", 933 [8] = "486 DX/4", 934 [9] = "486 DX/4-WB" 935 } 936 }, 937 { .family = 5, .model_names = 938 { 939 [0] = "Pentium 60/66 A-step", 940 [1] = "Pentium 60/66", 941 [2] = "Pentium 75 - 200", 942 [3] = "OverDrive PODP5V83", 943 [4] = "Pentium MMX", 944 [7] = "Mobile Pentium 75 - 200", 945 [8] = "Mobile Pentium MMX", 946 [9] = "Quark SoC X1000", 947 } 948 }, 949 { .family = 6, .model_names = 950 { 951 [0] = "Pentium Pro A-step", 952 [1] = "Pentium Pro", 953 [3] = "Pentium II (Klamath)", 954 [4] = "Pentium II (Deschutes)", 955 [5] = "Pentium II (Deschutes)", 956 [6] = "Mobile Pentium II", 957 [7] = "Pentium III (Katmai)", 958 [8] = "Pentium III (Coppermine)", 959 [10] = "Pentium III (Cascades)", 960 [11] = "Pentium III (Tualatin)", 961 } 962 }, 963 { .family = 15, .model_names = 964 { 965 [0] = "Pentium 4 (Unknown)", 966 [1] = "Pentium 4 (Willamette)", 967 [2] = "Pentium 4 (Northwood)", 968 [4] = "Pentium 4 (Foster)", 969 [5] = "Pentium 4 (Foster)", 970 } 971 }, 972 }, 973 .legacy_cache_size = intel_size_cache, 974 #endif 975 .c_detect_tlb = intel_detect_tlb, 976 .c_early_init = early_init_intel, 977 .c_bsp_init = bsp_init_intel, 978 .c_init = init_intel, 979 .c_x86_vendor = X86_VENDOR_INTEL, 980 }; 981 982 cpu_dev_register(intel_cpu_dev); 983 984 #undef pr_fmt 985 #define pr_fmt(fmt) "x86/split lock detection: " fmt 986 987 static const struct { 988 const char *option; 989 enum split_lock_detect_state state; 990 } sld_options[] __initconst = { 991 { "off", sld_off }, 992 { "warn", sld_warn }, 993 { "fatal", sld_fatal }, 994 }; 995 996 static inline bool match_option(const char *arg, int arglen, const char *opt) 997 { 998 int len = strlen(opt); 999 1000 return len == arglen && !strncmp(arg, opt, len); 1001 } 1002 1003 static bool split_lock_verify_msr(bool on) 1004 { 1005 u64 ctrl, tmp; 1006 1007 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl)) 1008 return false; 1009 if (on) 1010 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 1011 else 1012 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 1013 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl)) 1014 return false; 1015 rdmsrl(MSR_TEST_CTRL, tmp); 1016 return ctrl == tmp; 1017 } 1018 1019 static void __init split_lock_setup(void) 1020 { 1021 enum split_lock_detect_state state = sld_warn; 1022 char arg[20]; 1023 int i, ret; 1024 1025 if (!split_lock_verify_msr(false)) { 1026 pr_info("MSR access failed: Disabled\n"); 1027 return; 1028 } 1029 1030 ret = cmdline_find_option(boot_command_line, "split_lock_detect", 1031 arg, sizeof(arg)); 1032 if (ret >= 0) { 1033 for (i = 0; i < ARRAY_SIZE(sld_options); i++) { 1034 if (match_option(arg, ret, sld_options[i].option)) { 1035 state = sld_options[i].state; 1036 break; 1037 } 1038 } 1039 } 1040 1041 switch (state) { 1042 case sld_off: 1043 pr_info("disabled\n"); 1044 return; 1045 case sld_warn: 1046 pr_info("warning about user-space split_locks\n"); 1047 break; 1048 case sld_fatal: 1049 pr_info("sending SIGBUS on user-space split_locks\n"); 1050 break; 1051 } 1052 1053 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache); 1054 1055 if (!split_lock_verify_msr(true)) { 1056 pr_info("MSR access failed: Disabled\n"); 1057 return; 1058 } 1059 1060 sld_state = state; 1061 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); 1062 } 1063 1064 /* 1065 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking 1066 * is not implemented as one thread could undo the setting of the other 1067 * thread immediately after dropping the lock anyway. 1068 */ 1069 static void sld_update_msr(bool on) 1070 { 1071 u64 test_ctrl_val = msr_test_ctrl_cache; 1072 1073 if (on) 1074 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 1075 1076 wrmsrl(MSR_TEST_CTRL, test_ctrl_val); 1077 } 1078 1079 static void split_lock_init(void) 1080 { 1081 if (cpu_model_supports_sld) 1082 split_lock_verify_msr(sld_state != sld_off); 1083 } 1084 1085 static void split_lock_warn(unsigned long ip) 1086 { 1087 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n", 1088 current->comm, current->pid, ip); 1089 1090 /* 1091 * Disable the split lock detection for this task so it can make 1092 * progress and set TIF_SLD so the detection is re-enabled via 1093 * switch_to_sld() when the task is scheduled out. 1094 */ 1095 sld_update_msr(false); 1096 set_tsk_thread_flag(current, TIF_SLD); 1097 } 1098 1099 bool handle_guest_split_lock(unsigned long ip) 1100 { 1101 if (sld_state == sld_warn) { 1102 split_lock_warn(ip); 1103 return true; 1104 } 1105 1106 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n", 1107 current->comm, current->pid, 1108 sld_state == sld_fatal ? "fatal" : "bogus", ip); 1109 1110 current->thread.error_code = 0; 1111 current->thread.trap_nr = X86_TRAP_AC; 1112 force_sig_fault(SIGBUS, BUS_ADRALN, NULL); 1113 return false; 1114 } 1115 EXPORT_SYMBOL_GPL(handle_guest_split_lock); 1116 1117 bool handle_user_split_lock(struct pt_regs *regs, long error_code) 1118 { 1119 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal) 1120 return false; 1121 split_lock_warn(regs->ip); 1122 return true; 1123 } 1124 1125 /* 1126 * This function is called only when switching between tasks with 1127 * different split-lock detection modes. It sets the MSR for the 1128 * mode of the new task. This is right most of the time, but since 1129 * the MSR is shared by hyperthreads on a physical core there can 1130 * be glitches when the two threads need different modes. 1131 */ 1132 void switch_to_sld(unsigned long tifn) 1133 { 1134 sld_update_msr(!(tifn & _TIF_SLD)); 1135 } 1136 1137 /* 1138 * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should 1139 * only be trusted if it is confirmed that a CPU model implements a 1140 * specific feature at a particular bit position. 1141 * 1142 * The possible driver data field values: 1143 * 1144 * - 0: CPU models that are known to have the per-core split-lock detection 1145 * feature even though they do not enumerate IA32_CORE_CAPABILITIES. 1146 * 1147 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use 1148 * bit 5 to enumerate the per-core split-lock detection feature. 1149 */ 1150 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = { 1151 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0), 1152 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0), 1153 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0), 1154 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1), 1155 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1), 1156 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1), 1157 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, 1), 1158 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, 1), 1159 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 1), 1160 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 1), 1161 {} 1162 }; 1163 1164 void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) 1165 { 1166 const struct x86_cpu_id *m; 1167 u64 ia32_core_caps; 1168 1169 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1170 return; 1171 1172 m = x86_match_cpu(split_lock_cpu_ids); 1173 if (!m) 1174 return; 1175 1176 switch (m->driver_data) { 1177 case 0: 1178 break; 1179 case 1: 1180 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) 1181 return; 1182 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps); 1183 if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)) 1184 return; 1185 break; 1186 default: 1187 return; 1188 } 1189 1190 cpu_model_supports_sld = true; 1191 split_lock_setup(); 1192 } 1193