1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/pgtable.h>
4
5 #include <linux/string.h>
6 #include <linux/bitops.h>
7 #include <linux/smp.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/semaphore.h>
11 #include <linux/thread_info.h>
12 #include <linux/init.h>
13 #include <linux/uaccess.h>
14 #include <linux/workqueue.h>
15 #include <linux/delay.h>
16 #include <linux/cpuhotplug.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/msr.h>
20 #include <asm/bugs.h>
21 #include <asm/cpu.h>
22 #include <asm/intel-family.h>
23 #include <asm/microcode.h>
24 #include <asm/hwcap2.h>
25 #include <asm/elf.h>
26 #include <asm/cpu_device_id.h>
27 #include <asm/cmdline.h>
28 #include <asm/traps.h>
29 #include <asm/resctrl.h>
30 #include <asm/numa.h>
31 #include <asm/thermal.h>
32
33 #ifdef CONFIG_X86_64
34 #include <linux/topology.h>
35 #endif
36
37 #include "cpu.h"
38
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/mpspec.h>
41 #include <asm/apic.h>
42 #endif
43
44 enum split_lock_detect_state {
45 sld_off = 0,
46 sld_warn,
47 sld_fatal,
48 sld_ratelimit,
49 };
50
51 /*
52 * Default to sld_off because most systems do not support split lock detection.
53 * sld_state_setup() will switch this to sld_warn on systems that support
54 * split lock/bus lock detect, unless there is a command line override.
55 */
56 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
57 static u64 msr_test_ctrl_cache __ro_after_init;
58
59 /*
60 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
61 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it
62 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
63 */
64 static bool cpu_model_supports_sld __ro_after_init;
65
66 /*
67 * Processors which have self-snooping capability can handle conflicting
68 * memory type across CPUs by snooping its own cache. However, there exists
69 * CPU models in which having conflicting memory types still leads to
70 * unpredictable behavior, machine check errors, or hangs. Clear this
71 * feature to prevent its use on machines with known erratas.
72 */
check_memory_type_self_snoop_errata(struct cpuinfo_x86 * c)73 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
74 {
75 switch (c->x86_model) {
76 case INTEL_FAM6_CORE_YONAH:
77 case INTEL_FAM6_CORE2_MEROM:
78 case INTEL_FAM6_CORE2_MEROM_L:
79 case INTEL_FAM6_CORE2_PENRYN:
80 case INTEL_FAM6_CORE2_DUNNINGTON:
81 case INTEL_FAM6_NEHALEM:
82 case INTEL_FAM6_NEHALEM_G:
83 case INTEL_FAM6_NEHALEM_EP:
84 case INTEL_FAM6_NEHALEM_EX:
85 case INTEL_FAM6_WESTMERE:
86 case INTEL_FAM6_WESTMERE_EP:
87 case INTEL_FAM6_SANDYBRIDGE:
88 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
89 }
90 }
91
92 static bool ring3mwait_disabled __read_mostly;
93
ring3mwait_disable(char * __unused)94 static int __init ring3mwait_disable(char *__unused)
95 {
96 ring3mwait_disabled = true;
97 return 1;
98 }
99 __setup("ring3mwait=disable", ring3mwait_disable);
100
probe_xeon_phi_r3mwait(struct cpuinfo_x86 * c)101 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
102 {
103 /*
104 * Ring 3 MONITOR/MWAIT feature cannot be detected without
105 * cpu model and family comparison.
106 */
107 if (c->x86 != 6)
108 return;
109 switch (c->x86_model) {
110 case INTEL_FAM6_XEON_PHI_KNL:
111 case INTEL_FAM6_XEON_PHI_KNM:
112 break;
113 default:
114 return;
115 }
116
117 if (ring3mwait_disabled)
118 return;
119
120 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
121 this_cpu_or(msr_misc_features_shadow,
122 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
123
124 if (c == &boot_cpu_data)
125 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
126 }
127
128 /*
129 * Early microcode releases for the Spectre v2 mitigation were broken.
130 * Information taken from;
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
135 */
136 struct sku_microcode {
137 u8 model;
138 u8 stepping;
139 u32 microcode;
140 };
141 static const struct sku_microcode spectre_bad_microcodes[] = {
142 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
143 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
144 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
145 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
146 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
147 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
148 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
149 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
150 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
151 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
152 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
153 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
154 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
155 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
156 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
157 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
158 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
159 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
160 /* Observed in the wild */
161 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
162 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
163 };
164
bad_spectre_microcode(struct cpuinfo_x86 * c)165 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
166 {
167 int i;
168
169 /*
170 * We know that the hypervisor lie to us on the microcode version so
171 * we may as well hope that it is running the correct version.
172 */
173 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
174 return false;
175
176 if (c->x86 != 6)
177 return false;
178
179 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
180 if (c->x86_model == spectre_bad_microcodes[i].model &&
181 c->x86_stepping == spectre_bad_microcodes[i].stepping)
182 return (c->microcode <= spectre_bad_microcodes[i].microcode);
183 }
184 return false;
185 }
186
187 #define MSR_IA32_TME_ACTIVATE 0x982
188
189 /* Helpers to access TME_ACTIVATE MSR */
190 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
191 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
192
193 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
194 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
195
196 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
197
198 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
199 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
200
201 /* Values for mktme_status (SW only construct) */
202 #define MKTME_ENABLED 0
203 #define MKTME_DISABLED 1
204 #define MKTME_UNINITIALIZED 2
205 static int mktme_status = MKTME_UNINITIALIZED;
206
detect_tme_early(struct cpuinfo_x86 * c)207 static void detect_tme_early(struct cpuinfo_x86 *c)
208 {
209 u64 tme_activate, tme_policy, tme_crypto_algs;
210 int keyid_bits = 0, nr_keyids = 0;
211 static u64 tme_activate_cpu0 = 0;
212
213 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
214
215 if (mktme_status != MKTME_UNINITIALIZED) {
216 if (tme_activate != tme_activate_cpu0) {
217 /* Broken BIOS? */
218 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
219 pr_err_once("x86/tme: MKTME is not usable\n");
220 mktme_status = MKTME_DISABLED;
221
222 /* Proceed. We may need to exclude bits from x86_phys_bits. */
223 }
224 } else {
225 tme_activate_cpu0 = tme_activate;
226 }
227
228 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
229 pr_info_once("x86/tme: not enabled by BIOS\n");
230 mktme_status = MKTME_DISABLED;
231 return;
232 }
233
234 if (mktme_status != MKTME_UNINITIALIZED)
235 goto detect_keyid_bits;
236
237 pr_info("x86/tme: enabled by BIOS\n");
238
239 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
240 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
241 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
242
243 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
244 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
245 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
246 tme_crypto_algs);
247 mktme_status = MKTME_DISABLED;
248 }
249 detect_keyid_bits:
250 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
251 nr_keyids = (1UL << keyid_bits) - 1;
252 if (nr_keyids) {
253 pr_info_once("x86/mktme: enabled by BIOS\n");
254 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
255 } else {
256 pr_info_once("x86/mktme: disabled by BIOS\n");
257 }
258
259 if (mktme_status == MKTME_UNINITIALIZED) {
260 /* MKTME is usable */
261 mktme_status = MKTME_ENABLED;
262 }
263
264 /*
265 * KeyID bits effectively lower the number of physical address
266 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
267 */
268 c->x86_phys_bits -= keyid_bits;
269 }
270
early_init_intel(struct cpuinfo_x86 * c)271 static void early_init_intel(struct cpuinfo_x86 *c)
272 {
273 u64 misc_enable;
274
275 /* Unmask CPUID levels if masked: */
276 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
277 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
278 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
279 c->cpuid_level = cpuid_eax(0);
280 get_cpu_cap(c);
281 }
282 }
283
284 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
285 (c->x86 == 0x6 && c->x86_model >= 0x0e))
286 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
287
288 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
289 c->microcode = intel_get_microcode_revision();
290
291 /* Now if any of them are set, check the blacklist and clear the lot */
292 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
293 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
294 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
295 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
296 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
297 setup_clear_cpu_cap(X86_FEATURE_IBRS);
298 setup_clear_cpu_cap(X86_FEATURE_IBPB);
299 setup_clear_cpu_cap(X86_FEATURE_STIBP);
300 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
301 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
302 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
303 setup_clear_cpu_cap(X86_FEATURE_SSBD);
304 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
305 }
306
307 /*
308 * Atom erratum AAE44/AAF40/AAG38/AAH41:
309 *
310 * A race condition between speculative fetches and invalidating
311 * a large page. This is worked around in microcode, but we
312 * need the microcode to have already been loaded... so if it is
313 * not, recommend a BIOS update and disable large pages.
314 */
315 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
316 c->microcode < 0x20e) {
317 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
318 clear_cpu_cap(c, X86_FEATURE_PSE);
319 }
320
321 #ifdef CONFIG_X86_64
322 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
323 #else
324 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
325 if (c->x86 == 15 && c->x86_cache_alignment == 64)
326 c->x86_cache_alignment = 128;
327 #endif
328
329 /* CPUID workaround for 0F33/0F34 CPU */
330 if (c->x86 == 0xF && c->x86_model == 0x3
331 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
332 c->x86_phys_bits = 36;
333
334 /*
335 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
336 * with P/T states and does not stop in deep C-states.
337 *
338 * It is also reliable across cores and sockets. (but not across
339 * cabinets - we turn it off in that case explicitly.)
340 */
341 if (c->x86_power & (1 << 8)) {
342 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
343 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
344 }
345
346 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
347 if (c->x86 == 6) {
348 switch (c->x86_model) {
349 case INTEL_FAM6_ATOM_SALTWELL_MID:
350 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
351 case INTEL_FAM6_ATOM_SILVERMONT_MID:
352 case INTEL_FAM6_ATOM_AIRMONT_NP:
353 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
354 break;
355 default:
356 break;
357 }
358 }
359
360 /*
361 * There is a known erratum on Pentium III and Core Solo
362 * and Core Duo CPUs.
363 * " Page with PAT set to WC while associated MTRR is UC
364 * may consolidate to UC "
365 * Because of this erratum, it is better to stick with
366 * setting WC in MTRR rather than using PAT on these CPUs.
367 *
368 * Enable PAT WC only on P4, Core 2 or later CPUs.
369 */
370 if (c->x86 == 6 && c->x86_model < 15)
371 clear_cpu_cap(c, X86_FEATURE_PAT);
372
373 /*
374 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
375 * clear the fast string and enhanced fast string CPU capabilities.
376 */
377 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
378 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
379 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
380 pr_info("Disabled fast string operations\n");
381 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
382 setup_clear_cpu_cap(X86_FEATURE_ERMS);
383 }
384 }
385
386 /*
387 * Intel Quark Core DevMan_001.pdf section 6.4.11
388 * "The operating system also is required to invalidate (i.e., flush)
389 * the TLB when any changes are made to any of the page table entries.
390 * The operating system must reload CR3 to cause the TLB to be flushed"
391 *
392 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
393 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
394 * to be modified.
395 */
396 if (c->x86 == 5 && c->x86_model == 9) {
397 pr_info("Disabling PGE capability bit\n");
398 setup_clear_cpu_cap(X86_FEATURE_PGE);
399 }
400
401 if (c->cpuid_level >= 0x00000001) {
402 u32 eax, ebx, ecx, edx;
403
404 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
405 /*
406 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
407 * apicids which are reserved per package. Store the resulting
408 * shift value for the package management code.
409 */
410 if (edx & (1U << 28))
411 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
412 }
413
414 check_memory_type_self_snoop_errata(c);
415
416 /*
417 * Get the number of SMT siblings early from the extended topology
418 * leaf, if available. Otherwise try the legacy SMT detection.
419 */
420 if (detect_extended_topology_early(c) < 0)
421 detect_ht_early(c);
422
423 /*
424 * Adjust the number of physical bits early because it affects the
425 * valid bits of the MTRR mask registers.
426 */
427 if (cpu_has(c, X86_FEATURE_TME))
428 detect_tme_early(c);
429 }
430
bsp_init_intel(struct cpuinfo_x86 * c)431 static void bsp_init_intel(struct cpuinfo_x86 *c)
432 {
433 resctrl_cpu_detect(c);
434 }
435
436 #ifdef CONFIG_X86_32
437 /*
438 * Early probe support logic for ppro memory erratum #50
439 *
440 * This is called before we do cpu ident work
441 */
442
ppro_with_ram_bug(void)443 int ppro_with_ram_bug(void)
444 {
445 /* Uses data from early_cpu_detect now */
446 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
447 boot_cpu_data.x86 == 6 &&
448 boot_cpu_data.x86_model == 1 &&
449 boot_cpu_data.x86_stepping < 8) {
450 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
451 return 1;
452 }
453 return 0;
454 }
455
intel_smp_check(struct cpuinfo_x86 * c)456 static void intel_smp_check(struct cpuinfo_x86 *c)
457 {
458 /* calling is from identify_secondary_cpu() ? */
459 if (!c->cpu_index)
460 return;
461
462 /*
463 * Mask B, Pentium, but not Pentium MMX
464 */
465 if (c->x86 == 5 &&
466 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
467 c->x86_model <= 3) {
468 /*
469 * Remember we have B step Pentia with bugs
470 */
471 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
472 "with B stepping processors.\n");
473 }
474 }
475
476 static int forcepae;
forcepae_setup(char * __unused)477 static int __init forcepae_setup(char *__unused)
478 {
479 forcepae = 1;
480 return 1;
481 }
482 __setup("forcepae", forcepae_setup);
483
intel_workarounds(struct cpuinfo_x86 * c)484 static void intel_workarounds(struct cpuinfo_x86 *c)
485 {
486 #ifdef CONFIG_X86_F00F_BUG
487 /*
488 * All models of Pentium and Pentium with MMX technology CPUs
489 * have the F0 0F bug, which lets nonprivileged users lock up the
490 * system. Announce that the fault handler will be checking for it.
491 * The Quark is also family 5, but does not have the same bug.
492 */
493 clear_cpu_bug(c, X86_BUG_F00F);
494 if (c->x86 == 5 && c->x86_model < 9) {
495 static int f00f_workaround_enabled;
496
497 set_cpu_bug(c, X86_BUG_F00F);
498 if (!f00f_workaround_enabled) {
499 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
500 f00f_workaround_enabled = 1;
501 }
502 }
503 #endif
504
505 /*
506 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
507 * model 3 mask 3
508 */
509 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
510 clear_cpu_cap(c, X86_FEATURE_SEP);
511
512 /*
513 * PAE CPUID issue: many Pentium M report no PAE but may have a
514 * functionally usable PAE implementation.
515 * Forcefully enable PAE if kernel parameter "forcepae" is present.
516 */
517 if (forcepae) {
518 pr_warn("PAE forced!\n");
519 set_cpu_cap(c, X86_FEATURE_PAE);
520 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
521 }
522
523 /*
524 * P4 Xeon erratum 037 workaround.
525 * Hardware prefetcher may cause stale data to be loaded into the cache.
526 */
527 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
528 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
529 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
530 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
531 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
532 }
533 }
534
535 /*
536 * See if we have a good local APIC by checking for buggy Pentia,
537 * i.e. all B steppings and the C2 stepping of P54C when using their
538 * integrated APIC (see 11AP erratum in "Pentium Processor
539 * Specification Update").
540 */
541 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
542 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
543 set_cpu_bug(c, X86_BUG_11AP);
544
545
546 #ifdef CONFIG_X86_INTEL_USERCOPY
547 /*
548 * Set up the preferred alignment for movsl bulk memory moves
549 */
550 switch (c->x86) {
551 case 4: /* 486: untested */
552 break;
553 case 5: /* Old Pentia: untested */
554 break;
555 case 6: /* PII/PIII only like movsl with 8-byte alignment */
556 movsl_mask.mask = 7;
557 break;
558 case 15: /* P4 is OK down to 8-byte alignment */
559 movsl_mask.mask = 7;
560 break;
561 }
562 #endif
563
564 intel_smp_check(c);
565 }
566 #else
intel_workarounds(struct cpuinfo_x86 * c)567 static void intel_workarounds(struct cpuinfo_x86 *c)
568 {
569 }
570 #endif
571
srat_detect_node(struct cpuinfo_x86 * c)572 static void srat_detect_node(struct cpuinfo_x86 *c)
573 {
574 #ifdef CONFIG_NUMA
575 unsigned node;
576 int cpu = smp_processor_id();
577
578 /* Don't do the funky fallback heuristics the AMD version employs
579 for now. */
580 node = numa_cpu_node(cpu);
581 if (node == NUMA_NO_NODE || !node_online(node)) {
582 /* reuse the value from init_cpu_to_node() */
583 node = cpu_to_node(cpu);
584 }
585 numa_set_node(cpu, node);
586 #endif
587 }
588
init_cpuid_fault(struct cpuinfo_x86 * c)589 static void init_cpuid_fault(struct cpuinfo_x86 *c)
590 {
591 u64 msr;
592
593 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
594 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
595 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
596 }
597 }
598
init_intel_misc_features(struct cpuinfo_x86 * c)599 static void init_intel_misc_features(struct cpuinfo_x86 *c)
600 {
601 u64 msr;
602
603 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
604 return;
605
606 /* Clear all MISC features */
607 this_cpu_write(msr_misc_features_shadow, 0);
608
609 /* Check features and update capabilities and shadow control bits */
610 init_cpuid_fault(c);
611 probe_xeon_phi_r3mwait(c);
612
613 msr = this_cpu_read(msr_misc_features_shadow);
614 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
615 }
616
617 static void split_lock_init(void);
618 static void bus_lock_init(void);
619
init_intel(struct cpuinfo_x86 * c)620 static void init_intel(struct cpuinfo_x86 *c)
621 {
622 early_init_intel(c);
623
624 intel_workarounds(c);
625
626 /*
627 * Detect the extended topology information if available. This
628 * will reinitialise the initial_apicid which will be used
629 * in init_intel_cacheinfo()
630 */
631 detect_extended_topology(c);
632
633 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
634 /*
635 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
636 * detection.
637 */
638 detect_num_cpu_cores(c);
639 #ifdef CONFIG_X86_32
640 detect_ht(c);
641 #endif
642 }
643
644 init_intel_cacheinfo(c);
645
646 if (c->cpuid_level > 9) {
647 unsigned eax = cpuid_eax(10);
648 /* Check for version and the number of counters */
649 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
650 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
651 }
652
653 if (cpu_has(c, X86_FEATURE_XMM2))
654 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
655
656 if (boot_cpu_has(X86_FEATURE_DS)) {
657 unsigned int l1, l2;
658
659 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
660 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
661 set_cpu_cap(c, X86_FEATURE_BTS);
662 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
663 set_cpu_cap(c, X86_FEATURE_PEBS);
664 }
665
666 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
667 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
668 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
669
670 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
671 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
672 set_cpu_bug(c, X86_BUG_MONITOR);
673
674 #ifdef CONFIG_X86_64
675 if (c->x86 == 15)
676 c->x86_cache_alignment = c->x86_clflush_size * 2;
677 if (c->x86 == 6)
678 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
679 #else
680 /*
681 * Names for the Pentium II/Celeron processors
682 * detectable only by also checking the cache size.
683 * Dixon is NOT a Celeron.
684 */
685 if (c->x86 == 6) {
686 unsigned int l2 = c->x86_cache_size;
687 char *p = NULL;
688
689 switch (c->x86_model) {
690 case 5:
691 if (l2 == 0)
692 p = "Celeron (Covington)";
693 else if (l2 == 256)
694 p = "Mobile Pentium II (Dixon)";
695 break;
696
697 case 6:
698 if (l2 == 128)
699 p = "Celeron (Mendocino)";
700 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
701 p = "Celeron-A";
702 break;
703
704 case 8:
705 if (l2 == 128)
706 p = "Celeron (Coppermine)";
707 break;
708 }
709
710 if (p)
711 strcpy(c->x86_model_id, p);
712 }
713
714 if (c->x86 == 15)
715 set_cpu_cap(c, X86_FEATURE_P4);
716 if (c->x86 == 6)
717 set_cpu_cap(c, X86_FEATURE_P3);
718 #endif
719
720 /* Work around errata */
721 srat_detect_node(c);
722
723 init_ia32_feat_ctl(c);
724
725 init_intel_misc_features(c);
726
727 split_lock_init();
728 bus_lock_init();
729
730 intel_init_thermal(c);
731 }
732
733 #ifdef CONFIG_X86_32
intel_size_cache(struct cpuinfo_x86 * c,unsigned int size)734 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
735 {
736 /*
737 * Intel PIII Tualatin. This comes in two flavours.
738 * One has 256kb of cache, the other 512. We have no way
739 * to determine which, so we use a boottime override
740 * for the 512kb model, and assume 256 otherwise.
741 */
742 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
743 size = 256;
744
745 /*
746 * Intel Quark SoC X1000 contains a 4-way set associative
747 * 16K cache with a 16 byte cache line and 256 lines per tag
748 */
749 if ((c->x86 == 5) && (c->x86_model == 9))
750 size = 16;
751 return size;
752 }
753 #endif
754
755 #define TLB_INST_4K 0x01
756 #define TLB_INST_4M 0x02
757 #define TLB_INST_2M_4M 0x03
758
759 #define TLB_INST_ALL 0x05
760 #define TLB_INST_1G 0x06
761
762 #define TLB_DATA_4K 0x11
763 #define TLB_DATA_4M 0x12
764 #define TLB_DATA_2M_4M 0x13
765 #define TLB_DATA_4K_4M 0x14
766
767 #define TLB_DATA_1G 0x16
768
769 #define TLB_DATA0_4K 0x21
770 #define TLB_DATA0_4M 0x22
771 #define TLB_DATA0_2M_4M 0x23
772
773 #define STLB_4K 0x41
774 #define STLB_4K_2M 0x42
775
776 static const struct _tlb_table intel_tlb_table[] = {
777 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
778 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
779 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
780 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
781 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
782 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
783 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
784 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
785 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
786 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
787 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
788 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
789 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
790 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
791 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
792 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
793 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
794 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
795 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
796 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
797 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
798 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
799 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
800 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
801 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
802 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
803 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
804 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
805 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
806 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
807 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
808 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
809 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
810 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
811 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
812 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
813 { 0x00, 0, 0 }
814 };
815
intel_tlb_lookup(const unsigned char desc)816 static void intel_tlb_lookup(const unsigned char desc)
817 {
818 unsigned char k;
819 if (desc == 0)
820 return;
821
822 /* look up this descriptor in the table */
823 for (k = 0; intel_tlb_table[k].descriptor != desc &&
824 intel_tlb_table[k].descriptor != 0; k++)
825 ;
826
827 if (intel_tlb_table[k].tlb_type == 0)
828 return;
829
830 switch (intel_tlb_table[k].tlb_type) {
831 case STLB_4K:
832 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
833 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
834 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
835 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
836 break;
837 case STLB_4K_2M:
838 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
839 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
840 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
841 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
842 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
843 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
844 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
845 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
846 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
847 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
848 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
849 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
850 break;
851 case TLB_INST_ALL:
852 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
853 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
854 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
855 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
856 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
857 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
858 break;
859 case TLB_INST_4K:
860 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
861 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
862 break;
863 case TLB_INST_4M:
864 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
865 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
866 break;
867 case TLB_INST_2M_4M:
868 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
869 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
870 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
871 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
872 break;
873 case TLB_DATA_4K:
874 case TLB_DATA0_4K:
875 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
876 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
877 break;
878 case TLB_DATA_4M:
879 case TLB_DATA0_4M:
880 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
881 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
882 break;
883 case TLB_DATA_2M_4M:
884 case TLB_DATA0_2M_4M:
885 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
886 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
887 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
888 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
889 break;
890 case TLB_DATA_4K_4M:
891 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
892 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
893 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
894 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
895 break;
896 case TLB_DATA_1G:
897 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
898 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
899 break;
900 }
901 }
902
intel_detect_tlb(struct cpuinfo_x86 * c)903 static void intel_detect_tlb(struct cpuinfo_x86 *c)
904 {
905 int i, j, n;
906 unsigned int regs[4];
907 unsigned char *desc = (unsigned char *)regs;
908
909 if (c->cpuid_level < 2)
910 return;
911
912 /* Number of times to iterate */
913 n = cpuid_eax(2) & 0xFF;
914
915 for (i = 0 ; i < n ; i++) {
916 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
917
918 /* If bit 31 is set, this is an unknown format */
919 for (j = 0 ; j < 3 ; j++)
920 if (regs[j] & (1 << 31))
921 regs[j] = 0;
922
923 /* Byte 0 is level count, not a descriptor */
924 for (j = 1 ; j < 16 ; j++)
925 intel_tlb_lookup(desc[j]);
926 }
927 }
928
929 static const struct cpu_dev intel_cpu_dev = {
930 .c_vendor = "Intel",
931 .c_ident = { "GenuineIntel" },
932 #ifdef CONFIG_X86_32
933 .legacy_models = {
934 { .family = 4, .model_names =
935 {
936 [0] = "486 DX-25/33",
937 [1] = "486 DX-50",
938 [2] = "486 SX",
939 [3] = "486 DX/2",
940 [4] = "486 SL",
941 [5] = "486 SX/2",
942 [7] = "486 DX/2-WB",
943 [8] = "486 DX/4",
944 [9] = "486 DX/4-WB"
945 }
946 },
947 { .family = 5, .model_names =
948 {
949 [0] = "Pentium 60/66 A-step",
950 [1] = "Pentium 60/66",
951 [2] = "Pentium 75 - 200",
952 [3] = "OverDrive PODP5V83",
953 [4] = "Pentium MMX",
954 [7] = "Mobile Pentium 75 - 200",
955 [8] = "Mobile Pentium MMX",
956 [9] = "Quark SoC X1000",
957 }
958 },
959 { .family = 6, .model_names =
960 {
961 [0] = "Pentium Pro A-step",
962 [1] = "Pentium Pro",
963 [3] = "Pentium II (Klamath)",
964 [4] = "Pentium II (Deschutes)",
965 [5] = "Pentium II (Deschutes)",
966 [6] = "Mobile Pentium II",
967 [7] = "Pentium III (Katmai)",
968 [8] = "Pentium III (Coppermine)",
969 [10] = "Pentium III (Cascades)",
970 [11] = "Pentium III (Tualatin)",
971 }
972 },
973 { .family = 15, .model_names =
974 {
975 [0] = "Pentium 4 (Unknown)",
976 [1] = "Pentium 4 (Willamette)",
977 [2] = "Pentium 4 (Northwood)",
978 [4] = "Pentium 4 (Foster)",
979 [5] = "Pentium 4 (Foster)",
980 }
981 },
982 },
983 .legacy_cache_size = intel_size_cache,
984 #endif
985 .c_detect_tlb = intel_detect_tlb,
986 .c_early_init = early_init_intel,
987 .c_bsp_init = bsp_init_intel,
988 .c_init = init_intel,
989 .c_x86_vendor = X86_VENDOR_INTEL,
990 };
991
992 cpu_dev_register(intel_cpu_dev);
993
994 #undef pr_fmt
995 #define pr_fmt(fmt) "x86/split lock detection: " fmt
996
997 static const struct {
998 const char *option;
999 enum split_lock_detect_state state;
1000 } sld_options[] __initconst = {
1001 { "off", sld_off },
1002 { "warn", sld_warn },
1003 { "fatal", sld_fatal },
1004 { "ratelimit:", sld_ratelimit },
1005 };
1006
1007 static struct ratelimit_state bld_ratelimit;
1008
1009 static unsigned int sysctl_sld_mitigate = 1;
1010 static DEFINE_SEMAPHORE(buslock_sem, 1);
1011
1012 #ifdef CONFIG_PROC_SYSCTL
1013 static struct ctl_table sld_sysctls[] = {
1014 {
1015 .procname = "split_lock_mitigate",
1016 .data = &sysctl_sld_mitigate,
1017 .maxlen = sizeof(unsigned int),
1018 .mode = 0644,
1019 .proc_handler = proc_douintvec_minmax,
1020 .extra1 = SYSCTL_ZERO,
1021 .extra2 = SYSCTL_ONE,
1022 },
1023 {}
1024 };
1025
sld_mitigate_sysctl_init(void)1026 static int __init sld_mitigate_sysctl_init(void)
1027 {
1028 register_sysctl_init("kernel", sld_sysctls);
1029 return 0;
1030 }
1031
1032 late_initcall(sld_mitigate_sysctl_init);
1033 #endif
1034
match_option(const char * arg,int arglen,const char * opt)1035 static inline bool match_option(const char *arg, int arglen, const char *opt)
1036 {
1037 int len = strlen(opt), ratelimit;
1038
1039 if (strncmp(arg, opt, len))
1040 return false;
1041
1042 /*
1043 * Min ratelimit is 1 bus lock/sec.
1044 * Max ratelimit is 1000 bus locks/sec.
1045 */
1046 if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 &&
1047 ratelimit > 0 && ratelimit <= 1000) {
1048 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit);
1049 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE);
1050 return true;
1051 }
1052
1053 return len == arglen;
1054 }
1055
split_lock_verify_msr(bool on)1056 static bool split_lock_verify_msr(bool on)
1057 {
1058 u64 ctrl, tmp;
1059
1060 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
1061 return false;
1062 if (on)
1063 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1064 else
1065 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1066 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1067 return false;
1068 rdmsrl(MSR_TEST_CTRL, tmp);
1069 return ctrl == tmp;
1070 }
1071
sld_state_setup(void)1072 static void __init sld_state_setup(void)
1073 {
1074 enum split_lock_detect_state state = sld_warn;
1075 char arg[20];
1076 int i, ret;
1077
1078 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1079 !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1080 return;
1081
1082 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1083 arg, sizeof(arg));
1084 if (ret >= 0) {
1085 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1086 if (match_option(arg, ret, sld_options[i].option)) {
1087 state = sld_options[i].state;
1088 break;
1089 }
1090 }
1091 }
1092 sld_state = state;
1093 }
1094
__split_lock_setup(void)1095 static void __init __split_lock_setup(void)
1096 {
1097 if (!split_lock_verify_msr(false)) {
1098 pr_info("MSR access failed: Disabled\n");
1099 return;
1100 }
1101
1102 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1103
1104 if (!split_lock_verify_msr(true)) {
1105 pr_info("MSR access failed: Disabled\n");
1106 return;
1107 }
1108
1109 /* Restore the MSR to its cached value. */
1110 wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1111
1112 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1113 }
1114
1115 /*
1116 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1117 * is not implemented as one thread could undo the setting of the other
1118 * thread immediately after dropping the lock anyway.
1119 */
sld_update_msr(bool on)1120 static void sld_update_msr(bool on)
1121 {
1122 u64 test_ctrl_val = msr_test_ctrl_cache;
1123
1124 if (on)
1125 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1126
1127 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1128 }
1129
split_lock_init(void)1130 static void split_lock_init(void)
1131 {
1132 /*
1133 * #DB for bus lock handles ratelimit and #AC for split lock is
1134 * disabled.
1135 */
1136 if (sld_state == sld_ratelimit) {
1137 split_lock_verify_msr(false);
1138 return;
1139 }
1140
1141 if (cpu_model_supports_sld)
1142 split_lock_verify_msr(sld_state != sld_off);
1143 }
1144
__split_lock_reenable_unlock(struct work_struct * work)1145 static void __split_lock_reenable_unlock(struct work_struct *work)
1146 {
1147 sld_update_msr(true);
1148 up(&buslock_sem);
1149 }
1150
1151 static DECLARE_DELAYED_WORK(sl_reenable_unlock, __split_lock_reenable_unlock);
1152
__split_lock_reenable(struct work_struct * work)1153 static void __split_lock_reenable(struct work_struct *work)
1154 {
1155 sld_update_msr(true);
1156 }
1157 static DECLARE_DELAYED_WORK(sl_reenable, __split_lock_reenable);
1158
1159 /*
1160 * If a CPU goes offline with pending delayed work to re-enable split lock
1161 * detection then the delayed work will be executed on some other CPU. That
1162 * handles releasing the buslock_sem, but because it executes on a
1163 * different CPU probably won't re-enable split lock detection. This is a
1164 * problem on HT systems since the sibling CPU on the same core may then be
1165 * left running with split lock detection disabled.
1166 *
1167 * Unconditionally re-enable detection here.
1168 */
splitlock_cpu_offline(unsigned int cpu)1169 static int splitlock_cpu_offline(unsigned int cpu)
1170 {
1171 sld_update_msr(true);
1172
1173 return 0;
1174 }
1175
split_lock_warn(unsigned long ip)1176 static void split_lock_warn(unsigned long ip)
1177 {
1178 struct delayed_work *work;
1179 int cpu;
1180
1181 if (!current->reported_split_lock)
1182 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1183 current->comm, current->pid, ip);
1184 current->reported_split_lock = 1;
1185
1186 if (sysctl_sld_mitigate) {
1187 /*
1188 * misery factor #1:
1189 * sleep 10ms before trying to execute split lock.
1190 */
1191 if (msleep_interruptible(10) > 0)
1192 return;
1193 /*
1194 * Misery factor #2:
1195 * only allow one buslocked disabled core at a time.
1196 */
1197 if (down_interruptible(&buslock_sem) == -EINTR)
1198 return;
1199 work = &sl_reenable_unlock;
1200 } else {
1201 work = &sl_reenable;
1202 }
1203
1204 cpu = get_cpu();
1205 schedule_delayed_work_on(cpu, work, 2);
1206
1207 /* Disable split lock detection on this CPU to make progress */
1208 sld_update_msr(false);
1209 put_cpu();
1210 }
1211
handle_guest_split_lock(unsigned long ip)1212 bool handle_guest_split_lock(unsigned long ip)
1213 {
1214 if (sld_state == sld_warn) {
1215 split_lock_warn(ip);
1216 return true;
1217 }
1218
1219 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1220 current->comm, current->pid,
1221 sld_state == sld_fatal ? "fatal" : "bogus", ip);
1222
1223 current->thread.error_code = 0;
1224 current->thread.trap_nr = X86_TRAP_AC;
1225 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1226 return false;
1227 }
1228 EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1229
bus_lock_init(void)1230 static void bus_lock_init(void)
1231 {
1232 u64 val;
1233
1234 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1235 return;
1236
1237 rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
1238
1239 if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1240 (sld_state == sld_warn || sld_state == sld_fatal)) ||
1241 sld_state == sld_off) {
1242 /*
1243 * Warn and fatal are handled by #AC for split lock if #AC for
1244 * split lock is supported.
1245 */
1246 val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1247 } else {
1248 val |= DEBUGCTLMSR_BUS_LOCK_DETECT;
1249 }
1250
1251 wrmsrl(MSR_IA32_DEBUGCTLMSR, val);
1252 }
1253
handle_user_split_lock(struct pt_regs * regs,long error_code)1254 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1255 {
1256 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1257 return false;
1258 split_lock_warn(regs->ip);
1259 return true;
1260 }
1261
handle_bus_lock(struct pt_regs * regs)1262 void handle_bus_lock(struct pt_regs *regs)
1263 {
1264 switch (sld_state) {
1265 case sld_off:
1266 break;
1267 case sld_ratelimit:
1268 /* Enforce no more than bld_ratelimit bus locks/sec. */
1269 while (!__ratelimit(&bld_ratelimit))
1270 msleep(20);
1271 /* Warn on the bus lock. */
1272 fallthrough;
1273 case sld_warn:
1274 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",
1275 current->comm, current->pid, regs->ip);
1276 break;
1277 case sld_fatal:
1278 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1279 break;
1280 }
1281 }
1282
1283 /*
1284 * CPU models that are known to have the per-core split-lock detection
1285 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1286 */
1287 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1288 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
1289 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
1290 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
1291 {}
1292 };
1293
split_lock_setup(struct cpuinfo_x86 * c)1294 static void __init split_lock_setup(struct cpuinfo_x86 *c)
1295 {
1296 const struct x86_cpu_id *m;
1297 u64 ia32_core_caps;
1298
1299 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1300 return;
1301
1302 /* Check for CPUs that have support but do not enumerate it: */
1303 m = x86_match_cpu(split_lock_cpu_ids);
1304 if (m)
1305 goto supported;
1306
1307 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1308 return;
1309
1310 /*
1311 * Not all bits in MSR_IA32_CORE_CAPS are architectural, but
1312 * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is. All CPUs that set
1313 * it have split lock detection.
1314 */
1315 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1316 if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)
1317 goto supported;
1318
1319 /* CPU is not in the model list and does not have the MSR bit: */
1320 return;
1321
1322 supported:
1323 cpu_model_supports_sld = true;
1324 __split_lock_setup();
1325 }
1326
sld_state_show(void)1327 static void sld_state_show(void)
1328 {
1329 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
1330 !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1331 return;
1332
1333 switch (sld_state) {
1334 case sld_off:
1335 pr_info("disabled\n");
1336 break;
1337 case sld_warn:
1338 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1339 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1340 if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1341 "x86/splitlock", NULL, splitlock_cpu_offline) < 0)
1342 pr_warn("No splitlock CPU offline handler\n");
1343 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1344 pr_info("#DB: warning on user-space bus_locks\n");
1345 }
1346 break;
1347 case sld_fatal:
1348 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1349 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1350 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1351 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1352 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
1353 " from non-WB" : "");
1354 }
1355 break;
1356 case sld_ratelimit:
1357 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1358 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst);
1359 break;
1360 }
1361 }
1362
sld_setup(struct cpuinfo_x86 * c)1363 void __init sld_setup(struct cpuinfo_x86 *c)
1364 {
1365 split_lock_setup(c);
1366 sld_state_setup();
1367 sld_state_show();
1368 }
1369
1370 #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24
1371
1372 /**
1373 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
1374 *
1375 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
1376 * a hybrid processor. If the processor is not hybrid, returns 0.
1377 */
get_this_hybrid_cpu_type(void)1378 u8 get_this_hybrid_cpu_type(void)
1379 {
1380 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1381 return 0;
1382
1383 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;
1384 }
1385