1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/delay.h> 4 #include <linux/pci.h> 5 #include <asm/dma.h> 6 #include <asm/io.h> 7 #include <asm/processor-cyrix.h> 8 #include <asm/processor-flags.h> 9 #include <asm/timer.h> 10 #include <asm/pci-direct.h> 11 #include <asm/tsc.h> 12 13 #include "cpu.h" 14 15 /* 16 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU 17 */ 18 static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) 19 { 20 unsigned char ccr2, ccr3; 21 unsigned long flags; 22 23 /* we test for DEVID by checking whether CCR3 is writable */ 24 local_irq_save(flags); 25 ccr3 = getCx86(CX86_CCR3); 26 setCx86(CX86_CCR3, ccr3 ^ 0x80); 27 getCx86(0xc0); /* dummy to change bus */ 28 29 if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */ 30 ccr2 = getCx86(CX86_CCR2); 31 setCx86(CX86_CCR2, ccr2 ^ 0x04); 32 getCx86(0xc0); /* dummy */ 33 34 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */ 35 *dir0 = 0xfd; 36 else { /* Cx486S A step */ 37 setCx86(CX86_CCR2, ccr2); 38 *dir0 = 0xfe; 39 } 40 } else { 41 setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ 42 43 /* read DIR0 and DIR1 CPU registers */ 44 *dir0 = getCx86(CX86_DIR0); 45 *dir1 = getCx86(CX86_DIR1); 46 } 47 local_irq_restore(flags); 48 } 49 50 /* 51 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in 52 * order to identify the Cyrix CPU model after we're out of setup.c 53 * 54 * Actually since bugs.h doesn't even reference this perhaps someone should 55 * fix the documentation ??? 56 */ 57 static unsigned char Cx86_dir0_msb __cpuinitdata = 0; 58 59 static char Cx86_model[][9] __cpuinitdata = { 60 "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ", 61 "M II ", "Unknown" 62 }; 63 static char Cx486_name[][5] __cpuinitdata = { 64 "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx", 65 "SRx2", "DRx2" 66 }; 67 static char Cx486S_name[][4] __cpuinitdata = { 68 "S", "S2", "Se", "S2e" 69 }; 70 static char Cx486D_name[][4] __cpuinitdata = { 71 "DX", "DX2", "?", "?", "?", "DX4" 72 }; 73 static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock"; 74 static char cyrix_model_mult1[] __cpuinitdata = "12??43"; 75 static char cyrix_model_mult2[] __cpuinitdata = "12233445"; 76 77 /* 78 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old 79 * BIOSes for compatibility with DOS games. This makes the udelay loop 80 * work correctly, and improves performance. 81 * 82 * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP 83 */ 84 85 static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c) 86 { 87 unsigned long flags; 88 89 if (Cx86_dir0_msb == 3) { 90 unsigned char ccr3, ccr5; 91 92 local_irq_save(flags); 93 ccr3 = getCx86(CX86_CCR3); 94 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 95 ccr5 = getCx86(CX86_CCR5); 96 if (ccr5 & 2) 97 setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */ 98 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 99 local_irq_restore(flags); 100 101 if (ccr5 & 2) { /* possible wrong calibration done */ 102 printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n"); 103 calibrate_delay(); 104 c->loops_per_jiffy = loops_per_jiffy; 105 } 106 } 107 } 108 109 110 static void __cpuinit set_cx86_reorder(void) 111 { 112 u8 ccr3; 113 114 printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n"); 115 ccr3 = getCx86(CX86_CCR3); 116 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 117 118 /* Load/Store Serialize to mem access disable (=reorder it) */ 119 setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80); 120 /* set load/store serialize from 1GB to 4GB */ 121 ccr3 |= 0xe0; 122 setCx86(CX86_CCR3, ccr3); 123 } 124 125 static void __cpuinit set_cx86_memwb(void) 126 { 127 printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n"); 128 129 /* CCR2 bit 2: unlock NW bit */ 130 setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04); 131 /* set 'Not Write-through' */ 132 write_cr0(read_cr0() | X86_CR0_NW); 133 /* CCR2 bit 2: lock NW bit and set WT1 */ 134 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14); 135 } 136 137 static void __cpuinit set_cx86_inc(void) 138 { 139 unsigned char ccr3; 140 141 printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n"); 142 143 ccr3 = getCx86(CX86_CCR3); 144 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 145 /* PCR1 -- Performance Control */ 146 /* Incrementor on, whatever that is */ 147 setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02); 148 /* PCR0 -- Performance Control */ 149 /* Incrementor Margin 10 */ 150 setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04); 151 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 152 } 153 154 /* 155 * Configure later MediaGX and/or Geode processor. 156 */ 157 158 static void __cpuinit geode_configure(void) 159 { 160 unsigned long flags; 161 u8 ccr3; 162 local_irq_save(flags); 163 164 /* Suspend on halt power saving and enable #SUSP pin */ 165 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); 166 167 ccr3 = getCx86(CX86_CCR3); 168 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 169 170 171 /* FPU fast, DTE cache, Mem bypass */ 172 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38); 173 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 174 175 set_cx86_memwb(); 176 set_cx86_reorder(); 177 set_cx86_inc(); 178 179 local_irq_restore(flags); 180 } 181 182 183 static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) 184 { 185 unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0; 186 char *buf = c->x86_model_id; 187 const char *p = NULL; 188 189 /* 190 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 191 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 192 */ 193 clear_cpu_cap(c, 0*32+31); 194 195 /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */ 196 if (test_cpu_cap(c, 1*32+24)) { 197 clear_cpu_cap(c, 1*32+24); 198 set_cpu_cap(c, X86_FEATURE_CXMMX); 199 } 200 201 do_cyrix_devid(&dir0, &dir1); 202 203 check_cx686_slop(c); 204 205 Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */ 206 dir0_lsn = dir0 & 0xf; /* model or clock multiplier */ 207 208 /* common case step number/rev -- exceptions handled below */ 209 c->x86_model = (dir1 >> 4) + 1; 210 c->x86_mask = dir1 & 0xf; 211 212 /* Now cook; the original recipe is by Channing Corn, from Cyrix. 213 * We do the same thing for each generation: we work out 214 * the model, multiplier and stepping. Black magic included, 215 * to make the silicon step/rev numbers match the printed ones. 216 */ 217 218 switch (dir0_msn) { 219 unsigned char tmp; 220 221 case 0: /* Cx486SLC/DLC/SRx/DRx */ 222 p = Cx486_name[dir0_lsn & 7]; 223 break; 224 225 case 1: /* Cx486S/DX/DX2/DX4 */ 226 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5] 227 : Cx486S_name[dir0_lsn & 3]; 228 break; 229 230 case 2: /* 5x86 */ 231 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]; 232 p = Cx86_cb+2; 233 break; 234 235 case 3: /* 6x86/6x86L */ 236 Cx86_cb[1] = ' '; 237 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]; 238 if (dir1 > 0x21) { /* 686L */ 239 Cx86_cb[0] = 'L'; 240 p = Cx86_cb; 241 (c->x86_model)++; 242 } else /* 686 */ 243 p = Cx86_cb+1; 244 /* Emulate MTRRs using Cyrix's ARRs. */ 245 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 246 /* 6x86's contain this bug */ 247 c->coma_bug = 1; 248 break; 249 250 case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */ 251 #ifdef CONFIG_PCI 252 { 253 u32 vendor, device; 254 /* 255 * It isn't really a PCI quirk directly, but the cure is the 256 * same. The MediaGX has deep magic SMM stuff that handles the 257 * SB emulation. It throws away the fifo on disable_dma() which 258 * is wrong and ruins the audio. 259 * 260 * Bug2: VSA1 has a wrap bug so that using maximum sized DMA 261 * causes bad things. According to NatSemi VSA2 has another 262 * bug to do with 'hlt'. I've not seen any boards using VSA2 263 * and X doesn't seem to support it either so who cares 8). 264 * VSA1 we work around however. 265 */ 266 267 printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n"); 268 isa_dma_bridge_buggy = 2; 269 270 /* We do this before the PCI layer is running. However we 271 are safe here as we know the bridge must be a Cyrix 272 companion and must be present */ 273 vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID); 274 device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID); 275 276 /* 277 * The 5510/5520 companion chips have a funky PIT. 278 */ 279 if (vendor == PCI_VENDOR_ID_CYRIX && 280 (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520)) 281 mark_tsc_unstable("cyrix 5510/5520 detected"); 282 } 283 #endif 284 c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */ 285 286 /* GXm supports extended cpuid levels 'ala' AMD */ 287 if (c->cpuid_level == 2) { 288 /* Enable cxMMX extensions (GX1 Datasheet 54) */ 289 setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1); 290 291 /* 292 * GXm : 0x30 ... 0x5f GXm datasheet 51 293 * GXlv: 0x6x GXlv datasheet 54 294 * ? : 0x7x 295 * GX1 : 0x8x GX1 datasheet 56 296 */ 297 if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f)) 298 geode_configure(); 299 get_model_name(c); /* get CPU marketing name */ 300 return; 301 } else { /* MediaGX */ 302 Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4'; 303 p = Cx86_cb+2; 304 c->x86_model = (dir1 & 0x20) ? 1 : 2; 305 } 306 break; 307 308 case 5: /* 6x86MX/M II */ 309 if (dir1 > 7) { 310 dir0_msn++; /* M II */ 311 /* Enable MMX extensions (App note 108) */ 312 setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1); 313 } else { 314 c->coma_bug = 1; /* 6x86MX, it has the bug. */ 315 } 316 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; 317 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]; 318 p = Cx86_cb+tmp; 319 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) 320 (c->x86_model)++; 321 /* Emulate MTRRs using Cyrix's ARRs. */ 322 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 323 break; 324 325 case 0xf: /* Cyrix 486 without DEVID registers */ 326 switch (dir0_lsn) { 327 case 0xd: /* either a 486SLC or DLC w/o DEVID */ 328 dir0_msn = 0; 329 p = Cx486_name[(c->hard_math) ? 1 : 0]; 330 break; 331 332 case 0xe: /* a 486S A step */ 333 dir0_msn = 0; 334 p = Cx486S_name[0]; 335 break; 336 } 337 break; 338 339 default: /* unknown (shouldn't happen, we know everyone ;-) */ 340 dir0_msn = 7; 341 break; 342 } 343 strcpy(buf, Cx86_model[dir0_msn & 7]); 344 if (p) 345 strcat(buf, p); 346 return; 347 } 348 349 /* 350 * Handle National Semiconductor branded processors 351 */ 352 static void __cpuinit init_nsc(struct cpuinfo_x86 *c) 353 { 354 /* 355 * There may be GX1 processors in the wild that are branded 356 * NSC and not Cyrix. 357 * 358 * This function only handles the GX processor, and kicks every 359 * thing else to the Cyrix init function above - that should 360 * cover any processors that might have been branded differently 361 * after NSC acquired Cyrix. 362 * 363 * If this breaks your GX1 horribly, please e-mail 364 * info-linux@ldcmail.amd.com to tell us. 365 */ 366 367 /* Handle the GX (Formally known as the GX2) */ 368 369 if (c->x86 == 5 && c->x86_model == 5) 370 display_cacheinfo(c); 371 else 372 init_cyrix(c); 373 } 374 375 /* 376 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 377 * by the fact that they preserve the flags across the division of 5/2. 378 * PII and PPro exhibit this behavior too, but they have cpuid available. 379 */ 380 381 /* 382 * Perform the Cyrix 5/2 test. A Cyrix won't change 383 * the flags, while other 486 chips will. 384 */ 385 static inline int test_cyrix_52div(void) 386 { 387 unsigned int test; 388 389 __asm__ __volatile__( 390 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 391 "div %b2\n\t" /* divide 5 by 2 */ 392 "lahf" /* store flags into %ah */ 393 : "=a" (test) 394 : "0" (5), "q" (2) 395 : "cc"); 396 397 /* AH is 0x02 on Cyrix after the divide.. */ 398 return (unsigned char) (test >> 8) == 0x02; 399 } 400 401 static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c) 402 { 403 /* Detect Cyrix with disabled CPUID */ 404 if (c->x86 == 4 && test_cyrix_52div()) { 405 unsigned char dir0, dir1; 406 407 strcpy(c->x86_vendor_id, "CyrixInstead"); 408 c->x86_vendor = X86_VENDOR_CYRIX; 409 410 /* Actually enable cpuid on the older cyrix */ 411 412 /* Retrieve CPU revisions */ 413 414 do_cyrix_devid(&dir0, &dir1); 415 416 dir0 >>= 4; 417 418 /* Check it is an affected model */ 419 420 if (dir0 == 5 || dir0 == 3) { 421 unsigned char ccr3; 422 unsigned long flags; 423 printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n"); 424 local_irq_save(flags); 425 ccr3 = getCx86(CX86_CCR3); 426 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 427 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80); /* enable cpuid */ 428 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 429 local_irq_restore(flags); 430 } 431 } 432 } 433 434 static struct cpu_dev cyrix_cpu_dev __cpuinitdata = { 435 .c_vendor = "Cyrix", 436 .c_ident = { "CyrixInstead" }, 437 .c_init = init_cyrix, 438 .c_identify = cyrix_identify, 439 }; 440 441 cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev); 442 443 static struct cpu_dev nsc_cpu_dev __cpuinitdata = { 444 .c_vendor = "NSC", 445 .c_ident = { "Geode by NSC" }, 446 .c_init = init_nsc, 447 }; 448 449 cpu_vendor_dev_register(X86_VENDOR_NSC, &nsc_cpu_dev); 450