1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/bitops.h> 3 #include <linux/delay.h> 4 #include <linux/isa-dma.h> 5 #include <linux/pci.h> 6 #include <asm/dma.h> 7 #include <linux/io.h> 8 #include <asm/processor-cyrix.h> 9 #include <asm/processor-flags.h> 10 #include <linux/timer.h> 11 #include <asm/pci-direct.h> 12 #include <asm/tsc.h> 13 #include <asm/cpufeature.h> 14 #include <linux/sched.h> 15 #include <linux/sched/clock.h> 16 17 #include "cpu.h" 18 19 /* 20 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU 21 */ 22 static void __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) 23 { 24 unsigned char ccr2, ccr3; 25 26 /* we test for DEVID by checking whether CCR3 is writable */ 27 ccr3 = getCx86(CX86_CCR3); 28 setCx86(CX86_CCR3, ccr3 ^ 0x80); 29 getCx86(0xc0); /* dummy to change bus */ 30 31 if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */ 32 ccr2 = getCx86(CX86_CCR2); 33 setCx86(CX86_CCR2, ccr2 ^ 0x04); 34 getCx86(0xc0); /* dummy */ 35 36 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */ 37 *dir0 = 0xfd; 38 else { /* Cx486S A step */ 39 setCx86(CX86_CCR2, ccr2); 40 *dir0 = 0xfe; 41 } 42 } else { 43 setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ 44 45 /* read DIR0 and DIR1 CPU registers */ 46 *dir0 = getCx86(CX86_DIR0); 47 *dir1 = getCx86(CX86_DIR1); 48 } 49 } 50 51 static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) 52 { 53 unsigned long flags; 54 55 local_irq_save(flags); 56 __do_cyrix_devid(dir0, dir1); 57 local_irq_restore(flags); 58 } 59 /* 60 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in 61 * order to identify the Cyrix CPU model after we're out of setup.c 62 * 63 * Actually since bugs.h doesn't even reference this perhaps someone should 64 * fix the documentation ??? 65 */ 66 static unsigned char Cx86_dir0_msb = 0; 67 68 static const char Cx86_model[][9] = { 69 "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ", 70 "M II ", "Unknown" 71 }; 72 static const char Cx486_name[][5] = { 73 "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx", 74 "SRx2", "DRx2" 75 }; 76 static const char Cx486S_name[][4] = { 77 "S", "S2", "Se", "S2e" 78 }; 79 static const char Cx486D_name[][4] = { 80 "DX", "DX2", "?", "?", "?", "DX4" 81 }; 82 static char Cx86_cb[] = "?.5x Core/Bus Clock"; 83 static const char cyrix_model_mult1[] = "12??43"; 84 static const char cyrix_model_mult2[] = "12233445"; 85 86 /* 87 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old 88 * BIOSes for compatibility with DOS games. This makes the udelay loop 89 * work correctly, and improves performance. 90 * 91 * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP 92 */ 93 94 static void check_cx686_slop(struct cpuinfo_x86 *c) 95 { 96 unsigned long flags; 97 98 if (Cx86_dir0_msb == 3) { 99 unsigned char ccr3, ccr5; 100 101 local_irq_save(flags); 102 ccr3 = getCx86(CX86_CCR3); 103 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 104 ccr5 = getCx86(CX86_CCR5); 105 if (ccr5 & 2) 106 setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */ 107 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 108 local_irq_restore(flags); 109 110 if (ccr5 & 2) { /* possible wrong calibration done */ 111 pr_info("Recalibrating delay loop with SLOP bit reset\n"); 112 calibrate_delay(); 113 c->loops_per_jiffy = loops_per_jiffy; 114 } 115 } 116 } 117 118 119 static void set_cx86_reorder(void) 120 { 121 u8 ccr3; 122 123 pr_info("Enable Memory access reorder on Cyrix/NSC processor.\n"); 124 ccr3 = getCx86(CX86_CCR3); 125 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 126 127 /* Load/Store Serialize to mem access disable (=reorder it) */ 128 setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80); 129 /* set load/store serialize from 1GB to 4GB */ 130 ccr3 |= 0xe0; 131 setCx86(CX86_CCR3, ccr3); 132 } 133 134 static void set_cx86_memwb(void) 135 { 136 pr_info("Enable Memory-Write-back mode on Cyrix/NSC processor.\n"); 137 138 /* CCR2 bit 2: unlock NW bit */ 139 setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04); 140 /* set 'Not Write-through' */ 141 write_cr0(read_cr0() | X86_CR0_NW); 142 /* CCR2 bit 2: lock NW bit and set WT1 */ 143 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14); 144 } 145 146 /* 147 * Configure later MediaGX and/or Geode processor. 148 */ 149 150 static void geode_configure(void) 151 { 152 unsigned long flags; 153 u8 ccr3; 154 local_irq_save(flags); 155 156 /* Suspend on halt power saving and enable #SUSP pin */ 157 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); 158 159 ccr3 = getCx86(CX86_CCR3); 160 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 161 162 163 /* FPU fast, DTE cache, Mem bypass */ 164 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38); 165 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 166 167 set_cx86_memwb(); 168 set_cx86_reorder(); 169 170 local_irq_restore(flags); 171 } 172 173 static void early_init_cyrix(struct cpuinfo_x86 *c) 174 { 175 unsigned char dir0, dir0_msn, dir1 = 0; 176 177 __do_cyrix_devid(&dir0, &dir1); 178 dir0_msn = dir0 >> 4; /* identifies CPU "family" */ 179 180 switch (dir0_msn) { 181 case 3: /* 6x86/6x86L */ 182 /* Emulate MTRRs using Cyrix's ARRs. */ 183 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 184 break; 185 case 5: /* 6x86MX/M II */ 186 /* Emulate MTRRs using Cyrix's ARRs. */ 187 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 188 break; 189 } 190 } 191 192 static void init_cyrix(struct cpuinfo_x86 *c) 193 { 194 unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0; 195 char *buf = c->x86_model_id; 196 const char *p = NULL; 197 198 /* 199 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 200 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 201 */ 202 clear_cpu_cap(c, 0*32+31); 203 204 /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */ 205 if (test_cpu_cap(c, 1*32+24)) { 206 clear_cpu_cap(c, 1*32+24); 207 set_cpu_cap(c, X86_FEATURE_CXMMX); 208 } 209 210 do_cyrix_devid(&dir0, &dir1); 211 212 check_cx686_slop(c); 213 214 Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */ 215 dir0_lsn = dir0 & 0xf; /* model or clock multiplier */ 216 217 /* common case step number/rev -- exceptions handled below */ 218 c->x86_model = (dir1 >> 4) + 1; 219 c->x86_stepping = dir1 & 0xf; 220 221 /* Now cook; the original recipe is by Channing Corn, from Cyrix. 222 * We do the same thing for each generation: we work out 223 * the model, multiplier and stepping. Black magic included, 224 * to make the silicon step/rev numbers match the printed ones. 225 */ 226 227 switch (dir0_msn) { 228 unsigned char tmp; 229 230 case 0: /* Cx486SLC/DLC/SRx/DRx */ 231 p = Cx486_name[dir0_lsn & 7]; 232 break; 233 234 case 1: /* Cx486S/DX/DX2/DX4 */ 235 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5] 236 : Cx486S_name[dir0_lsn & 3]; 237 break; 238 239 case 2: /* 5x86 */ 240 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]; 241 p = Cx86_cb+2; 242 break; 243 244 case 3: /* 6x86/6x86L */ 245 Cx86_cb[1] = ' '; 246 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]; 247 if (dir1 > 0x21) { /* 686L */ 248 Cx86_cb[0] = 'L'; 249 p = Cx86_cb; 250 (c->x86_model)++; 251 } else /* 686 */ 252 p = Cx86_cb+1; 253 /* Emulate MTRRs using Cyrix's ARRs. */ 254 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 255 /* 6x86's contain this bug */ 256 set_cpu_bug(c, X86_BUG_COMA); 257 break; 258 259 case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */ 260 case 11: /* GX1 with inverted Device ID */ 261 #ifdef CONFIG_PCI 262 { 263 u32 vendor, device; 264 /* 265 * It isn't really a PCI quirk directly, but the cure is the 266 * same. The MediaGX has deep magic SMM stuff that handles the 267 * SB emulation. It throws away the fifo on disable_dma() which 268 * is wrong and ruins the audio. 269 * 270 * Bug2: VSA1 has a wrap bug so that using maximum sized DMA 271 * causes bad things. According to NatSemi VSA2 has another 272 * bug to do with 'hlt'. I've not seen any boards using VSA2 273 * and X doesn't seem to support it either so who cares 8). 274 * VSA1 we work around however. 275 */ 276 277 pr_info("Working around Cyrix MediaGX virtual DMA bugs.\n"); 278 isa_dma_bridge_buggy = 2; 279 280 /* We do this before the PCI layer is running. However we 281 are safe here as we know the bridge must be a Cyrix 282 companion and must be present */ 283 vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID); 284 device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID); 285 286 /* 287 * The 5510/5520 companion chips have a funky PIT. 288 */ 289 if (vendor == PCI_VENDOR_ID_CYRIX && 290 (device == PCI_DEVICE_ID_CYRIX_5510 || 291 device == PCI_DEVICE_ID_CYRIX_5520)) 292 mark_tsc_unstable("cyrix 5510/5520 detected"); 293 } 294 #endif 295 c->x86_cache_size = 16; /* Yep 16K integrated cache that's it */ 296 297 /* GXm supports extended cpuid levels 'ala' AMD */ 298 if (c->cpuid_level == 2) { 299 /* Enable cxMMX extensions (GX1 Datasheet 54) */ 300 setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1); 301 302 /* 303 * GXm : 0x30 ... 0x5f GXm datasheet 51 304 * GXlv: 0x6x GXlv datasheet 54 305 * ? : 0x7x 306 * GX1 : 0x8x GX1 datasheet 56 307 */ 308 if ((0x30 <= dir1 && dir1 <= 0x6f) || 309 (0x80 <= dir1 && dir1 <= 0x8f)) 310 geode_configure(); 311 return; 312 } else { /* MediaGX */ 313 Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4'; 314 p = Cx86_cb+2; 315 c->x86_model = (dir1 & 0x20) ? 1 : 2; 316 } 317 break; 318 319 case 5: /* 6x86MX/M II */ 320 if (dir1 > 7) { 321 dir0_msn++; /* M II */ 322 /* Enable MMX extensions (App note 108) */ 323 setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1); 324 } else { 325 /* A 6x86MX - it has the bug. */ 326 set_cpu_bug(c, X86_BUG_COMA); 327 } 328 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; 329 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]; 330 p = Cx86_cb+tmp; 331 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) 332 (c->x86_model)++; 333 /* Emulate MTRRs using Cyrix's ARRs. */ 334 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 335 break; 336 337 case 0xf: /* Cyrix 486 without DEVID registers */ 338 switch (dir0_lsn) { 339 case 0xd: /* either a 486SLC or DLC w/o DEVID */ 340 dir0_msn = 0; 341 p = Cx486_name[!!boot_cpu_has(X86_FEATURE_FPU)]; 342 break; 343 344 case 0xe: /* a 486S A step */ 345 dir0_msn = 0; 346 p = Cx486S_name[0]; 347 break; 348 } 349 break; 350 351 default: /* unknown (shouldn't happen, we know everyone ;-) */ 352 dir0_msn = 7; 353 break; 354 } 355 strcpy(buf, Cx86_model[dir0_msn & 7]); 356 if (p) 357 strcat(buf, p); 358 return; 359 } 360 361 /* 362 * Handle National Semiconductor branded processors 363 */ 364 static void init_nsc(struct cpuinfo_x86 *c) 365 { 366 /* 367 * There may be GX1 processors in the wild that are branded 368 * NSC and not Cyrix. 369 * 370 * This function only handles the GX processor, and kicks every 371 * thing else to the Cyrix init function above - that should 372 * cover any processors that might have been branded differently 373 * after NSC acquired Cyrix. 374 * 375 * If this breaks your GX1 horribly, please e-mail 376 * info-linux@ldcmail.amd.com to tell us. 377 */ 378 379 /* Handle the GX (Formally known as the GX2) */ 380 381 if (c->x86 == 5 && c->x86_model == 5) 382 cpu_detect_cache_sizes(c); 383 else 384 init_cyrix(c); 385 } 386 387 /* 388 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 389 * by the fact that they preserve the flags across the division of 5/2. 390 * PII and PPro exhibit this behavior too, but they have cpuid available. 391 */ 392 393 /* 394 * Perform the Cyrix 5/2 test. A Cyrix won't change 395 * the flags, while other 486 chips will. 396 */ 397 static inline int test_cyrix_52div(void) 398 { 399 unsigned int test; 400 401 __asm__ __volatile__( 402 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 403 "div %b2\n\t" /* divide 5 by 2 */ 404 "lahf" /* store flags into %ah */ 405 : "=a" (test) 406 : "0" (5), "q" (2) 407 : "cc"); 408 409 /* AH is 0x02 on Cyrix after the divide.. */ 410 return (unsigned char) (test >> 8) == 0x02; 411 } 412 413 static void cyrix_identify(struct cpuinfo_x86 *c) 414 { 415 /* Detect Cyrix with disabled CPUID */ 416 if (c->x86 == 4 && test_cyrix_52div()) { 417 unsigned char dir0, dir1; 418 419 strcpy(c->x86_vendor_id, "CyrixInstead"); 420 c->x86_vendor = X86_VENDOR_CYRIX; 421 422 /* Actually enable cpuid on the older cyrix */ 423 424 /* Retrieve CPU revisions */ 425 426 do_cyrix_devid(&dir0, &dir1); 427 428 dir0 >>= 4; 429 430 /* Check it is an affected model */ 431 432 if (dir0 == 5 || dir0 == 3) { 433 unsigned char ccr3; 434 unsigned long flags; 435 pr_info("Enabling CPUID on Cyrix processor.\n"); 436 local_irq_save(flags); 437 ccr3 = getCx86(CX86_CCR3); 438 /* enable MAPEN */ 439 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); 440 /* enable cpuid */ 441 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80); 442 /* disable MAPEN */ 443 setCx86(CX86_CCR3, ccr3); 444 local_irq_restore(flags); 445 } 446 } 447 } 448 449 static const struct cpu_dev cyrix_cpu_dev = { 450 .c_vendor = "Cyrix", 451 .c_ident = { "CyrixInstead" }, 452 .c_early_init = early_init_cyrix, 453 .c_init = init_cyrix, 454 .c_identify = cyrix_identify, 455 .c_x86_vendor = X86_VENDOR_CYRIX, 456 }; 457 458 cpu_dev_register(cyrix_cpu_dev); 459 460 static const struct cpu_dev nsc_cpu_dev = { 461 .c_vendor = "NSC", 462 .c_ident = { "Geode by NSC" }, 463 .c_init = init_nsc, 464 .c_x86_vendor = X86_VENDOR_NSC, 465 }; 466 467 cpu_dev_register(nsc_cpu_dev); 468