xref: /openbmc/linux/arch/x86/kernel/cpu/cyrix.c (revision b830f94f)
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bitops.h>
3 #include <linux/delay.h>
4 #include <linux/pci.h>
5 #include <asm/dma.h>
6 #include <linux/io.h>
7 #include <asm/processor-cyrix.h>
8 #include <asm/processor-flags.h>
9 #include <linux/timer.h>
10 #include <asm/pci-direct.h>
11 #include <asm/tsc.h>
12 #include <asm/cpufeature.h>
13 #include <linux/sched.h>
14 #include <linux/sched/clock.h>
15 
16 #include "cpu.h"
17 
18 /*
19  * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
20  */
21 static void __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
22 {
23 	unsigned char ccr2, ccr3;
24 
25 	/* we test for DEVID by checking whether CCR3 is writable */
26 	ccr3 = getCx86(CX86_CCR3);
27 	setCx86(CX86_CCR3, ccr3 ^ 0x80);
28 	getCx86(0xc0);   /* dummy to change bus */
29 
30 	if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
31 		ccr2 = getCx86(CX86_CCR2);
32 		setCx86(CX86_CCR2, ccr2 ^ 0x04);
33 		getCx86(0xc0);  /* dummy */
34 
35 		if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
36 			*dir0 = 0xfd;
37 		else {                          /* Cx486S A step */
38 			setCx86(CX86_CCR2, ccr2);
39 			*dir0 = 0xfe;
40 		}
41 	} else {
42 		setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */
43 
44 		/* read DIR0 and DIR1 CPU registers */
45 		*dir0 = getCx86(CX86_DIR0);
46 		*dir1 = getCx86(CX86_DIR1);
47 	}
48 }
49 
50 static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
51 {
52 	unsigned long flags;
53 
54 	local_irq_save(flags);
55 	__do_cyrix_devid(dir0, dir1);
56 	local_irq_restore(flags);
57 }
58 /*
59  * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
60  * order to identify the Cyrix CPU model after we're out of setup.c
61  *
62  * Actually since bugs.h doesn't even reference this perhaps someone should
63  * fix the documentation ???
64  */
65 static unsigned char Cx86_dir0_msb = 0;
66 
67 static const char Cx86_model[][9] = {
68 	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
69 	"M II ", "Unknown"
70 };
71 static const char Cx486_name[][5] = {
72 	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
73 	"SRx2", "DRx2"
74 };
75 static const char Cx486S_name[][4] = {
76 	"S", "S2", "Se", "S2e"
77 };
78 static const char Cx486D_name[][4] = {
79 	"DX", "DX2", "?", "?", "?", "DX4"
80 };
81 static char Cx86_cb[] = "?.5x Core/Bus Clock";
82 static const char cyrix_model_mult1[] = "12??43";
83 static const char cyrix_model_mult2[] = "12233445";
84 
85 /*
86  * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
87  * BIOSes for compatibility with DOS games.  This makes the udelay loop
88  * work correctly, and improves performance.
89  *
90  * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
91  */
92 
93 static void check_cx686_slop(struct cpuinfo_x86 *c)
94 {
95 	unsigned long flags;
96 
97 	if (Cx86_dir0_msb == 3) {
98 		unsigned char ccr3, ccr5;
99 
100 		local_irq_save(flags);
101 		ccr3 = getCx86(CX86_CCR3);
102 		setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
103 		ccr5 = getCx86(CX86_CCR5);
104 		if (ccr5 & 2)
105 			setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
106 		setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
107 		local_irq_restore(flags);
108 
109 		if (ccr5 & 2) { /* possible wrong calibration done */
110 			pr_info("Recalibrating delay loop with SLOP bit reset\n");
111 			calibrate_delay();
112 			c->loops_per_jiffy = loops_per_jiffy;
113 		}
114 	}
115 }
116 
117 
118 static void set_cx86_reorder(void)
119 {
120 	u8 ccr3;
121 
122 	pr_info("Enable Memory access reorder on Cyrix/NSC processor.\n");
123 	ccr3 = getCx86(CX86_CCR3);
124 	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
125 
126 	/* Load/Store Serialize to mem access disable (=reorder it) */
127 	setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
128 	/* set load/store serialize from 1GB to 4GB */
129 	ccr3 |= 0xe0;
130 	setCx86(CX86_CCR3, ccr3);
131 }
132 
133 static void set_cx86_memwb(void)
134 {
135 	pr_info("Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
136 
137 	/* CCR2 bit 2: unlock NW bit */
138 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
139 	/* set 'Not Write-through' */
140 	write_cr0(read_cr0() | X86_CR0_NW);
141 	/* CCR2 bit 2: lock NW bit and set WT1 */
142 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
143 }
144 
145 /*
146  *	Configure later MediaGX and/or Geode processor.
147  */
148 
149 static void geode_configure(void)
150 {
151 	unsigned long flags;
152 	u8 ccr3;
153 	local_irq_save(flags);
154 
155 	/* Suspend on halt power saving and enable #SUSP pin */
156 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
157 
158 	ccr3 = getCx86(CX86_CCR3);
159 	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */
160 
161 
162 	/* FPU fast, DTE cache, Mem bypass */
163 	setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
164 	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */
165 
166 	set_cx86_memwb();
167 	set_cx86_reorder();
168 
169 	local_irq_restore(flags);
170 }
171 
172 static void early_init_cyrix(struct cpuinfo_x86 *c)
173 {
174 	unsigned char dir0, dir0_msn, dir1 = 0;
175 
176 	__do_cyrix_devid(&dir0, &dir1);
177 	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
178 
179 	switch (dir0_msn) {
180 	case 3: /* 6x86/6x86L */
181 		/* Emulate MTRRs using Cyrix's ARRs. */
182 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
183 		break;
184 	case 5: /* 6x86MX/M II */
185 		/* Emulate MTRRs using Cyrix's ARRs. */
186 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
187 		break;
188 	}
189 }
190 
191 static void init_cyrix(struct cpuinfo_x86 *c)
192 {
193 	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
194 	char *buf = c->x86_model_id;
195 	const char *p = NULL;
196 
197 	/*
198 	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
199 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
200 	 */
201 	clear_cpu_cap(c, 0*32+31);
202 
203 	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
204 	if (test_cpu_cap(c, 1*32+24)) {
205 		clear_cpu_cap(c, 1*32+24);
206 		set_cpu_cap(c, X86_FEATURE_CXMMX);
207 	}
208 
209 	do_cyrix_devid(&dir0, &dir1);
210 
211 	check_cx686_slop(c);
212 
213 	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
214 	dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */
215 
216 	/* common case step number/rev -- exceptions handled below */
217 	c->x86_model = (dir1 >> 4) + 1;
218 	c->x86_stepping = dir1 & 0xf;
219 
220 	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
221 	 * We do the same thing for each generation: we work out
222 	 * the model, multiplier and stepping.  Black magic included,
223 	 * to make the silicon step/rev numbers match the printed ones.
224 	 */
225 
226 	switch (dir0_msn) {
227 		unsigned char tmp;
228 
229 	case 0: /* Cx486SLC/DLC/SRx/DRx */
230 		p = Cx486_name[dir0_lsn & 7];
231 		break;
232 
233 	case 1: /* Cx486S/DX/DX2/DX4 */
234 		p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
235 			: Cx486S_name[dir0_lsn & 3];
236 		break;
237 
238 	case 2: /* 5x86 */
239 		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
240 		p = Cx86_cb+2;
241 		break;
242 
243 	case 3: /* 6x86/6x86L */
244 		Cx86_cb[1] = ' ';
245 		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
246 		if (dir1 > 0x21) { /* 686L */
247 			Cx86_cb[0] = 'L';
248 			p = Cx86_cb;
249 			(c->x86_model)++;
250 		} else             /* 686 */
251 			p = Cx86_cb+1;
252 		/* Emulate MTRRs using Cyrix's ARRs. */
253 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
254 		/* 6x86's contain this bug */
255 		set_cpu_bug(c, X86_BUG_COMA);
256 		break;
257 
258 	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
259 	case 11: /* GX1 with inverted Device ID */
260 #ifdef CONFIG_PCI
261 	{
262 		u32 vendor, device;
263 		/*
264 		 * It isn't really a PCI quirk directly, but the cure is the
265 		 * same. The MediaGX has deep magic SMM stuff that handles the
266 		 * SB emulation. It throws away the fifo on disable_dma() which
267 		 * is wrong and ruins the audio.
268 		 *
269 		 *  Bug2: VSA1 has a wrap bug so that using maximum sized DMA
270 		 *  causes bad things. According to NatSemi VSA2 has another
271 		 *  bug to do with 'hlt'. I've not seen any boards using VSA2
272 		 *  and X doesn't seem to support it either so who cares 8).
273 		 *  VSA1 we work around however.
274 		 */
275 
276 		pr_info("Working around Cyrix MediaGX virtual DMA bugs.\n");
277 		isa_dma_bridge_buggy = 2;
278 
279 		/* We do this before the PCI layer is running. However we
280 		   are safe here as we know the bridge must be a Cyrix
281 		   companion and must be present */
282 		vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
283 		device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
284 
285 		/*
286 		 *  The 5510/5520 companion chips have a funky PIT.
287 		 */
288 		if (vendor == PCI_VENDOR_ID_CYRIX &&
289 			(device == PCI_DEVICE_ID_CYRIX_5510 ||
290 					device == PCI_DEVICE_ID_CYRIX_5520))
291 			mark_tsc_unstable("cyrix 5510/5520 detected");
292 	}
293 #endif
294 		c->x86_cache_size = 16;	/* Yep 16K integrated cache thats it */
295 
296 		/* GXm supports extended cpuid levels 'ala' AMD */
297 		if (c->cpuid_level == 2) {
298 			/* Enable cxMMX extensions (GX1 Datasheet 54) */
299 			setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
300 
301 			/*
302 			 * GXm : 0x30 ... 0x5f GXm  datasheet 51
303 			 * GXlv: 0x6x          GXlv datasheet 54
304 			 *  ?  : 0x7x
305 			 * GX1 : 0x8x          GX1  datasheet 56
306 			 */
307 			if ((0x30 <= dir1 && dir1 <= 0x6f) ||
308 					(0x80 <= dir1 && dir1 <= 0x8f))
309 				geode_configure();
310 			return;
311 		} else { /* MediaGX */
312 			Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
313 			p = Cx86_cb+2;
314 			c->x86_model = (dir1 & 0x20) ? 1 : 2;
315 		}
316 		break;
317 
318 	case 5: /* 6x86MX/M II */
319 		if (dir1 > 7) {
320 			dir0_msn++;  /* M II */
321 			/* Enable MMX extensions (App note 108) */
322 			setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
323 		} else {
324 			/* A 6x86MX - it has the bug. */
325 			set_cpu_bug(c, X86_BUG_COMA);
326 		}
327 		tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
328 		Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
329 		p = Cx86_cb+tmp;
330 		if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
331 			(c->x86_model)++;
332 		/* Emulate MTRRs using Cyrix's ARRs. */
333 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
334 		break;
335 
336 	case 0xf:  /* Cyrix 486 without DEVID registers */
337 		switch (dir0_lsn) {
338 		case 0xd:  /* either a 486SLC or DLC w/o DEVID */
339 			dir0_msn = 0;
340 			p = Cx486_name[!!boot_cpu_has(X86_FEATURE_FPU)];
341 			break;
342 
343 		case 0xe:  /* a 486S A step */
344 			dir0_msn = 0;
345 			p = Cx486S_name[0];
346 			break;
347 		}
348 		break;
349 
350 	default:  /* unknown (shouldn't happen, we know everyone ;-) */
351 		dir0_msn = 7;
352 		break;
353 	}
354 	strcpy(buf, Cx86_model[dir0_msn & 7]);
355 	if (p)
356 		strcat(buf, p);
357 	return;
358 }
359 
360 /*
361  * Handle National Semiconductor branded processors
362  */
363 static void init_nsc(struct cpuinfo_x86 *c)
364 {
365 	/*
366 	 * There may be GX1 processors in the wild that are branded
367 	 * NSC and not Cyrix.
368 	 *
369 	 * This function only handles the GX processor, and kicks every
370 	 * thing else to the Cyrix init function above - that should
371 	 * cover any processors that might have been branded differently
372 	 * after NSC acquired Cyrix.
373 	 *
374 	 * If this breaks your GX1 horribly, please e-mail
375 	 * info-linux@ldcmail.amd.com to tell us.
376 	 */
377 
378 	/* Handle the GX (Formally known as the GX2) */
379 
380 	if (c->x86 == 5 && c->x86_model == 5)
381 		cpu_detect_cache_sizes(c);
382 	else
383 		init_cyrix(c);
384 }
385 
386 /*
387  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
388  * by the fact that they preserve the flags across the division of 5/2.
389  * PII and PPro exhibit this behavior too, but they have cpuid available.
390  */
391 
392 /*
393  * Perform the Cyrix 5/2 test. A Cyrix won't change
394  * the flags, while other 486 chips will.
395  */
396 static inline int test_cyrix_52div(void)
397 {
398 	unsigned int test;
399 
400 	__asm__ __volatile__(
401 	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
402 	     "div %b2\n\t"	/* divide 5 by 2 */
403 	     "lahf"		/* store flags into %ah */
404 	     : "=a" (test)
405 	     : "0" (5), "q" (2)
406 	     : "cc");
407 
408 	/* AH is 0x02 on Cyrix after the divide.. */
409 	return (unsigned char) (test >> 8) == 0x02;
410 }
411 
412 static void cyrix_identify(struct cpuinfo_x86 *c)
413 {
414 	/* Detect Cyrix with disabled CPUID */
415 	if (c->x86 == 4 && test_cyrix_52div()) {
416 		unsigned char dir0, dir1;
417 
418 		strcpy(c->x86_vendor_id, "CyrixInstead");
419 		c->x86_vendor = X86_VENDOR_CYRIX;
420 
421 		/* Actually enable cpuid on the older cyrix */
422 
423 		/* Retrieve CPU revisions */
424 
425 		do_cyrix_devid(&dir0, &dir1);
426 
427 		dir0 >>= 4;
428 
429 		/* Check it is an affected model */
430 
431 		if (dir0 == 5 || dir0 == 3) {
432 			unsigned char ccr3;
433 			unsigned long flags;
434 			pr_info("Enabling CPUID on Cyrix processor.\n");
435 			local_irq_save(flags);
436 			ccr3 = getCx86(CX86_CCR3);
437 			/* enable MAPEN  */
438 			setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
439 			/* enable cpuid  */
440 			setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80);
441 			/* disable MAPEN */
442 			setCx86(CX86_CCR3, ccr3);
443 			local_irq_restore(flags);
444 		}
445 	}
446 }
447 
448 static const struct cpu_dev cyrix_cpu_dev = {
449 	.c_vendor	= "Cyrix",
450 	.c_ident	= { "CyrixInstead" },
451 	.c_early_init	= early_init_cyrix,
452 	.c_init		= init_cyrix,
453 	.c_identify	= cyrix_identify,
454 	.c_x86_vendor	= X86_VENDOR_CYRIX,
455 };
456 
457 cpu_dev_register(cyrix_cpu_dev);
458 
459 static const struct cpu_dev nsc_cpu_dev = {
460 	.c_vendor	= "NSC",
461 	.c_ident	= { "Geode by NSC" },
462 	.c_init		= init_nsc,
463 	.c_x86_vendor	= X86_VENDOR_NSC,
464 };
465 
466 cpu_dev_register(nsc_cpu_dev);
467