1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_counter.h> 17 #include <asm/mmu_context.h> 18 #include <asm/hypervisor.h> 19 #include <asm/processor.h> 20 #include <asm/sections.h> 21 #include <linux/topology.h> 22 #include <linux/cpumask.h> 23 #include <asm/pgtable.h> 24 #include <asm/atomic.h> 25 #include <asm/proto.h> 26 #include <asm/setup.h> 27 #include <asm/apic.h> 28 #include <asm/desc.h> 29 #include <asm/i387.h> 30 #include <asm/mtrr.h> 31 #include <linux/numa.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/mce.h> 35 #include <asm/msr.h> 36 #include <asm/pat.h> 37 38 #ifdef CONFIG_X86_LOCAL_APIC 39 #include <asm/uv/uv.h> 40 #endif 41 42 #include "cpu.h" 43 44 /* all of these masks are initialized in setup_cpu_local_masks() */ 45 cpumask_var_t cpu_initialized_mask; 46 cpumask_var_t cpu_callout_mask; 47 cpumask_var_t cpu_callin_mask; 48 49 /* representing cpus for which sibling maps can be computed */ 50 cpumask_var_t cpu_sibling_setup_mask; 51 52 /* correctly size the local cpu masks */ 53 void __init setup_cpu_local_masks(void) 54 { 55 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 56 alloc_bootmem_cpumask_var(&cpu_callin_mask); 57 alloc_bootmem_cpumask_var(&cpu_callout_mask); 58 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 59 } 60 61 static void __cpuinit default_init(struct cpuinfo_x86 *c) 62 { 63 #ifdef CONFIG_X86_64 64 display_cacheinfo(c); 65 #else 66 /* Not much we can do here... */ 67 /* Check if at least it has cpuid */ 68 if (c->cpuid_level == -1) { 69 /* No cpuid. It must be an ancient CPU */ 70 if (c->x86 == 4) 71 strcpy(c->x86_model_id, "486"); 72 else if (c->x86 == 3) 73 strcpy(c->x86_model_id, "386"); 74 } 75 #endif 76 } 77 78 static const struct cpu_dev __cpuinitconst default_cpu = { 79 .c_init = default_init, 80 .c_vendor = "Unknown", 81 .c_x86_vendor = X86_VENDOR_UNKNOWN, 82 }; 83 84 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; 85 86 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 87 #ifdef CONFIG_X86_64 88 /* 89 * We need valid kernel segments for data and code in long mode too 90 * IRET will check the segment types kkeil 2000/10/28 91 * Also sysret mandates a special GDT layout 92 * 93 * TLS descriptors are currently at a different place compared to i386. 94 * Hopefully nobody expects them at a fixed place (Wine?) 95 */ 96 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 97 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 98 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 99 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 100 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 101 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 102 #else 103 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 104 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 105 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 106 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 107 /* 108 * Segments used for calling PnP BIOS have byte granularity. 109 * They code segments and data segments have fixed 64k limits, 110 * the transfer segment sizes are set at run time. 111 */ 112 /* 32-bit code */ 113 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 114 /* 16-bit code */ 115 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 116 /* 16-bit data */ 117 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 118 /* 16-bit data */ 119 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 120 /* 16-bit data */ 121 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 122 /* 123 * The APM segments have byte granularity and their bases 124 * are set at run time. All have 64k limits. 125 */ 126 /* 32-bit code */ 127 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 128 /* 16-bit code */ 129 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 130 /* data */ 131 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 132 133 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 134 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 135 GDT_STACK_CANARY_INIT 136 #endif 137 } }; 138 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 139 140 static int __init x86_xsave_setup(char *s) 141 { 142 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 143 return 1; 144 } 145 __setup("noxsave", x86_xsave_setup); 146 147 #ifdef CONFIG_X86_32 148 static int cachesize_override __cpuinitdata = -1; 149 static int disable_x86_serial_nr __cpuinitdata = 1; 150 151 static int __init cachesize_setup(char *str) 152 { 153 get_option(&str, &cachesize_override); 154 return 1; 155 } 156 __setup("cachesize=", cachesize_setup); 157 158 static int __init x86_fxsr_setup(char *s) 159 { 160 setup_clear_cpu_cap(X86_FEATURE_FXSR); 161 setup_clear_cpu_cap(X86_FEATURE_XMM); 162 return 1; 163 } 164 __setup("nofxsr", x86_fxsr_setup); 165 166 static int __init x86_sep_setup(char *s) 167 { 168 setup_clear_cpu_cap(X86_FEATURE_SEP); 169 return 1; 170 } 171 __setup("nosep", x86_sep_setup); 172 173 /* Standard macro to see if a specific flag is changeable */ 174 static inline int flag_is_changeable_p(u32 flag) 175 { 176 u32 f1, f2; 177 178 /* 179 * Cyrix and IDT cpus allow disabling of CPUID 180 * so the code below may return different results 181 * when it is executed before and after enabling 182 * the CPUID. Add "volatile" to not allow gcc to 183 * optimize the subsequent calls to this function. 184 */ 185 asm volatile ("pushfl \n\t" 186 "pushfl \n\t" 187 "popl %0 \n\t" 188 "movl %0, %1 \n\t" 189 "xorl %2, %0 \n\t" 190 "pushl %0 \n\t" 191 "popfl \n\t" 192 "pushfl \n\t" 193 "popl %0 \n\t" 194 "popfl \n\t" 195 196 : "=&r" (f1), "=&r" (f2) 197 : "ir" (flag)); 198 199 return ((f1^f2) & flag) != 0; 200 } 201 202 /* Probe for the CPUID instruction */ 203 static int __cpuinit have_cpuid_p(void) 204 { 205 return flag_is_changeable_p(X86_EFLAGS_ID); 206 } 207 208 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 209 { 210 unsigned long lo, hi; 211 212 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 213 return; 214 215 /* Disable processor serial number: */ 216 217 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 218 lo |= 0x200000; 219 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 220 221 printk(KERN_NOTICE "CPU serial number disabled.\n"); 222 clear_cpu_cap(c, X86_FEATURE_PN); 223 224 /* Disabling the serial number may affect the cpuid level */ 225 c->cpuid_level = cpuid_eax(0); 226 } 227 228 static int __init x86_serial_nr_setup(char *s) 229 { 230 disable_x86_serial_nr = 0; 231 return 1; 232 } 233 __setup("serialnumber", x86_serial_nr_setup); 234 #else 235 static inline int flag_is_changeable_p(u32 flag) 236 { 237 return 1; 238 } 239 /* Probe for the CPUID instruction */ 240 static inline int have_cpuid_p(void) 241 { 242 return 1; 243 } 244 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 245 { 246 } 247 #endif 248 249 /* 250 * Some CPU features depend on higher CPUID levels, which may not always 251 * be available due to CPUID level capping or broken virtualization 252 * software. Add those features to this table to auto-disable them. 253 */ 254 struct cpuid_dependent_feature { 255 u32 feature; 256 u32 level; 257 }; 258 259 static const struct cpuid_dependent_feature __cpuinitconst 260 cpuid_dependent_features[] = { 261 { X86_FEATURE_MWAIT, 0x00000005 }, 262 { X86_FEATURE_DCA, 0x00000009 }, 263 { X86_FEATURE_XSAVE, 0x0000000d }, 264 { 0, 0 } 265 }; 266 267 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 268 { 269 const struct cpuid_dependent_feature *df; 270 271 for (df = cpuid_dependent_features; df->feature; df++) { 272 273 if (!cpu_has(c, df->feature)) 274 continue; 275 /* 276 * Note: cpuid_level is set to -1 if unavailable, but 277 * extended_extended_level is set to 0 if unavailable 278 * and the legitimate extended levels are all negative 279 * when signed; hence the weird messing around with 280 * signs here... 281 */ 282 if (!((s32)df->level < 0 ? 283 (u32)df->level > (u32)c->extended_cpuid_level : 284 (s32)df->level > (s32)c->cpuid_level)) 285 continue; 286 287 clear_cpu_cap(c, df->feature); 288 if (!warn) 289 continue; 290 291 printk(KERN_WARNING 292 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 293 x86_cap_flags[df->feature], df->level); 294 } 295 } 296 297 /* 298 * Naming convention should be: <Name> [(<Codename>)] 299 * This table only is used unless init_<vendor>() below doesn't set it; 300 * in particular, if CPUID levels 0x80000002..4 are supported, this 301 * isn't used 302 */ 303 304 /* Look up CPU names by table lookup. */ 305 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 306 { 307 const struct cpu_model_info *info; 308 309 if (c->x86_model >= 16) 310 return NULL; /* Range check */ 311 312 if (!this_cpu) 313 return NULL; 314 315 info = this_cpu->c_models; 316 317 while (info && info->family) { 318 if (info->family == c->x86) 319 return info->model_names[c->x86_model]; 320 info++; 321 } 322 return NULL; /* Not found */ 323 } 324 325 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; 326 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; 327 328 void load_percpu_segment(int cpu) 329 { 330 #ifdef CONFIG_X86_32 331 loadsegment(fs, __KERNEL_PERCPU); 332 #else 333 loadsegment(gs, 0); 334 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 335 #endif 336 load_stack_canary_segment(); 337 } 338 339 /* 340 * Current gdt points %fs at the "master" per-cpu area: after this, 341 * it's on the real one. 342 */ 343 void switch_to_new_gdt(int cpu) 344 { 345 struct desc_ptr gdt_descr; 346 347 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 348 gdt_descr.size = GDT_SIZE - 1; 349 load_gdt(&gdt_descr); 350 /* Reload the per-cpu base */ 351 352 load_percpu_segment(cpu); 353 } 354 355 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 356 357 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 358 { 359 unsigned int *v; 360 char *p, *q; 361 362 if (c->extended_cpuid_level < 0x80000004) 363 return; 364 365 v = (unsigned int *)c->x86_model_id; 366 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 367 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 368 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 369 c->x86_model_id[48] = 0; 370 371 /* 372 * Intel chips right-justify this string for some dumb reason; 373 * undo that brain damage: 374 */ 375 p = q = &c->x86_model_id[0]; 376 while (*p == ' ') 377 p++; 378 if (p != q) { 379 while (*p) 380 *q++ = *p++; 381 while (q <= &c->x86_model_id[48]) 382 *q++ = '\0'; /* Zero-pad the rest */ 383 } 384 } 385 386 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 387 { 388 unsigned int n, dummy, ebx, ecx, edx, l2size; 389 390 n = c->extended_cpuid_level; 391 392 if (n >= 0x80000005) { 393 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 394 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 395 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 396 c->x86_cache_size = (ecx>>24) + (edx>>24); 397 #ifdef CONFIG_X86_64 398 /* On K8 L1 TLB is inclusive, so don't count it */ 399 c->x86_tlbsize = 0; 400 #endif 401 } 402 403 if (n < 0x80000006) /* Some chips just has a large L1. */ 404 return; 405 406 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 407 l2size = ecx >> 16; 408 409 #ifdef CONFIG_X86_64 410 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 411 #else 412 /* do processor-specific cache resizing */ 413 if (this_cpu->c_size_cache) 414 l2size = this_cpu->c_size_cache(c, l2size); 415 416 /* Allow user to override all this if necessary. */ 417 if (cachesize_override != -1) 418 l2size = cachesize_override; 419 420 if (l2size == 0) 421 return; /* Again, no L2 cache is possible */ 422 #endif 423 424 c->x86_cache_size = l2size; 425 426 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 427 l2size, ecx & 0xFF); 428 } 429 430 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 431 { 432 #ifdef CONFIG_X86_HT 433 u32 eax, ebx, ecx, edx; 434 int index_msb, core_bits; 435 436 if (!cpu_has(c, X86_FEATURE_HT)) 437 return; 438 439 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 440 goto out; 441 442 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 443 return; 444 445 cpuid(1, &eax, &ebx, &ecx, &edx); 446 447 smp_num_siblings = (ebx & 0xff0000) >> 16; 448 449 if (smp_num_siblings == 1) { 450 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 451 goto out; 452 } 453 454 if (smp_num_siblings <= 1) 455 goto out; 456 457 if (smp_num_siblings > nr_cpu_ids) { 458 pr_warning("CPU: Unsupported number of siblings %d", 459 smp_num_siblings); 460 smp_num_siblings = 1; 461 return; 462 } 463 464 index_msb = get_count_order(smp_num_siblings); 465 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 466 467 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 468 469 index_msb = get_count_order(smp_num_siblings); 470 471 core_bits = get_count_order(c->x86_max_cores); 472 473 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 474 ((1 << core_bits) - 1); 475 476 out: 477 if ((c->x86_max_cores * smp_num_siblings) > 1) { 478 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 479 c->phys_proc_id); 480 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 481 c->cpu_core_id); 482 } 483 #endif 484 } 485 486 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 487 { 488 char *v = c->x86_vendor_id; 489 int i; 490 491 for (i = 0; i < X86_VENDOR_NUM; i++) { 492 if (!cpu_devs[i]) 493 break; 494 495 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 496 (cpu_devs[i]->c_ident[1] && 497 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 498 499 this_cpu = cpu_devs[i]; 500 c->x86_vendor = this_cpu->c_x86_vendor; 501 return; 502 } 503 } 504 505 printk_once(KERN_ERR 506 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 507 "CPU: Your system may be unstable.\n", v); 508 509 c->x86_vendor = X86_VENDOR_UNKNOWN; 510 this_cpu = &default_cpu; 511 } 512 513 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 514 { 515 /* Get vendor name */ 516 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 517 (unsigned int *)&c->x86_vendor_id[0], 518 (unsigned int *)&c->x86_vendor_id[8], 519 (unsigned int *)&c->x86_vendor_id[4]); 520 521 c->x86 = 4; 522 /* Intel-defined flags: level 0x00000001 */ 523 if (c->cpuid_level >= 0x00000001) { 524 u32 junk, tfms, cap0, misc; 525 526 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 527 c->x86 = (tfms >> 8) & 0xf; 528 c->x86_model = (tfms >> 4) & 0xf; 529 c->x86_mask = tfms & 0xf; 530 531 if (c->x86 == 0xf) 532 c->x86 += (tfms >> 20) & 0xff; 533 if (c->x86 >= 0x6) 534 c->x86_model += ((tfms >> 16) & 0xf) << 4; 535 536 if (cap0 & (1<<19)) { 537 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 538 c->x86_cache_alignment = c->x86_clflush_size; 539 } 540 } 541 } 542 543 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 544 { 545 u32 tfms, xlvl; 546 u32 ebx; 547 548 /* Intel-defined flags: level 0x00000001 */ 549 if (c->cpuid_level >= 0x00000001) { 550 u32 capability, excap; 551 552 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 553 c->x86_capability[0] = capability; 554 c->x86_capability[4] = excap; 555 } 556 557 /* AMD-defined flags: level 0x80000001 */ 558 xlvl = cpuid_eax(0x80000000); 559 c->extended_cpuid_level = xlvl; 560 561 if ((xlvl & 0xffff0000) == 0x80000000) { 562 if (xlvl >= 0x80000001) { 563 c->x86_capability[1] = cpuid_edx(0x80000001); 564 c->x86_capability[6] = cpuid_ecx(0x80000001); 565 } 566 } 567 568 if (c->extended_cpuid_level >= 0x80000008) { 569 u32 eax = cpuid_eax(0x80000008); 570 571 c->x86_virt_bits = (eax >> 8) & 0xff; 572 c->x86_phys_bits = eax & 0xff; 573 } 574 #ifdef CONFIG_X86_32 575 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 576 c->x86_phys_bits = 36; 577 #endif 578 579 if (c->extended_cpuid_level >= 0x80000007) 580 c->x86_power = cpuid_edx(0x80000007); 581 582 } 583 584 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 585 { 586 #ifdef CONFIG_X86_32 587 int i; 588 589 /* 590 * First of all, decide if this is a 486 or higher 591 * It's a 486 if we can modify the AC flag 592 */ 593 if (flag_is_changeable_p(X86_EFLAGS_AC)) 594 c->x86 = 4; 595 else 596 c->x86 = 3; 597 598 for (i = 0; i < X86_VENDOR_NUM; i++) 599 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 600 c->x86_vendor_id[0] = 0; 601 cpu_devs[i]->c_identify(c); 602 if (c->x86_vendor_id[0]) { 603 get_cpu_vendor(c); 604 break; 605 } 606 } 607 #endif 608 } 609 610 /* 611 * Do minimum CPU detection early. 612 * Fields really needed: vendor, cpuid_level, family, model, mask, 613 * cache alignment. 614 * The others are not touched to avoid unwanted side effects. 615 * 616 * WARNING: this function is only called on the BP. Don't add code here 617 * that is supposed to run on all CPUs. 618 */ 619 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 620 { 621 #ifdef CONFIG_X86_64 622 c->x86_clflush_size = 64; 623 c->x86_phys_bits = 36; 624 c->x86_virt_bits = 48; 625 #else 626 c->x86_clflush_size = 32; 627 c->x86_phys_bits = 32; 628 c->x86_virt_bits = 32; 629 #endif 630 c->x86_cache_alignment = c->x86_clflush_size; 631 632 memset(&c->x86_capability, 0, sizeof c->x86_capability); 633 c->extended_cpuid_level = 0; 634 635 if (!have_cpuid_p()) 636 identify_cpu_without_cpuid(c); 637 638 /* cyrix could have cpuid enabled via c_identify()*/ 639 if (!have_cpuid_p()) 640 return; 641 642 cpu_detect(c); 643 644 get_cpu_vendor(c); 645 646 get_cpu_cap(c); 647 648 if (this_cpu->c_early_init) 649 this_cpu->c_early_init(c); 650 651 #ifdef CONFIG_SMP 652 c->cpu_index = boot_cpu_id; 653 #endif 654 filter_cpuid_features(c, false); 655 } 656 657 void __init early_cpu_init(void) 658 { 659 const struct cpu_dev *const *cdev; 660 int count = 0; 661 662 printk(KERN_INFO "KERNEL supported cpus:\n"); 663 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 664 const struct cpu_dev *cpudev = *cdev; 665 unsigned int j; 666 667 if (count >= X86_VENDOR_NUM) 668 break; 669 cpu_devs[count] = cpudev; 670 count++; 671 672 for (j = 0; j < 2; j++) { 673 if (!cpudev->c_ident[j]) 674 continue; 675 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 676 cpudev->c_ident[j]); 677 } 678 } 679 680 early_identify_cpu(&boot_cpu_data); 681 } 682 683 /* 684 * The NOPL instruction is supposed to exist on all CPUs with 685 * family >= 6; unfortunately, that's not true in practice because 686 * of early VIA chips and (more importantly) broken virtualizers that 687 * are not easy to detect. In the latter case it doesn't even *fail* 688 * reliably, so probing for it doesn't even work. Disable it completely 689 * unless we can find a reliable way to detect all the broken cases. 690 */ 691 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 692 { 693 clear_cpu_cap(c, X86_FEATURE_NOPL); 694 } 695 696 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 697 { 698 c->extended_cpuid_level = 0; 699 700 if (!have_cpuid_p()) 701 identify_cpu_without_cpuid(c); 702 703 /* cyrix could have cpuid enabled via c_identify()*/ 704 if (!have_cpuid_p()) 705 return; 706 707 cpu_detect(c); 708 709 get_cpu_vendor(c); 710 711 get_cpu_cap(c); 712 713 if (c->cpuid_level >= 0x00000001) { 714 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 715 #ifdef CONFIG_X86_32 716 # ifdef CONFIG_X86_HT 717 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 718 # else 719 c->apicid = c->initial_apicid; 720 # endif 721 #endif 722 723 #ifdef CONFIG_X86_HT 724 c->phys_proc_id = c->initial_apicid; 725 #endif 726 } 727 728 get_model_name(c); /* Default name */ 729 730 init_scattered_cpuid_features(c); 731 detect_nopl(c); 732 } 733 734 /* 735 * This does the hard work of actually picking apart the CPU stuff... 736 */ 737 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 738 { 739 int i; 740 741 c->loops_per_jiffy = loops_per_jiffy; 742 c->x86_cache_size = -1; 743 c->x86_vendor = X86_VENDOR_UNKNOWN; 744 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 745 c->x86_vendor_id[0] = '\0'; /* Unset */ 746 c->x86_model_id[0] = '\0'; /* Unset */ 747 c->x86_max_cores = 1; 748 c->x86_coreid_bits = 0; 749 #ifdef CONFIG_X86_64 750 c->x86_clflush_size = 64; 751 c->x86_phys_bits = 36; 752 c->x86_virt_bits = 48; 753 #else 754 c->cpuid_level = -1; /* CPUID not detected */ 755 c->x86_clflush_size = 32; 756 c->x86_phys_bits = 32; 757 c->x86_virt_bits = 32; 758 #endif 759 c->x86_cache_alignment = c->x86_clflush_size; 760 memset(&c->x86_capability, 0, sizeof c->x86_capability); 761 762 generic_identify(c); 763 764 if (this_cpu->c_identify) 765 this_cpu->c_identify(c); 766 767 /* Clear/Set all flags overriden by options, after probe */ 768 for (i = 0; i < NCAPINTS; i++) { 769 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 770 c->x86_capability[i] |= cpu_caps_set[i]; 771 } 772 773 #ifdef CONFIG_X86_64 774 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 775 #endif 776 777 /* 778 * Vendor-specific initialization. In this section we 779 * canonicalize the feature flags, meaning if there are 780 * features a certain CPU supports which CPUID doesn't 781 * tell us, CPUID claiming incorrect flags, or other bugs, 782 * we handle them here. 783 * 784 * At the end of this section, c->x86_capability better 785 * indicate the features this CPU genuinely supports! 786 */ 787 if (this_cpu->c_init) 788 this_cpu->c_init(c); 789 790 /* Disable the PN if appropriate */ 791 squash_the_stupid_serial_number(c); 792 793 /* 794 * The vendor-specific functions might have changed features. 795 * Now we do "generic changes." 796 */ 797 798 /* Filter out anything that depends on CPUID levels we don't have */ 799 filter_cpuid_features(c, true); 800 801 /* If the model name is still unset, do table lookup. */ 802 if (!c->x86_model_id[0]) { 803 const char *p; 804 p = table_lookup_model(c); 805 if (p) 806 strcpy(c->x86_model_id, p); 807 else 808 /* Last resort... */ 809 sprintf(c->x86_model_id, "%02x/%02x", 810 c->x86, c->x86_model); 811 } 812 813 #ifdef CONFIG_X86_64 814 detect_ht(c); 815 #endif 816 817 init_hypervisor(c); 818 819 /* 820 * Clear/Set all flags overriden by options, need do it 821 * before following smp all cpus cap AND. 822 */ 823 for (i = 0; i < NCAPINTS; i++) { 824 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 825 c->x86_capability[i] |= cpu_caps_set[i]; 826 } 827 828 /* 829 * On SMP, boot_cpu_data holds the common feature set between 830 * all CPUs; so make sure that we indicate which features are 831 * common between the CPUs. The first time this routine gets 832 * executed, c == &boot_cpu_data. 833 */ 834 if (c != &boot_cpu_data) { 835 /* AND the already accumulated flags with these */ 836 for (i = 0; i < NCAPINTS; i++) 837 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 838 } 839 840 #ifdef CONFIG_X86_MCE 841 /* Init Machine Check Exception if available. */ 842 mcheck_init(c); 843 #endif 844 845 select_idle_routine(c); 846 847 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 848 numa_add_cpu(smp_processor_id()); 849 #endif 850 } 851 852 #ifdef CONFIG_X86_64 853 static void vgetcpu_set_mode(void) 854 { 855 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 856 vgetcpu_mode = VGETCPU_RDTSCP; 857 else 858 vgetcpu_mode = VGETCPU_LSL; 859 } 860 #endif 861 862 void __init identify_boot_cpu(void) 863 { 864 identify_cpu(&boot_cpu_data); 865 init_c1e_mask(); 866 #ifdef CONFIG_X86_32 867 sysenter_setup(); 868 enable_sep_cpu(); 869 #else 870 vgetcpu_set_mode(); 871 #endif 872 init_hw_perf_counters(); 873 } 874 875 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 876 { 877 BUG_ON(c == &boot_cpu_data); 878 identify_cpu(c); 879 #ifdef CONFIG_X86_32 880 enable_sep_cpu(); 881 #endif 882 mtrr_ap_init(); 883 } 884 885 struct msr_range { 886 unsigned min; 887 unsigned max; 888 }; 889 890 static const struct msr_range msr_range_array[] __cpuinitconst = { 891 { 0x00000000, 0x00000418}, 892 { 0xc0000000, 0xc000040b}, 893 { 0xc0010000, 0xc0010142}, 894 { 0xc0011000, 0xc001103b}, 895 }; 896 897 static void __cpuinit print_cpu_msr(void) 898 { 899 unsigned index_min, index_max; 900 unsigned index; 901 u64 val; 902 int i; 903 904 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 905 index_min = msr_range_array[i].min; 906 index_max = msr_range_array[i].max; 907 908 for (index = index_min; index < index_max; index++) { 909 if (rdmsrl_amd_safe(index, &val)) 910 continue; 911 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 912 } 913 } 914 } 915 916 static int show_msr __cpuinitdata; 917 918 static __init int setup_show_msr(char *arg) 919 { 920 int num; 921 922 get_option(&arg, &num); 923 924 if (num > 0) 925 show_msr = num; 926 return 1; 927 } 928 __setup("show_msr=", setup_show_msr); 929 930 static __init int setup_noclflush(char *arg) 931 { 932 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 933 return 1; 934 } 935 __setup("noclflush", setup_noclflush); 936 937 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 938 { 939 const char *vendor = NULL; 940 941 if (c->x86_vendor < X86_VENDOR_NUM) { 942 vendor = this_cpu->c_vendor; 943 } else { 944 if (c->cpuid_level >= 0) 945 vendor = c->x86_vendor_id; 946 } 947 948 if (vendor && !strstr(c->x86_model_id, vendor)) 949 printk(KERN_CONT "%s ", vendor); 950 951 if (c->x86_model_id[0]) 952 printk(KERN_CONT "%s", c->x86_model_id); 953 else 954 printk(KERN_CONT "%d86", c->x86); 955 956 if (c->x86_mask || c->cpuid_level >= 0) 957 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 958 else 959 printk(KERN_CONT "\n"); 960 961 #ifdef CONFIG_SMP 962 if (c->cpu_index < show_msr) 963 print_cpu_msr(); 964 #else 965 if (show_msr) 966 print_cpu_msr(); 967 #endif 968 } 969 970 static __init int setup_disablecpuid(char *arg) 971 { 972 int bit; 973 974 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 975 setup_clear_cpu_cap(bit); 976 else 977 return 0; 978 979 return 1; 980 } 981 __setup("clearcpuid=", setup_disablecpuid); 982 983 #ifdef CONFIG_X86_64 984 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 985 986 DEFINE_PER_CPU_FIRST(union irq_stack_union, 987 irq_stack_union) __aligned(PAGE_SIZE); 988 989 /* 990 * The following four percpu variables are hot. Align current_task to 991 * cacheline size such that all four fall in the same cacheline. 992 */ 993 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 994 &init_task; 995 EXPORT_PER_CPU_SYMBOL(current_task); 996 997 DEFINE_PER_CPU(unsigned long, kernel_stack) = 998 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 999 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1000 1001 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1002 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1003 1004 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 1005 1006 /* 1007 * Special IST stacks which the CPU switches to when it calls 1008 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1009 * limit), all of them are 4K, except the debug stack which 1010 * is 8K. 1011 */ 1012 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1013 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1014 [DEBUG_STACK - 1] = DEBUG_STKSZ 1015 }; 1016 1017 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1018 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1019 1020 /* May not be marked __init: used by software suspend */ 1021 void syscall_init(void) 1022 { 1023 /* 1024 * LSTAR and STAR live in a bit strange symbiosis. 1025 * They both write to the same internal register. STAR allows to 1026 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1027 */ 1028 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1029 wrmsrl(MSR_LSTAR, system_call); 1030 wrmsrl(MSR_CSTAR, ignore_sysret); 1031 1032 #ifdef CONFIG_IA32_EMULATION 1033 syscall32_cpu_init(); 1034 #endif 1035 1036 /* Flags to clear on syscall */ 1037 wrmsrl(MSR_SYSCALL_MASK, 1038 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 1039 } 1040 1041 unsigned long kernel_eflags; 1042 1043 /* 1044 * Copies of the original ist values from the tss are only accessed during 1045 * debugging, no special alignment required. 1046 */ 1047 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1048 1049 #else /* CONFIG_X86_64 */ 1050 1051 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1052 EXPORT_PER_CPU_SYMBOL(current_task); 1053 1054 #ifdef CONFIG_CC_STACKPROTECTOR 1055 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1056 #endif 1057 1058 /* Make sure %fs and %gs are initialized properly in idle threads */ 1059 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 1060 { 1061 memset(regs, 0, sizeof(struct pt_regs)); 1062 regs->fs = __KERNEL_PERCPU; 1063 regs->gs = __KERNEL_STACK_CANARY; 1064 1065 return regs; 1066 } 1067 #endif /* CONFIG_X86_64 */ 1068 1069 /* 1070 * Clear all 6 debug registers: 1071 */ 1072 static void clear_all_debug_regs(void) 1073 { 1074 int i; 1075 1076 for (i = 0; i < 8; i++) { 1077 /* Ignore db4, db5 */ 1078 if ((i == 4) || (i == 5)) 1079 continue; 1080 1081 set_debugreg(0, i); 1082 } 1083 } 1084 1085 /* 1086 * cpu_init() initializes state that is per-CPU. Some data is already 1087 * initialized (naturally) in the bootstrap process, such as the GDT 1088 * and IDT. We reload them nevertheless, this function acts as a 1089 * 'CPU state barrier', nothing should get across. 1090 * A lot of state is already set up in PDA init for 64 bit 1091 */ 1092 #ifdef CONFIG_X86_64 1093 1094 void __cpuinit cpu_init(void) 1095 { 1096 struct orig_ist *orig_ist; 1097 struct task_struct *me; 1098 struct tss_struct *t; 1099 unsigned long v; 1100 int cpu; 1101 int i; 1102 1103 cpu = stack_smp_processor_id(); 1104 t = &per_cpu(init_tss, cpu); 1105 orig_ist = &per_cpu(orig_ist, cpu); 1106 1107 #ifdef CONFIG_NUMA 1108 if (cpu != 0 && percpu_read(node_number) == 0 && 1109 cpu_to_node(cpu) != NUMA_NO_NODE) 1110 percpu_write(node_number, cpu_to_node(cpu)); 1111 #endif 1112 1113 me = current; 1114 1115 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1116 panic("CPU#%d already initialized!\n", cpu); 1117 1118 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1119 1120 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1121 1122 /* 1123 * Initialize the per-CPU GDT with the boot GDT, 1124 * and set up the GDT descriptor: 1125 */ 1126 1127 switch_to_new_gdt(cpu); 1128 loadsegment(fs, 0); 1129 1130 load_idt((const struct desc_ptr *)&idt_descr); 1131 1132 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1133 syscall_init(); 1134 1135 wrmsrl(MSR_FS_BASE, 0); 1136 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1137 barrier(); 1138 1139 check_efer(); 1140 if (cpu != 0) 1141 enable_x2apic(); 1142 1143 /* 1144 * set up and load the per-CPU TSS 1145 */ 1146 if (!orig_ist->ist[0]) { 1147 char *estacks = per_cpu(exception_stacks, cpu); 1148 1149 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1150 estacks += exception_stack_sizes[v]; 1151 orig_ist->ist[v] = t->x86_tss.ist[v] = 1152 (unsigned long)estacks; 1153 } 1154 } 1155 1156 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1157 1158 /* 1159 * <= is required because the CPU will access up to 1160 * 8 bits beyond the end of the IO permission bitmap. 1161 */ 1162 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1163 t->io_bitmap[i] = ~0UL; 1164 1165 atomic_inc(&init_mm.mm_count); 1166 me->active_mm = &init_mm; 1167 BUG_ON(me->mm); 1168 enter_lazy_tlb(&init_mm, me); 1169 1170 load_sp0(t, ¤t->thread); 1171 set_tss_desc(cpu, t); 1172 load_TR_desc(); 1173 load_LDT(&init_mm.context); 1174 1175 #ifdef CONFIG_KGDB 1176 /* 1177 * If the kgdb is connected no debug regs should be altered. This 1178 * is only applicable when KGDB and a KGDB I/O module are built 1179 * into the kernel and you are using early debugging with 1180 * kgdbwait. KGDB will control the kernel HW breakpoint registers. 1181 */ 1182 if (kgdb_connected && arch_kgdb_ops.correct_hw_break) 1183 arch_kgdb_ops.correct_hw_break(); 1184 else 1185 #endif 1186 clear_all_debug_regs(); 1187 1188 fpu_init(); 1189 1190 raw_local_save_flags(kernel_eflags); 1191 1192 if (is_uv_system()) 1193 uv_cpu_init(); 1194 } 1195 1196 #else 1197 1198 void __cpuinit cpu_init(void) 1199 { 1200 int cpu = smp_processor_id(); 1201 struct task_struct *curr = current; 1202 struct tss_struct *t = &per_cpu(init_tss, cpu); 1203 struct thread_struct *thread = &curr->thread; 1204 1205 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1206 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1207 for (;;) 1208 local_irq_enable(); 1209 } 1210 1211 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1212 1213 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1214 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1215 1216 load_idt(&idt_descr); 1217 switch_to_new_gdt(cpu); 1218 1219 /* 1220 * Set up and load the per-CPU TSS and LDT 1221 */ 1222 atomic_inc(&init_mm.mm_count); 1223 curr->active_mm = &init_mm; 1224 BUG_ON(curr->mm); 1225 enter_lazy_tlb(&init_mm, curr); 1226 1227 load_sp0(t, thread); 1228 set_tss_desc(cpu, t); 1229 load_TR_desc(); 1230 load_LDT(&init_mm.context); 1231 1232 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1233 1234 #ifdef CONFIG_DOUBLEFAULT 1235 /* Set up doublefault TSS pointer in the GDT */ 1236 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1237 #endif 1238 1239 clear_all_debug_regs(); 1240 1241 /* 1242 * Force FPU initialization: 1243 */ 1244 if (cpu_has_xsave) 1245 current_thread_info()->status = TS_XSAVE; 1246 else 1247 current_thread_info()->status = 0; 1248 clear_used_math(); 1249 mxcsr_feature_mask_init(); 1250 1251 /* 1252 * Boot processor to setup the FP and extended state context info. 1253 */ 1254 if (smp_processor_id() == boot_cpu_id) 1255 init_thread_xstate(); 1256 1257 xsave_init(); 1258 } 1259 #endif 1260