1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 26 #include <asm/cmdline.h> 27 #include <asm/stackprotector.h> 28 #include <asm/perf_event.h> 29 #include <asm/mmu_context.h> 30 #include <asm/doublefault.h> 31 #include <asm/archrandom.h> 32 #include <asm/hypervisor.h> 33 #include <asm/processor.h> 34 #include <asm/tlbflush.h> 35 #include <asm/debugreg.h> 36 #include <asm/sections.h> 37 #include <asm/vsyscall.h> 38 #include <linux/topology.h> 39 #include <linux/cpumask.h> 40 #include <linux/atomic.h> 41 #include <asm/proto.h> 42 #include <asm/setup.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/fpu/api.h> 46 #include <asm/mtrr.h> 47 #include <asm/hwcap2.h> 48 #include <linux/numa.h> 49 #include <asm/numa.h> 50 #include <asm/asm.h> 51 #include <asm/bugs.h> 52 #include <asm/cpu.h> 53 #include <asm/mce.h> 54 #include <asm/msr.h> 55 #include <asm/memtype.h> 56 #include <asm/microcode.h> 57 #include <asm/microcode_intel.h> 58 #include <asm/intel-family.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/uv/uv.h> 61 #include <asm/sigframe.h> 62 #include <asm/traps.h> 63 #include <asm/sev.h> 64 65 #include "cpu.h" 66 67 u32 elf_hwcap2 __read_mostly; 68 69 /* all of these masks are initialized in setup_cpu_local_masks() */ 70 cpumask_var_t cpu_initialized_mask; 71 cpumask_var_t cpu_callout_mask; 72 cpumask_var_t cpu_callin_mask; 73 74 /* representing cpus for which sibling maps can be computed */ 75 cpumask_var_t cpu_sibling_setup_mask; 76 77 /* Number of siblings per CPU package */ 78 int smp_num_siblings = 1; 79 EXPORT_SYMBOL(smp_num_siblings); 80 81 /* Last level cache ID of each logical CPU */ 82 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 83 84 u16 get_llc_id(unsigned int cpu) 85 { 86 return per_cpu(cpu_llc_id, cpu); 87 } 88 EXPORT_SYMBOL_GPL(get_llc_id); 89 90 /* L2 cache ID of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 92 93 static struct ppin_info { 94 int feature; 95 int msr_ppin_ctl; 96 int msr_ppin; 97 } ppin_info[] = { 98 [X86_VENDOR_INTEL] = { 99 .feature = X86_FEATURE_INTEL_PPIN, 100 .msr_ppin_ctl = MSR_PPIN_CTL, 101 .msr_ppin = MSR_PPIN 102 }, 103 [X86_VENDOR_AMD] = { 104 .feature = X86_FEATURE_AMD_PPIN, 105 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 106 .msr_ppin = MSR_AMD_PPIN 107 }, 108 }; 109 110 static const struct x86_cpu_id ppin_cpuids[] = { 111 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 112 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 113 114 /* Legacy models without CPUID enumeration */ 115 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 116 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 117 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 125 126 {} 127 }; 128 129 static void ppin_init(struct cpuinfo_x86 *c) 130 { 131 const struct x86_cpu_id *id; 132 unsigned long long val; 133 struct ppin_info *info; 134 135 id = x86_match_cpu(ppin_cpuids); 136 if (!id) 137 return; 138 139 /* 140 * Testing the presence of the MSR is not enough. Need to check 141 * that the PPIN_CTL allows reading of the PPIN. 142 */ 143 info = (struct ppin_info *)id->driver_data; 144 145 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 146 goto clear_ppin; 147 148 if ((val & 3UL) == 1UL) { 149 /* PPIN locked in disabled mode */ 150 goto clear_ppin; 151 } 152 153 /* If PPIN is disabled, try to enable */ 154 if (!(val & 2UL)) { 155 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 156 rdmsrl_safe(info->msr_ppin_ctl, &val); 157 } 158 159 /* Is the enable bit set? */ 160 if (val & 2UL) { 161 c->ppin = __rdmsr(info->msr_ppin); 162 set_cpu_cap(c, info->feature); 163 return; 164 } 165 166 clear_ppin: 167 clear_cpu_cap(c, info->feature); 168 } 169 170 /* correctly size the local cpu masks */ 171 void __init setup_cpu_local_masks(void) 172 { 173 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 174 alloc_bootmem_cpumask_var(&cpu_callin_mask); 175 alloc_bootmem_cpumask_var(&cpu_callout_mask); 176 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 177 } 178 179 static void default_init(struct cpuinfo_x86 *c) 180 { 181 #ifdef CONFIG_X86_64 182 cpu_detect_cache_sizes(c); 183 #else 184 /* Not much we can do here... */ 185 /* Check if at least it has cpuid */ 186 if (c->cpuid_level == -1) { 187 /* No cpuid. It must be an ancient CPU */ 188 if (c->x86 == 4) 189 strcpy(c->x86_model_id, "486"); 190 else if (c->x86 == 3) 191 strcpy(c->x86_model_id, "386"); 192 } 193 #endif 194 } 195 196 static const struct cpu_dev default_cpu = { 197 .c_init = default_init, 198 .c_vendor = "Unknown", 199 .c_x86_vendor = X86_VENDOR_UNKNOWN, 200 }; 201 202 static const struct cpu_dev *this_cpu = &default_cpu; 203 204 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 205 #ifdef CONFIG_X86_64 206 /* 207 * We need valid kernel segments for data and code in long mode too 208 * IRET will check the segment types kkeil 2000/10/28 209 * Also sysret mandates a special GDT layout 210 * 211 * TLS descriptors are currently at a different place compared to i386. 212 * Hopefully nobody expects them at a fixed place (Wine?) 213 */ 214 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 215 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 216 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 217 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 218 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 219 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 220 #else 221 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 222 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 223 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 224 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 225 /* 226 * Segments used for calling PnP BIOS have byte granularity. 227 * They code segments and data segments have fixed 64k limits, 228 * the transfer segment sizes are set at run time. 229 */ 230 /* 32-bit code */ 231 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 232 /* 16-bit code */ 233 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 234 /* 16-bit data */ 235 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 236 /* 16-bit data */ 237 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 238 /* 16-bit data */ 239 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 240 /* 241 * The APM segments have byte granularity and their bases 242 * are set at run time. All have 64k limits. 243 */ 244 /* 32-bit code */ 245 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 246 /* 16-bit code */ 247 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 248 /* data */ 249 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 250 251 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 252 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 253 #endif 254 } }; 255 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 256 257 #ifdef CONFIG_X86_64 258 static int __init x86_nopcid_setup(char *s) 259 { 260 /* nopcid doesn't accept parameters */ 261 if (s) 262 return -EINVAL; 263 264 /* do not emit a message if the feature is not present */ 265 if (!boot_cpu_has(X86_FEATURE_PCID)) 266 return 0; 267 268 setup_clear_cpu_cap(X86_FEATURE_PCID); 269 pr_info("nopcid: PCID feature disabled\n"); 270 return 0; 271 } 272 early_param("nopcid", x86_nopcid_setup); 273 #endif 274 275 static int __init x86_noinvpcid_setup(char *s) 276 { 277 /* noinvpcid doesn't accept parameters */ 278 if (s) 279 return -EINVAL; 280 281 /* do not emit a message if the feature is not present */ 282 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 283 return 0; 284 285 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 286 pr_info("noinvpcid: INVPCID feature disabled\n"); 287 return 0; 288 } 289 early_param("noinvpcid", x86_noinvpcid_setup); 290 291 #ifdef CONFIG_X86_32 292 static int cachesize_override = -1; 293 static int disable_x86_serial_nr = 1; 294 295 static int __init cachesize_setup(char *str) 296 { 297 get_option(&str, &cachesize_override); 298 return 1; 299 } 300 __setup("cachesize=", cachesize_setup); 301 302 static int __init x86_sep_setup(char *s) 303 { 304 setup_clear_cpu_cap(X86_FEATURE_SEP); 305 return 1; 306 } 307 __setup("nosep", x86_sep_setup); 308 309 /* Standard macro to see if a specific flag is changeable */ 310 static inline int flag_is_changeable_p(u32 flag) 311 { 312 u32 f1, f2; 313 314 /* 315 * Cyrix and IDT cpus allow disabling of CPUID 316 * so the code below may return different results 317 * when it is executed before and after enabling 318 * the CPUID. Add "volatile" to not allow gcc to 319 * optimize the subsequent calls to this function. 320 */ 321 asm volatile ("pushfl \n\t" 322 "pushfl \n\t" 323 "popl %0 \n\t" 324 "movl %0, %1 \n\t" 325 "xorl %2, %0 \n\t" 326 "pushl %0 \n\t" 327 "popfl \n\t" 328 "pushfl \n\t" 329 "popl %0 \n\t" 330 "popfl \n\t" 331 332 : "=&r" (f1), "=&r" (f2) 333 : "ir" (flag)); 334 335 return ((f1^f2) & flag) != 0; 336 } 337 338 /* Probe for the CPUID instruction */ 339 int have_cpuid_p(void) 340 { 341 return flag_is_changeable_p(X86_EFLAGS_ID); 342 } 343 344 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 345 { 346 unsigned long lo, hi; 347 348 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 349 return; 350 351 /* Disable processor serial number: */ 352 353 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 354 lo |= 0x200000; 355 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 356 357 pr_notice("CPU serial number disabled.\n"); 358 clear_cpu_cap(c, X86_FEATURE_PN); 359 360 /* Disabling the serial number may affect the cpuid level */ 361 c->cpuid_level = cpuid_eax(0); 362 } 363 364 static int __init x86_serial_nr_setup(char *s) 365 { 366 disable_x86_serial_nr = 0; 367 return 1; 368 } 369 __setup("serialnumber", x86_serial_nr_setup); 370 #else 371 static inline int flag_is_changeable_p(u32 flag) 372 { 373 return 1; 374 } 375 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 376 { 377 } 378 #endif 379 380 static __init int setup_disable_smep(char *arg) 381 { 382 setup_clear_cpu_cap(X86_FEATURE_SMEP); 383 return 1; 384 } 385 __setup("nosmep", setup_disable_smep); 386 387 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 388 { 389 if (cpu_has(c, X86_FEATURE_SMEP)) 390 cr4_set_bits(X86_CR4_SMEP); 391 } 392 393 static __init int setup_disable_smap(char *arg) 394 { 395 setup_clear_cpu_cap(X86_FEATURE_SMAP); 396 return 1; 397 } 398 __setup("nosmap", setup_disable_smap); 399 400 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 401 { 402 unsigned long eflags = native_save_fl(); 403 404 /* This should have been cleared long ago */ 405 BUG_ON(eflags & X86_EFLAGS_AC); 406 407 if (cpu_has(c, X86_FEATURE_SMAP)) { 408 #ifdef CONFIG_X86_SMAP 409 cr4_set_bits(X86_CR4_SMAP); 410 #else 411 clear_cpu_cap(c, X86_FEATURE_SMAP); 412 cr4_clear_bits(X86_CR4_SMAP); 413 #endif 414 } 415 } 416 417 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 418 { 419 /* Check the boot processor, plus build option for UMIP. */ 420 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 421 goto out; 422 423 /* Check the current processor's cpuid bits. */ 424 if (!cpu_has(c, X86_FEATURE_UMIP)) 425 goto out; 426 427 cr4_set_bits(X86_CR4_UMIP); 428 429 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 430 431 return; 432 433 out: 434 /* 435 * Make sure UMIP is disabled in case it was enabled in a 436 * previous boot (e.g., via kexec). 437 */ 438 cr4_clear_bits(X86_CR4_UMIP); 439 } 440 441 /* These bits should not change their value after CPU init is finished. */ 442 static const unsigned long cr4_pinned_mask = 443 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 444 X86_CR4_FSGSBASE | X86_CR4_CET; 445 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 446 static unsigned long cr4_pinned_bits __ro_after_init; 447 448 void native_write_cr0(unsigned long val) 449 { 450 unsigned long bits_missing = 0; 451 452 set_register: 453 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 454 455 if (static_branch_likely(&cr_pinning)) { 456 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 457 bits_missing = X86_CR0_WP; 458 val |= bits_missing; 459 goto set_register; 460 } 461 /* Warn after we've set the missing bits. */ 462 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 463 } 464 } 465 EXPORT_SYMBOL(native_write_cr0); 466 467 void __no_profile native_write_cr4(unsigned long val) 468 { 469 unsigned long bits_changed = 0; 470 471 set_register: 472 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 473 474 if (static_branch_likely(&cr_pinning)) { 475 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 476 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 477 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 478 goto set_register; 479 } 480 /* Warn after we've corrected the changed bits. */ 481 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 482 bits_changed); 483 } 484 } 485 #if IS_MODULE(CONFIG_LKDTM) 486 EXPORT_SYMBOL_GPL(native_write_cr4); 487 #endif 488 489 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 490 { 491 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 492 493 lockdep_assert_irqs_disabled(); 494 495 newval = (cr4 & ~clear) | set; 496 if (newval != cr4) { 497 this_cpu_write(cpu_tlbstate.cr4, newval); 498 __write_cr4(newval); 499 } 500 } 501 EXPORT_SYMBOL(cr4_update_irqsoff); 502 503 /* Read the CR4 shadow. */ 504 unsigned long cr4_read_shadow(void) 505 { 506 return this_cpu_read(cpu_tlbstate.cr4); 507 } 508 EXPORT_SYMBOL_GPL(cr4_read_shadow); 509 510 void cr4_init(void) 511 { 512 unsigned long cr4 = __read_cr4(); 513 514 if (boot_cpu_has(X86_FEATURE_PCID)) 515 cr4 |= X86_CR4_PCIDE; 516 if (static_branch_likely(&cr_pinning)) 517 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 518 519 __write_cr4(cr4); 520 521 /* Initialize cr4 shadow for this CPU. */ 522 this_cpu_write(cpu_tlbstate.cr4, cr4); 523 } 524 525 /* 526 * Once CPU feature detection is finished (and boot params have been 527 * parsed), record any of the sensitive CR bits that are set, and 528 * enable CR pinning. 529 */ 530 static void __init setup_cr_pinning(void) 531 { 532 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 533 static_key_enable(&cr_pinning.key); 534 } 535 536 static __init int x86_nofsgsbase_setup(char *arg) 537 { 538 /* Require an exact match without trailing characters. */ 539 if (strlen(arg)) 540 return 0; 541 542 /* Do not emit a message if the feature is not present. */ 543 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 544 return 1; 545 546 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 547 pr_info("FSGSBASE disabled via kernel command line\n"); 548 return 1; 549 } 550 __setup("nofsgsbase", x86_nofsgsbase_setup); 551 552 /* 553 * Protection Keys are not available in 32-bit mode. 554 */ 555 static bool pku_disabled; 556 557 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 558 { 559 if (c == &boot_cpu_data) { 560 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 561 return; 562 /* 563 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 564 * bit to be set. Enforce it. 565 */ 566 setup_force_cpu_cap(X86_FEATURE_OSPKE); 567 568 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 569 return; 570 } 571 572 cr4_set_bits(X86_CR4_PKE); 573 /* Load the default PKRU value */ 574 pkru_write_default(); 575 } 576 577 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 578 static __init int setup_disable_pku(char *arg) 579 { 580 /* 581 * Do not clear the X86_FEATURE_PKU bit. All of the 582 * runtime checks are against OSPKE so clearing the 583 * bit does nothing. 584 * 585 * This way, we will see "pku" in cpuinfo, but not 586 * "ospke", which is exactly what we want. It shows 587 * that the CPU has PKU, but the OS has not enabled it. 588 * This happens to be exactly how a system would look 589 * if we disabled the config option. 590 */ 591 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 592 pku_disabled = true; 593 return 1; 594 } 595 __setup("nopku", setup_disable_pku); 596 #endif /* CONFIG_X86_64 */ 597 598 #ifdef CONFIG_X86_KERNEL_IBT 599 600 __noendbr u64 ibt_save(void) 601 { 602 u64 msr = 0; 603 604 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 605 rdmsrl(MSR_IA32_S_CET, msr); 606 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 607 } 608 609 return msr; 610 } 611 612 __noendbr void ibt_restore(u64 save) 613 { 614 u64 msr; 615 616 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 617 rdmsrl(MSR_IA32_S_CET, msr); 618 msr &= ~CET_ENDBR_EN; 619 msr |= (save & CET_ENDBR_EN); 620 wrmsrl(MSR_IA32_S_CET, msr); 621 } 622 } 623 624 #endif 625 626 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 627 { 628 u64 msr = CET_ENDBR_EN; 629 630 if (!HAS_KERNEL_IBT || 631 !cpu_feature_enabled(X86_FEATURE_IBT)) 632 return; 633 634 wrmsrl(MSR_IA32_S_CET, msr); 635 cr4_set_bits(X86_CR4_CET); 636 637 if (!ibt_selftest()) { 638 pr_err("IBT selftest: Failed!\n"); 639 setup_clear_cpu_cap(X86_FEATURE_IBT); 640 return; 641 } 642 } 643 644 __noendbr void cet_disable(void) 645 { 646 if (cpu_feature_enabled(X86_FEATURE_IBT)) 647 wrmsrl(MSR_IA32_S_CET, 0); 648 } 649 650 /* 651 * Some CPU features depend on higher CPUID levels, which may not always 652 * be available due to CPUID level capping or broken virtualization 653 * software. Add those features to this table to auto-disable them. 654 */ 655 struct cpuid_dependent_feature { 656 u32 feature; 657 u32 level; 658 }; 659 660 static const struct cpuid_dependent_feature 661 cpuid_dependent_features[] = { 662 { X86_FEATURE_MWAIT, 0x00000005 }, 663 { X86_FEATURE_DCA, 0x00000009 }, 664 { X86_FEATURE_XSAVE, 0x0000000d }, 665 { 0, 0 } 666 }; 667 668 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 669 { 670 const struct cpuid_dependent_feature *df; 671 672 for (df = cpuid_dependent_features; df->feature; df++) { 673 674 if (!cpu_has(c, df->feature)) 675 continue; 676 /* 677 * Note: cpuid_level is set to -1 if unavailable, but 678 * extended_extended_level is set to 0 if unavailable 679 * and the legitimate extended levels are all negative 680 * when signed; hence the weird messing around with 681 * signs here... 682 */ 683 if (!((s32)df->level < 0 ? 684 (u32)df->level > (u32)c->extended_cpuid_level : 685 (s32)df->level > (s32)c->cpuid_level)) 686 continue; 687 688 clear_cpu_cap(c, df->feature); 689 if (!warn) 690 continue; 691 692 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 693 x86_cap_flag(df->feature), df->level); 694 } 695 } 696 697 /* 698 * Naming convention should be: <Name> [(<Codename>)] 699 * This table only is used unless init_<vendor>() below doesn't set it; 700 * in particular, if CPUID levels 0x80000002..4 are supported, this 701 * isn't used 702 */ 703 704 /* Look up CPU names by table lookup. */ 705 static const char *table_lookup_model(struct cpuinfo_x86 *c) 706 { 707 #ifdef CONFIG_X86_32 708 const struct legacy_cpu_model_info *info; 709 710 if (c->x86_model >= 16) 711 return NULL; /* Range check */ 712 713 if (!this_cpu) 714 return NULL; 715 716 info = this_cpu->legacy_models; 717 718 while (info->family) { 719 if (info->family == c->x86) 720 return info->model_names[c->x86_model]; 721 info++; 722 } 723 #endif 724 return NULL; /* Not found */ 725 } 726 727 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 728 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 729 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 730 731 void load_percpu_segment(int cpu) 732 { 733 #ifdef CONFIG_X86_32 734 loadsegment(fs, __KERNEL_PERCPU); 735 #else 736 __loadsegment_simple(gs, 0); 737 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 738 #endif 739 } 740 741 #ifdef CONFIG_X86_32 742 /* The 32-bit entry code needs to find cpu_entry_area. */ 743 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 744 #endif 745 746 /* Load the original GDT from the per-cpu structure */ 747 void load_direct_gdt(int cpu) 748 { 749 struct desc_ptr gdt_descr; 750 751 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 752 gdt_descr.size = GDT_SIZE - 1; 753 load_gdt(&gdt_descr); 754 } 755 EXPORT_SYMBOL_GPL(load_direct_gdt); 756 757 /* Load a fixmap remapping of the per-cpu GDT */ 758 void load_fixmap_gdt(int cpu) 759 { 760 struct desc_ptr gdt_descr; 761 762 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 763 gdt_descr.size = GDT_SIZE - 1; 764 load_gdt(&gdt_descr); 765 } 766 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 767 768 /* 769 * Current gdt points %fs at the "master" per-cpu area: after this, 770 * it's on the real one. 771 */ 772 void switch_to_new_gdt(int cpu) 773 { 774 /* Load the original GDT */ 775 load_direct_gdt(cpu); 776 /* Reload the per-cpu base */ 777 load_percpu_segment(cpu); 778 } 779 780 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 781 782 static void get_model_name(struct cpuinfo_x86 *c) 783 { 784 unsigned int *v; 785 char *p, *q, *s; 786 787 if (c->extended_cpuid_level < 0x80000004) 788 return; 789 790 v = (unsigned int *)c->x86_model_id; 791 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 792 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 793 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 794 c->x86_model_id[48] = 0; 795 796 /* Trim whitespace */ 797 p = q = s = &c->x86_model_id[0]; 798 799 while (*p == ' ') 800 p++; 801 802 while (*p) { 803 /* Note the last non-whitespace index */ 804 if (!isspace(*p)) 805 s = q; 806 807 *q++ = *p++; 808 } 809 810 *(s + 1) = '\0'; 811 } 812 813 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 814 { 815 unsigned int eax, ebx, ecx, edx; 816 817 c->x86_max_cores = 1; 818 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 819 return; 820 821 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 822 if (eax & 0x1f) 823 c->x86_max_cores = (eax >> 26) + 1; 824 } 825 826 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 827 { 828 unsigned int n, dummy, ebx, ecx, edx, l2size; 829 830 n = c->extended_cpuid_level; 831 832 if (n >= 0x80000005) { 833 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 834 c->x86_cache_size = (ecx>>24) + (edx>>24); 835 #ifdef CONFIG_X86_64 836 /* On K8 L1 TLB is inclusive, so don't count it */ 837 c->x86_tlbsize = 0; 838 #endif 839 } 840 841 if (n < 0x80000006) /* Some chips just has a large L1. */ 842 return; 843 844 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 845 l2size = ecx >> 16; 846 847 #ifdef CONFIG_X86_64 848 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 849 #else 850 /* do processor-specific cache resizing */ 851 if (this_cpu->legacy_cache_size) 852 l2size = this_cpu->legacy_cache_size(c, l2size); 853 854 /* Allow user to override all this if necessary. */ 855 if (cachesize_override != -1) 856 l2size = cachesize_override; 857 858 if (l2size == 0) 859 return; /* Again, no L2 cache is possible */ 860 #endif 861 862 c->x86_cache_size = l2size; 863 } 864 865 u16 __read_mostly tlb_lli_4k[NR_INFO]; 866 u16 __read_mostly tlb_lli_2m[NR_INFO]; 867 u16 __read_mostly tlb_lli_4m[NR_INFO]; 868 u16 __read_mostly tlb_lld_4k[NR_INFO]; 869 u16 __read_mostly tlb_lld_2m[NR_INFO]; 870 u16 __read_mostly tlb_lld_4m[NR_INFO]; 871 u16 __read_mostly tlb_lld_1g[NR_INFO]; 872 873 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 874 { 875 if (this_cpu->c_detect_tlb) 876 this_cpu->c_detect_tlb(c); 877 878 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 879 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 880 tlb_lli_4m[ENTRIES]); 881 882 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 883 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 884 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 885 } 886 887 int detect_ht_early(struct cpuinfo_x86 *c) 888 { 889 #ifdef CONFIG_SMP 890 u32 eax, ebx, ecx, edx; 891 892 if (!cpu_has(c, X86_FEATURE_HT)) 893 return -1; 894 895 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 896 return -1; 897 898 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 899 return -1; 900 901 cpuid(1, &eax, &ebx, &ecx, &edx); 902 903 smp_num_siblings = (ebx & 0xff0000) >> 16; 904 if (smp_num_siblings == 1) 905 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 906 #endif 907 return 0; 908 } 909 910 void detect_ht(struct cpuinfo_x86 *c) 911 { 912 #ifdef CONFIG_SMP 913 int index_msb, core_bits; 914 915 if (detect_ht_early(c) < 0) 916 return; 917 918 index_msb = get_count_order(smp_num_siblings); 919 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 920 921 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 922 923 index_msb = get_count_order(smp_num_siblings); 924 925 core_bits = get_count_order(c->x86_max_cores); 926 927 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 928 ((1 << core_bits) - 1); 929 #endif 930 } 931 932 static void get_cpu_vendor(struct cpuinfo_x86 *c) 933 { 934 char *v = c->x86_vendor_id; 935 int i; 936 937 for (i = 0; i < X86_VENDOR_NUM; i++) { 938 if (!cpu_devs[i]) 939 break; 940 941 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 942 (cpu_devs[i]->c_ident[1] && 943 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 944 945 this_cpu = cpu_devs[i]; 946 c->x86_vendor = this_cpu->c_x86_vendor; 947 return; 948 } 949 } 950 951 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 952 "CPU: Your system may be unstable.\n", v); 953 954 c->x86_vendor = X86_VENDOR_UNKNOWN; 955 this_cpu = &default_cpu; 956 } 957 958 void cpu_detect(struct cpuinfo_x86 *c) 959 { 960 /* Get vendor name */ 961 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 962 (unsigned int *)&c->x86_vendor_id[0], 963 (unsigned int *)&c->x86_vendor_id[8], 964 (unsigned int *)&c->x86_vendor_id[4]); 965 966 c->x86 = 4; 967 /* Intel-defined flags: level 0x00000001 */ 968 if (c->cpuid_level >= 0x00000001) { 969 u32 junk, tfms, cap0, misc; 970 971 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 972 c->x86 = x86_family(tfms); 973 c->x86_model = x86_model(tfms); 974 c->x86_stepping = x86_stepping(tfms); 975 976 if (cap0 & (1<<19)) { 977 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 978 c->x86_cache_alignment = c->x86_clflush_size; 979 } 980 } 981 } 982 983 static void apply_forced_caps(struct cpuinfo_x86 *c) 984 { 985 int i; 986 987 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 988 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 989 c->x86_capability[i] |= cpu_caps_set[i]; 990 } 991 } 992 993 static void init_speculation_control(struct cpuinfo_x86 *c) 994 { 995 /* 996 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 997 * and they also have a different bit for STIBP support. Also, 998 * a hypervisor might have set the individual AMD bits even on 999 * Intel CPUs, for finer-grained selection of what's available. 1000 */ 1001 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 1002 set_cpu_cap(c, X86_FEATURE_IBRS); 1003 set_cpu_cap(c, X86_FEATURE_IBPB); 1004 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1005 } 1006 1007 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 1008 set_cpu_cap(c, X86_FEATURE_STIBP); 1009 1010 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 1011 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 1012 set_cpu_cap(c, X86_FEATURE_SSBD); 1013 1014 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 1015 set_cpu_cap(c, X86_FEATURE_IBRS); 1016 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1017 } 1018 1019 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 1020 set_cpu_cap(c, X86_FEATURE_IBPB); 1021 1022 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 1023 set_cpu_cap(c, X86_FEATURE_STIBP); 1024 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1025 } 1026 1027 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1028 set_cpu_cap(c, X86_FEATURE_SSBD); 1029 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1030 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1031 } 1032 } 1033 1034 void get_cpu_cap(struct cpuinfo_x86 *c) 1035 { 1036 u32 eax, ebx, ecx, edx; 1037 1038 /* Intel-defined flags: level 0x00000001 */ 1039 if (c->cpuid_level >= 0x00000001) { 1040 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1041 1042 c->x86_capability[CPUID_1_ECX] = ecx; 1043 c->x86_capability[CPUID_1_EDX] = edx; 1044 } 1045 1046 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1047 if (c->cpuid_level >= 0x00000006) 1048 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1049 1050 /* Additional Intel-defined flags: level 0x00000007 */ 1051 if (c->cpuid_level >= 0x00000007) { 1052 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1053 c->x86_capability[CPUID_7_0_EBX] = ebx; 1054 c->x86_capability[CPUID_7_ECX] = ecx; 1055 c->x86_capability[CPUID_7_EDX] = edx; 1056 1057 /* Check valid sub-leaf index before accessing it */ 1058 if (eax >= 1) { 1059 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1060 c->x86_capability[CPUID_7_1_EAX] = eax; 1061 } 1062 } 1063 1064 /* Extended state features: level 0x0000000d */ 1065 if (c->cpuid_level >= 0x0000000d) { 1066 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1067 1068 c->x86_capability[CPUID_D_1_EAX] = eax; 1069 } 1070 1071 /* AMD-defined flags: level 0x80000001 */ 1072 eax = cpuid_eax(0x80000000); 1073 c->extended_cpuid_level = eax; 1074 1075 if ((eax & 0xffff0000) == 0x80000000) { 1076 if (eax >= 0x80000001) { 1077 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1078 1079 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1080 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1081 } 1082 } 1083 1084 if (c->extended_cpuid_level >= 0x80000007) { 1085 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1086 1087 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1088 c->x86_power = edx; 1089 } 1090 1091 if (c->extended_cpuid_level >= 0x80000008) { 1092 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1093 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1094 } 1095 1096 if (c->extended_cpuid_level >= 0x8000000a) 1097 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1098 1099 if (c->extended_cpuid_level >= 0x8000001f) 1100 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1101 1102 init_scattered_cpuid_features(c); 1103 init_speculation_control(c); 1104 1105 /* 1106 * Clear/Set all flags overridden by options, after probe. 1107 * This needs to happen each time we re-probe, which may happen 1108 * several times during CPU initialization. 1109 */ 1110 apply_forced_caps(c); 1111 } 1112 1113 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1114 { 1115 u32 eax, ebx, ecx, edx; 1116 1117 if (c->extended_cpuid_level >= 0x80000008) { 1118 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1119 1120 c->x86_virt_bits = (eax >> 8) & 0xff; 1121 c->x86_phys_bits = eax & 0xff; 1122 } 1123 #ifdef CONFIG_X86_32 1124 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 1125 c->x86_phys_bits = 36; 1126 #endif 1127 c->x86_cache_bits = c->x86_phys_bits; 1128 } 1129 1130 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1131 { 1132 #ifdef CONFIG_X86_32 1133 int i; 1134 1135 /* 1136 * First of all, decide if this is a 486 or higher 1137 * It's a 486 if we can modify the AC flag 1138 */ 1139 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1140 c->x86 = 4; 1141 else 1142 c->x86 = 3; 1143 1144 for (i = 0; i < X86_VENDOR_NUM; i++) 1145 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1146 c->x86_vendor_id[0] = 0; 1147 cpu_devs[i]->c_identify(c); 1148 if (c->x86_vendor_id[0]) { 1149 get_cpu_vendor(c); 1150 break; 1151 } 1152 } 1153 #endif 1154 } 1155 1156 #define NO_SPECULATION BIT(0) 1157 #define NO_MELTDOWN BIT(1) 1158 #define NO_SSB BIT(2) 1159 #define NO_L1TF BIT(3) 1160 #define NO_MDS BIT(4) 1161 #define MSBDS_ONLY BIT(5) 1162 #define NO_SWAPGS BIT(6) 1163 #define NO_ITLB_MULTIHIT BIT(7) 1164 #define NO_SPECTRE_V2 BIT(8) 1165 1166 #define VULNWL(vendor, family, model, whitelist) \ 1167 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1168 1169 #define VULNWL_INTEL(model, whitelist) \ 1170 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1171 1172 #define VULNWL_AMD(family, whitelist) \ 1173 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1174 1175 #define VULNWL_HYGON(family, whitelist) \ 1176 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1177 1178 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1179 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1180 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1181 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1182 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1183 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1184 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1185 1186 /* Intel Family 6 */ 1187 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1188 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1189 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1190 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1191 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1192 1193 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1194 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1195 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1196 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1197 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1198 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1199 1200 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1201 1202 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1203 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1204 1205 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1206 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1207 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1208 1209 /* 1210 * Technically, swapgs isn't serializing on AMD (despite it previously 1211 * being documented as such in the APM). But according to AMD, %gs is 1212 * updated non-speculatively, and the issuing of %gs-relative memory 1213 * operands will be blocked until the %gs update completes, which is 1214 * good enough for our purposes. 1215 */ 1216 1217 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1218 1219 /* AMD Family 0xf - 0x12 */ 1220 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1221 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1222 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1223 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1224 1225 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1226 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1227 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1228 1229 /* Zhaoxin Family 7 */ 1230 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1231 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1232 {} 1233 }; 1234 1235 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1236 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1237 INTEL_FAM6_##model, steppings, \ 1238 X86_FEATURE_ANY, issues) 1239 1240 #define SRBDS BIT(0) 1241 1242 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1243 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1244 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1245 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1246 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1247 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1248 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1249 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS), 1250 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS), 1251 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS), 1252 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS), 1253 {} 1254 }; 1255 1256 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1257 { 1258 const struct x86_cpu_id *m = x86_match_cpu(table); 1259 1260 return m && !!(m->driver_data & which); 1261 } 1262 1263 u64 x86_read_arch_cap_msr(void) 1264 { 1265 u64 ia32_cap = 0; 1266 1267 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1268 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1269 1270 return ia32_cap; 1271 } 1272 1273 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1274 { 1275 u64 ia32_cap = x86_read_arch_cap_msr(); 1276 1277 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1278 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1279 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1280 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1281 1282 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1283 return; 1284 1285 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1286 1287 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1288 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1289 1290 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1291 !(ia32_cap & ARCH_CAP_SSB_NO) && 1292 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1293 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1294 1295 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1296 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1297 1298 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1299 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1300 setup_force_cpu_bug(X86_BUG_MDS); 1301 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1302 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1303 } 1304 1305 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1306 setup_force_cpu_bug(X86_BUG_SWAPGS); 1307 1308 /* 1309 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1310 * - TSX is supported or 1311 * - TSX_CTRL is present 1312 * 1313 * TSX_CTRL check is needed for cases when TSX could be disabled before 1314 * the kernel boot e.g. kexec. 1315 * TSX_CTRL check alone is not sufficient for cases when the microcode 1316 * update is not present or running as guest that don't get TSX_CTRL. 1317 */ 1318 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1319 (cpu_has(c, X86_FEATURE_RTM) || 1320 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1321 setup_force_cpu_bug(X86_BUG_TAA); 1322 1323 /* 1324 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1325 * in the vulnerability blacklist. 1326 */ 1327 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1328 cpu_has(c, X86_FEATURE_RDSEED)) && 1329 cpu_matches(cpu_vuln_blacklist, SRBDS)) 1330 setup_force_cpu_bug(X86_BUG_SRBDS); 1331 1332 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1333 return; 1334 1335 /* Rogue Data Cache Load? No! */ 1336 if (ia32_cap & ARCH_CAP_RDCL_NO) 1337 return; 1338 1339 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1340 1341 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1342 return; 1343 1344 setup_force_cpu_bug(X86_BUG_L1TF); 1345 } 1346 1347 /* 1348 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1349 * unfortunately, that's not true in practice because of early VIA 1350 * chips and (more importantly) broken virtualizers that are not easy 1351 * to detect. In the latter case it doesn't even *fail* reliably, so 1352 * probing for it doesn't even work. Disable it completely on 32-bit 1353 * unless we can find a reliable way to detect all the broken cases. 1354 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1355 */ 1356 static void detect_nopl(void) 1357 { 1358 #ifdef CONFIG_X86_32 1359 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1360 #else 1361 setup_force_cpu_cap(X86_FEATURE_NOPL); 1362 #endif 1363 } 1364 1365 /* 1366 * We parse cpu parameters early because fpu__init_system() is executed 1367 * before parse_early_param(). 1368 */ 1369 static void __init cpu_parse_early_param(void) 1370 { 1371 char arg[128]; 1372 char *argptr = arg; 1373 int arglen, res, bit; 1374 1375 #ifdef CONFIG_X86_32 1376 if (cmdline_find_option_bool(boot_command_line, "no387")) 1377 #ifdef CONFIG_MATH_EMULATION 1378 setup_clear_cpu_cap(X86_FEATURE_FPU); 1379 #else 1380 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1381 #endif 1382 1383 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1384 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1385 #endif 1386 1387 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1388 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1389 1390 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1391 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1392 1393 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1394 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1395 1396 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1397 if (arglen <= 0) 1398 return; 1399 1400 pr_info("Clearing CPUID bits:"); 1401 do { 1402 res = get_option(&argptr, &bit); 1403 if (res == 0 || res == 3) 1404 break; 1405 1406 /* If the argument was too long, the last bit may be cut off */ 1407 if (res == 1 && arglen >= sizeof(arg)) 1408 break; 1409 1410 if (bit >= 0 && bit < NCAPINTS * 32) { 1411 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1412 setup_clear_cpu_cap(bit); 1413 } 1414 } while (res == 2); 1415 pr_cont("\n"); 1416 } 1417 1418 /* 1419 * Do minimum CPU detection early. 1420 * Fields really needed: vendor, cpuid_level, family, model, mask, 1421 * cache alignment. 1422 * The others are not touched to avoid unwanted side effects. 1423 * 1424 * WARNING: this function is only called on the boot CPU. Don't add code 1425 * here that is supposed to run on all CPUs. 1426 */ 1427 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1428 { 1429 #ifdef CONFIG_X86_64 1430 c->x86_clflush_size = 64; 1431 c->x86_phys_bits = 36; 1432 c->x86_virt_bits = 48; 1433 #else 1434 c->x86_clflush_size = 32; 1435 c->x86_phys_bits = 32; 1436 c->x86_virt_bits = 32; 1437 #endif 1438 c->x86_cache_alignment = c->x86_clflush_size; 1439 1440 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1441 c->extended_cpuid_level = 0; 1442 1443 if (!have_cpuid_p()) 1444 identify_cpu_without_cpuid(c); 1445 1446 /* cyrix could have cpuid enabled via c_identify()*/ 1447 if (have_cpuid_p()) { 1448 cpu_detect(c); 1449 get_cpu_vendor(c); 1450 get_cpu_cap(c); 1451 get_cpu_address_sizes(c); 1452 setup_force_cpu_cap(X86_FEATURE_CPUID); 1453 cpu_parse_early_param(); 1454 1455 if (this_cpu->c_early_init) 1456 this_cpu->c_early_init(c); 1457 1458 c->cpu_index = 0; 1459 filter_cpuid_features(c, false); 1460 1461 if (this_cpu->c_bsp_init) 1462 this_cpu->c_bsp_init(c); 1463 } else { 1464 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1465 } 1466 1467 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1468 1469 cpu_set_bug_bits(c); 1470 1471 sld_setup(c); 1472 1473 fpu__init_system(c); 1474 1475 init_sigframe_size(); 1476 1477 #ifdef CONFIG_X86_32 1478 /* 1479 * Regardless of whether PCID is enumerated, the SDM says 1480 * that it can't be enabled in 32-bit mode. 1481 */ 1482 setup_clear_cpu_cap(X86_FEATURE_PCID); 1483 #endif 1484 1485 /* 1486 * Later in the boot process pgtable_l5_enabled() relies on 1487 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1488 * enabled by this point we need to clear the feature bit to avoid 1489 * false-positives at the later stage. 1490 * 1491 * pgtable_l5_enabled() can be false here for several reasons: 1492 * - 5-level paging is disabled compile-time; 1493 * - it's 32-bit kernel; 1494 * - machine doesn't support 5-level paging; 1495 * - user specified 'no5lvl' in kernel command line. 1496 */ 1497 if (!pgtable_l5_enabled()) 1498 setup_clear_cpu_cap(X86_FEATURE_LA57); 1499 1500 detect_nopl(); 1501 } 1502 1503 void __init early_cpu_init(void) 1504 { 1505 const struct cpu_dev *const *cdev; 1506 int count = 0; 1507 1508 #ifdef CONFIG_PROCESSOR_SELECT 1509 pr_info("KERNEL supported cpus:\n"); 1510 #endif 1511 1512 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1513 const struct cpu_dev *cpudev = *cdev; 1514 1515 if (count >= X86_VENDOR_NUM) 1516 break; 1517 cpu_devs[count] = cpudev; 1518 count++; 1519 1520 #ifdef CONFIG_PROCESSOR_SELECT 1521 { 1522 unsigned int j; 1523 1524 for (j = 0; j < 2; j++) { 1525 if (!cpudev->c_ident[j]) 1526 continue; 1527 pr_info(" %s %s\n", cpudev->c_vendor, 1528 cpudev->c_ident[j]); 1529 } 1530 } 1531 #endif 1532 } 1533 early_identify_cpu(&boot_cpu_data); 1534 } 1535 1536 static bool detect_null_seg_behavior(void) 1537 { 1538 /* 1539 * Empirically, writing zero to a segment selector on AMD does 1540 * not clear the base, whereas writing zero to a segment 1541 * selector on Intel does clear the base. Intel's behavior 1542 * allows slightly faster context switches in the common case 1543 * where GS is unused by the prev and next threads. 1544 * 1545 * Since neither vendor documents this anywhere that I can see, 1546 * detect it directly instead of hard-coding the choice by 1547 * vendor. 1548 * 1549 * I've designated AMD's behavior as the "bug" because it's 1550 * counterintuitive and less friendly. 1551 */ 1552 1553 unsigned long old_base, tmp; 1554 rdmsrl(MSR_FS_BASE, old_base); 1555 wrmsrl(MSR_FS_BASE, 1); 1556 loadsegment(fs, 0); 1557 rdmsrl(MSR_FS_BASE, tmp); 1558 wrmsrl(MSR_FS_BASE, old_base); 1559 return tmp == 0; 1560 } 1561 1562 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1563 { 1564 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1565 if (!IS_ENABLED(CONFIG_X86_64)) 1566 return; 1567 1568 /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ 1569 if (c->extended_cpuid_level >= 0x80000021 && 1570 cpuid_eax(0x80000021) & BIT(6)) 1571 return; 1572 1573 /* 1574 * CPUID bit above wasn't set. If this kernel is still running 1575 * as a HV guest, then the HV has decided not to advertize 1576 * that CPUID bit for whatever reason. For example, one 1577 * member of the migration pool might be vulnerable. Which 1578 * means, the bug is present: set the BUG flag and return. 1579 */ 1580 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1581 set_cpu_bug(c, X86_BUG_NULL_SEG); 1582 return; 1583 } 1584 1585 /* 1586 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1587 * 0x18 is the respective family for Hygon. 1588 */ 1589 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1590 detect_null_seg_behavior()) 1591 return; 1592 1593 /* All the remaining ones are affected */ 1594 set_cpu_bug(c, X86_BUG_NULL_SEG); 1595 } 1596 1597 static void generic_identify(struct cpuinfo_x86 *c) 1598 { 1599 c->extended_cpuid_level = 0; 1600 1601 if (!have_cpuid_p()) 1602 identify_cpu_without_cpuid(c); 1603 1604 /* cyrix could have cpuid enabled via c_identify()*/ 1605 if (!have_cpuid_p()) 1606 return; 1607 1608 cpu_detect(c); 1609 1610 get_cpu_vendor(c); 1611 1612 get_cpu_cap(c); 1613 1614 get_cpu_address_sizes(c); 1615 1616 if (c->cpuid_level >= 0x00000001) { 1617 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1618 #ifdef CONFIG_X86_32 1619 # ifdef CONFIG_SMP 1620 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1621 # else 1622 c->apicid = c->initial_apicid; 1623 # endif 1624 #endif 1625 c->phys_proc_id = c->initial_apicid; 1626 } 1627 1628 get_model_name(c); /* Default name */ 1629 1630 /* 1631 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1632 * systems that run Linux at CPL > 0 may or may not have the 1633 * issue, but, even if they have the issue, there's absolutely 1634 * nothing we can do about it because we can't use the real IRET 1635 * instruction. 1636 * 1637 * NB: For the time being, only 32-bit kernels support 1638 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1639 * whether to apply espfix using paravirt hooks. If any 1640 * non-paravirt system ever shows up that does *not* have the 1641 * ESPFIX issue, we can change this. 1642 */ 1643 #ifdef CONFIG_X86_32 1644 set_cpu_bug(c, X86_BUG_ESPFIX); 1645 #endif 1646 } 1647 1648 /* 1649 * Validate that ACPI/mptables have the same information about the 1650 * effective APIC id and update the package map. 1651 */ 1652 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1653 { 1654 #ifdef CONFIG_SMP 1655 unsigned int apicid, cpu = smp_processor_id(); 1656 1657 apicid = apic->cpu_present_to_apicid(cpu); 1658 1659 if (apicid != c->apicid) { 1660 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1661 cpu, apicid, c->initial_apicid); 1662 } 1663 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1664 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1665 #else 1666 c->logical_proc_id = 0; 1667 #endif 1668 } 1669 1670 /* 1671 * This does the hard work of actually picking apart the CPU stuff... 1672 */ 1673 static void identify_cpu(struct cpuinfo_x86 *c) 1674 { 1675 int i; 1676 1677 c->loops_per_jiffy = loops_per_jiffy; 1678 c->x86_cache_size = 0; 1679 c->x86_vendor = X86_VENDOR_UNKNOWN; 1680 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1681 c->x86_vendor_id[0] = '\0'; /* Unset */ 1682 c->x86_model_id[0] = '\0'; /* Unset */ 1683 c->x86_max_cores = 1; 1684 c->x86_coreid_bits = 0; 1685 c->cu_id = 0xff; 1686 #ifdef CONFIG_X86_64 1687 c->x86_clflush_size = 64; 1688 c->x86_phys_bits = 36; 1689 c->x86_virt_bits = 48; 1690 #else 1691 c->cpuid_level = -1; /* CPUID not detected */ 1692 c->x86_clflush_size = 32; 1693 c->x86_phys_bits = 32; 1694 c->x86_virt_bits = 32; 1695 #endif 1696 c->x86_cache_alignment = c->x86_clflush_size; 1697 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1698 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1699 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1700 #endif 1701 1702 generic_identify(c); 1703 1704 if (this_cpu->c_identify) 1705 this_cpu->c_identify(c); 1706 1707 /* Clear/Set all flags overridden by options, after probe */ 1708 apply_forced_caps(c); 1709 1710 #ifdef CONFIG_X86_64 1711 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1712 #endif 1713 1714 /* 1715 * Vendor-specific initialization. In this section we 1716 * canonicalize the feature flags, meaning if there are 1717 * features a certain CPU supports which CPUID doesn't 1718 * tell us, CPUID claiming incorrect flags, or other bugs, 1719 * we handle them here. 1720 * 1721 * At the end of this section, c->x86_capability better 1722 * indicate the features this CPU genuinely supports! 1723 */ 1724 if (this_cpu->c_init) 1725 this_cpu->c_init(c); 1726 1727 /* Disable the PN if appropriate */ 1728 squash_the_stupid_serial_number(c); 1729 1730 /* Set up SMEP/SMAP/UMIP */ 1731 setup_smep(c); 1732 setup_smap(c); 1733 setup_umip(c); 1734 1735 /* Enable FSGSBASE instructions if available. */ 1736 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1737 cr4_set_bits(X86_CR4_FSGSBASE); 1738 elf_hwcap2 |= HWCAP2_FSGSBASE; 1739 } 1740 1741 /* 1742 * The vendor-specific functions might have changed features. 1743 * Now we do "generic changes." 1744 */ 1745 1746 /* Filter out anything that depends on CPUID levels we don't have */ 1747 filter_cpuid_features(c, true); 1748 1749 /* If the model name is still unset, do table lookup. */ 1750 if (!c->x86_model_id[0]) { 1751 const char *p; 1752 p = table_lookup_model(c); 1753 if (p) 1754 strcpy(c->x86_model_id, p); 1755 else 1756 /* Last resort... */ 1757 sprintf(c->x86_model_id, "%02x/%02x", 1758 c->x86, c->x86_model); 1759 } 1760 1761 #ifdef CONFIG_X86_64 1762 detect_ht(c); 1763 #endif 1764 1765 x86_init_rdrand(c); 1766 setup_pku(c); 1767 setup_cet(c); 1768 1769 /* 1770 * Clear/Set all flags overridden by options, need do it 1771 * before following smp all cpus cap AND. 1772 */ 1773 apply_forced_caps(c); 1774 1775 /* 1776 * On SMP, boot_cpu_data holds the common feature set between 1777 * all CPUs; so make sure that we indicate which features are 1778 * common between the CPUs. The first time this routine gets 1779 * executed, c == &boot_cpu_data. 1780 */ 1781 if (c != &boot_cpu_data) { 1782 /* AND the already accumulated flags with these */ 1783 for (i = 0; i < NCAPINTS; i++) 1784 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1785 1786 /* OR, i.e. replicate the bug flags */ 1787 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1788 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1789 } 1790 1791 ppin_init(c); 1792 1793 /* Init Machine Check Exception if available. */ 1794 mcheck_cpu_init(c); 1795 1796 select_idle_routine(c); 1797 1798 #ifdef CONFIG_NUMA 1799 numa_add_cpu(smp_processor_id()); 1800 #endif 1801 } 1802 1803 /* 1804 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1805 * on 32-bit kernels: 1806 */ 1807 #ifdef CONFIG_X86_32 1808 void enable_sep_cpu(void) 1809 { 1810 struct tss_struct *tss; 1811 int cpu; 1812 1813 if (!boot_cpu_has(X86_FEATURE_SEP)) 1814 return; 1815 1816 cpu = get_cpu(); 1817 tss = &per_cpu(cpu_tss_rw, cpu); 1818 1819 /* 1820 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1821 * see the big comment in struct x86_hw_tss's definition. 1822 */ 1823 1824 tss->x86_tss.ss1 = __KERNEL_CS; 1825 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1826 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1827 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1828 1829 put_cpu(); 1830 } 1831 #endif 1832 1833 void __init identify_boot_cpu(void) 1834 { 1835 identify_cpu(&boot_cpu_data); 1836 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1837 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1838 #ifdef CONFIG_X86_32 1839 sysenter_setup(); 1840 enable_sep_cpu(); 1841 #endif 1842 cpu_detect_tlb(&boot_cpu_data); 1843 setup_cr_pinning(); 1844 1845 tsx_init(); 1846 } 1847 1848 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1849 { 1850 BUG_ON(c == &boot_cpu_data); 1851 identify_cpu(c); 1852 #ifdef CONFIG_X86_32 1853 enable_sep_cpu(); 1854 #endif 1855 mtrr_ap_init(); 1856 validate_apic_and_package_id(c); 1857 x86_spec_ctrl_setup_ap(); 1858 update_srbds_msr(); 1859 } 1860 1861 static __init int setup_noclflush(char *arg) 1862 { 1863 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1864 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1865 return 1; 1866 } 1867 __setup("noclflush", setup_noclflush); 1868 1869 void print_cpu_info(struct cpuinfo_x86 *c) 1870 { 1871 const char *vendor = NULL; 1872 1873 if (c->x86_vendor < X86_VENDOR_NUM) { 1874 vendor = this_cpu->c_vendor; 1875 } else { 1876 if (c->cpuid_level >= 0) 1877 vendor = c->x86_vendor_id; 1878 } 1879 1880 if (vendor && !strstr(c->x86_model_id, vendor)) 1881 pr_cont("%s ", vendor); 1882 1883 if (c->x86_model_id[0]) 1884 pr_cont("%s", c->x86_model_id); 1885 else 1886 pr_cont("%d86", c->x86); 1887 1888 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1889 1890 if (c->x86_stepping || c->cpuid_level >= 0) 1891 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1892 else 1893 pr_cont(")\n"); 1894 } 1895 1896 /* 1897 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 1898 * function prevents it from becoming an environment variable for init. 1899 */ 1900 static __init int setup_clearcpuid(char *arg) 1901 { 1902 return 1; 1903 } 1904 __setup("clearcpuid=", setup_clearcpuid); 1905 1906 #ifdef CONFIG_X86_64 1907 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1908 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1909 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1910 1911 /* 1912 * The following percpu variables are hot. Align current_task to 1913 * cacheline size such that they fall in the same cacheline. 1914 */ 1915 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1916 &init_task; 1917 EXPORT_PER_CPU_SYMBOL(current_task); 1918 1919 DEFINE_PER_CPU(void *, hardirq_stack_ptr); 1920 DEFINE_PER_CPU(bool, hardirq_stack_inuse); 1921 1922 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1923 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1924 1925 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 1926 1927 static void wrmsrl_cstar(unsigned long val) 1928 { 1929 /* 1930 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 1931 * is so far ignored by the CPU, but raises a #VE trap in a TDX 1932 * guest. Avoid the pointless write on all Intel CPUs. 1933 */ 1934 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 1935 wrmsrl(MSR_CSTAR, val); 1936 } 1937 1938 /* May not be marked __init: used by software suspend */ 1939 void syscall_init(void) 1940 { 1941 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1942 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1943 1944 #ifdef CONFIG_IA32_EMULATION 1945 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 1946 /* 1947 * This only works on Intel CPUs. 1948 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1949 * This does not cause SYSENTER to jump to the wrong location, because 1950 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1951 */ 1952 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1953 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1954 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1955 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1956 #else 1957 wrmsrl_cstar((unsigned long)ignore_sysret); 1958 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1959 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1960 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1961 #endif 1962 1963 /* 1964 * Flags to clear on syscall; clear as much as possible 1965 * to minimize user space-kernel interference. 1966 */ 1967 wrmsrl(MSR_SYSCALL_MASK, 1968 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 1969 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 1970 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 1971 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 1972 X86_EFLAGS_AC|X86_EFLAGS_ID); 1973 } 1974 1975 #else /* CONFIG_X86_64 */ 1976 1977 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1978 EXPORT_PER_CPU_SYMBOL(current_task); 1979 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1980 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1981 1982 /* 1983 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1984 * the top of the kernel stack. Use an extra percpu variable to track the 1985 * top of the kernel stack directly. 1986 */ 1987 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1988 (unsigned long)&init_thread_union + THREAD_SIZE; 1989 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1990 1991 #ifdef CONFIG_STACKPROTECTOR 1992 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 1993 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 1994 #endif 1995 1996 #endif /* CONFIG_X86_64 */ 1997 1998 /* 1999 * Clear all 6 debug registers: 2000 */ 2001 static void clear_all_debug_regs(void) 2002 { 2003 int i; 2004 2005 for (i = 0; i < 8; i++) { 2006 /* Ignore db4, db5 */ 2007 if ((i == 4) || (i == 5)) 2008 continue; 2009 2010 set_debugreg(0, i); 2011 } 2012 } 2013 2014 #ifdef CONFIG_KGDB 2015 /* 2016 * Restore debug regs if using kgdbwait and you have a kernel debugger 2017 * connection established. 2018 */ 2019 static void dbg_restore_debug_regs(void) 2020 { 2021 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2022 arch_kgdb_ops.correct_hw_break(); 2023 } 2024 #else /* ! CONFIG_KGDB */ 2025 #define dbg_restore_debug_regs() 2026 #endif /* ! CONFIG_KGDB */ 2027 2028 static void wait_for_master_cpu(int cpu) 2029 { 2030 #ifdef CONFIG_SMP 2031 /* 2032 * wait for ACK from master CPU before continuing 2033 * with AP initialization 2034 */ 2035 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 2036 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 2037 cpu_relax(); 2038 #endif 2039 } 2040 2041 #ifdef CONFIG_X86_64 2042 static inline void setup_getcpu(int cpu) 2043 { 2044 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2045 struct desc_struct d = { }; 2046 2047 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2048 wrmsr(MSR_TSC_AUX, cpudata, 0); 2049 2050 /* Store CPU and node number in limit. */ 2051 d.limit0 = cpudata; 2052 d.limit1 = cpudata >> 16; 2053 2054 d.type = 5; /* RO data, expand down, accessed */ 2055 d.dpl = 3; /* Visible to user code */ 2056 d.s = 1; /* Not a system segment */ 2057 d.p = 1; /* Present */ 2058 d.d = 1; /* 32-bit */ 2059 2060 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2061 } 2062 2063 static inline void ucode_cpu_init(int cpu) 2064 { 2065 if (cpu) 2066 load_ucode_ap(); 2067 } 2068 2069 static inline void tss_setup_ist(struct tss_struct *tss) 2070 { 2071 /* Set up the per-CPU TSS IST stacks */ 2072 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2073 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2074 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2075 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2076 /* Only mapped when SEV-ES is active */ 2077 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2078 } 2079 2080 #else /* CONFIG_X86_64 */ 2081 2082 static inline void setup_getcpu(int cpu) { } 2083 2084 static inline void ucode_cpu_init(int cpu) 2085 { 2086 show_ucode_info_early(); 2087 } 2088 2089 static inline void tss_setup_ist(struct tss_struct *tss) { } 2090 2091 #endif /* !CONFIG_X86_64 */ 2092 2093 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2094 { 2095 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2096 2097 #ifdef CONFIG_X86_IOPL_IOPERM 2098 tss->io_bitmap.prev_max = 0; 2099 tss->io_bitmap.prev_sequence = 0; 2100 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2101 /* 2102 * Invalidate the extra array entry past the end of the all 2103 * permission bitmap as required by the hardware. 2104 */ 2105 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2106 #endif 2107 } 2108 2109 /* 2110 * Setup everything needed to handle exceptions from the IDT, including the IST 2111 * exceptions which use paranoid_entry(). 2112 */ 2113 void cpu_init_exception_handling(void) 2114 { 2115 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2116 int cpu = raw_smp_processor_id(); 2117 2118 /* paranoid_entry() gets the CPU number from the GDT */ 2119 setup_getcpu(cpu); 2120 2121 /* IST vectors need TSS to be set up. */ 2122 tss_setup_ist(tss); 2123 tss_setup_io_bitmap(tss); 2124 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2125 2126 load_TR_desc(); 2127 2128 /* GHCB needs to be setup to handle #VC. */ 2129 setup_ghcb(); 2130 2131 /* Finally load the IDT */ 2132 load_current_idt(); 2133 } 2134 2135 /* 2136 * cpu_init() initializes state that is per-CPU. Some data is already 2137 * initialized (naturally) in the bootstrap process, such as the GDT. We 2138 * reload it nevertheless, this function acts as a 'CPU state barrier', 2139 * nothing should get across. 2140 */ 2141 void cpu_init(void) 2142 { 2143 struct task_struct *cur = current; 2144 int cpu = raw_smp_processor_id(); 2145 2146 wait_for_master_cpu(cpu); 2147 2148 ucode_cpu_init(cpu); 2149 2150 #ifdef CONFIG_NUMA 2151 if (this_cpu_read(numa_node) == 0 && 2152 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2153 set_numa_node(early_cpu_to_node(cpu)); 2154 #endif 2155 pr_debug("Initializing CPU#%d\n", cpu); 2156 2157 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2158 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2159 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2160 2161 /* 2162 * Initialize the per-CPU GDT with the boot GDT, 2163 * and set up the GDT descriptor: 2164 */ 2165 switch_to_new_gdt(cpu); 2166 2167 if (IS_ENABLED(CONFIG_X86_64)) { 2168 loadsegment(fs, 0); 2169 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2170 syscall_init(); 2171 2172 wrmsrl(MSR_FS_BASE, 0); 2173 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2174 barrier(); 2175 2176 x2apic_setup(); 2177 } 2178 2179 mmgrab(&init_mm); 2180 cur->active_mm = &init_mm; 2181 BUG_ON(cur->mm); 2182 initialize_tlbstate_and_flush(); 2183 enter_lazy_tlb(&init_mm, cur); 2184 2185 /* 2186 * sp0 points to the entry trampoline stack regardless of what task 2187 * is running. 2188 */ 2189 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2190 2191 load_mm_ldt(&init_mm); 2192 2193 clear_all_debug_regs(); 2194 dbg_restore_debug_regs(); 2195 2196 doublefault_init_cpu_tss(); 2197 2198 fpu__init_cpu(); 2199 2200 if (is_uv_system()) 2201 uv_cpu_init(); 2202 2203 load_fixmap_gdt(cpu); 2204 } 2205 2206 #ifdef CONFIG_SMP 2207 void cpu_init_secondary(void) 2208 { 2209 /* 2210 * Relies on the BP having set-up the IDT tables, which are loaded 2211 * on this CPU in cpu_init_exception_handling(). 2212 */ 2213 cpu_init_exception_handling(); 2214 cpu_init(); 2215 } 2216 #endif 2217 2218 /* 2219 * The microcode loader calls this upon late microcode load to recheck features, 2220 * only when microcode has been updated. Caller holds microcode_mutex and CPU 2221 * hotplug lock. 2222 */ 2223 void microcode_check(void) 2224 { 2225 struct cpuinfo_x86 info; 2226 2227 perf_check_microcode(); 2228 2229 /* Reload CPUID max function as it might've changed. */ 2230 info.cpuid_level = cpuid_eax(0); 2231 2232 /* 2233 * Copy all capability leafs to pick up the synthetic ones so that 2234 * memcmp() below doesn't fail on that. The ones coming from CPUID will 2235 * get overwritten in get_cpu_cap(). 2236 */ 2237 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 2238 2239 get_cpu_cap(&info); 2240 2241 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 2242 return; 2243 2244 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2245 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2246 } 2247 2248 /* 2249 * Invoked from core CPU hotplug code after hotplug operations 2250 */ 2251 void arch_smt_update(void) 2252 { 2253 /* Handle the speculative execution misfeatures */ 2254 cpu_bugs_smt_update(); 2255 /* Check whether IPI broadcasting can be enabled */ 2256 apic_smt_update(); 2257 } 2258