1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kprobes.h> 12 #include <linux/kgdb.h> 13 #include <linux/smp.h> 14 #include <linux/io.h> 15 16 #include <asm/stackprotector.h> 17 #include <asm/perf_event.h> 18 #include <asm/mmu_context.h> 19 #include <asm/archrandom.h> 20 #include <asm/hypervisor.h> 21 #include <asm/processor.h> 22 #include <asm/debugreg.h> 23 #include <asm/sections.h> 24 #include <asm/vsyscall.h> 25 #include <linux/topology.h> 26 #include <linux/cpumask.h> 27 #include <asm/pgtable.h> 28 #include <linux/atomic.h> 29 #include <asm/proto.h> 30 #include <asm/setup.h> 31 #include <asm/apic.h> 32 #include <asm/desc.h> 33 #include <asm/i387.h> 34 #include <asm/fpu-internal.h> 35 #include <asm/mtrr.h> 36 #include <linux/numa.h> 37 #include <asm/asm.h> 38 #include <asm/cpu.h> 39 #include <asm/mce.h> 40 #include <asm/msr.h> 41 #include <asm/pat.h> 42 #include <asm/microcode.h> 43 #include <asm/microcode_intel.h> 44 45 #ifdef CONFIG_X86_LOCAL_APIC 46 #include <asm/uv/uv.h> 47 #endif 48 49 #include "cpu.h" 50 51 /* all of these masks are initialized in setup_cpu_local_masks() */ 52 cpumask_var_t cpu_initialized_mask; 53 cpumask_var_t cpu_callout_mask; 54 cpumask_var_t cpu_callin_mask; 55 56 /* representing cpus for which sibling maps can be computed */ 57 cpumask_var_t cpu_sibling_setup_mask; 58 59 /* correctly size the local cpu masks */ 60 void __init setup_cpu_local_masks(void) 61 { 62 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 63 alloc_bootmem_cpumask_var(&cpu_callin_mask); 64 alloc_bootmem_cpumask_var(&cpu_callout_mask); 65 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 66 } 67 68 static void default_init(struct cpuinfo_x86 *c) 69 { 70 #ifdef CONFIG_X86_64 71 cpu_detect_cache_sizes(c); 72 #else 73 /* Not much we can do here... */ 74 /* Check if at least it has cpuid */ 75 if (c->cpuid_level == -1) { 76 /* No cpuid. It must be an ancient CPU */ 77 if (c->x86 == 4) 78 strcpy(c->x86_model_id, "486"); 79 else if (c->x86 == 3) 80 strcpy(c->x86_model_id, "386"); 81 } 82 #endif 83 } 84 85 static const struct cpu_dev default_cpu = { 86 .c_init = default_init, 87 .c_vendor = "Unknown", 88 .c_x86_vendor = X86_VENDOR_UNKNOWN, 89 }; 90 91 static const struct cpu_dev *this_cpu = &default_cpu; 92 93 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 94 #ifdef CONFIG_X86_64 95 /* 96 * We need valid kernel segments for data and code in long mode too 97 * IRET will check the segment types kkeil 2000/10/28 98 * Also sysret mandates a special GDT layout 99 * 100 * TLS descriptors are currently at a different place compared to i386. 101 * Hopefully nobody expects them at a fixed place (Wine?) 102 */ 103 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 104 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 105 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 106 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 107 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 109 #else 110 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 111 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 112 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 113 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 114 /* 115 * Segments used for calling PnP BIOS have byte granularity. 116 * They code segments and data segments have fixed 64k limits, 117 * the transfer segment sizes are set at run time. 118 */ 119 /* 32-bit code */ 120 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 121 /* 16-bit code */ 122 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 123 /* 16-bit data */ 124 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 125 /* 16-bit data */ 126 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 127 /* 16-bit data */ 128 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 129 /* 130 * The APM segments have byte granularity and their bases 131 * are set at run time. All have 64k limits. 132 */ 133 /* 32-bit code */ 134 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 135 /* 16-bit code */ 136 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 137 /* data */ 138 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 139 140 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 141 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 142 GDT_STACK_CANARY_INIT 143 #endif 144 } }; 145 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 146 147 static int __init x86_xsave_setup(char *s) 148 { 149 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 150 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 151 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 152 setup_clear_cpu_cap(X86_FEATURE_AVX); 153 setup_clear_cpu_cap(X86_FEATURE_AVX2); 154 return 1; 155 } 156 __setup("noxsave", x86_xsave_setup); 157 158 static int __init x86_xsaveopt_setup(char *s) 159 { 160 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 161 return 1; 162 } 163 __setup("noxsaveopt", x86_xsaveopt_setup); 164 165 static int __init x86_xsaves_setup(char *s) 166 { 167 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 168 return 1; 169 } 170 __setup("noxsaves", x86_xsaves_setup); 171 172 #ifdef CONFIG_X86_32 173 static int cachesize_override = -1; 174 static int disable_x86_serial_nr = 1; 175 176 static int __init cachesize_setup(char *str) 177 { 178 get_option(&str, &cachesize_override); 179 return 1; 180 } 181 __setup("cachesize=", cachesize_setup); 182 183 static int __init x86_fxsr_setup(char *s) 184 { 185 setup_clear_cpu_cap(X86_FEATURE_FXSR); 186 setup_clear_cpu_cap(X86_FEATURE_XMM); 187 return 1; 188 } 189 __setup("nofxsr", x86_fxsr_setup); 190 191 static int __init x86_sep_setup(char *s) 192 { 193 setup_clear_cpu_cap(X86_FEATURE_SEP); 194 return 1; 195 } 196 __setup("nosep", x86_sep_setup); 197 198 /* Standard macro to see if a specific flag is changeable */ 199 static inline int flag_is_changeable_p(u32 flag) 200 { 201 u32 f1, f2; 202 203 /* 204 * Cyrix and IDT cpus allow disabling of CPUID 205 * so the code below may return different results 206 * when it is executed before and after enabling 207 * the CPUID. Add "volatile" to not allow gcc to 208 * optimize the subsequent calls to this function. 209 */ 210 asm volatile ("pushfl \n\t" 211 "pushfl \n\t" 212 "popl %0 \n\t" 213 "movl %0, %1 \n\t" 214 "xorl %2, %0 \n\t" 215 "pushl %0 \n\t" 216 "popfl \n\t" 217 "pushfl \n\t" 218 "popl %0 \n\t" 219 "popfl \n\t" 220 221 : "=&r" (f1), "=&r" (f2) 222 : "ir" (flag)); 223 224 return ((f1^f2) & flag) != 0; 225 } 226 227 /* Probe for the CPUID instruction */ 228 int have_cpuid_p(void) 229 { 230 return flag_is_changeable_p(X86_EFLAGS_ID); 231 } 232 233 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 234 { 235 unsigned long lo, hi; 236 237 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 238 return; 239 240 /* Disable processor serial number: */ 241 242 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 243 lo |= 0x200000; 244 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 245 246 printk(KERN_NOTICE "CPU serial number disabled.\n"); 247 clear_cpu_cap(c, X86_FEATURE_PN); 248 249 /* Disabling the serial number may affect the cpuid level */ 250 c->cpuid_level = cpuid_eax(0); 251 } 252 253 static int __init x86_serial_nr_setup(char *s) 254 { 255 disable_x86_serial_nr = 0; 256 return 1; 257 } 258 __setup("serialnumber", x86_serial_nr_setup); 259 #else 260 static inline int flag_is_changeable_p(u32 flag) 261 { 262 return 1; 263 } 264 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 265 { 266 } 267 #endif 268 269 static __init int setup_disable_smep(char *arg) 270 { 271 setup_clear_cpu_cap(X86_FEATURE_SMEP); 272 return 1; 273 } 274 __setup("nosmep", setup_disable_smep); 275 276 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 277 { 278 if (cpu_has(c, X86_FEATURE_SMEP)) 279 set_in_cr4(X86_CR4_SMEP); 280 } 281 282 static __init int setup_disable_smap(char *arg) 283 { 284 setup_clear_cpu_cap(X86_FEATURE_SMAP); 285 return 1; 286 } 287 __setup("nosmap", setup_disable_smap); 288 289 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 290 { 291 unsigned long eflags; 292 293 /* This should have been cleared long ago */ 294 raw_local_save_flags(eflags); 295 BUG_ON(eflags & X86_EFLAGS_AC); 296 297 if (cpu_has(c, X86_FEATURE_SMAP)) { 298 #ifdef CONFIG_X86_SMAP 299 set_in_cr4(X86_CR4_SMAP); 300 #else 301 clear_in_cr4(X86_CR4_SMAP); 302 #endif 303 } 304 } 305 306 /* 307 * Some CPU features depend on higher CPUID levels, which may not always 308 * be available due to CPUID level capping or broken virtualization 309 * software. Add those features to this table to auto-disable them. 310 */ 311 struct cpuid_dependent_feature { 312 u32 feature; 313 u32 level; 314 }; 315 316 static const struct cpuid_dependent_feature 317 cpuid_dependent_features[] = { 318 { X86_FEATURE_MWAIT, 0x00000005 }, 319 { X86_FEATURE_DCA, 0x00000009 }, 320 { X86_FEATURE_XSAVE, 0x0000000d }, 321 { 0, 0 } 322 }; 323 324 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 325 { 326 const struct cpuid_dependent_feature *df; 327 328 for (df = cpuid_dependent_features; df->feature; df++) { 329 330 if (!cpu_has(c, df->feature)) 331 continue; 332 /* 333 * Note: cpuid_level is set to -1 if unavailable, but 334 * extended_extended_level is set to 0 if unavailable 335 * and the legitimate extended levels are all negative 336 * when signed; hence the weird messing around with 337 * signs here... 338 */ 339 if (!((s32)df->level < 0 ? 340 (u32)df->level > (u32)c->extended_cpuid_level : 341 (s32)df->level > (s32)c->cpuid_level)) 342 continue; 343 344 clear_cpu_cap(c, df->feature); 345 if (!warn) 346 continue; 347 348 printk(KERN_WARNING 349 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 350 x86_cap_flags[df->feature], df->level); 351 } 352 } 353 354 /* 355 * Naming convention should be: <Name> [(<Codename>)] 356 * This table only is used unless init_<vendor>() below doesn't set it; 357 * in particular, if CPUID levels 0x80000002..4 are supported, this 358 * isn't used 359 */ 360 361 /* Look up CPU names by table lookup. */ 362 static const char *table_lookup_model(struct cpuinfo_x86 *c) 363 { 364 #ifdef CONFIG_X86_32 365 const struct legacy_cpu_model_info *info; 366 367 if (c->x86_model >= 16) 368 return NULL; /* Range check */ 369 370 if (!this_cpu) 371 return NULL; 372 373 info = this_cpu->legacy_models; 374 375 while (info->family) { 376 if (info->family == c->x86) 377 return info->model_names[c->x86_model]; 378 info++; 379 } 380 #endif 381 return NULL; /* Not found */ 382 } 383 384 __u32 cpu_caps_cleared[NCAPINTS]; 385 __u32 cpu_caps_set[NCAPINTS]; 386 387 void load_percpu_segment(int cpu) 388 { 389 #ifdef CONFIG_X86_32 390 loadsegment(fs, __KERNEL_PERCPU); 391 #else 392 loadsegment(gs, 0); 393 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 394 #endif 395 load_stack_canary_segment(); 396 } 397 398 /* 399 * Current gdt points %fs at the "master" per-cpu area: after this, 400 * it's on the real one. 401 */ 402 void switch_to_new_gdt(int cpu) 403 { 404 struct desc_ptr gdt_descr; 405 406 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 407 gdt_descr.size = GDT_SIZE - 1; 408 load_gdt(&gdt_descr); 409 /* Reload the per-cpu base */ 410 411 load_percpu_segment(cpu); 412 } 413 414 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 415 416 static void get_model_name(struct cpuinfo_x86 *c) 417 { 418 unsigned int *v; 419 char *p, *q; 420 421 if (c->extended_cpuid_level < 0x80000004) 422 return; 423 424 v = (unsigned int *)c->x86_model_id; 425 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 426 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 427 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 428 c->x86_model_id[48] = 0; 429 430 /* 431 * Intel chips right-justify this string for some dumb reason; 432 * undo that brain damage: 433 */ 434 p = q = &c->x86_model_id[0]; 435 while (*p == ' ') 436 p++; 437 if (p != q) { 438 while (*p) 439 *q++ = *p++; 440 while (q <= &c->x86_model_id[48]) 441 *q++ = '\0'; /* Zero-pad the rest */ 442 } 443 } 444 445 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 446 { 447 unsigned int n, dummy, ebx, ecx, edx, l2size; 448 449 n = c->extended_cpuid_level; 450 451 if (n >= 0x80000005) { 452 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 453 c->x86_cache_size = (ecx>>24) + (edx>>24); 454 #ifdef CONFIG_X86_64 455 /* On K8 L1 TLB is inclusive, so don't count it */ 456 c->x86_tlbsize = 0; 457 #endif 458 } 459 460 if (n < 0x80000006) /* Some chips just has a large L1. */ 461 return; 462 463 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 464 l2size = ecx >> 16; 465 466 #ifdef CONFIG_X86_64 467 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 468 #else 469 /* do processor-specific cache resizing */ 470 if (this_cpu->legacy_cache_size) 471 l2size = this_cpu->legacy_cache_size(c, l2size); 472 473 /* Allow user to override all this if necessary. */ 474 if (cachesize_override != -1) 475 l2size = cachesize_override; 476 477 if (l2size == 0) 478 return; /* Again, no L2 cache is possible */ 479 #endif 480 481 c->x86_cache_size = l2size; 482 } 483 484 u16 __read_mostly tlb_lli_4k[NR_INFO]; 485 u16 __read_mostly tlb_lli_2m[NR_INFO]; 486 u16 __read_mostly tlb_lli_4m[NR_INFO]; 487 u16 __read_mostly tlb_lld_4k[NR_INFO]; 488 u16 __read_mostly tlb_lld_2m[NR_INFO]; 489 u16 __read_mostly tlb_lld_4m[NR_INFO]; 490 u16 __read_mostly tlb_lld_1g[NR_INFO]; 491 492 void cpu_detect_tlb(struct cpuinfo_x86 *c) 493 { 494 if (this_cpu->c_detect_tlb) 495 this_cpu->c_detect_tlb(c); 496 497 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" 498 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 499 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 500 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], 501 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], 502 tlb_lld_1g[ENTRIES]); 503 } 504 505 void detect_ht(struct cpuinfo_x86 *c) 506 { 507 #ifdef CONFIG_X86_HT 508 u32 eax, ebx, ecx, edx; 509 int index_msb, core_bits; 510 static bool printed; 511 512 if (!cpu_has(c, X86_FEATURE_HT)) 513 return; 514 515 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 516 goto out; 517 518 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 519 return; 520 521 cpuid(1, &eax, &ebx, &ecx, &edx); 522 523 smp_num_siblings = (ebx & 0xff0000) >> 16; 524 525 if (smp_num_siblings == 1) { 526 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 527 goto out; 528 } 529 530 if (smp_num_siblings <= 1) 531 goto out; 532 533 index_msb = get_count_order(smp_num_siblings); 534 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 535 536 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 537 538 index_msb = get_count_order(smp_num_siblings); 539 540 core_bits = get_count_order(c->x86_max_cores); 541 542 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 543 ((1 << core_bits) - 1); 544 545 out: 546 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 547 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 548 c->phys_proc_id); 549 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 550 c->cpu_core_id); 551 printed = 1; 552 } 553 #endif 554 } 555 556 static void get_cpu_vendor(struct cpuinfo_x86 *c) 557 { 558 char *v = c->x86_vendor_id; 559 int i; 560 561 for (i = 0; i < X86_VENDOR_NUM; i++) { 562 if (!cpu_devs[i]) 563 break; 564 565 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 566 (cpu_devs[i]->c_ident[1] && 567 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 568 569 this_cpu = cpu_devs[i]; 570 c->x86_vendor = this_cpu->c_x86_vendor; 571 return; 572 } 573 } 574 575 printk_once(KERN_ERR 576 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 577 "CPU: Your system may be unstable.\n", v); 578 579 c->x86_vendor = X86_VENDOR_UNKNOWN; 580 this_cpu = &default_cpu; 581 } 582 583 void cpu_detect(struct cpuinfo_x86 *c) 584 { 585 /* Get vendor name */ 586 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 587 (unsigned int *)&c->x86_vendor_id[0], 588 (unsigned int *)&c->x86_vendor_id[8], 589 (unsigned int *)&c->x86_vendor_id[4]); 590 591 c->x86 = 4; 592 /* Intel-defined flags: level 0x00000001 */ 593 if (c->cpuid_level >= 0x00000001) { 594 u32 junk, tfms, cap0, misc; 595 596 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 597 c->x86 = (tfms >> 8) & 0xf; 598 c->x86_model = (tfms >> 4) & 0xf; 599 c->x86_mask = tfms & 0xf; 600 601 if (c->x86 == 0xf) 602 c->x86 += (tfms >> 20) & 0xff; 603 if (c->x86 >= 0x6) 604 c->x86_model += ((tfms >> 16) & 0xf) << 4; 605 606 if (cap0 & (1<<19)) { 607 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 608 c->x86_cache_alignment = c->x86_clflush_size; 609 } 610 } 611 } 612 613 void get_cpu_cap(struct cpuinfo_x86 *c) 614 { 615 u32 tfms, xlvl; 616 u32 ebx; 617 618 /* Intel-defined flags: level 0x00000001 */ 619 if (c->cpuid_level >= 0x00000001) { 620 u32 capability, excap; 621 622 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 623 c->x86_capability[0] = capability; 624 c->x86_capability[4] = excap; 625 } 626 627 /* Additional Intel-defined flags: level 0x00000007 */ 628 if (c->cpuid_level >= 0x00000007) { 629 u32 eax, ebx, ecx, edx; 630 631 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 632 633 c->x86_capability[9] = ebx; 634 } 635 636 /* Extended state features: level 0x0000000d */ 637 if (c->cpuid_level >= 0x0000000d) { 638 u32 eax, ebx, ecx, edx; 639 640 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 641 642 c->x86_capability[10] = eax; 643 } 644 645 /* AMD-defined flags: level 0x80000001 */ 646 xlvl = cpuid_eax(0x80000000); 647 c->extended_cpuid_level = xlvl; 648 649 if ((xlvl & 0xffff0000) == 0x80000000) { 650 if (xlvl >= 0x80000001) { 651 c->x86_capability[1] = cpuid_edx(0x80000001); 652 c->x86_capability[6] = cpuid_ecx(0x80000001); 653 } 654 } 655 656 if (c->extended_cpuid_level >= 0x80000008) { 657 u32 eax = cpuid_eax(0x80000008); 658 659 c->x86_virt_bits = (eax >> 8) & 0xff; 660 c->x86_phys_bits = eax & 0xff; 661 } 662 #ifdef CONFIG_X86_32 663 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 664 c->x86_phys_bits = 36; 665 #endif 666 667 if (c->extended_cpuid_level >= 0x80000007) 668 c->x86_power = cpuid_edx(0x80000007); 669 670 init_scattered_cpuid_features(c); 671 } 672 673 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 674 { 675 #ifdef CONFIG_X86_32 676 int i; 677 678 /* 679 * First of all, decide if this is a 486 or higher 680 * It's a 486 if we can modify the AC flag 681 */ 682 if (flag_is_changeable_p(X86_EFLAGS_AC)) 683 c->x86 = 4; 684 else 685 c->x86 = 3; 686 687 for (i = 0; i < X86_VENDOR_NUM; i++) 688 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 689 c->x86_vendor_id[0] = 0; 690 cpu_devs[i]->c_identify(c); 691 if (c->x86_vendor_id[0]) { 692 get_cpu_vendor(c); 693 break; 694 } 695 } 696 #endif 697 } 698 699 /* 700 * Do minimum CPU detection early. 701 * Fields really needed: vendor, cpuid_level, family, model, mask, 702 * cache alignment. 703 * The others are not touched to avoid unwanted side effects. 704 * 705 * WARNING: this function is only called on the BP. Don't add code here 706 * that is supposed to run on all CPUs. 707 */ 708 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 709 { 710 #ifdef CONFIG_X86_64 711 c->x86_clflush_size = 64; 712 c->x86_phys_bits = 36; 713 c->x86_virt_bits = 48; 714 #else 715 c->x86_clflush_size = 32; 716 c->x86_phys_bits = 32; 717 c->x86_virt_bits = 32; 718 #endif 719 c->x86_cache_alignment = c->x86_clflush_size; 720 721 memset(&c->x86_capability, 0, sizeof c->x86_capability); 722 c->extended_cpuid_level = 0; 723 724 if (!have_cpuid_p()) 725 identify_cpu_without_cpuid(c); 726 727 /* cyrix could have cpuid enabled via c_identify()*/ 728 if (!have_cpuid_p()) 729 return; 730 731 cpu_detect(c); 732 get_cpu_vendor(c); 733 get_cpu_cap(c); 734 fpu_detect(c); 735 736 if (this_cpu->c_early_init) 737 this_cpu->c_early_init(c); 738 739 c->cpu_index = 0; 740 filter_cpuid_features(c, false); 741 742 if (this_cpu->c_bsp_init) 743 this_cpu->c_bsp_init(c); 744 745 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 746 } 747 748 void __init early_cpu_init(void) 749 { 750 const struct cpu_dev *const *cdev; 751 int count = 0; 752 753 #ifdef CONFIG_PROCESSOR_SELECT 754 printk(KERN_INFO "KERNEL supported cpus:\n"); 755 #endif 756 757 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 758 const struct cpu_dev *cpudev = *cdev; 759 760 if (count >= X86_VENDOR_NUM) 761 break; 762 cpu_devs[count] = cpudev; 763 count++; 764 765 #ifdef CONFIG_PROCESSOR_SELECT 766 { 767 unsigned int j; 768 769 for (j = 0; j < 2; j++) { 770 if (!cpudev->c_ident[j]) 771 continue; 772 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 773 cpudev->c_ident[j]); 774 } 775 } 776 #endif 777 } 778 early_identify_cpu(&boot_cpu_data); 779 } 780 781 /* 782 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 783 * unfortunately, that's not true in practice because of early VIA 784 * chips and (more importantly) broken virtualizers that are not easy 785 * to detect. In the latter case it doesn't even *fail* reliably, so 786 * probing for it doesn't even work. Disable it completely on 32-bit 787 * unless we can find a reliable way to detect all the broken cases. 788 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 789 */ 790 static void detect_nopl(struct cpuinfo_x86 *c) 791 { 792 #ifdef CONFIG_X86_32 793 clear_cpu_cap(c, X86_FEATURE_NOPL); 794 #else 795 set_cpu_cap(c, X86_FEATURE_NOPL); 796 #endif 797 } 798 799 static void generic_identify(struct cpuinfo_x86 *c) 800 { 801 c->extended_cpuid_level = 0; 802 803 if (!have_cpuid_p()) 804 identify_cpu_without_cpuid(c); 805 806 /* cyrix could have cpuid enabled via c_identify()*/ 807 if (!have_cpuid_p()) 808 return; 809 810 cpu_detect(c); 811 812 get_cpu_vendor(c); 813 814 get_cpu_cap(c); 815 816 if (c->cpuid_level >= 0x00000001) { 817 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 818 #ifdef CONFIG_X86_32 819 # ifdef CONFIG_X86_HT 820 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 821 # else 822 c->apicid = c->initial_apicid; 823 # endif 824 #endif 825 c->phys_proc_id = c->initial_apicid; 826 } 827 828 get_model_name(c); /* Default name */ 829 830 detect_nopl(c); 831 } 832 833 /* 834 * This does the hard work of actually picking apart the CPU stuff... 835 */ 836 static void identify_cpu(struct cpuinfo_x86 *c) 837 { 838 int i; 839 840 c->loops_per_jiffy = loops_per_jiffy; 841 c->x86_cache_size = -1; 842 c->x86_vendor = X86_VENDOR_UNKNOWN; 843 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 844 c->x86_vendor_id[0] = '\0'; /* Unset */ 845 c->x86_model_id[0] = '\0'; /* Unset */ 846 c->x86_max_cores = 1; 847 c->x86_coreid_bits = 0; 848 #ifdef CONFIG_X86_64 849 c->x86_clflush_size = 64; 850 c->x86_phys_bits = 36; 851 c->x86_virt_bits = 48; 852 #else 853 c->cpuid_level = -1; /* CPUID not detected */ 854 c->x86_clflush_size = 32; 855 c->x86_phys_bits = 32; 856 c->x86_virt_bits = 32; 857 #endif 858 c->x86_cache_alignment = c->x86_clflush_size; 859 memset(&c->x86_capability, 0, sizeof c->x86_capability); 860 861 generic_identify(c); 862 863 if (this_cpu->c_identify) 864 this_cpu->c_identify(c); 865 866 /* Clear/Set all flags overriden by options, after probe */ 867 for (i = 0; i < NCAPINTS; i++) { 868 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 869 c->x86_capability[i] |= cpu_caps_set[i]; 870 } 871 872 #ifdef CONFIG_X86_64 873 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 874 #endif 875 876 /* 877 * Vendor-specific initialization. In this section we 878 * canonicalize the feature flags, meaning if there are 879 * features a certain CPU supports which CPUID doesn't 880 * tell us, CPUID claiming incorrect flags, or other bugs, 881 * we handle them here. 882 * 883 * At the end of this section, c->x86_capability better 884 * indicate the features this CPU genuinely supports! 885 */ 886 if (this_cpu->c_init) 887 this_cpu->c_init(c); 888 889 /* Disable the PN if appropriate */ 890 squash_the_stupid_serial_number(c); 891 892 /* Set up SMEP/SMAP */ 893 setup_smep(c); 894 setup_smap(c); 895 896 /* 897 * The vendor-specific functions might have changed features. 898 * Now we do "generic changes." 899 */ 900 901 /* Filter out anything that depends on CPUID levels we don't have */ 902 filter_cpuid_features(c, true); 903 904 /* If the model name is still unset, do table lookup. */ 905 if (!c->x86_model_id[0]) { 906 const char *p; 907 p = table_lookup_model(c); 908 if (p) 909 strcpy(c->x86_model_id, p); 910 else 911 /* Last resort... */ 912 sprintf(c->x86_model_id, "%02x/%02x", 913 c->x86, c->x86_model); 914 } 915 916 #ifdef CONFIG_X86_64 917 detect_ht(c); 918 #endif 919 920 init_hypervisor(c); 921 x86_init_rdrand(c); 922 923 /* 924 * Clear/Set all flags overriden by options, need do it 925 * before following smp all cpus cap AND. 926 */ 927 for (i = 0; i < NCAPINTS; i++) { 928 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 929 c->x86_capability[i] |= cpu_caps_set[i]; 930 } 931 932 /* 933 * On SMP, boot_cpu_data holds the common feature set between 934 * all CPUs; so make sure that we indicate which features are 935 * common between the CPUs. The first time this routine gets 936 * executed, c == &boot_cpu_data. 937 */ 938 if (c != &boot_cpu_data) { 939 /* AND the already accumulated flags with these */ 940 for (i = 0; i < NCAPINTS; i++) 941 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 942 943 /* OR, i.e. replicate the bug flags */ 944 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 945 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 946 } 947 948 /* Init Machine Check Exception if available. */ 949 mcheck_cpu_init(c); 950 951 select_idle_routine(c); 952 953 #ifdef CONFIG_NUMA 954 numa_add_cpu(smp_processor_id()); 955 #endif 956 } 957 958 #ifdef CONFIG_X86_64 959 static void vgetcpu_set_mode(void) 960 { 961 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 962 vgetcpu_mode = VGETCPU_RDTSCP; 963 else 964 vgetcpu_mode = VGETCPU_LSL; 965 } 966 967 /* May not be __init: called during resume */ 968 static void syscall32_cpu_init(void) 969 { 970 /* Load these always in case some future AMD CPU supports 971 SYSENTER from compat mode too. */ 972 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 973 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 974 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); 975 976 wrmsrl(MSR_CSTAR, ia32_cstar_target); 977 } 978 #endif 979 980 #ifdef CONFIG_X86_32 981 void enable_sep_cpu(void) 982 { 983 int cpu = get_cpu(); 984 struct tss_struct *tss = &per_cpu(init_tss, cpu); 985 986 if (!boot_cpu_has(X86_FEATURE_SEP)) { 987 put_cpu(); 988 return; 989 } 990 991 tss->x86_tss.ss1 = __KERNEL_CS; 992 tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss; 993 wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); 994 wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0); 995 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0); 996 put_cpu(); 997 } 998 #endif 999 1000 void __init identify_boot_cpu(void) 1001 { 1002 identify_cpu(&boot_cpu_data); 1003 init_amd_e400_c1e_mask(); 1004 #ifdef CONFIG_X86_32 1005 sysenter_setup(); 1006 enable_sep_cpu(); 1007 #else 1008 vgetcpu_set_mode(); 1009 #endif 1010 cpu_detect_tlb(&boot_cpu_data); 1011 } 1012 1013 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1014 { 1015 BUG_ON(c == &boot_cpu_data); 1016 identify_cpu(c); 1017 #ifdef CONFIG_X86_32 1018 enable_sep_cpu(); 1019 #endif 1020 mtrr_ap_init(); 1021 } 1022 1023 struct msr_range { 1024 unsigned min; 1025 unsigned max; 1026 }; 1027 1028 static const struct msr_range msr_range_array[] = { 1029 { 0x00000000, 0x00000418}, 1030 { 0xc0000000, 0xc000040b}, 1031 { 0xc0010000, 0xc0010142}, 1032 { 0xc0011000, 0xc001103b}, 1033 }; 1034 1035 static void __print_cpu_msr(void) 1036 { 1037 unsigned index_min, index_max; 1038 unsigned index; 1039 u64 val; 1040 int i; 1041 1042 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 1043 index_min = msr_range_array[i].min; 1044 index_max = msr_range_array[i].max; 1045 1046 for (index = index_min; index < index_max; index++) { 1047 if (rdmsrl_safe(index, &val)) 1048 continue; 1049 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 1050 } 1051 } 1052 } 1053 1054 static int show_msr; 1055 1056 static __init int setup_show_msr(char *arg) 1057 { 1058 int num; 1059 1060 get_option(&arg, &num); 1061 1062 if (num > 0) 1063 show_msr = num; 1064 return 1; 1065 } 1066 __setup("show_msr=", setup_show_msr); 1067 1068 static __init int setup_noclflush(char *arg) 1069 { 1070 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1071 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1072 return 1; 1073 } 1074 __setup("noclflush", setup_noclflush); 1075 1076 void print_cpu_info(struct cpuinfo_x86 *c) 1077 { 1078 const char *vendor = NULL; 1079 1080 if (c->x86_vendor < X86_VENDOR_NUM) { 1081 vendor = this_cpu->c_vendor; 1082 } else { 1083 if (c->cpuid_level >= 0) 1084 vendor = c->x86_vendor_id; 1085 } 1086 1087 if (vendor && !strstr(c->x86_model_id, vendor)) 1088 printk(KERN_CONT "%s ", vendor); 1089 1090 if (c->x86_model_id[0]) 1091 printk(KERN_CONT "%s", strim(c->x86_model_id)); 1092 else 1093 printk(KERN_CONT "%d86", c->x86); 1094 1095 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); 1096 1097 if (c->x86_mask || c->cpuid_level >= 0) 1098 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); 1099 else 1100 printk(KERN_CONT ")\n"); 1101 1102 print_cpu_msr(c); 1103 } 1104 1105 void print_cpu_msr(struct cpuinfo_x86 *c) 1106 { 1107 if (c->cpu_index < show_msr) 1108 __print_cpu_msr(); 1109 } 1110 1111 static __init int setup_disablecpuid(char *arg) 1112 { 1113 int bit; 1114 1115 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1116 setup_clear_cpu_cap(bit); 1117 else 1118 return 0; 1119 1120 return 1; 1121 } 1122 __setup("clearcpuid=", setup_disablecpuid); 1123 1124 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1125 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1126 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1127 1128 #ifdef CONFIG_X86_64 1129 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1130 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1131 (unsigned long) debug_idt_table }; 1132 1133 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1134 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1135 1136 /* 1137 * The following four percpu variables are hot. Align current_task to 1138 * cacheline size such that all four fall in the same cacheline. 1139 */ 1140 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1141 &init_task; 1142 EXPORT_PER_CPU_SYMBOL(current_task); 1143 1144 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1145 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1146 1147 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1148 1149 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1150 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1151 1152 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1153 1154 /* 1155 * Special IST stacks which the CPU switches to when it calls 1156 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1157 * limit), all of them are 4K, except the debug stack which 1158 * is 8K. 1159 */ 1160 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1161 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1162 [DEBUG_STACK - 1] = DEBUG_STKSZ 1163 }; 1164 1165 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1166 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1167 1168 /* May not be marked __init: used by software suspend */ 1169 void syscall_init(void) 1170 { 1171 /* 1172 * LSTAR and STAR live in a bit strange symbiosis. 1173 * They both write to the same internal register. STAR allows to 1174 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1175 */ 1176 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1177 wrmsrl(MSR_LSTAR, system_call); 1178 wrmsrl(MSR_CSTAR, ignore_sysret); 1179 1180 #ifdef CONFIG_IA32_EMULATION 1181 syscall32_cpu_init(); 1182 #endif 1183 1184 /* Flags to clear on syscall */ 1185 wrmsrl(MSR_SYSCALL_MASK, 1186 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1187 X86_EFLAGS_IOPL|X86_EFLAGS_AC); 1188 } 1189 1190 /* 1191 * Copies of the original ist values from the tss are only accessed during 1192 * debugging, no special alignment required. 1193 */ 1194 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1195 1196 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1197 DEFINE_PER_CPU(int, debug_stack_usage); 1198 1199 int is_debug_stack(unsigned long addr) 1200 { 1201 return __get_cpu_var(debug_stack_usage) || 1202 (addr <= __get_cpu_var(debug_stack_addr) && 1203 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); 1204 } 1205 NOKPROBE_SYMBOL(is_debug_stack); 1206 1207 DEFINE_PER_CPU(u32, debug_idt_ctr); 1208 1209 void debug_stack_set_zero(void) 1210 { 1211 this_cpu_inc(debug_idt_ctr); 1212 load_current_idt(); 1213 } 1214 NOKPROBE_SYMBOL(debug_stack_set_zero); 1215 1216 void debug_stack_reset(void) 1217 { 1218 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1219 return; 1220 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1221 load_current_idt(); 1222 } 1223 NOKPROBE_SYMBOL(debug_stack_reset); 1224 1225 #else /* CONFIG_X86_64 */ 1226 1227 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1228 EXPORT_PER_CPU_SYMBOL(current_task); 1229 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1230 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1231 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1232 1233 #ifdef CONFIG_CC_STACKPROTECTOR 1234 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1235 #endif 1236 1237 #endif /* CONFIG_X86_64 */ 1238 1239 /* 1240 * Clear all 6 debug registers: 1241 */ 1242 static void clear_all_debug_regs(void) 1243 { 1244 int i; 1245 1246 for (i = 0; i < 8; i++) { 1247 /* Ignore db4, db5 */ 1248 if ((i == 4) || (i == 5)) 1249 continue; 1250 1251 set_debugreg(0, i); 1252 } 1253 } 1254 1255 #ifdef CONFIG_KGDB 1256 /* 1257 * Restore debug regs if using kgdbwait and you have a kernel debugger 1258 * connection established. 1259 */ 1260 static void dbg_restore_debug_regs(void) 1261 { 1262 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1263 arch_kgdb_ops.correct_hw_break(); 1264 } 1265 #else /* ! CONFIG_KGDB */ 1266 #define dbg_restore_debug_regs() 1267 #endif /* ! CONFIG_KGDB */ 1268 1269 /* 1270 * cpu_init() initializes state that is per-CPU. Some data is already 1271 * initialized (naturally) in the bootstrap process, such as the GDT 1272 * and IDT. We reload them nevertheless, this function acts as a 1273 * 'CPU state barrier', nothing should get across. 1274 * A lot of state is already set up in PDA init for 64 bit 1275 */ 1276 #ifdef CONFIG_X86_64 1277 1278 void cpu_init(void) 1279 { 1280 struct orig_ist *oist; 1281 struct task_struct *me; 1282 struct tss_struct *t; 1283 unsigned long v; 1284 int cpu; 1285 int i; 1286 1287 /* 1288 * Load microcode on this cpu if a valid microcode is available. 1289 * This is early microcode loading procedure. 1290 */ 1291 load_ucode_ap(); 1292 1293 cpu = stack_smp_processor_id(); 1294 t = &per_cpu(init_tss, cpu); 1295 oist = &per_cpu(orig_ist, cpu); 1296 1297 #ifdef CONFIG_NUMA 1298 if (this_cpu_read(numa_node) == 0 && 1299 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1300 set_numa_node(early_cpu_to_node(cpu)); 1301 #endif 1302 1303 me = current; 1304 1305 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1306 panic("CPU#%d already initialized!\n", cpu); 1307 1308 pr_debug("Initializing CPU#%d\n", cpu); 1309 1310 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1311 1312 /* 1313 * Initialize the per-CPU GDT with the boot GDT, 1314 * and set up the GDT descriptor: 1315 */ 1316 1317 switch_to_new_gdt(cpu); 1318 loadsegment(fs, 0); 1319 1320 load_current_idt(); 1321 1322 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1323 syscall_init(); 1324 1325 wrmsrl(MSR_FS_BASE, 0); 1326 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1327 barrier(); 1328 1329 x86_configure_nx(); 1330 enable_x2apic(); 1331 1332 /* 1333 * set up and load the per-CPU TSS 1334 */ 1335 if (!oist->ist[0]) { 1336 char *estacks = per_cpu(exception_stacks, cpu); 1337 1338 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1339 estacks += exception_stack_sizes[v]; 1340 oist->ist[v] = t->x86_tss.ist[v] = 1341 (unsigned long)estacks; 1342 if (v == DEBUG_STACK-1) 1343 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1344 } 1345 } 1346 1347 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1348 1349 /* 1350 * <= is required because the CPU will access up to 1351 * 8 bits beyond the end of the IO permission bitmap. 1352 */ 1353 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1354 t->io_bitmap[i] = ~0UL; 1355 1356 atomic_inc(&init_mm.mm_count); 1357 me->active_mm = &init_mm; 1358 BUG_ON(me->mm); 1359 enter_lazy_tlb(&init_mm, me); 1360 1361 load_sp0(t, ¤t->thread); 1362 set_tss_desc(cpu, t); 1363 load_TR_desc(); 1364 load_LDT(&init_mm.context); 1365 1366 clear_all_debug_regs(); 1367 dbg_restore_debug_regs(); 1368 1369 fpu_init(); 1370 1371 if (is_uv_system()) 1372 uv_cpu_init(); 1373 } 1374 1375 #else 1376 1377 void cpu_init(void) 1378 { 1379 int cpu = smp_processor_id(); 1380 struct task_struct *curr = current; 1381 struct tss_struct *t = &per_cpu(init_tss, cpu); 1382 struct thread_struct *thread = &curr->thread; 1383 1384 show_ucode_info_early(); 1385 1386 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1387 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1388 for (;;) 1389 local_irq_enable(); 1390 } 1391 1392 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1393 1394 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1395 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1396 1397 load_current_idt(); 1398 switch_to_new_gdt(cpu); 1399 1400 /* 1401 * Set up and load the per-CPU TSS and LDT 1402 */ 1403 atomic_inc(&init_mm.mm_count); 1404 curr->active_mm = &init_mm; 1405 BUG_ON(curr->mm); 1406 enter_lazy_tlb(&init_mm, curr); 1407 1408 load_sp0(t, thread); 1409 set_tss_desc(cpu, t); 1410 load_TR_desc(); 1411 load_LDT(&init_mm.context); 1412 1413 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1414 1415 #ifdef CONFIG_DOUBLEFAULT 1416 /* Set up doublefault TSS pointer in the GDT */ 1417 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1418 #endif 1419 1420 clear_all_debug_regs(); 1421 dbg_restore_debug_regs(); 1422 1423 fpu_init(); 1424 } 1425 #endif 1426 1427 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 1428 void warn_pre_alternatives(void) 1429 { 1430 WARN(1, "You're using static_cpu_has before alternatives have run!\n"); 1431 } 1432 EXPORT_SYMBOL_GPL(warn_pre_alternatives); 1433 #endif 1434 1435 inline bool __static_cpu_has_safe(u16 bit) 1436 { 1437 return boot_cpu_has(bit); 1438 } 1439 EXPORT_SYMBOL_GPL(__static_cpu_has_safe); 1440