1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/mem_encrypt.h> 22 #include <linux/smp.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/pgtable.h> 27 #include <linux/stackprotector.h> 28 #include <linux/utsname.h> 29 30 #include <asm/alternative.h> 31 #include <asm/cmdline.h> 32 #include <asm/perf_event.h> 33 #include <asm/mmu_context.h> 34 #include <asm/doublefault.h> 35 #include <asm/archrandom.h> 36 #include <asm/hypervisor.h> 37 #include <asm/processor.h> 38 #include <asm/tlbflush.h> 39 #include <asm/debugreg.h> 40 #include <asm/sections.h> 41 #include <asm/vsyscall.h> 42 #include <linux/topology.h> 43 #include <linux/cpumask.h> 44 #include <linux/atomic.h> 45 #include <asm/proto.h> 46 #include <asm/setup.h> 47 #include <asm/apic.h> 48 #include <asm/desc.h> 49 #include <asm/fpu/api.h> 50 #include <asm/mtrr.h> 51 #include <asm/hwcap2.h> 52 #include <linux/numa.h> 53 #include <asm/numa.h> 54 #include <asm/asm.h> 55 #include <asm/bugs.h> 56 #include <asm/cpu.h> 57 #include <asm/mce.h> 58 #include <asm/msr.h> 59 #include <asm/cacheinfo.h> 60 #include <asm/memtype.h> 61 #include <asm/microcode.h> 62 #include <asm/intel-family.h> 63 #include <asm/cpu_device_id.h> 64 #include <asm/uv/uv.h> 65 #include <asm/set_memory.h> 66 #include <asm/traps.h> 67 #include <asm/sev.h> 68 69 #include "cpu.h" 70 71 u32 elf_hwcap2 __read_mostly; 72 73 /* Number of siblings per CPU package */ 74 int smp_num_siblings = 1; 75 EXPORT_SYMBOL(smp_num_siblings); 76 77 /* Last level cache ID of each logical CPU */ 78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 79 80 u16 get_llc_id(unsigned int cpu) 81 { 82 return per_cpu(cpu_llc_id, cpu); 83 } 84 EXPORT_SYMBOL_GPL(get_llc_id); 85 86 /* L2 cache ID of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 88 89 static struct ppin_info { 90 int feature; 91 int msr_ppin_ctl; 92 int msr_ppin; 93 } ppin_info[] = { 94 [X86_VENDOR_INTEL] = { 95 .feature = X86_FEATURE_INTEL_PPIN, 96 .msr_ppin_ctl = MSR_PPIN_CTL, 97 .msr_ppin = MSR_PPIN 98 }, 99 [X86_VENDOR_AMD] = { 100 .feature = X86_FEATURE_AMD_PPIN, 101 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 102 .msr_ppin = MSR_AMD_PPIN 103 }, 104 }; 105 106 static const struct x86_cpu_id ppin_cpuids[] = { 107 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 108 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 109 110 /* Legacy models without CPUID enumeration */ 111 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 112 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 113 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 114 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 115 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 116 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 117 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 122 123 {} 124 }; 125 126 static void ppin_init(struct cpuinfo_x86 *c) 127 { 128 const struct x86_cpu_id *id; 129 unsigned long long val; 130 struct ppin_info *info; 131 132 id = x86_match_cpu(ppin_cpuids); 133 if (!id) 134 return; 135 136 /* 137 * Testing the presence of the MSR is not enough. Need to check 138 * that the PPIN_CTL allows reading of the PPIN. 139 */ 140 info = (struct ppin_info *)id->driver_data; 141 142 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 143 goto clear_ppin; 144 145 if ((val & 3UL) == 1UL) { 146 /* PPIN locked in disabled mode */ 147 goto clear_ppin; 148 } 149 150 /* If PPIN is disabled, try to enable */ 151 if (!(val & 2UL)) { 152 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 153 rdmsrl_safe(info->msr_ppin_ctl, &val); 154 } 155 156 /* Is the enable bit set? */ 157 if (val & 2UL) { 158 c->ppin = __rdmsr(info->msr_ppin); 159 set_cpu_cap(c, info->feature); 160 return; 161 } 162 163 clear_ppin: 164 clear_cpu_cap(c, info->feature); 165 } 166 167 static void default_init(struct cpuinfo_x86 *c) 168 { 169 #ifdef CONFIG_X86_64 170 cpu_detect_cache_sizes(c); 171 #else 172 /* Not much we can do here... */ 173 /* Check if at least it has cpuid */ 174 if (c->cpuid_level == -1) { 175 /* No cpuid. It must be an ancient CPU */ 176 if (c->x86 == 4) 177 strcpy(c->x86_model_id, "486"); 178 else if (c->x86 == 3) 179 strcpy(c->x86_model_id, "386"); 180 } 181 #endif 182 } 183 184 static const struct cpu_dev default_cpu = { 185 .c_init = default_init, 186 .c_vendor = "Unknown", 187 .c_x86_vendor = X86_VENDOR_UNKNOWN, 188 }; 189 190 static const struct cpu_dev *this_cpu = &default_cpu; 191 192 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 193 #ifdef CONFIG_X86_64 194 /* 195 * We need valid kernel segments for data and code in long mode too 196 * IRET will check the segment types kkeil 2000/10/28 197 * Also sysret mandates a special GDT layout 198 * 199 * TLS descriptors are currently at a different place compared to i386. 200 * Hopefully nobody expects them at a fixed place (Wine?) 201 */ 202 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 203 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 204 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 205 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 206 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 207 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 208 #else 209 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 210 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 211 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 212 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 213 /* 214 * Segments used for calling PnP BIOS have byte granularity. 215 * They code segments and data segments have fixed 64k limits, 216 * the transfer segment sizes are set at run time. 217 */ 218 /* 32-bit code */ 219 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 220 /* 16-bit code */ 221 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 222 /* 16-bit data */ 223 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 224 /* 16-bit data */ 225 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 226 /* 16-bit data */ 227 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 228 /* 229 * The APM segments have byte granularity and their bases 230 * are set at run time. All have 64k limits. 231 */ 232 /* 32-bit code */ 233 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 234 /* 16-bit code */ 235 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 236 /* data */ 237 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 238 239 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 240 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 241 #endif 242 } }; 243 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 244 245 #ifdef CONFIG_X86_64 246 static int __init x86_nopcid_setup(char *s) 247 { 248 /* nopcid doesn't accept parameters */ 249 if (s) 250 return -EINVAL; 251 252 /* do not emit a message if the feature is not present */ 253 if (!boot_cpu_has(X86_FEATURE_PCID)) 254 return 0; 255 256 setup_clear_cpu_cap(X86_FEATURE_PCID); 257 pr_info("nopcid: PCID feature disabled\n"); 258 return 0; 259 } 260 early_param("nopcid", x86_nopcid_setup); 261 #endif 262 263 static int __init x86_noinvpcid_setup(char *s) 264 { 265 /* noinvpcid doesn't accept parameters */ 266 if (s) 267 return -EINVAL; 268 269 /* do not emit a message if the feature is not present */ 270 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 271 return 0; 272 273 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 274 pr_info("noinvpcid: INVPCID feature disabled\n"); 275 return 0; 276 } 277 early_param("noinvpcid", x86_noinvpcid_setup); 278 279 #ifdef CONFIG_X86_32 280 static int cachesize_override = -1; 281 static int disable_x86_serial_nr = 1; 282 283 static int __init cachesize_setup(char *str) 284 { 285 get_option(&str, &cachesize_override); 286 return 1; 287 } 288 __setup("cachesize=", cachesize_setup); 289 290 /* Standard macro to see if a specific flag is changeable */ 291 static inline int flag_is_changeable_p(u32 flag) 292 { 293 u32 f1, f2; 294 295 /* 296 * Cyrix and IDT cpus allow disabling of CPUID 297 * so the code below may return different results 298 * when it is executed before and after enabling 299 * the CPUID. Add "volatile" to not allow gcc to 300 * optimize the subsequent calls to this function. 301 */ 302 asm volatile ("pushfl \n\t" 303 "pushfl \n\t" 304 "popl %0 \n\t" 305 "movl %0, %1 \n\t" 306 "xorl %2, %0 \n\t" 307 "pushl %0 \n\t" 308 "popfl \n\t" 309 "pushfl \n\t" 310 "popl %0 \n\t" 311 "popfl \n\t" 312 313 : "=&r" (f1), "=&r" (f2) 314 : "ir" (flag)); 315 316 return ((f1^f2) & flag) != 0; 317 } 318 319 /* Probe for the CPUID instruction */ 320 int have_cpuid_p(void) 321 { 322 return flag_is_changeable_p(X86_EFLAGS_ID); 323 } 324 325 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 326 { 327 unsigned long lo, hi; 328 329 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 330 return; 331 332 /* Disable processor serial number: */ 333 334 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 335 lo |= 0x200000; 336 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 337 338 pr_notice("CPU serial number disabled.\n"); 339 clear_cpu_cap(c, X86_FEATURE_PN); 340 341 /* Disabling the serial number may affect the cpuid level */ 342 c->cpuid_level = cpuid_eax(0); 343 } 344 345 static int __init x86_serial_nr_setup(char *s) 346 { 347 disable_x86_serial_nr = 0; 348 return 1; 349 } 350 __setup("serialnumber", x86_serial_nr_setup); 351 #else 352 static inline int flag_is_changeable_p(u32 flag) 353 { 354 return 1; 355 } 356 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 357 { 358 } 359 #endif 360 361 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 362 { 363 if (cpu_has(c, X86_FEATURE_SMEP)) 364 cr4_set_bits(X86_CR4_SMEP); 365 } 366 367 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 368 { 369 unsigned long eflags = native_save_fl(); 370 371 /* This should have been cleared long ago */ 372 BUG_ON(eflags & X86_EFLAGS_AC); 373 374 if (cpu_has(c, X86_FEATURE_SMAP)) 375 cr4_set_bits(X86_CR4_SMAP); 376 } 377 378 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 379 { 380 /* Check the boot processor, plus build option for UMIP. */ 381 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 382 goto out; 383 384 /* Check the current processor's cpuid bits. */ 385 if (!cpu_has(c, X86_FEATURE_UMIP)) 386 goto out; 387 388 cr4_set_bits(X86_CR4_UMIP); 389 390 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 391 392 return; 393 394 out: 395 /* 396 * Make sure UMIP is disabled in case it was enabled in a 397 * previous boot (e.g., via kexec). 398 */ 399 cr4_clear_bits(X86_CR4_UMIP); 400 } 401 402 /* These bits should not change their value after CPU init is finished. */ 403 static const unsigned long cr4_pinned_mask = 404 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 405 X86_CR4_FSGSBASE | X86_CR4_CET; 406 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 407 static unsigned long cr4_pinned_bits __ro_after_init; 408 409 void native_write_cr0(unsigned long val) 410 { 411 unsigned long bits_missing = 0; 412 413 set_register: 414 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 415 416 if (static_branch_likely(&cr_pinning)) { 417 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 418 bits_missing = X86_CR0_WP; 419 val |= bits_missing; 420 goto set_register; 421 } 422 /* Warn after we've set the missing bits. */ 423 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 424 } 425 } 426 EXPORT_SYMBOL(native_write_cr0); 427 428 void __no_profile native_write_cr4(unsigned long val) 429 { 430 unsigned long bits_changed = 0; 431 432 set_register: 433 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 434 435 if (static_branch_likely(&cr_pinning)) { 436 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 437 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 438 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 439 goto set_register; 440 } 441 /* Warn after we've corrected the changed bits. */ 442 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 443 bits_changed); 444 } 445 } 446 #if IS_MODULE(CONFIG_LKDTM) 447 EXPORT_SYMBOL_GPL(native_write_cr4); 448 #endif 449 450 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 451 { 452 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 453 454 lockdep_assert_irqs_disabled(); 455 456 newval = (cr4 & ~clear) | set; 457 if (newval != cr4) { 458 this_cpu_write(cpu_tlbstate.cr4, newval); 459 __write_cr4(newval); 460 } 461 } 462 EXPORT_SYMBOL(cr4_update_irqsoff); 463 464 /* Read the CR4 shadow. */ 465 unsigned long cr4_read_shadow(void) 466 { 467 return this_cpu_read(cpu_tlbstate.cr4); 468 } 469 EXPORT_SYMBOL_GPL(cr4_read_shadow); 470 471 void cr4_init(void) 472 { 473 unsigned long cr4 = __read_cr4(); 474 475 if (boot_cpu_has(X86_FEATURE_PCID)) 476 cr4 |= X86_CR4_PCIDE; 477 if (static_branch_likely(&cr_pinning)) 478 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 479 480 __write_cr4(cr4); 481 482 /* Initialize cr4 shadow for this CPU. */ 483 this_cpu_write(cpu_tlbstate.cr4, cr4); 484 } 485 486 /* 487 * Once CPU feature detection is finished (and boot params have been 488 * parsed), record any of the sensitive CR bits that are set, and 489 * enable CR pinning. 490 */ 491 static void __init setup_cr_pinning(void) 492 { 493 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 494 static_key_enable(&cr_pinning.key); 495 } 496 497 static __init int x86_nofsgsbase_setup(char *arg) 498 { 499 /* Require an exact match without trailing characters. */ 500 if (strlen(arg)) 501 return 0; 502 503 /* Do not emit a message if the feature is not present. */ 504 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 505 return 1; 506 507 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 508 pr_info("FSGSBASE disabled via kernel command line\n"); 509 return 1; 510 } 511 __setup("nofsgsbase", x86_nofsgsbase_setup); 512 513 /* 514 * Protection Keys are not available in 32-bit mode. 515 */ 516 static bool pku_disabled; 517 518 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 519 { 520 if (c == &boot_cpu_data) { 521 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 522 return; 523 /* 524 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 525 * bit to be set. Enforce it. 526 */ 527 setup_force_cpu_cap(X86_FEATURE_OSPKE); 528 529 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 530 return; 531 } 532 533 cr4_set_bits(X86_CR4_PKE); 534 /* Load the default PKRU value */ 535 pkru_write_default(); 536 } 537 538 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 539 static __init int setup_disable_pku(char *arg) 540 { 541 /* 542 * Do not clear the X86_FEATURE_PKU bit. All of the 543 * runtime checks are against OSPKE so clearing the 544 * bit does nothing. 545 * 546 * This way, we will see "pku" in cpuinfo, but not 547 * "ospke", which is exactly what we want. It shows 548 * that the CPU has PKU, but the OS has not enabled it. 549 * This happens to be exactly how a system would look 550 * if we disabled the config option. 551 */ 552 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 553 pku_disabled = true; 554 return 1; 555 } 556 __setup("nopku", setup_disable_pku); 557 #endif 558 559 #ifdef CONFIG_X86_KERNEL_IBT 560 561 __noendbr u64 ibt_save(bool disable) 562 { 563 u64 msr = 0; 564 565 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 566 rdmsrl(MSR_IA32_S_CET, msr); 567 if (disable) 568 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 569 } 570 571 return msr; 572 } 573 574 __noendbr void ibt_restore(u64 save) 575 { 576 u64 msr; 577 578 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 579 rdmsrl(MSR_IA32_S_CET, msr); 580 msr &= ~CET_ENDBR_EN; 581 msr |= (save & CET_ENDBR_EN); 582 wrmsrl(MSR_IA32_S_CET, msr); 583 } 584 } 585 586 #endif 587 588 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 589 { 590 bool user_shstk, kernel_ibt; 591 592 if (!IS_ENABLED(CONFIG_X86_CET)) 593 return; 594 595 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 596 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 597 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 598 599 if (!kernel_ibt && !user_shstk) 600 return; 601 602 if (user_shstk) 603 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 604 605 if (kernel_ibt) 606 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN); 607 else 608 wrmsrl(MSR_IA32_S_CET, 0); 609 610 cr4_set_bits(X86_CR4_CET); 611 612 if (kernel_ibt && ibt_selftest()) { 613 pr_err("IBT selftest: Failed!\n"); 614 wrmsrl(MSR_IA32_S_CET, 0); 615 setup_clear_cpu_cap(X86_FEATURE_IBT); 616 } 617 } 618 619 __noendbr void cet_disable(void) 620 { 621 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 622 cpu_feature_enabled(X86_FEATURE_SHSTK))) 623 return; 624 625 wrmsrl(MSR_IA32_S_CET, 0); 626 wrmsrl(MSR_IA32_U_CET, 0); 627 } 628 629 /* 630 * Some CPU features depend on higher CPUID levels, which may not always 631 * be available due to CPUID level capping or broken virtualization 632 * software. Add those features to this table to auto-disable them. 633 */ 634 struct cpuid_dependent_feature { 635 u32 feature; 636 u32 level; 637 }; 638 639 static const struct cpuid_dependent_feature 640 cpuid_dependent_features[] = { 641 { X86_FEATURE_MWAIT, 0x00000005 }, 642 { X86_FEATURE_DCA, 0x00000009 }, 643 { X86_FEATURE_XSAVE, 0x0000000d }, 644 { 0, 0 } 645 }; 646 647 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 648 { 649 const struct cpuid_dependent_feature *df; 650 651 for (df = cpuid_dependent_features; df->feature; df++) { 652 653 if (!cpu_has(c, df->feature)) 654 continue; 655 /* 656 * Note: cpuid_level is set to -1 if unavailable, but 657 * extended_extended_level is set to 0 if unavailable 658 * and the legitimate extended levels are all negative 659 * when signed; hence the weird messing around with 660 * signs here... 661 */ 662 if (!((s32)df->level < 0 ? 663 (u32)df->level > (u32)c->extended_cpuid_level : 664 (s32)df->level > (s32)c->cpuid_level)) 665 continue; 666 667 clear_cpu_cap(c, df->feature); 668 if (!warn) 669 continue; 670 671 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 672 x86_cap_flag(df->feature), df->level); 673 } 674 } 675 676 /* 677 * Naming convention should be: <Name> [(<Codename>)] 678 * This table only is used unless init_<vendor>() below doesn't set it; 679 * in particular, if CPUID levels 0x80000002..4 are supported, this 680 * isn't used 681 */ 682 683 /* Look up CPU names by table lookup. */ 684 static const char *table_lookup_model(struct cpuinfo_x86 *c) 685 { 686 #ifdef CONFIG_X86_32 687 const struct legacy_cpu_model_info *info; 688 689 if (c->x86_model >= 16) 690 return NULL; /* Range check */ 691 692 if (!this_cpu) 693 return NULL; 694 695 info = this_cpu->legacy_models; 696 697 while (info->family) { 698 if (info->family == c->x86) 699 return info->model_names[c->x86_model]; 700 info++; 701 } 702 #endif 703 return NULL; /* Not found */ 704 } 705 706 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 707 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 708 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 709 710 #ifdef CONFIG_X86_32 711 /* The 32-bit entry code needs to find cpu_entry_area. */ 712 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 713 #endif 714 715 /* Load the original GDT from the per-cpu structure */ 716 void load_direct_gdt(int cpu) 717 { 718 struct desc_ptr gdt_descr; 719 720 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 721 gdt_descr.size = GDT_SIZE - 1; 722 load_gdt(&gdt_descr); 723 } 724 EXPORT_SYMBOL_GPL(load_direct_gdt); 725 726 /* Load a fixmap remapping of the per-cpu GDT */ 727 void load_fixmap_gdt(int cpu) 728 { 729 struct desc_ptr gdt_descr; 730 731 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 732 gdt_descr.size = GDT_SIZE - 1; 733 load_gdt(&gdt_descr); 734 } 735 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 736 737 /** 738 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 739 * @cpu: The CPU number for which this is invoked 740 * 741 * Invoked during early boot to switch from early GDT and early per CPU to 742 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 743 * switch is implicit by loading the direct GDT. On 64bit this requires 744 * to update GSBASE. 745 */ 746 void __init switch_gdt_and_percpu_base(int cpu) 747 { 748 load_direct_gdt(cpu); 749 750 #ifdef CONFIG_X86_64 751 /* 752 * No need to load %gs. It is already correct. 753 * 754 * Writing %gs on 64bit would zero GSBASE which would make any per 755 * CPU operation up to the point of the wrmsrl() fault. 756 * 757 * Set GSBASE to the new offset. Until the wrmsrl() happens the 758 * early mapping is still valid. That means the GSBASE update will 759 * lose any prior per CPU data which was not copied over in 760 * setup_per_cpu_areas(). 761 * 762 * This works even with stackprotector enabled because the 763 * per CPU stack canary is 0 in both per CPU areas. 764 */ 765 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 766 #else 767 /* 768 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 769 * it is required to load FS again so that the 'hidden' part is 770 * updated from the new GDT. Up to this point the early per CPU 771 * translation is active. Any content of the early per CPU data 772 * which was not copied over in setup_per_cpu_areas() is lost. 773 */ 774 loadsegment(fs, __KERNEL_PERCPU); 775 #endif 776 } 777 778 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 779 780 static void get_model_name(struct cpuinfo_x86 *c) 781 { 782 unsigned int *v; 783 char *p, *q, *s; 784 785 if (c->extended_cpuid_level < 0x80000004) 786 return; 787 788 v = (unsigned int *)c->x86_model_id; 789 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 790 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 791 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 792 c->x86_model_id[48] = 0; 793 794 /* Trim whitespace */ 795 p = q = s = &c->x86_model_id[0]; 796 797 while (*p == ' ') 798 p++; 799 800 while (*p) { 801 /* Note the last non-whitespace index */ 802 if (!isspace(*p)) 803 s = q; 804 805 *q++ = *p++; 806 } 807 808 *(s + 1) = '\0'; 809 } 810 811 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 812 { 813 unsigned int eax, ebx, ecx, edx; 814 815 c->x86_max_cores = 1; 816 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 817 return; 818 819 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 820 if (eax & 0x1f) 821 c->x86_max_cores = (eax >> 26) + 1; 822 } 823 824 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 825 { 826 unsigned int n, dummy, ebx, ecx, edx, l2size; 827 828 n = c->extended_cpuid_level; 829 830 if (n >= 0x80000005) { 831 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 832 c->x86_cache_size = (ecx>>24) + (edx>>24); 833 #ifdef CONFIG_X86_64 834 /* On K8 L1 TLB is inclusive, so don't count it */ 835 c->x86_tlbsize = 0; 836 #endif 837 } 838 839 if (n < 0x80000006) /* Some chips just has a large L1. */ 840 return; 841 842 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 843 l2size = ecx >> 16; 844 845 #ifdef CONFIG_X86_64 846 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 847 #else 848 /* do processor-specific cache resizing */ 849 if (this_cpu->legacy_cache_size) 850 l2size = this_cpu->legacy_cache_size(c, l2size); 851 852 /* Allow user to override all this if necessary. */ 853 if (cachesize_override != -1) 854 l2size = cachesize_override; 855 856 if (l2size == 0) 857 return; /* Again, no L2 cache is possible */ 858 #endif 859 860 c->x86_cache_size = l2size; 861 } 862 863 u16 __read_mostly tlb_lli_4k[NR_INFO]; 864 u16 __read_mostly tlb_lli_2m[NR_INFO]; 865 u16 __read_mostly tlb_lli_4m[NR_INFO]; 866 u16 __read_mostly tlb_lld_4k[NR_INFO]; 867 u16 __read_mostly tlb_lld_2m[NR_INFO]; 868 u16 __read_mostly tlb_lld_4m[NR_INFO]; 869 u16 __read_mostly tlb_lld_1g[NR_INFO]; 870 871 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 872 { 873 if (this_cpu->c_detect_tlb) 874 this_cpu->c_detect_tlb(c); 875 876 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 877 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 878 tlb_lli_4m[ENTRIES]); 879 880 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 881 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 882 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 883 } 884 885 int detect_ht_early(struct cpuinfo_x86 *c) 886 { 887 #ifdef CONFIG_SMP 888 u32 eax, ebx, ecx, edx; 889 890 if (!cpu_has(c, X86_FEATURE_HT)) 891 return -1; 892 893 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 894 return -1; 895 896 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 897 return -1; 898 899 cpuid(1, &eax, &ebx, &ecx, &edx); 900 901 smp_num_siblings = (ebx & 0xff0000) >> 16; 902 if (smp_num_siblings == 1) 903 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 904 #endif 905 return 0; 906 } 907 908 void detect_ht(struct cpuinfo_x86 *c) 909 { 910 #ifdef CONFIG_SMP 911 int index_msb, core_bits; 912 913 if (detect_ht_early(c) < 0) 914 return; 915 916 index_msb = get_count_order(smp_num_siblings); 917 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 918 919 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 920 921 index_msb = get_count_order(smp_num_siblings); 922 923 core_bits = get_count_order(c->x86_max_cores); 924 925 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 926 ((1 << core_bits) - 1); 927 #endif 928 } 929 930 static void get_cpu_vendor(struct cpuinfo_x86 *c) 931 { 932 char *v = c->x86_vendor_id; 933 int i; 934 935 for (i = 0; i < X86_VENDOR_NUM; i++) { 936 if (!cpu_devs[i]) 937 break; 938 939 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 940 (cpu_devs[i]->c_ident[1] && 941 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 942 943 this_cpu = cpu_devs[i]; 944 c->x86_vendor = this_cpu->c_x86_vendor; 945 return; 946 } 947 } 948 949 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 950 "CPU: Your system may be unstable.\n", v); 951 952 c->x86_vendor = X86_VENDOR_UNKNOWN; 953 this_cpu = &default_cpu; 954 } 955 956 void cpu_detect(struct cpuinfo_x86 *c) 957 { 958 /* Get vendor name */ 959 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 960 (unsigned int *)&c->x86_vendor_id[0], 961 (unsigned int *)&c->x86_vendor_id[8], 962 (unsigned int *)&c->x86_vendor_id[4]); 963 964 c->x86 = 4; 965 /* Intel-defined flags: level 0x00000001 */ 966 if (c->cpuid_level >= 0x00000001) { 967 u32 junk, tfms, cap0, misc; 968 969 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 970 c->x86 = x86_family(tfms); 971 c->x86_model = x86_model(tfms); 972 c->x86_stepping = x86_stepping(tfms); 973 974 if (cap0 & (1<<19)) { 975 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 976 c->x86_cache_alignment = c->x86_clflush_size; 977 } 978 } 979 } 980 981 static void apply_forced_caps(struct cpuinfo_x86 *c) 982 { 983 int i; 984 985 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 986 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 987 c->x86_capability[i] |= cpu_caps_set[i]; 988 } 989 } 990 991 static void init_speculation_control(struct cpuinfo_x86 *c) 992 { 993 /* 994 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 995 * and they also have a different bit for STIBP support. Also, 996 * a hypervisor might have set the individual AMD bits even on 997 * Intel CPUs, for finer-grained selection of what's available. 998 */ 999 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 1000 set_cpu_cap(c, X86_FEATURE_IBRS); 1001 set_cpu_cap(c, X86_FEATURE_IBPB); 1002 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1003 } 1004 1005 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 1006 set_cpu_cap(c, X86_FEATURE_STIBP); 1007 1008 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 1009 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 1010 set_cpu_cap(c, X86_FEATURE_SSBD); 1011 1012 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 1013 set_cpu_cap(c, X86_FEATURE_IBRS); 1014 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1015 } 1016 1017 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 1018 set_cpu_cap(c, X86_FEATURE_IBPB); 1019 1020 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 1021 set_cpu_cap(c, X86_FEATURE_STIBP); 1022 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1023 } 1024 1025 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1026 set_cpu_cap(c, X86_FEATURE_SSBD); 1027 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1028 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1029 } 1030 } 1031 1032 void get_cpu_cap(struct cpuinfo_x86 *c) 1033 { 1034 u32 eax, ebx, ecx, edx; 1035 1036 /* Intel-defined flags: level 0x00000001 */ 1037 if (c->cpuid_level >= 0x00000001) { 1038 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1039 1040 c->x86_capability[CPUID_1_ECX] = ecx; 1041 c->x86_capability[CPUID_1_EDX] = edx; 1042 } 1043 1044 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1045 if (c->cpuid_level >= 0x00000006) 1046 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1047 1048 /* Additional Intel-defined flags: level 0x00000007 */ 1049 if (c->cpuid_level >= 0x00000007) { 1050 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1051 c->x86_capability[CPUID_7_0_EBX] = ebx; 1052 c->x86_capability[CPUID_7_ECX] = ecx; 1053 c->x86_capability[CPUID_7_EDX] = edx; 1054 1055 /* Check valid sub-leaf index before accessing it */ 1056 if (eax >= 1) { 1057 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1058 c->x86_capability[CPUID_7_1_EAX] = eax; 1059 } 1060 } 1061 1062 /* Extended state features: level 0x0000000d */ 1063 if (c->cpuid_level >= 0x0000000d) { 1064 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1065 1066 c->x86_capability[CPUID_D_1_EAX] = eax; 1067 } 1068 1069 /* AMD-defined flags: level 0x80000001 */ 1070 eax = cpuid_eax(0x80000000); 1071 c->extended_cpuid_level = eax; 1072 1073 if ((eax & 0xffff0000) == 0x80000000) { 1074 if (eax >= 0x80000001) { 1075 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1076 1077 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1078 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1079 } 1080 } 1081 1082 if (c->extended_cpuid_level >= 0x80000007) { 1083 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1084 1085 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1086 c->x86_power = edx; 1087 } 1088 1089 if (c->extended_cpuid_level >= 0x80000008) { 1090 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1091 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1092 } 1093 1094 if (c->extended_cpuid_level >= 0x8000000a) 1095 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1096 1097 if (c->extended_cpuid_level >= 0x8000001f) 1098 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1099 1100 if (c->extended_cpuid_level >= 0x80000021) 1101 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1102 1103 init_scattered_cpuid_features(c); 1104 init_speculation_control(c); 1105 1106 /* 1107 * Clear/Set all flags overridden by options, after probe. 1108 * This needs to happen each time we re-probe, which may happen 1109 * several times during CPU initialization. 1110 */ 1111 apply_forced_caps(c); 1112 } 1113 1114 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1115 { 1116 u32 eax, ebx, ecx, edx; 1117 1118 if (c->extended_cpuid_level >= 0x80000008) { 1119 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1120 1121 c->x86_virt_bits = (eax >> 8) & 0xff; 1122 c->x86_phys_bits = eax & 0xff; 1123 } 1124 #ifdef CONFIG_X86_32 1125 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 1126 c->x86_phys_bits = 36; 1127 #endif 1128 c->x86_cache_bits = c->x86_phys_bits; 1129 } 1130 1131 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1132 { 1133 #ifdef CONFIG_X86_32 1134 int i; 1135 1136 /* 1137 * First of all, decide if this is a 486 or higher 1138 * It's a 486 if we can modify the AC flag 1139 */ 1140 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1141 c->x86 = 4; 1142 else 1143 c->x86 = 3; 1144 1145 for (i = 0; i < X86_VENDOR_NUM; i++) 1146 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1147 c->x86_vendor_id[0] = 0; 1148 cpu_devs[i]->c_identify(c); 1149 if (c->x86_vendor_id[0]) { 1150 get_cpu_vendor(c); 1151 break; 1152 } 1153 } 1154 #endif 1155 } 1156 1157 #define NO_SPECULATION BIT(0) 1158 #define NO_MELTDOWN BIT(1) 1159 #define NO_SSB BIT(2) 1160 #define NO_L1TF BIT(3) 1161 #define NO_MDS BIT(4) 1162 #define MSBDS_ONLY BIT(5) 1163 #define NO_SWAPGS BIT(6) 1164 #define NO_ITLB_MULTIHIT BIT(7) 1165 #define NO_SPECTRE_V2 BIT(8) 1166 #define NO_MMIO BIT(9) 1167 #define NO_EIBRS_PBRSB BIT(10) 1168 #define NO_BHI BIT(11) 1169 1170 #define VULNWL(vendor, family, model, whitelist) \ 1171 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1172 1173 #define VULNWL_INTEL(model, whitelist) \ 1174 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1175 1176 #define VULNWL_AMD(family, whitelist) \ 1177 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1178 1179 #define VULNWL_HYGON(family, whitelist) \ 1180 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1181 1182 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1183 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1184 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1185 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1186 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1187 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1188 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1189 1190 /* Intel Family 6 */ 1191 VULNWL_INTEL(TIGERLAKE, NO_MMIO), 1192 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), 1193 VULNWL_INTEL(ALDERLAKE, NO_MMIO), 1194 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), 1195 1196 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1197 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1198 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1199 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1200 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1201 1202 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1203 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1204 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1205 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1206 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1207 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1208 1209 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1210 1211 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1212 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1213 1214 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1215 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1216 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1217 1218 /* 1219 * Technically, swapgs isn't serializing on AMD (despite it previously 1220 * being documented as such in the APM). But according to AMD, %gs is 1221 * updated non-speculatively, and the issuing of %gs-relative memory 1222 * operands will be blocked until the %gs update completes, which is 1223 * good enough for our purposes. 1224 */ 1225 1226 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), 1227 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1228 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1229 1230 /* AMD Family 0xf - 0x12 */ 1231 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1232 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1233 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1234 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1235 1236 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1237 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1238 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1239 1240 /* Zhaoxin Family 7 */ 1241 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1242 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1243 {} 1244 }; 1245 1246 #define VULNBL(vendor, family, model, blacklist) \ 1247 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1248 1249 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1250 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1251 INTEL_FAM6_##model, steppings, \ 1252 X86_FEATURE_ANY, issues) 1253 1254 #define VULNBL_AMD(family, blacklist) \ 1255 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1256 1257 #define VULNBL_HYGON(family, blacklist) \ 1258 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1259 1260 #define SRBDS BIT(0) 1261 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1262 #define MMIO BIT(1) 1263 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1264 #define MMIO_SBDS BIT(2) 1265 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1266 #define RETBLEED BIT(3) 1267 /* CPU is affected by SMT (cross-thread) return predictions */ 1268 #define SMT_RSB BIT(4) 1269 /* CPU is affected by SRSO */ 1270 #define SRSO BIT(5) 1271 /* CPU is affected by GDS */ 1272 #define GDS BIT(6) 1273 /* CPU is affected by Register File Data Sampling */ 1274 #define RFDS BIT(7) 1275 1276 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1277 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1278 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1279 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1280 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1281 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), 1282 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), 1283 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1284 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), 1285 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1286 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1287 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1288 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1289 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1290 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1291 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), 1292 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1293 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), 1294 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), 1295 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1296 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), 1297 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1298 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS), 1299 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS), 1300 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1301 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1302 VULNBL_INTEL_STEPPINGS(ALDERLAKE, X86_STEPPING_ANY, RFDS), 1303 VULNBL_INTEL_STEPPINGS(ALDERLAKE_L, X86_STEPPING_ANY, RFDS), 1304 VULNBL_INTEL_STEPPINGS(RAPTORLAKE, X86_STEPPING_ANY, RFDS), 1305 VULNBL_INTEL_STEPPINGS(RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), 1306 VULNBL_INTEL_STEPPINGS(RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), 1307 VULNBL_INTEL_STEPPINGS(ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), 1308 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), 1309 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS), 1310 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), 1311 VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS), 1312 VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS), 1313 VULNBL_INTEL_STEPPINGS(ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS), 1314 1315 VULNBL_AMD(0x15, RETBLEED), 1316 VULNBL_AMD(0x16, RETBLEED), 1317 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), 1318 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), 1319 VULNBL_AMD(0x19, SRSO), 1320 {} 1321 }; 1322 1323 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1324 { 1325 const struct x86_cpu_id *m = x86_match_cpu(table); 1326 1327 return m && !!(m->driver_data & which); 1328 } 1329 1330 u64 x86_read_arch_cap_msr(void) 1331 { 1332 u64 x86_arch_cap_msr = 0; 1333 1334 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1335 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1336 1337 return x86_arch_cap_msr; 1338 } 1339 1340 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr) 1341 { 1342 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO && 1343 x86_arch_cap_msr & ARCH_CAP_PSDP_NO && 1344 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO); 1345 } 1346 1347 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr) 1348 { 1349 /* The "immunity" bit trumps everything else: */ 1350 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO) 1351 return false; 1352 1353 /* 1354 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to 1355 * indicate that mitigation is needed because guest is running on a 1356 * vulnerable hardware or may migrate to such hardware: 1357 */ 1358 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 1359 return true; 1360 1361 /* Only consult the blacklist when there is no enumeration: */ 1362 return cpu_matches(cpu_vuln_blacklist, RFDS); 1363 } 1364 1365 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1366 { 1367 u64 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1368 1369 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1370 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1371 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO)) 1372 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1373 1374 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1375 return; 1376 1377 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1378 1379 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1380 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1381 1382 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1383 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) && 1384 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1385 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1386 1387 /* 1388 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1389 * flag and protect from vendor-specific bugs via the whitelist. 1390 */ 1391 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { 1392 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1393 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1394 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO)) 1395 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1396 } 1397 1398 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1399 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) { 1400 setup_force_cpu_bug(X86_BUG_MDS); 1401 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1402 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1403 } 1404 1405 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1406 setup_force_cpu_bug(X86_BUG_SWAPGS); 1407 1408 /* 1409 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1410 * - TSX is supported or 1411 * - TSX_CTRL is present 1412 * 1413 * TSX_CTRL check is needed for cases when TSX could be disabled before 1414 * the kernel boot e.g. kexec. 1415 * TSX_CTRL check alone is not sufficient for cases when the microcode 1416 * update is not present or running as guest that don't get TSX_CTRL. 1417 */ 1418 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) && 1419 (cpu_has(c, X86_FEATURE_RTM) || 1420 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))) 1421 setup_force_cpu_bug(X86_BUG_TAA); 1422 1423 /* 1424 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1425 * in the vulnerability blacklist. 1426 * 1427 * Some of the implications and mitigation of Shared Buffers Data 1428 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1429 * SRBDS. 1430 */ 1431 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1432 cpu_has(c, X86_FEATURE_RDSEED)) && 1433 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1434 setup_force_cpu_bug(X86_BUG_SRBDS); 1435 1436 /* 1437 * Processor MMIO Stale Data bug enumeration 1438 * 1439 * Affected CPU list is generally enough to enumerate the vulnerability, 1440 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1441 * not want the guest to enumerate the bug. 1442 * 1443 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1444 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1445 */ 1446 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { 1447 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1448 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1449 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1450 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1451 } 1452 1453 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1454 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA)) 1455 setup_force_cpu_bug(X86_BUG_RETBLEED); 1456 } 1457 1458 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1459 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1460 1461 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1462 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1463 setup_force_cpu_bug(X86_BUG_SRSO); 1464 } 1465 1466 /* 1467 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1468 * an affected processor, the VMM may have disabled the use of GATHER by 1469 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1470 * which means that AVX will be disabled. 1471 */ 1472 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) && 1473 boot_cpu_has(X86_FEATURE_AVX)) 1474 setup_force_cpu_bug(X86_BUG_GDS); 1475 1476 if (vulnerable_to_rfds(x86_arch_cap_msr)) 1477 setup_force_cpu_bug(X86_BUG_RFDS); 1478 1479 /* When virtualized, eIBRS could be hidden, assume vulnerable */ 1480 if (!(x86_arch_cap_msr & ARCH_CAP_BHI_NO) && 1481 !cpu_matches(cpu_vuln_whitelist, NO_BHI) && 1482 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) || 1483 boot_cpu_has(X86_FEATURE_HYPERVISOR))) 1484 setup_force_cpu_bug(X86_BUG_BHI); 1485 1486 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET)) 1487 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET); 1488 1489 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1490 return; 1491 1492 /* Rogue Data Cache Load? No! */ 1493 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO) 1494 return; 1495 1496 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1497 1498 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1499 return; 1500 1501 setup_force_cpu_bug(X86_BUG_L1TF); 1502 } 1503 1504 /* 1505 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1506 * unfortunately, that's not true in practice because of early VIA 1507 * chips and (more importantly) broken virtualizers that are not easy 1508 * to detect. In the latter case it doesn't even *fail* reliably, so 1509 * probing for it doesn't even work. Disable it completely on 32-bit 1510 * unless we can find a reliable way to detect all the broken cases. 1511 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1512 */ 1513 static void detect_nopl(void) 1514 { 1515 #ifdef CONFIG_X86_32 1516 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1517 #else 1518 setup_force_cpu_cap(X86_FEATURE_NOPL); 1519 #endif 1520 } 1521 1522 /* 1523 * We parse cpu parameters early because fpu__init_system() is executed 1524 * before parse_early_param(). 1525 */ 1526 static void __init cpu_parse_early_param(void) 1527 { 1528 char arg[128]; 1529 char *argptr = arg, *opt; 1530 int arglen, taint = 0; 1531 1532 #ifdef CONFIG_X86_32 1533 if (cmdline_find_option_bool(boot_command_line, "no387")) 1534 #ifdef CONFIG_MATH_EMULATION 1535 setup_clear_cpu_cap(X86_FEATURE_FPU); 1536 #else 1537 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1538 #endif 1539 1540 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1541 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1542 #endif 1543 1544 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1545 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1546 1547 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1548 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1549 1550 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1551 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1552 1553 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1554 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1555 1556 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1557 if (arglen <= 0) 1558 return; 1559 1560 pr_info("Clearing CPUID bits:"); 1561 1562 while (argptr) { 1563 bool found __maybe_unused = false; 1564 unsigned int bit; 1565 1566 opt = strsep(&argptr, ","); 1567 1568 /* 1569 * Handle naked numbers first for feature flags which don't 1570 * have names. 1571 */ 1572 if (!kstrtouint(opt, 10, &bit)) { 1573 if (bit < NCAPINTS * 32) { 1574 1575 /* empty-string, i.e., ""-defined feature flags */ 1576 if (!x86_cap_flags[bit]) 1577 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1578 else 1579 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1580 1581 setup_clear_cpu_cap(bit); 1582 taint++; 1583 } 1584 /* 1585 * The assumption is that there are no feature names with only 1586 * numbers in the name thus go to the next argument. 1587 */ 1588 continue; 1589 } 1590 1591 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1592 if (!x86_cap_flag(bit)) 1593 continue; 1594 1595 if (strcmp(x86_cap_flag(bit), opt)) 1596 continue; 1597 1598 pr_cont(" %s", opt); 1599 setup_clear_cpu_cap(bit); 1600 taint++; 1601 found = true; 1602 break; 1603 } 1604 1605 if (!found) 1606 pr_cont(" (unknown: %s)", opt); 1607 } 1608 pr_cont("\n"); 1609 1610 if (taint) 1611 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1612 } 1613 1614 /* 1615 * Do minimum CPU detection early. 1616 * Fields really needed: vendor, cpuid_level, family, model, mask, 1617 * cache alignment. 1618 * The others are not touched to avoid unwanted side effects. 1619 * 1620 * WARNING: this function is only called on the boot CPU. Don't add code 1621 * here that is supposed to run on all CPUs. 1622 */ 1623 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1624 { 1625 #ifdef CONFIG_X86_64 1626 c->x86_clflush_size = 64; 1627 c->x86_phys_bits = 36; 1628 c->x86_virt_bits = 48; 1629 #else 1630 c->x86_clflush_size = 32; 1631 c->x86_phys_bits = 32; 1632 c->x86_virt_bits = 32; 1633 #endif 1634 c->x86_cache_alignment = c->x86_clflush_size; 1635 1636 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1637 c->extended_cpuid_level = 0; 1638 1639 if (!have_cpuid_p()) 1640 identify_cpu_without_cpuid(c); 1641 1642 /* cyrix could have cpuid enabled via c_identify()*/ 1643 if (have_cpuid_p()) { 1644 cpu_detect(c); 1645 get_cpu_vendor(c); 1646 get_cpu_cap(c); 1647 get_cpu_address_sizes(c); 1648 setup_force_cpu_cap(X86_FEATURE_CPUID); 1649 cpu_parse_early_param(); 1650 1651 if (this_cpu->c_early_init) 1652 this_cpu->c_early_init(c); 1653 1654 c->cpu_index = 0; 1655 filter_cpuid_features(c, false); 1656 1657 if (this_cpu->c_bsp_init) 1658 this_cpu->c_bsp_init(c); 1659 } else { 1660 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1661 } 1662 1663 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1664 1665 cpu_set_bug_bits(c); 1666 1667 sld_setup(c); 1668 1669 #ifdef CONFIG_X86_32 1670 /* 1671 * Regardless of whether PCID is enumerated, the SDM says 1672 * that it can't be enabled in 32-bit mode. 1673 */ 1674 setup_clear_cpu_cap(X86_FEATURE_PCID); 1675 #endif 1676 1677 /* 1678 * Later in the boot process pgtable_l5_enabled() relies on 1679 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1680 * enabled by this point we need to clear the feature bit to avoid 1681 * false-positives at the later stage. 1682 * 1683 * pgtable_l5_enabled() can be false here for several reasons: 1684 * - 5-level paging is disabled compile-time; 1685 * - it's 32-bit kernel; 1686 * - machine doesn't support 5-level paging; 1687 * - user specified 'no5lvl' in kernel command line. 1688 */ 1689 if (!pgtable_l5_enabled()) 1690 setup_clear_cpu_cap(X86_FEATURE_LA57); 1691 1692 detect_nopl(); 1693 } 1694 1695 void __init early_cpu_init(void) 1696 { 1697 const struct cpu_dev *const *cdev; 1698 int count = 0; 1699 1700 #ifdef CONFIG_PROCESSOR_SELECT 1701 pr_info("KERNEL supported cpus:\n"); 1702 #endif 1703 1704 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1705 const struct cpu_dev *cpudev = *cdev; 1706 1707 if (count >= X86_VENDOR_NUM) 1708 break; 1709 cpu_devs[count] = cpudev; 1710 count++; 1711 1712 #ifdef CONFIG_PROCESSOR_SELECT 1713 { 1714 unsigned int j; 1715 1716 for (j = 0; j < 2; j++) { 1717 if (!cpudev->c_ident[j]) 1718 continue; 1719 pr_info(" %s %s\n", cpudev->c_vendor, 1720 cpudev->c_ident[j]); 1721 } 1722 } 1723 #endif 1724 } 1725 early_identify_cpu(&boot_cpu_data); 1726 } 1727 1728 static bool detect_null_seg_behavior(void) 1729 { 1730 /* 1731 * Empirically, writing zero to a segment selector on AMD does 1732 * not clear the base, whereas writing zero to a segment 1733 * selector on Intel does clear the base. Intel's behavior 1734 * allows slightly faster context switches in the common case 1735 * where GS is unused by the prev and next threads. 1736 * 1737 * Since neither vendor documents this anywhere that I can see, 1738 * detect it directly instead of hard-coding the choice by 1739 * vendor. 1740 * 1741 * I've designated AMD's behavior as the "bug" because it's 1742 * counterintuitive and less friendly. 1743 */ 1744 1745 unsigned long old_base, tmp; 1746 rdmsrl(MSR_FS_BASE, old_base); 1747 wrmsrl(MSR_FS_BASE, 1); 1748 loadsegment(fs, 0); 1749 rdmsrl(MSR_FS_BASE, tmp); 1750 wrmsrl(MSR_FS_BASE, old_base); 1751 return tmp == 0; 1752 } 1753 1754 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1755 { 1756 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1757 if (!IS_ENABLED(CONFIG_X86_64)) 1758 return; 1759 1760 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1761 return; 1762 1763 /* 1764 * CPUID bit above wasn't set. If this kernel is still running 1765 * as a HV guest, then the HV has decided not to advertize 1766 * that CPUID bit for whatever reason. For example, one 1767 * member of the migration pool might be vulnerable. Which 1768 * means, the bug is present: set the BUG flag and return. 1769 */ 1770 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1771 set_cpu_bug(c, X86_BUG_NULL_SEG); 1772 return; 1773 } 1774 1775 /* 1776 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1777 * 0x18 is the respective family for Hygon. 1778 */ 1779 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1780 detect_null_seg_behavior()) 1781 return; 1782 1783 /* All the remaining ones are affected */ 1784 set_cpu_bug(c, X86_BUG_NULL_SEG); 1785 } 1786 1787 static void generic_identify(struct cpuinfo_x86 *c) 1788 { 1789 c->extended_cpuid_level = 0; 1790 1791 if (!have_cpuid_p()) 1792 identify_cpu_without_cpuid(c); 1793 1794 /* cyrix could have cpuid enabled via c_identify()*/ 1795 if (!have_cpuid_p()) 1796 return; 1797 1798 cpu_detect(c); 1799 1800 get_cpu_vendor(c); 1801 1802 get_cpu_cap(c); 1803 1804 get_cpu_address_sizes(c); 1805 1806 if (c->cpuid_level >= 0x00000001) { 1807 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1808 #ifdef CONFIG_X86_32 1809 # ifdef CONFIG_SMP 1810 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1811 # else 1812 c->apicid = c->initial_apicid; 1813 # endif 1814 #endif 1815 c->phys_proc_id = c->initial_apicid; 1816 } 1817 1818 get_model_name(c); /* Default name */ 1819 1820 /* 1821 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1822 * systems that run Linux at CPL > 0 may or may not have the 1823 * issue, but, even if they have the issue, there's absolutely 1824 * nothing we can do about it because we can't use the real IRET 1825 * instruction. 1826 * 1827 * NB: For the time being, only 32-bit kernels support 1828 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1829 * whether to apply espfix using paravirt hooks. If any 1830 * non-paravirt system ever shows up that does *not* have the 1831 * ESPFIX issue, we can change this. 1832 */ 1833 #ifdef CONFIG_X86_32 1834 set_cpu_bug(c, X86_BUG_ESPFIX); 1835 #endif 1836 } 1837 1838 /* 1839 * Validate that ACPI/mptables have the same information about the 1840 * effective APIC id and update the package map. 1841 */ 1842 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1843 { 1844 #ifdef CONFIG_SMP 1845 unsigned int apicid, cpu = smp_processor_id(); 1846 1847 apicid = apic->cpu_present_to_apicid(cpu); 1848 1849 if (apicid != c->apicid) { 1850 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1851 cpu, apicid, c->initial_apicid); 1852 } 1853 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1854 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1855 #else 1856 c->logical_proc_id = 0; 1857 #endif 1858 } 1859 1860 /* 1861 * This does the hard work of actually picking apart the CPU stuff... 1862 */ 1863 static void identify_cpu(struct cpuinfo_x86 *c) 1864 { 1865 int i; 1866 1867 c->loops_per_jiffy = loops_per_jiffy; 1868 c->x86_cache_size = 0; 1869 c->x86_vendor = X86_VENDOR_UNKNOWN; 1870 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1871 c->x86_vendor_id[0] = '\0'; /* Unset */ 1872 c->x86_model_id[0] = '\0'; /* Unset */ 1873 c->x86_max_cores = 1; 1874 c->x86_coreid_bits = 0; 1875 c->cu_id = 0xff; 1876 #ifdef CONFIG_X86_64 1877 c->x86_clflush_size = 64; 1878 c->x86_phys_bits = 36; 1879 c->x86_virt_bits = 48; 1880 #else 1881 c->cpuid_level = -1; /* CPUID not detected */ 1882 c->x86_clflush_size = 32; 1883 c->x86_phys_bits = 32; 1884 c->x86_virt_bits = 32; 1885 #endif 1886 c->x86_cache_alignment = c->x86_clflush_size; 1887 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1888 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1889 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1890 #endif 1891 1892 generic_identify(c); 1893 1894 if (this_cpu->c_identify) 1895 this_cpu->c_identify(c); 1896 1897 /* Clear/Set all flags overridden by options, after probe */ 1898 apply_forced_caps(c); 1899 1900 #ifdef CONFIG_X86_64 1901 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1902 #endif 1903 1904 1905 /* 1906 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 1907 * Hygon will clear it in ->c_init() below. 1908 */ 1909 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1910 1911 /* 1912 * Vendor-specific initialization. In this section we 1913 * canonicalize the feature flags, meaning if there are 1914 * features a certain CPU supports which CPUID doesn't 1915 * tell us, CPUID claiming incorrect flags, or other bugs, 1916 * we handle them here. 1917 * 1918 * At the end of this section, c->x86_capability better 1919 * indicate the features this CPU genuinely supports! 1920 */ 1921 if (this_cpu->c_init) 1922 this_cpu->c_init(c); 1923 1924 /* Disable the PN if appropriate */ 1925 squash_the_stupid_serial_number(c); 1926 1927 /* Set up SMEP/SMAP/UMIP */ 1928 setup_smep(c); 1929 setup_smap(c); 1930 setup_umip(c); 1931 1932 /* Enable FSGSBASE instructions if available. */ 1933 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1934 cr4_set_bits(X86_CR4_FSGSBASE); 1935 elf_hwcap2 |= HWCAP2_FSGSBASE; 1936 } 1937 1938 /* 1939 * The vendor-specific functions might have changed features. 1940 * Now we do "generic changes." 1941 */ 1942 1943 /* Filter out anything that depends on CPUID levels we don't have */ 1944 filter_cpuid_features(c, true); 1945 1946 /* If the model name is still unset, do table lookup. */ 1947 if (!c->x86_model_id[0]) { 1948 const char *p; 1949 p = table_lookup_model(c); 1950 if (p) 1951 strcpy(c->x86_model_id, p); 1952 else 1953 /* Last resort... */ 1954 sprintf(c->x86_model_id, "%02x/%02x", 1955 c->x86, c->x86_model); 1956 } 1957 1958 #ifdef CONFIG_X86_64 1959 detect_ht(c); 1960 #endif 1961 1962 x86_init_rdrand(c); 1963 setup_pku(c); 1964 setup_cet(c); 1965 1966 /* 1967 * Clear/Set all flags overridden by options, need do it 1968 * before following smp all cpus cap AND. 1969 */ 1970 apply_forced_caps(c); 1971 1972 /* 1973 * On SMP, boot_cpu_data holds the common feature set between 1974 * all CPUs; so make sure that we indicate which features are 1975 * common between the CPUs. The first time this routine gets 1976 * executed, c == &boot_cpu_data. 1977 */ 1978 if (c != &boot_cpu_data) { 1979 /* AND the already accumulated flags with these */ 1980 for (i = 0; i < NCAPINTS; i++) 1981 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1982 1983 /* OR, i.e. replicate the bug flags */ 1984 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1985 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1986 } 1987 1988 ppin_init(c); 1989 1990 /* Init Machine Check Exception if available. */ 1991 mcheck_cpu_init(c); 1992 1993 select_idle_routine(c); 1994 1995 #ifdef CONFIG_NUMA 1996 numa_add_cpu(smp_processor_id()); 1997 #endif 1998 } 1999 2000 /* 2001 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 2002 * on 32-bit kernels: 2003 */ 2004 #ifdef CONFIG_X86_32 2005 void enable_sep_cpu(void) 2006 { 2007 struct tss_struct *tss; 2008 int cpu; 2009 2010 if (!boot_cpu_has(X86_FEATURE_SEP)) 2011 return; 2012 2013 cpu = get_cpu(); 2014 tss = &per_cpu(cpu_tss_rw, cpu); 2015 2016 /* 2017 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 2018 * see the big comment in struct x86_hw_tss's definition. 2019 */ 2020 2021 tss->x86_tss.ss1 = __KERNEL_CS; 2022 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 2023 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 2024 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 2025 2026 put_cpu(); 2027 } 2028 #endif 2029 2030 static __init void identify_boot_cpu(void) 2031 { 2032 identify_cpu(&boot_cpu_data); 2033 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 2034 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 2035 #ifdef CONFIG_X86_32 2036 enable_sep_cpu(); 2037 #endif 2038 cpu_detect_tlb(&boot_cpu_data); 2039 setup_cr_pinning(); 2040 2041 tsx_init(); 2042 lkgs_init(); 2043 } 2044 2045 void identify_secondary_cpu(struct cpuinfo_x86 *c) 2046 { 2047 BUG_ON(c == &boot_cpu_data); 2048 identify_cpu(c); 2049 #ifdef CONFIG_X86_32 2050 enable_sep_cpu(); 2051 #endif 2052 validate_apic_and_package_id(c); 2053 x86_spec_ctrl_setup_ap(); 2054 update_srbds_msr(); 2055 if (boot_cpu_has_bug(X86_BUG_GDS)) 2056 update_gds_msr(); 2057 2058 tsx_ap_init(); 2059 } 2060 2061 void print_cpu_info(struct cpuinfo_x86 *c) 2062 { 2063 const char *vendor = NULL; 2064 2065 if (c->x86_vendor < X86_VENDOR_NUM) { 2066 vendor = this_cpu->c_vendor; 2067 } else { 2068 if (c->cpuid_level >= 0) 2069 vendor = c->x86_vendor_id; 2070 } 2071 2072 if (vendor && !strstr(c->x86_model_id, vendor)) 2073 pr_cont("%s ", vendor); 2074 2075 if (c->x86_model_id[0]) 2076 pr_cont("%s", c->x86_model_id); 2077 else 2078 pr_cont("%d86", c->x86); 2079 2080 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2081 2082 if (c->x86_stepping || c->cpuid_level >= 0) 2083 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2084 else 2085 pr_cont(")\n"); 2086 } 2087 2088 /* 2089 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 2090 * function prevents it from becoming an environment variable for init. 2091 */ 2092 static __init int setup_clearcpuid(char *arg) 2093 { 2094 return 1; 2095 } 2096 __setup("clearcpuid=", setup_clearcpuid); 2097 2098 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = { 2099 .current_task = &init_task, 2100 .preempt_count = INIT_PREEMPT_COUNT, 2101 .top_of_stack = TOP_OF_INIT_STACK, 2102 }; 2103 EXPORT_PER_CPU_SYMBOL(pcpu_hot); 2104 2105 #ifdef CONFIG_X86_64 2106 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 2107 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 2108 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2109 2110 static void wrmsrl_cstar(unsigned long val) 2111 { 2112 /* 2113 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2114 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2115 * guest. Avoid the pointless write on all Intel CPUs. 2116 */ 2117 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2118 wrmsrl(MSR_CSTAR, val); 2119 } 2120 2121 /* May not be marked __init: used by software suspend */ 2122 void syscall_init(void) 2123 { 2124 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2125 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2126 2127 #ifdef CONFIG_IA32_EMULATION 2128 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2129 /* 2130 * This only works on Intel CPUs. 2131 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2132 * This does not cause SYSENTER to jump to the wrong location, because 2133 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2134 */ 2135 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2136 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2137 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2138 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2139 #else 2140 wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore); 2141 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2142 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2143 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2144 #endif 2145 2146 /* 2147 * Flags to clear on syscall; clear as much as possible 2148 * to minimize user space-kernel interference. 2149 */ 2150 wrmsrl(MSR_SYSCALL_MASK, 2151 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2152 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2153 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2154 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2155 X86_EFLAGS_AC|X86_EFLAGS_ID); 2156 } 2157 2158 #else /* CONFIG_X86_64 */ 2159 2160 #ifdef CONFIG_STACKPROTECTOR 2161 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2162 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2163 #endif 2164 2165 #endif /* CONFIG_X86_64 */ 2166 2167 /* 2168 * Clear all 6 debug registers: 2169 */ 2170 static void clear_all_debug_regs(void) 2171 { 2172 int i; 2173 2174 for (i = 0; i < 8; i++) { 2175 /* Ignore db4, db5 */ 2176 if ((i == 4) || (i == 5)) 2177 continue; 2178 2179 set_debugreg(0, i); 2180 } 2181 } 2182 2183 #ifdef CONFIG_KGDB 2184 /* 2185 * Restore debug regs if using kgdbwait and you have a kernel debugger 2186 * connection established. 2187 */ 2188 static void dbg_restore_debug_regs(void) 2189 { 2190 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2191 arch_kgdb_ops.correct_hw_break(); 2192 } 2193 #else /* ! CONFIG_KGDB */ 2194 #define dbg_restore_debug_regs() 2195 #endif /* ! CONFIG_KGDB */ 2196 2197 static inline void setup_getcpu(int cpu) 2198 { 2199 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2200 struct desc_struct d = { }; 2201 2202 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2203 wrmsr(MSR_TSC_AUX, cpudata, 0); 2204 2205 /* Store CPU and node number in limit. */ 2206 d.limit0 = cpudata; 2207 d.limit1 = cpudata >> 16; 2208 2209 d.type = 5; /* RO data, expand down, accessed */ 2210 d.dpl = 3; /* Visible to user code */ 2211 d.s = 1; /* Not a system segment */ 2212 d.p = 1; /* Present */ 2213 d.d = 1; /* 32-bit */ 2214 2215 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2216 } 2217 2218 #ifdef CONFIG_X86_64 2219 static inline void ucode_cpu_init(int cpu) { } 2220 2221 static inline void tss_setup_ist(struct tss_struct *tss) 2222 { 2223 /* Set up the per-CPU TSS IST stacks */ 2224 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2225 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2226 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2227 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2228 /* Only mapped when SEV-ES is active */ 2229 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2230 } 2231 2232 #else /* CONFIG_X86_64 */ 2233 2234 static inline void ucode_cpu_init(int cpu) 2235 { 2236 show_ucode_info_early(); 2237 } 2238 2239 static inline void tss_setup_ist(struct tss_struct *tss) { } 2240 2241 #endif /* !CONFIG_X86_64 */ 2242 2243 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2244 { 2245 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2246 2247 #ifdef CONFIG_X86_IOPL_IOPERM 2248 tss->io_bitmap.prev_max = 0; 2249 tss->io_bitmap.prev_sequence = 0; 2250 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2251 /* 2252 * Invalidate the extra array entry past the end of the all 2253 * permission bitmap as required by the hardware. 2254 */ 2255 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2256 #endif 2257 } 2258 2259 /* 2260 * Setup everything needed to handle exceptions from the IDT, including the IST 2261 * exceptions which use paranoid_entry(). 2262 */ 2263 void cpu_init_exception_handling(void) 2264 { 2265 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2266 int cpu = raw_smp_processor_id(); 2267 2268 /* paranoid_entry() gets the CPU number from the GDT */ 2269 setup_getcpu(cpu); 2270 2271 /* IST vectors need TSS to be set up. */ 2272 tss_setup_ist(tss); 2273 tss_setup_io_bitmap(tss); 2274 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2275 2276 load_TR_desc(); 2277 2278 /* GHCB needs to be setup to handle #VC. */ 2279 setup_ghcb(); 2280 2281 /* Finally load the IDT */ 2282 load_current_idt(); 2283 } 2284 2285 /* 2286 * cpu_init() initializes state that is per-CPU. Some data is already 2287 * initialized (naturally) in the bootstrap process, such as the GDT. We 2288 * reload it nevertheless, this function acts as a 'CPU state barrier', 2289 * nothing should get across. 2290 */ 2291 void cpu_init(void) 2292 { 2293 struct task_struct *cur = current; 2294 int cpu = raw_smp_processor_id(); 2295 2296 ucode_cpu_init(cpu); 2297 2298 #ifdef CONFIG_NUMA 2299 if (this_cpu_read(numa_node) == 0 && 2300 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2301 set_numa_node(early_cpu_to_node(cpu)); 2302 #endif 2303 pr_debug("Initializing CPU#%d\n", cpu); 2304 2305 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2306 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2307 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2308 2309 if (IS_ENABLED(CONFIG_X86_64)) { 2310 loadsegment(fs, 0); 2311 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2312 syscall_init(); 2313 2314 wrmsrl(MSR_FS_BASE, 0); 2315 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2316 barrier(); 2317 2318 x2apic_setup(); 2319 } 2320 2321 mmgrab(&init_mm); 2322 cur->active_mm = &init_mm; 2323 BUG_ON(cur->mm); 2324 initialize_tlbstate_and_flush(); 2325 enter_lazy_tlb(&init_mm, cur); 2326 2327 /* 2328 * sp0 points to the entry trampoline stack regardless of what task 2329 * is running. 2330 */ 2331 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2332 2333 load_mm_ldt(&init_mm); 2334 2335 clear_all_debug_regs(); 2336 dbg_restore_debug_regs(); 2337 2338 doublefault_init_cpu_tss(); 2339 2340 if (is_uv_system()) 2341 uv_cpu_init(); 2342 2343 load_fixmap_gdt(cpu); 2344 } 2345 2346 #ifdef CONFIG_MICROCODE_LATE_LOADING 2347 /** 2348 * store_cpu_caps() - Store a snapshot of CPU capabilities 2349 * @curr_info: Pointer where to store it 2350 * 2351 * Returns: None 2352 */ 2353 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2354 { 2355 /* Reload CPUID max function as it might've changed. */ 2356 curr_info->cpuid_level = cpuid_eax(0); 2357 2358 /* Copy all capability leafs and pick up the synthetic ones. */ 2359 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2360 sizeof(curr_info->x86_capability)); 2361 2362 /* Get the hardware CPUID leafs */ 2363 get_cpu_cap(curr_info); 2364 } 2365 2366 /** 2367 * microcode_check() - Check if any CPU capabilities changed after an update. 2368 * @prev_info: CPU capabilities stored before an update. 2369 * 2370 * The microcode loader calls this upon late microcode load to recheck features, 2371 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2372 * 2373 * Return: None 2374 */ 2375 void microcode_check(struct cpuinfo_x86 *prev_info) 2376 { 2377 struct cpuinfo_x86 curr_info; 2378 2379 perf_check_microcode(); 2380 2381 amd_check_microcode(); 2382 2383 store_cpu_caps(&curr_info); 2384 2385 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2386 sizeof(prev_info->x86_capability))) 2387 return; 2388 2389 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2390 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2391 } 2392 #endif 2393 2394 /* 2395 * Invoked from core CPU hotplug code after hotplug operations 2396 */ 2397 void arch_smt_update(void) 2398 { 2399 /* Handle the speculative execution misfeatures */ 2400 cpu_bugs_smt_update(); 2401 /* Check whether IPI broadcasting can be enabled */ 2402 apic_smt_update(); 2403 } 2404 2405 void __init arch_cpu_finalize_init(void) 2406 { 2407 identify_boot_cpu(); 2408 2409 /* 2410 * identify_boot_cpu() initialized SMT support information, let the 2411 * core code know. 2412 */ 2413 cpu_smt_set_num_threads(smp_num_siblings, smp_num_siblings); 2414 2415 if (!IS_ENABLED(CONFIG_SMP)) { 2416 pr_info("CPU: "); 2417 print_cpu_info(&boot_cpu_data); 2418 } 2419 2420 cpu_select_mitigations(); 2421 2422 arch_smt_update(); 2423 2424 if (IS_ENABLED(CONFIG_X86_32)) { 2425 /* 2426 * Check whether this is a real i386 which is not longer 2427 * supported and fixup the utsname. 2428 */ 2429 if (boot_cpu_data.x86 < 4) 2430 panic("Kernel requires i486+ for 'invlpg' and other features"); 2431 2432 init_utsname()->machine[1] = 2433 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2434 } 2435 2436 /* 2437 * Must be before alternatives because it might set or clear 2438 * feature bits. 2439 */ 2440 fpu__init_system(); 2441 fpu__init_cpu(); 2442 2443 alternative_instructions(); 2444 2445 if (IS_ENABLED(CONFIG_X86_64)) { 2446 /* 2447 * Make sure the first 2MB area is not mapped by huge pages 2448 * There are typically fixed size MTRRs in there and overlapping 2449 * MTRRs into large pages causes slow downs. 2450 * 2451 * Right now we don't do that with gbpages because there seems 2452 * very little benefit for that case. 2453 */ 2454 if (!direct_gbpages) 2455 set_memory_4k((unsigned long)__va(0), 1); 2456 } else { 2457 fpu__init_check_bugs(); 2458 } 2459 2460 /* 2461 * This needs to be called before any devices perform DMA 2462 * operations that might use the SWIOTLB bounce buffers. It will 2463 * mark the bounce buffers as decrypted so that their usage will 2464 * not cause "plain-text" data to be decrypted when accessed. It 2465 * must be called after late_time_init() so that Hyper-V x86/x64 2466 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2467 */ 2468 mem_encrypt_init(); 2469 } 2470