1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 51 #ifdef CONFIG_X86_LOCAL_APIC 52 #include <asm/uv/uv.h> 53 #endif 54 55 #include "cpu.h" 56 57 u32 elf_hwcap2 __read_mostly; 58 59 /* all of these masks are initialized in setup_cpu_local_masks() */ 60 cpumask_var_t cpu_initialized_mask; 61 cpumask_var_t cpu_callout_mask; 62 cpumask_var_t cpu_callin_mask; 63 64 /* representing cpus for which sibling maps can be computed */ 65 cpumask_var_t cpu_sibling_setup_mask; 66 67 /* correctly size the local cpu masks */ 68 void __init setup_cpu_local_masks(void) 69 { 70 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 71 alloc_bootmem_cpumask_var(&cpu_callin_mask); 72 alloc_bootmem_cpumask_var(&cpu_callout_mask); 73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 74 } 75 76 static void default_init(struct cpuinfo_x86 *c) 77 { 78 #ifdef CONFIG_X86_64 79 cpu_detect_cache_sizes(c); 80 #else 81 /* Not much we can do here... */ 82 /* Check if at least it has cpuid */ 83 if (c->cpuid_level == -1) { 84 /* No cpuid. It must be an ancient CPU */ 85 if (c->x86 == 4) 86 strcpy(c->x86_model_id, "486"); 87 else if (c->x86 == 3) 88 strcpy(c->x86_model_id, "386"); 89 } 90 #endif 91 } 92 93 static const struct cpu_dev default_cpu = { 94 .c_init = default_init, 95 .c_vendor = "Unknown", 96 .c_x86_vendor = X86_VENDOR_UNKNOWN, 97 }; 98 99 static const struct cpu_dev *this_cpu = &default_cpu; 100 101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 102 #ifdef CONFIG_X86_64 103 /* 104 * We need valid kernel segments for data and code in long mode too 105 * IRET will check the segment types kkeil 2000/10/28 106 * Also sysret mandates a special GDT layout 107 * 108 * TLS descriptors are currently at a different place compared to i386. 109 * Hopefully nobody expects them at a fixed place (Wine?) 110 */ 111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 117 #else 118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 122 /* 123 * Segments used for calling PnP BIOS have byte granularity. 124 * They code segments and data segments have fixed 64k limits, 125 * the transfer segment sizes are set at run time. 126 */ 127 /* 32-bit code */ 128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 129 /* 16-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 131 /* 16-bit data */ 132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 138 * The APM segments have byte granularity and their bases 139 * are set at run time. All have 64k limits. 140 */ 141 /* 32-bit code */ 142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 143 /* 16-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 145 /* data */ 146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 147 148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 150 GDT_STACK_CANARY_INIT 151 #endif 152 } }; 153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 154 155 static int __init x86_mpx_setup(char *s) 156 { 157 /* require an exact match without trailing characters */ 158 if (strlen(s)) 159 return 0; 160 161 /* do not emit a message if the feature is not present */ 162 if (!boot_cpu_has(X86_FEATURE_MPX)) 163 return 1; 164 165 setup_clear_cpu_cap(X86_FEATURE_MPX); 166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 167 return 1; 168 } 169 __setup("nompx", x86_mpx_setup); 170 171 static int __init x86_noinvpcid_setup(char *s) 172 { 173 /* noinvpcid doesn't accept parameters */ 174 if (s) 175 return -EINVAL; 176 177 /* do not emit a message if the feature is not present */ 178 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 179 return 0; 180 181 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 182 pr_info("noinvpcid: INVPCID feature disabled\n"); 183 return 0; 184 } 185 early_param("noinvpcid", x86_noinvpcid_setup); 186 187 #ifdef CONFIG_X86_32 188 static int cachesize_override = -1; 189 static int disable_x86_serial_nr = 1; 190 191 static int __init cachesize_setup(char *str) 192 { 193 get_option(&str, &cachesize_override); 194 return 1; 195 } 196 __setup("cachesize=", cachesize_setup); 197 198 static int __init x86_sep_setup(char *s) 199 { 200 setup_clear_cpu_cap(X86_FEATURE_SEP); 201 return 1; 202 } 203 __setup("nosep", x86_sep_setup); 204 205 /* Standard macro to see if a specific flag is changeable */ 206 static inline int flag_is_changeable_p(u32 flag) 207 { 208 u32 f1, f2; 209 210 /* 211 * Cyrix and IDT cpus allow disabling of CPUID 212 * so the code below may return different results 213 * when it is executed before and after enabling 214 * the CPUID. Add "volatile" to not allow gcc to 215 * optimize the subsequent calls to this function. 216 */ 217 asm volatile ("pushfl \n\t" 218 "pushfl \n\t" 219 "popl %0 \n\t" 220 "movl %0, %1 \n\t" 221 "xorl %2, %0 \n\t" 222 "pushl %0 \n\t" 223 "popfl \n\t" 224 "pushfl \n\t" 225 "popl %0 \n\t" 226 "popfl \n\t" 227 228 : "=&r" (f1), "=&r" (f2) 229 : "ir" (flag)); 230 231 return ((f1^f2) & flag) != 0; 232 } 233 234 /* Probe for the CPUID instruction */ 235 int have_cpuid_p(void) 236 { 237 return flag_is_changeable_p(X86_EFLAGS_ID); 238 } 239 240 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 241 { 242 unsigned long lo, hi; 243 244 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 245 return; 246 247 /* Disable processor serial number: */ 248 249 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 250 lo |= 0x200000; 251 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 252 253 pr_notice("CPU serial number disabled.\n"); 254 clear_cpu_cap(c, X86_FEATURE_PN); 255 256 /* Disabling the serial number may affect the cpuid level */ 257 c->cpuid_level = cpuid_eax(0); 258 } 259 260 static int __init x86_serial_nr_setup(char *s) 261 { 262 disable_x86_serial_nr = 0; 263 return 1; 264 } 265 __setup("serialnumber", x86_serial_nr_setup); 266 #else 267 static inline int flag_is_changeable_p(u32 flag) 268 { 269 return 1; 270 } 271 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 272 { 273 } 274 #endif 275 276 static __init int setup_disable_smep(char *arg) 277 { 278 setup_clear_cpu_cap(X86_FEATURE_SMEP); 279 /* Check for things that depend on SMEP being enabled: */ 280 check_mpx_erratum(&boot_cpu_data); 281 return 1; 282 } 283 __setup("nosmep", setup_disable_smep); 284 285 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 286 { 287 if (cpu_has(c, X86_FEATURE_SMEP)) 288 cr4_set_bits(X86_CR4_SMEP); 289 } 290 291 static __init int setup_disable_smap(char *arg) 292 { 293 setup_clear_cpu_cap(X86_FEATURE_SMAP); 294 return 1; 295 } 296 __setup("nosmap", setup_disable_smap); 297 298 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 299 { 300 unsigned long eflags = native_save_fl(); 301 302 /* This should have been cleared long ago */ 303 BUG_ON(eflags & X86_EFLAGS_AC); 304 305 if (cpu_has(c, X86_FEATURE_SMAP)) { 306 #ifdef CONFIG_X86_SMAP 307 cr4_set_bits(X86_CR4_SMAP); 308 #else 309 cr4_clear_bits(X86_CR4_SMAP); 310 #endif 311 } 312 } 313 314 /* 315 * Protection Keys are not available in 32-bit mode. 316 */ 317 static bool pku_disabled; 318 319 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 320 { 321 /* check the boot processor, plus compile options for PKU: */ 322 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 323 return; 324 /* checks the actual processor's cpuid bits: */ 325 if (!cpu_has(c, X86_FEATURE_PKU)) 326 return; 327 if (pku_disabled) 328 return; 329 330 cr4_set_bits(X86_CR4_PKE); 331 /* 332 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 333 * cpuid bit to be set. We need to ensure that we 334 * update that bit in this CPU's "cpu_info". 335 */ 336 get_cpu_cap(c); 337 } 338 339 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 340 static __init int setup_disable_pku(char *arg) 341 { 342 /* 343 * Do not clear the X86_FEATURE_PKU bit. All of the 344 * runtime checks are against OSPKE so clearing the 345 * bit does nothing. 346 * 347 * This way, we will see "pku" in cpuinfo, but not 348 * "ospke", which is exactly what we want. It shows 349 * that the CPU has PKU, but the OS has not enabled it. 350 * This happens to be exactly how a system would look 351 * if we disabled the config option. 352 */ 353 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 354 pku_disabled = true; 355 return 1; 356 } 357 __setup("nopku", setup_disable_pku); 358 #endif /* CONFIG_X86_64 */ 359 360 /* 361 * Some CPU features depend on higher CPUID levels, which may not always 362 * be available due to CPUID level capping or broken virtualization 363 * software. Add those features to this table to auto-disable them. 364 */ 365 struct cpuid_dependent_feature { 366 u32 feature; 367 u32 level; 368 }; 369 370 static const struct cpuid_dependent_feature 371 cpuid_dependent_features[] = { 372 { X86_FEATURE_MWAIT, 0x00000005 }, 373 { X86_FEATURE_DCA, 0x00000009 }, 374 { X86_FEATURE_XSAVE, 0x0000000d }, 375 { 0, 0 } 376 }; 377 378 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 379 { 380 const struct cpuid_dependent_feature *df; 381 382 for (df = cpuid_dependent_features; df->feature; df++) { 383 384 if (!cpu_has(c, df->feature)) 385 continue; 386 /* 387 * Note: cpuid_level is set to -1 if unavailable, but 388 * extended_extended_level is set to 0 if unavailable 389 * and the legitimate extended levels are all negative 390 * when signed; hence the weird messing around with 391 * signs here... 392 */ 393 if (!((s32)df->level < 0 ? 394 (u32)df->level > (u32)c->extended_cpuid_level : 395 (s32)df->level > (s32)c->cpuid_level)) 396 continue; 397 398 clear_cpu_cap(c, df->feature); 399 if (!warn) 400 continue; 401 402 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 403 x86_cap_flag(df->feature), df->level); 404 } 405 } 406 407 /* 408 * Naming convention should be: <Name> [(<Codename>)] 409 * This table only is used unless init_<vendor>() below doesn't set it; 410 * in particular, if CPUID levels 0x80000002..4 are supported, this 411 * isn't used 412 */ 413 414 /* Look up CPU names by table lookup. */ 415 static const char *table_lookup_model(struct cpuinfo_x86 *c) 416 { 417 #ifdef CONFIG_X86_32 418 const struct legacy_cpu_model_info *info; 419 420 if (c->x86_model >= 16) 421 return NULL; /* Range check */ 422 423 if (!this_cpu) 424 return NULL; 425 426 info = this_cpu->legacy_models; 427 428 while (info->family) { 429 if (info->family == c->x86) 430 return info->model_names[c->x86_model]; 431 info++; 432 } 433 #endif 434 return NULL; /* Not found */ 435 } 436 437 __u32 cpu_caps_cleared[NCAPINTS]; 438 __u32 cpu_caps_set[NCAPINTS]; 439 440 void load_percpu_segment(int cpu) 441 { 442 #ifdef CONFIG_X86_32 443 loadsegment(fs, __KERNEL_PERCPU); 444 #else 445 __loadsegment_simple(gs, 0); 446 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 447 #endif 448 load_stack_canary_segment(); 449 } 450 451 /* 452 * Current gdt points %fs at the "master" per-cpu area: after this, 453 * it's on the real one. 454 */ 455 void switch_to_new_gdt(int cpu) 456 { 457 struct desc_ptr gdt_descr; 458 459 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 460 gdt_descr.size = GDT_SIZE - 1; 461 load_gdt(&gdt_descr); 462 /* Reload the per-cpu base */ 463 464 load_percpu_segment(cpu); 465 } 466 467 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 468 469 static void get_model_name(struct cpuinfo_x86 *c) 470 { 471 unsigned int *v; 472 char *p, *q, *s; 473 474 if (c->extended_cpuid_level < 0x80000004) 475 return; 476 477 v = (unsigned int *)c->x86_model_id; 478 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 479 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 480 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 481 c->x86_model_id[48] = 0; 482 483 /* Trim whitespace */ 484 p = q = s = &c->x86_model_id[0]; 485 486 while (*p == ' ') 487 p++; 488 489 while (*p) { 490 /* Note the last non-whitespace index */ 491 if (!isspace(*p)) 492 s = q; 493 494 *q++ = *p++; 495 } 496 497 *(s + 1) = '\0'; 498 } 499 500 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 501 { 502 unsigned int n, dummy, ebx, ecx, edx, l2size; 503 504 n = c->extended_cpuid_level; 505 506 if (n >= 0x80000005) { 507 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 508 c->x86_cache_size = (ecx>>24) + (edx>>24); 509 #ifdef CONFIG_X86_64 510 /* On K8 L1 TLB is inclusive, so don't count it */ 511 c->x86_tlbsize = 0; 512 #endif 513 } 514 515 if (n < 0x80000006) /* Some chips just has a large L1. */ 516 return; 517 518 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 519 l2size = ecx >> 16; 520 521 #ifdef CONFIG_X86_64 522 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 523 #else 524 /* do processor-specific cache resizing */ 525 if (this_cpu->legacy_cache_size) 526 l2size = this_cpu->legacy_cache_size(c, l2size); 527 528 /* Allow user to override all this if necessary. */ 529 if (cachesize_override != -1) 530 l2size = cachesize_override; 531 532 if (l2size == 0) 533 return; /* Again, no L2 cache is possible */ 534 #endif 535 536 c->x86_cache_size = l2size; 537 } 538 539 u16 __read_mostly tlb_lli_4k[NR_INFO]; 540 u16 __read_mostly tlb_lli_2m[NR_INFO]; 541 u16 __read_mostly tlb_lli_4m[NR_INFO]; 542 u16 __read_mostly tlb_lld_4k[NR_INFO]; 543 u16 __read_mostly tlb_lld_2m[NR_INFO]; 544 u16 __read_mostly tlb_lld_4m[NR_INFO]; 545 u16 __read_mostly tlb_lld_1g[NR_INFO]; 546 547 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 548 { 549 if (this_cpu->c_detect_tlb) 550 this_cpu->c_detect_tlb(c); 551 552 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 553 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 554 tlb_lli_4m[ENTRIES]); 555 556 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 557 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 558 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 559 } 560 561 void detect_ht(struct cpuinfo_x86 *c) 562 { 563 #ifdef CONFIG_SMP 564 u32 eax, ebx, ecx, edx; 565 int index_msb, core_bits; 566 static bool printed; 567 568 if (!cpu_has(c, X86_FEATURE_HT)) 569 return; 570 571 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 572 goto out; 573 574 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 575 return; 576 577 cpuid(1, &eax, &ebx, &ecx, &edx); 578 579 smp_num_siblings = (ebx & 0xff0000) >> 16; 580 581 if (smp_num_siblings == 1) { 582 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 583 goto out; 584 } 585 586 if (smp_num_siblings <= 1) 587 goto out; 588 589 index_msb = get_count_order(smp_num_siblings); 590 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 591 592 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 593 594 index_msb = get_count_order(smp_num_siblings); 595 596 core_bits = get_count_order(c->x86_max_cores); 597 598 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 599 ((1 << core_bits) - 1); 600 601 out: 602 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 603 pr_info("CPU: Physical Processor ID: %d\n", 604 c->phys_proc_id); 605 pr_info("CPU: Processor Core ID: %d\n", 606 c->cpu_core_id); 607 printed = 1; 608 } 609 #endif 610 } 611 612 static void get_cpu_vendor(struct cpuinfo_x86 *c) 613 { 614 char *v = c->x86_vendor_id; 615 int i; 616 617 for (i = 0; i < X86_VENDOR_NUM; i++) { 618 if (!cpu_devs[i]) 619 break; 620 621 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 622 (cpu_devs[i]->c_ident[1] && 623 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 624 625 this_cpu = cpu_devs[i]; 626 c->x86_vendor = this_cpu->c_x86_vendor; 627 return; 628 } 629 } 630 631 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 632 "CPU: Your system may be unstable.\n", v); 633 634 c->x86_vendor = X86_VENDOR_UNKNOWN; 635 this_cpu = &default_cpu; 636 } 637 638 void cpu_detect(struct cpuinfo_x86 *c) 639 { 640 /* Get vendor name */ 641 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 642 (unsigned int *)&c->x86_vendor_id[0], 643 (unsigned int *)&c->x86_vendor_id[8], 644 (unsigned int *)&c->x86_vendor_id[4]); 645 646 c->x86 = 4; 647 /* Intel-defined flags: level 0x00000001 */ 648 if (c->cpuid_level >= 0x00000001) { 649 u32 junk, tfms, cap0, misc; 650 651 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 652 c->x86 = x86_family(tfms); 653 c->x86_model = x86_model(tfms); 654 c->x86_mask = x86_stepping(tfms); 655 656 if (cap0 & (1<<19)) { 657 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 658 c->x86_cache_alignment = c->x86_clflush_size; 659 } 660 } 661 } 662 663 static void apply_forced_caps(struct cpuinfo_x86 *c) 664 { 665 int i; 666 667 for (i = 0; i < NCAPINTS; i++) { 668 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 669 c->x86_capability[i] |= cpu_caps_set[i]; 670 } 671 } 672 673 void get_cpu_cap(struct cpuinfo_x86 *c) 674 { 675 u32 eax, ebx, ecx, edx; 676 677 /* Intel-defined flags: level 0x00000001 */ 678 if (c->cpuid_level >= 0x00000001) { 679 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 680 681 c->x86_capability[CPUID_1_ECX] = ecx; 682 c->x86_capability[CPUID_1_EDX] = edx; 683 } 684 685 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 686 if (c->cpuid_level >= 0x00000006) 687 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 688 689 /* Additional Intel-defined flags: level 0x00000007 */ 690 if (c->cpuid_level >= 0x00000007) { 691 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 692 c->x86_capability[CPUID_7_0_EBX] = ebx; 693 c->x86_capability[CPUID_7_ECX] = ecx; 694 } 695 696 /* Extended state features: level 0x0000000d */ 697 if (c->cpuid_level >= 0x0000000d) { 698 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 699 700 c->x86_capability[CPUID_D_1_EAX] = eax; 701 } 702 703 /* Additional Intel-defined flags: level 0x0000000F */ 704 if (c->cpuid_level >= 0x0000000F) { 705 706 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 707 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 708 c->x86_capability[CPUID_F_0_EDX] = edx; 709 710 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 711 /* will be overridden if occupancy monitoring exists */ 712 c->x86_cache_max_rmid = ebx; 713 714 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 715 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 716 c->x86_capability[CPUID_F_1_EDX] = edx; 717 718 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 719 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 720 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 721 c->x86_cache_max_rmid = ecx; 722 c->x86_cache_occ_scale = ebx; 723 } 724 } else { 725 c->x86_cache_max_rmid = -1; 726 c->x86_cache_occ_scale = -1; 727 } 728 } 729 730 /* AMD-defined flags: level 0x80000001 */ 731 eax = cpuid_eax(0x80000000); 732 c->extended_cpuid_level = eax; 733 734 if ((eax & 0xffff0000) == 0x80000000) { 735 if (eax >= 0x80000001) { 736 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 737 738 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 739 c->x86_capability[CPUID_8000_0001_EDX] = edx; 740 } 741 } 742 743 if (c->extended_cpuid_level >= 0x80000007) { 744 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 745 746 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 747 c->x86_power = edx; 748 } 749 750 if (c->extended_cpuid_level >= 0x80000008) { 751 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 752 753 c->x86_virt_bits = (eax >> 8) & 0xff; 754 c->x86_phys_bits = eax & 0xff; 755 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 756 } 757 #ifdef CONFIG_X86_32 758 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 759 c->x86_phys_bits = 36; 760 #endif 761 762 if (c->extended_cpuid_level >= 0x8000000a) 763 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 764 765 init_scattered_cpuid_features(c); 766 767 /* 768 * Clear/Set all flags overridden by options, after probe. 769 * This needs to happen each time we re-probe, which may happen 770 * several times during CPU initialization. 771 */ 772 apply_forced_caps(c); 773 } 774 775 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 776 { 777 #ifdef CONFIG_X86_32 778 int i; 779 780 /* 781 * First of all, decide if this is a 486 or higher 782 * It's a 486 if we can modify the AC flag 783 */ 784 if (flag_is_changeable_p(X86_EFLAGS_AC)) 785 c->x86 = 4; 786 else 787 c->x86 = 3; 788 789 for (i = 0; i < X86_VENDOR_NUM; i++) 790 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 791 c->x86_vendor_id[0] = 0; 792 cpu_devs[i]->c_identify(c); 793 if (c->x86_vendor_id[0]) { 794 get_cpu_vendor(c); 795 break; 796 } 797 } 798 #endif 799 } 800 801 /* 802 * Do minimum CPU detection early. 803 * Fields really needed: vendor, cpuid_level, family, model, mask, 804 * cache alignment. 805 * The others are not touched to avoid unwanted side effects. 806 * 807 * WARNING: this function is only called on the BP. Don't add code here 808 * that is supposed to run on all CPUs. 809 */ 810 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 811 { 812 #ifdef CONFIG_X86_64 813 c->x86_clflush_size = 64; 814 c->x86_phys_bits = 36; 815 c->x86_virt_bits = 48; 816 #else 817 c->x86_clflush_size = 32; 818 c->x86_phys_bits = 32; 819 c->x86_virt_bits = 32; 820 #endif 821 c->x86_cache_alignment = c->x86_clflush_size; 822 823 memset(&c->x86_capability, 0, sizeof c->x86_capability); 824 c->extended_cpuid_level = 0; 825 826 /* cyrix could have cpuid enabled via c_identify()*/ 827 if (have_cpuid_p()) { 828 cpu_detect(c); 829 get_cpu_vendor(c); 830 get_cpu_cap(c); 831 setup_force_cpu_cap(X86_FEATURE_CPUID); 832 833 if (this_cpu->c_early_init) 834 this_cpu->c_early_init(c); 835 836 c->cpu_index = 0; 837 filter_cpuid_features(c, false); 838 839 if (this_cpu->c_bsp_init) 840 this_cpu->c_bsp_init(c); 841 } else { 842 identify_cpu_without_cpuid(c); 843 setup_clear_cpu_cap(X86_FEATURE_CPUID); 844 } 845 846 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 847 fpu__init_system(c); 848 } 849 850 void __init early_cpu_init(void) 851 { 852 const struct cpu_dev *const *cdev; 853 int count = 0; 854 855 #ifdef CONFIG_PROCESSOR_SELECT 856 pr_info("KERNEL supported cpus:\n"); 857 #endif 858 859 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 860 const struct cpu_dev *cpudev = *cdev; 861 862 if (count >= X86_VENDOR_NUM) 863 break; 864 cpu_devs[count] = cpudev; 865 count++; 866 867 #ifdef CONFIG_PROCESSOR_SELECT 868 { 869 unsigned int j; 870 871 for (j = 0; j < 2; j++) { 872 if (!cpudev->c_ident[j]) 873 continue; 874 pr_info(" %s %s\n", cpudev->c_vendor, 875 cpudev->c_ident[j]); 876 } 877 } 878 #endif 879 } 880 early_identify_cpu(&boot_cpu_data); 881 } 882 883 /* 884 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 885 * unfortunately, that's not true in practice because of early VIA 886 * chips and (more importantly) broken virtualizers that are not easy 887 * to detect. In the latter case it doesn't even *fail* reliably, so 888 * probing for it doesn't even work. Disable it completely on 32-bit 889 * unless we can find a reliable way to detect all the broken cases. 890 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 891 */ 892 static void detect_nopl(struct cpuinfo_x86 *c) 893 { 894 #ifdef CONFIG_X86_32 895 clear_cpu_cap(c, X86_FEATURE_NOPL); 896 #else 897 set_cpu_cap(c, X86_FEATURE_NOPL); 898 #endif 899 } 900 901 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 902 { 903 #ifdef CONFIG_X86_64 904 /* 905 * Empirically, writing zero to a segment selector on AMD does 906 * not clear the base, whereas writing zero to a segment 907 * selector on Intel does clear the base. Intel's behavior 908 * allows slightly faster context switches in the common case 909 * where GS is unused by the prev and next threads. 910 * 911 * Since neither vendor documents this anywhere that I can see, 912 * detect it directly instead of hardcoding the choice by 913 * vendor. 914 * 915 * I've designated AMD's behavior as the "bug" because it's 916 * counterintuitive and less friendly. 917 */ 918 919 unsigned long old_base, tmp; 920 rdmsrl(MSR_FS_BASE, old_base); 921 wrmsrl(MSR_FS_BASE, 1); 922 loadsegment(fs, 0); 923 rdmsrl(MSR_FS_BASE, tmp); 924 if (tmp != 0) 925 set_cpu_bug(c, X86_BUG_NULL_SEG); 926 wrmsrl(MSR_FS_BASE, old_base); 927 #endif 928 } 929 930 static void generic_identify(struct cpuinfo_x86 *c) 931 { 932 c->extended_cpuid_level = 0; 933 934 if (!have_cpuid_p()) 935 identify_cpu_without_cpuid(c); 936 937 /* cyrix could have cpuid enabled via c_identify()*/ 938 if (!have_cpuid_p()) 939 return; 940 941 cpu_detect(c); 942 943 get_cpu_vendor(c); 944 945 get_cpu_cap(c); 946 947 if (c->cpuid_level >= 0x00000001) { 948 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 949 #ifdef CONFIG_X86_32 950 # ifdef CONFIG_SMP 951 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 952 # else 953 c->apicid = c->initial_apicid; 954 # endif 955 #endif 956 c->phys_proc_id = c->initial_apicid; 957 } 958 959 get_model_name(c); /* Default name */ 960 961 detect_nopl(c); 962 963 detect_null_seg_behavior(c); 964 965 /* 966 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 967 * systems that run Linux at CPL > 0 may or may not have the 968 * issue, but, even if they have the issue, there's absolutely 969 * nothing we can do about it because we can't use the real IRET 970 * instruction. 971 * 972 * NB: For the time being, only 32-bit kernels support 973 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 974 * whether to apply espfix using paravirt hooks. If any 975 * non-paravirt system ever shows up that does *not* have the 976 * ESPFIX issue, we can change this. 977 */ 978 #ifdef CONFIG_X86_32 979 # ifdef CONFIG_PARAVIRT 980 do { 981 extern void native_iret(void); 982 if (pv_cpu_ops.iret == native_iret) 983 set_cpu_bug(c, X86_BUG_ESPFIX); 984 } while (0); 985 # else 986 set_cpu_bug(c, X86_BUG_ESPFIX); 987 # endif 988 #endif 989 } 990 991 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 992 { 993 /* 994 * The heavy lifting of max_rmid and cache_occ_scale are handled 995 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 996 * in case CQM bits really aren't there in this CPU. 997 */ 998 if (c != &boot_cpu_data) { 999 boot_cpu_data.x86_cache_max_rmid = 1000 min(boot_cpu_data.x86_cache_max_rmid, 1001 c->x86_cache_max_rmid); 1002 } 1003 } 1004 1005 /* 1006 * Validate that ACPI/mptables have the same information about the 1007 * effective APIC id and update the package map. 1008 */ 1009 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1010 { 1011 #ifdef CONFIG_SMP 1012 unsigned int apicid, cpu = smp_processor_id(); 1013 1014 apicid = apic->cpu_present_to_apicid(cpu); 1015 1016 if (apicid != c->apicid) { 1017 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1018 cpu, apicid, c->initial_apicid); 1019 } 1020 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1021 #else 1022 c->logical_proc_id = 0; 1023 #endif 1024 } 1025 1026 /* 1027 * This does the hard work of actually picking apart the CPU stuff... 1028 */ 1029 static void identify_cpu(struct cpuinfo_x86 *c) 1030 { 1031 int i; 1032 1033 c->loops_per_jiffy = loops_per_jiffy; 1034 c->x86_cache_size = -1; 1035 c->x86_vendor = X86_VENDOR_UNKNOWN; 1036 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 1037 c->x86_vendor_id[0] = '\0'; /* Unset */ 1038 c->x86_model_id[0] = '\0'; /* Unset */ 1039 c->x86_max_cores = 1; 1040 c->x86_coreid_bits = 0; 1041 c->cu_id = 0xff; 1042 #ifdef CONFIG_X86_64 1043 c->x86_clflush_size = 64; 1044 c->x86_phys_bits = 36; 1045 c->x86_virt_bits = 48; 1046 #else 1047 c->cpuid_level = -1; /* CPUID not detected */ 1048 c->x86_clflush_size = 32; 1049 c->x86_phys_bits = 32; 1050 c->x86_virt_bits = 32; 1051 #endif 1052 c->x86_cache_alignment = c->x86_clflush_size; 1053 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1054 1055 generic_identify(c); 1056 1057 if (this_cpu->c_identify) 1058 this_cpu->c_identify(c); 1059 1060 /* Clear/Set all flags overridden by options, after probe */ 1061 apply_forced_caps(c); 1062 1063 #ifdef CONFIG_X86_64 1064 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1065 #endif 1066 1067 /* 1068 * Vendor-specific initialization. In this section we 1069 * canonicalize the feature flags, meaning if there are 1070 * features a certain CPU supports which CPUID doesn't 1071 * tell us, CPUID claiming incorrect flags, or other bugs, 1072 * we handle them here. 1073 * 1074 * At the end of this section, c->x86_capability better 1075 * indicate the features this CPU genuinely supports! 1076 */ 1077 if (this_cpu->c_init) 1078 this_cpu->c_init(c); 1079 1080 /* Disable the PN if appropriate */ 1081 squash_the_stupid_serial_number(c); 1082 1083 /* Set up SMEP/SMAP */ 1084 setup_smep(c); 1085 setup_smap(c); 1086 1087 /* 1088 * The vendor-specific functions might have changed features. 1089 * Now we do "generic changes." 1090 */ 1091 1092 /* Filter out anything that depends on CPUID levels we don't have */ 1093 filter_cpuid_features(c, true); 1094 1095 /* If the model name is still unset, do table lookup. */ 1096 if (!c->x86_model_id[0]) { 1097 const char *p; 1098 p = table_lookup_model(c); 1099 if (p) 1100 strcpy(c->x86_model_id, p); 1101 else 1102 /* Last resort... */ 1103 sprintf(c->x86_model_id, "%02x/%02x", 1104 c->x86, c->x86_model); 1105 } 1106 1107 #ifdef CONFIG_X86_64 1108 detect_ht(c); 1109 #endif 1110 1111 init_hypervisor(c); 1112 x86_init_rdrand(c); 1113 x86_init_cache_qos(c); 1114 setup_pku(c); 1115 1116 /* 1117 * Clear/Set all flags overridden by options, need do it 1118 * before following smp all cpus cap AND. 1119 */ 1120 apply_forced_caps(c); 1121 1122 /* 1123 * On SMP, boot_cpu_data holds the common feature set between 1124 * all CPUs; so make sure that we indicate which features are 1125 * common between the CPUs. The first time this routine gets 1126 * executed, c == &boot_cpu_data. 1127 */ 1128 if (c != &boot_cpu_data) { 1129 /* AND the already accumulated flags with these */ 1130 for (i = 0; i < NCAPINTS; i++) 1131 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1132 1133 /* OR, i.e. replicate the bug flags */ 1134 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1135 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1136 } 1137 1138 /* Init Machine Check Exception if available. */ 1139 mcheck_cpu_init(c); 1140 1141 select_idle_routine(c); 1142 1143 #ifdef CONFIG_NUMA 1144 numa_add_cpu(smp_processor_id()); 1145 #endif 1146 } 1147 1148 /* 1149 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1150 * on 32-bit kernels: 1151 */ 1152 #ifdef CONFIG_X86_32 1153 void enable_sep_cpu(void) 1154 { 1155 struct tss_struct *tss; 1156 int cpu; 1157 1158 if (!boot_cpu_has(X86_FEATURE_SEP)) 1159 return; 1160 1161 cpu = get_cpu(); 1162 tss = &per_cpu(cpu_tss, cpu); 1163 1164 /* 1165 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1166 * see the big comment in struct x86_hw_tss's definition. 1167 */ 1168 1169 tss->x86_tss.ss1 = __KERNEL_CS; 1170 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1171 1172 wrmsr(MSR_IA32_SYSENTER_ESP, 1173 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1174 0); 1175 1176 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1177 1178 put_cpu(); 1179 } 1180 #endif 1181 1182 void __init identify_boot_cpu(void) 1183 { 1184 identify_cpu(&boot_cpu_data); 1185 #ifdef CONFIG_X86_32 1186 sysenter_setup(); 1187 enable_sep_cpu(); 1188 #endif 1189 cpu_detect_tlb(&boot_cpu_data); 1190 } 1191 1192 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1193 { 1194 BUG_ON(c == &boot_cpu_data); 1195 identify_cpu(c); 1196 #ifdef CONFIG_X86_32 1197 enable_sep_cpu(); 1198 #endif 1199 mtrr_ap_init(); 1200 validate_apic_and_package_id(c); 1201 } 1202 1203 static __init int setup_noclflush(char *arg) 1204 { 1205 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1206 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1207 return 1; 1208 } 1209 __setup("noclflush", setup_noclflush); 1210 1211 void print_cpu_info(struct cpuinfo_x86 *c) 1212 { 1213 const char *vendor = NULL; 1214 1215 if (c->x86_vendor < X86_VENDOR_NUM) { 1216 vendor = this_cpu->c_vendor; 1217 } else { 1218 if (c->cpuid_level >= 0) 1219 vendor = c->x86_vendor_id; 1220 } 1221 1222 if (vendor && !strstr(c->x86_model_id, vendor)) 1223 pr_cont("%s ", vendor); 1224 1225 if (c->x86_model_id[0]) 1226 pr_cont("%s", c->x86_model_id); 1227 else 1228 pr_cont("%d86", c->x86); 1229 1230 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1231 1232 if (c->x86_mask || c->cpuid_level >= 0) 1233 pr_cont(", stepping: 0x%x)\n", c->x86_mask); 1234 else 1235 pr_cont(")\n"); 1236 } 1237 1238 static __init int setup_disablecpuid(char *arg) 1239 { 1240 int bit; 1241 1242 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32) 1243 setup_clear_cpu_cap(bit); 1244 else 1245 return 0; 1246 1247 return 1; 1248 } 1249 __setup("clearcpuid=", setup_disablecpuid); 1250 1251 #ifdef CONFIG_X86_64 1252 struct desc_ptr idt_descr __ro_after_init = { 1253 .size = NR_VECTORS * 16 - 1, 1254 .address = (unsigned long) idt_table, 1255 }; 1256 const struct desc_ptr debug_idt_descr = { 1257 .size = NR_VECTORS * 16 - 1, 1258 .address = (unsigned long) debug_idt_table, 1259 }; 1260 1261 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1262 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1263 1264 /* 1265 * The following percpu variables are hot. Align current_task to 1266 * cacheline size such that they fall in the same cacheline. 1267 */ 1268 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1269 &init_task; 1270 EXPORT_PER_CPU_SYMBOL(current_task); 1271 1272 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1273 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1274 1275 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1276 1277 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1278 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1279 1280 /* 1281 * Special IST stacks which the CPU switches to when it calls 1282 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1283 * limit), all of them are 4K, except the debug stack which 1284 * is 8K. 1285 */ 1286 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1287 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1288 [DEBUG_STACK - 1] = DEBUG_STKSZ 1289 }; 1290 1291 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1292 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1293 1294 /* May not be marked __init: used by software suspend */ 1295 void syscall_init(void) 1296 { 1297 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1298 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1299 1300 #ifdef CONFIG_IA32_EMULATION 1301 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1302 /* 1303 * This only works on Intel CPUs. 1304 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1305 * This does not cause SYSENTER to jump to the wrong location, because 1306 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1307 */ 1308 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1309 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1310 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1311 #else 1312 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1313 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1314 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1315 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1316 #endif 1317 1318 /* Flags to clear on syscall */ 1319 wrmsrl(MSR_SYSCALL_MASK, 1320 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1321 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1322 } 1323 1324 /* 1325 * Copies of the original ist values from the tss are only accessed during 1326 * debugging, no special alignment required. 1327 */ 1328 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1329 1330 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1331 DEFINE_PER_CPU(int, debug_stack_usage); 1332 1333 int is_debug_stack(unsigned long addr) 1334 { 1335 return __this_cpu_read(debug_stack_usage) || 1336 (addr <= __this_cpu_read(debug_stack_addr) && 1337 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1338 } 1339 NOKPROBE_SYMBOL(is_debug_stack); 1340 1341 DEFINE_PER_CPU(u32, debug_idt_ctr); 1342 1343 void debug_stack_set_zero(void) 1344 { 1345 this_cpu_inc(debug_idt_ctr); 1346 load_current_idt(); 1347 } 1348 NOKPROBE_SYMBOL(debug_stack_set_zero); 1349 1350 void debug_stack_reset(void) 1351 { 1352 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1353 return; 1354 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1355 load_current_idt(); 1356 } 1357 NOKPROBE_SYMBOL(debug_stack_reset); 1358 1359 #else /* CONFIG_X86_64 */ 1360 1361 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1362 EXPORT_PER_CPU_SYMBOL(current_task); 1363 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1364 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1365 1366 /* 1367 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1368 * the top of the kernel stack. Use an extra percpu variable to track the 1369 * top of the kernel stack directly. 1370 */ 1371 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1372 (unsigned long)&init_thread_union + THREAD_SIZE; 1373 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1374 1375 #ifdef CONFIG_CC_STACKPROTECTOR 1376 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1377 #endif 1378 1379 #endif /* CONFIG_X86_64 */ 1380 1381 /* 1382 * Clear all 6 debug registers: 1383 */ 1384 static void clear_all_debug_regs(void) 1385 { 1386 int i; 1387 1388 for (i = 0; i < 8; i++) { 1389 /* Ignore db4, db5 */ 1390 if ((i == 4) || (i == 5)) 1391 continue; 1392 1393 set_debugreg(0, i); 1394 } 1395 } 1396 1397 #ifdef CONFIG_KGDB 1398 /* 1399 * Restore debug regs if using kgdbwait and you have a kernel debugger 1400 * connection established. 1401 */ 1402 static void dbg_restore_debug_regs(void) 1403 { 1404 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1405 arch_kgdb_ops.correct_hw_break(); 1406 } 1407 #else /* ! CONFIG_KGDB */ 1408 #define dbg_restore_debug_regs() 1409 #endif /* ! CONFIG_KGDB */ 1410 1411 static void wait_for_master_cpu(int cpu) 1412 { 1413 #ifdef CONFIG_SMP 1414 /* 1415 * wait for ACK from master CPU before continuing 1416 * with AP initialization 1417 */ 1418 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1419 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1420 cpu_relax(); 1421 #endif 1422 } 1423 1424 /* 1425 * cpu_init() initializes state that is per-CPU. Some data is already 1426 * initialized (naturally) in the bootstrap process, such as the GDT 1427 * and IDT. We reload them nevertheless, this function acts as a 1428 * 'CPU state barrier', nothing should get across. 1429 * A lot of state is already set up in PDA init for 64 bit 1430 */ 1431 #ifdef CONFIG_X86_64 1432 1433 void cpu_init(void) 1434 { 1435 struct orig_ist *oist; 1436 struct task_struct *me; 1437 struct tss_struct *t; 1438 unsigned long v; 1439 int cpu = raw_smp_processor_id(); 1440 int i; 1441 1442 wait_for_master_cpu(cpu); 1443 1444 /* 1445 * Initialize the CR4 shadow before doing anything that could 1446 * try to read it. 1447 */ 1448 cr4_init_shadow(); 1449 1450 if (cpu) 1451 load_ucode_ap(); 1452 1453 t = &per_cpu(cpu_tss, cpu); 1454 oist = &per_cpu(orig_ist, cpu); 1455 1456 #ifdef CONFIG_NUMA 1457 if (this_cpu_read(numa_node) == 0 && 1458 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1459 set_numa_node(early_cpu_to_node(cpu)); 1460 #endif 1461 1462 me = current; 1463 1464 pr_debug("Initializing CPU#%d\n", cpu); 1465 1466 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1467 1468 /* 1469 * Initialize the per-CPU GDT with the boot GDT, 1470 * and set up the GDT descriptor: 1471 */ 1472 1473 switch_to_new_gdt(cpu); 1474 loadsegment(fs, 0); 1475 1476 load_current_idt(); 1477 1478 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1479 syscall_init(); 1480 1481 wrmsrl(MSR_FS_BASE, 0); 1482 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1483 barrier(); 1484 1485 x86_configure_nx(); 1486 x2apic_setup(); 1487 1488 /* 1489 * set up and load the per-CPU TSS 1490 */ 1491 if (!oist->ist[0]) { 1492 char *estacks = per_cpu(exception_stacks, cpu); 1493 1494 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1495 estacks += exception_stack_sizes[v]; 1496 oist->ist[v] = t->x86_tss.ist[v] = 1497 (unsigned long)estacks; 1498 if (v == DEBUG_STACK-1) 1499 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1500 } 1501 } 1502 1503 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1504 1505 /* 1506 * <= is required because the CPU will access up to 1507 * 8 bits beyond the end of the IO permission bitmap. 1508 */ 1509 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1510 t->io_bitmap[i] = ~0UL; 1511 1512 mmgrab(&init_mm); 1513 me->active_mm = &init_mm; 1514 BUG_ON(me->mm); 1515 enter_lazy_tlb(&init_mm, me); 1516 1517 load_sp0(t, ¤t->thread); 1518 set_tss_desc(cpu, t); 1519 load_TR_desc(); 1520 load_mm_ldt(&init_mm); 1521 1522 clear_all_debug_regs(); 1523 dbg_restore_debug_regs(); 1524 1525 fpu__init_cpu(); 1526 1527 if (is_uv_system()) 1528 uv_cpu_init(); 1529 } 1530 1531 #else 1532 1533 void cpu_init(void) 1534 { 1535 int cpu = smp_processor_id(); 1536 struct task_struct *curr = current; 1537 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1538 struct thread_struct *thread = &curr->thread; 1539 1540 wait_for_master_cpu(cpu); 1541 1542 /* 1543 * Initialize the CR4 shadow before doing anything that could 1544 * try to read it. 1545 */ 1546 cr4_init_shadow(); 1547 1548 show_ucode_info_early(); 1549 1550 pr_info("Initializing CPU#%d\n", cpu); 1551 1552 if (cpu_feature_enabled(X86_FEATURE_VME) || 1553 boot_cpu_has(X86_FEATURE_TSC) || 1554 boot_cpu_has(X86_FEATURE_DE)) 1555 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1556 1557 load_current_idt(); 1558 switch_to_new_gdt(cpu); 1559 1560 /* 1561 * Set up and load the per-CPU TSS and LDT 1562 */ 1563 mmgrab(&init_mm); 1564 curr->active_mm = &init_mm; 1565 BUG_ON(curr->mm); 1566 enter_lazy_tlb(&init_mm, curr); 1567 1568 load_sp0(t, thread); 1569 set_tss_desc(cpu, t); 1570 load_TR_desc(); 1571 load_mm_ldt(&init_mm); 1572 1573 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1574 1575 #ifdef CONFIG_DOUBLEFAULT 1576 /* Set up doublefault TSS pointer in the GDT */ 1577 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1578 #endif 1579 1580 clear_all_debug_regs(); 1581 dbg_restore_debug_regs(); 1582 1583 fpu__init_cpu(); 1584 } 1585 #endif 1586 1587 static void bsp_resume(void) 1588 { 1589 if (this_cpu->c_bsp_resume) 1590 this_cpu->c_bsp_resume(&boot_cpu_data); 1591 } 1592 1593 static struct syscore_ops cpu_syscore_ops = { 1594 .resume = bsp_resume, 1595 }; 1596 1597 static int __init init_cpu_syscore(void) 1598 { 1599 register_syscore_ops(&cpu_syscore_ops); 1600 return 0; 1601 } 1602 core_initcall(init_cpu_syscore); 1603