1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 51 #ifdef CONFIG_X86_LOCAL_APIC 52 #include <asm/uv/uv.h> 53 #endif 54 55 #include "cpu.h" 56 57 u32 elf_hwcap2 __read_mostly; 58 59 /* all of these masks are initialized in setup_cpu_local_masks() */ 60 cpumask_var_t cpu_initialized_mask; 61 cpumask_var_t cpu_callout_mask; 62 cpumask_var_t cpu_callin_mask; 63 64 /* representing cpus for which sibling maps can be computed */ 65 cpumask_var_t cpu_sibling_setup_mask; 66 67 /* correctly size the local cpu masks */ 68 void __init setup_cpu_local_masks(void) 69 { 70 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 71 alloc_bootmem_cpumask_var(&cpu_callin_mask); 72 alloc_bootmem_cpumask_var(&cpu_callout_mask); 73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 74 } 75 76 static void default_init(struct cpuinfo_x86 *c) 77 { 78 #ifdef CONFIG_X86_64 79 cpu_detect_cache_sizes(c); 80 #else 81 /* Not much we can do here... */ 82 /* Check if at least it has cpuid */ 83 if (c->cpuid_level == -1) { 84 /* No cpuid. It must be an ancient CPU */ 85 if (c->x86 == 4) 86 strcpy(c->x86_model_id, "486"); 87 else if (c->x86 == 3) 88 strcpy(c->x86_model_id, "386"); 89 } 90 #endif 91 } 92 93 static const struct cpu_dev default_cpu = { 94 .c_init = default_init, 95 .c_vendor = "Unknown", 96 .c_x86_vendor = X86_VENDOR_UNKNOWN, 97 }; 98 99 static const struct cpu_dev *this_cpu = &default_cpu; 100 101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 102 #ifdef CONFIG_X86_64 103 /* 104 * We need valid kernel segments for data and code in long mode too 105 * IRET will check the segment types kkeil 2000/10/28 106 * Also sysret mandates a special GDT layout 107 * 108 * TLS descriptors are currently at a different place compared to i386. 109 * Hopefully nobody expects them at a fixed place (Wine?) 110 */ 111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 117 #else 118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 122 /* 123 * Segments used for calling PnP BIOS have byte granularity. 124 * They code segments and data segments have fixed 64k limits, 125 * the transfer segment sizes are set at run time. 126 */ 127 /* 32-bit code */ 128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 129 /* 16-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 131 /* 16-bit data */ 132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 138 * The APM segments have byte granularity and their bases 139 * are set at run time. All have 64k limits. 140 */ 141 /* 32-bit code */ 142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 143 /* 16-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 145 /* data */ 146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 147 148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 150 GDT_STACK_CANARY_INIT 151 #endif 152 } }; 153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 154 155 static int __init x86_mpx_setup(char *s) 156 { 157 /* require an exact match without trailing characters */ 158 if (strlen(s)) 159 return 0; 160 161 /* do not emit a message if the feature is not present */ 162 if (!boot_cpu_has(X86_FEATURE_MPX)) 163 return 1; 164 165 setup_clear_cpu_cap(X86_FEATURE_MPX); 166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 167 return 1; 168 } 169 __setup("nompx", x86_mpx_setup); 170 171 #ifdef CONFIG_X86_64 172 static int __init x86_nopcid_setup(char *s) 173 { 174 /* nopcid doesn't accept parameters */ 175 if (s) 176 return -EINVAL; 177 178 /* do not emit a message if the feature is not present */ 179 if (!boot_cpu_has(X86_FEATURE_PCID)) 180 return 0; 181 182 setup_clear_cpu_cap(X86_FEATURE_PCID); 183 pr_info("nopcid: PCID feature disabled\n"); 184 return 0; 185 } 186 early_param("nopcid", x86_nopcid_setup); 187 #endif 188 189 static int __init x86_noinvpcid_setup(char *s) 190 { 191 /* noinvpcid doesn't accept parameters */ 192 if (s) 193 return -EINVAL; 194 195 /* do not emit a message if the feature is not present */ 196 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 197 return 0; 198 199 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 200 pr_info("noinvpcid: INVPCID feature disabled\n"); 201 return 0; 202 } 203 early_param("noinvpcid", x86_noinvpcid_setup); 204 205 #ifdef CONFIG_X86_32 206 static int cachesize_override = -1; 207 static int disable_x86_serial_nr = 1; 208 209 static int __init cachesize_setup(char *str) 210 { 211 get_option(&str, &cachesize_override); 212 return 1; 213 } 214 __setup("cachesize=", cachesize_setup); 215 216 static int __init x86_sep_setup(char *s) 217 { 218 setup_clear_cpu_cap(X86_FEATURE_SEP); 219 return 1; 220 } 221 __setup("nosep", x86_sep_setup); 222 223 /* Standard macro to see if a specific flag is changeable */ 224 static inline int flag_is_changeable_p(u32 flag) 225 { 226 u32 f1, f2; 227 228 /* 229 * Cyrix and IDT cpus allow disabling of CPUID 230 * so the code below may return different results 231 * when it is executed before and after enabling 232 * the CPUID. Add "volatile" to not allow gcc to 233 * optimize the subsequent calls to this function. 234 */ 235 asm volatile ("pushfl \n\t" 236 "pushfl \n\t" 237 "popl %0 \n\t" 238 "movl %0, %1 \n\t" 239 "xorl %2, %0 \n\t" 240 "pushl %0 \n\t" 241 "popfl \n\t" 242 "pushfl \n\t" 243 "popl %0 \n\t" 244 "popfl \n\t" 245 246 : "=&r" (f1), "=&r" (f2) 247 : "ir" (flag)); 248 249 return ((f1^f2) & flag) != 0; 250 } 251 252 /* Probe for the CPUID instruction */ 253 int have_cpuid_p(void) 254 { 255 return flag_is_changeable_p(X86_EFLAGS_ID); 256 } 257 258 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 259 { 260 unsigned long lo, hi; 261 262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 263 return; 264 265 /* Disable processor serial number: */ 266 267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 268 lo |= 0x200000; 269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 270 271 pr_notice("CPU serial number disabled.\n"); 272 clear_cpu_cap(c, X86_FEATURE_PN); 273 274 /* Disabling the serial number may affect the cpuid level */ 275 c->cpuid_level = cpuid_eax(0); 276 } 277 278 static int __init x86_serial_nr_setup(char *s) 279 { 280 disable_x86_serial_nr = 0; 281 return 1; 282 } 283 __setup("serialnumber", x86_serial_nr_setup); 284 #else 285 static inline int flag_is_changeable_p(u32 flag) 286 { 287 return 1; 288 } 289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 290 { 291 } 292 #endif 293 294 static __init int setup_disable_smep(char *arg) 295 { 296 setup_clear_cpu_cap(X86_FEATURE_SMEP); 297 /* Check for things that depend on SMEP being enabled: */ 298 check_mpx_erratum(&boot_cpu_data); 299 return 1; 300 } 301 __setup("nosmep", setup_disable_smep); 302 303 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 304 { 305 if (cpu_has(c, X86_FEATURE_SMEP)) 306 cr4_set_bits(X86_CR4_SMEP); 307 } 308 309 static __init int setup_disable_smap(char *arg) 310 { 311 setup_clear_cpu_cap(X86_FEATURE_SMAP); 312 return 1; 313 } 314 __setup("nosmap", setup_disable_smap); 315 316 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 317 { 318 unsigned long eflags = native_save_fl(); 319 320 /* This should have been cleared long ago */ 321 BUG_ON(eflags & X86_EFLAGS_AC); 322 323 if (cpu_has(c, X86_FEATURE_SMAP)) { 324 #ifdef CONFIG_X86_SMAP 325 cr4_set_bits(X86_CR4_SMAP); 326 #else 327 cr4_clear_bits(X86_CR4_SMAP); 328 #endif 329 } 330 } 331 332 /* 333 * Protection Keys are not available in 32-bit mode. 334 */ 335 static bool pku_disabled; 336 337 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 338 { 339 /* check the boot processor, plus compile options for PKU: */ 340 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 341 return; 342 /* checks the actual processor's cpuid bits: */ 343 if (!cpu_has(c, X86_FEATURE_PKU)) 344 return; 345 if (pku_disabled) 346 return; 347 348 cr4_set_bits(X86_CR4_PKE); 349 /* 350 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 351 * cpuid bit to be set. We need to ensure that we 352 * update that bit in this CPU's "cpu_info". 353 */ 354 get_cpu_cap(c); 355 } 356 357 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 358 static __init int setup_disable_pku(char *arg) 359 { 360 /* 361 * Do not clear the X86_FEATURE_PKU bit. All of the 362 * runtime checks are against OSPKE so clearing the 363 * bit does nothing. 364 * 365 * This way, we will see "pku" in cpuinfo, but not 366 * "ospke", which is exactly what we want. It shows 367 * that the CPU has PKU, but the OS has not enabled it. 368 * This happens to be exactly how a system would look 369 * if we disabled the config option. 370 */ 371 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 372 pku_disabled = true; 373 return 1; 374 } 375 __setup("nopku", setup_disable_pku); 376 #endif /* CONFIG_X86_64 */ 377 378 /* 379 * Some CPU features depend on higher CPUID levels, which may not always 380 * be available due to CPUID level capping or broken virtualization 381 * software. Add those features to this table to auto-disable them. 382 */ 383 struct cpuid_dependent_feature { 384 u32 feature; 385 u32 level; 386 }; 387 388 static const struct cpuid_dependent_feature 389 cpuid_dependent_features[] = { 390 { X86_FEATURE_MWAIT, 0x00000005 }, 391 { X86_FEATURE_DCA, 0x00000009 }, 392 { X86_FEATURE_XSAVE, 0x0000000d }, 393 { 0, 0 } 394 }; 395 396 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 397 { 398 const struct cpuid_dependent_feature *df; 399 400 for (df = cpuid_dependent_features; df->feature; df++) { 401 402 if (!cpu_has(c, df->feature)) 403 continue; 404 /* 405 * Note: cpuid_level is set to -1 if unavailable, but 406 * extended_extended_level is set to 0 if unavailable 407 * and the legitimate extended levels are all negative 408 * when signed; hence the weird messing around with 409 * signs here... 410 */ 411 if (!((s32)df->level < 0 ? 412 (u32)df->level > (u32)c->extended_cpuid_level : 413 (s32)df->level > (s32)c->cpuid_level)) 414 continue; 415 416 clear_cpu_cap(c, df->feature); 417 if (!warn) 418 continue; 419 420 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 421 x86_cap_flag(df->feature), df->level); 422 } 423 } 424 425 /* 426 * Naming convention should be: <Name> [(<Codename>)] 427 * This table only is used unless init_<vendor>() below doesn't set it; 428 * in particular, if CPUID levels 0x80000002..4 are supported, this 429 * isn't used 430 */ 431 432 /* Look up CPU names by table lookup. */ 433 static const char *table_lookup_model(struct cpuinfo_x86 *c) 434 { 435 #ifdef CONFIG_X86_32 436 const struct legacy_cpu_model_info *info; 437 438 if (c->x86_model >= 16) 439 return NULL; /* Range check */ 440 441 if (!this_cpu) 442 return NULL; 443 444 info = this_cpu->legacy_models; 445 446 while (info->family) { 447 if (info->family == c->x86) 448 return info->model_names[c->x86_model]; 449 info++; 450 } 451 #endif 452 return NULL; /* Not found */ 453 } 454 455 __u32 cpu_caps_cleared[NCAPINTS]; 456 __u32 cpu_caps_set[NCAPINTS]; 457 458 void load_percpu_segment(int cpu) 459 { 460 #ifdef CONFIG_X86_32 461 loadsegment(fs, __KERNEL_PERCPU); 462 #else 463 __loadsegment_simple(gs, 0); 464 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 465 #endif 466 load_stack_canary_segment(); 467 } 468 469 /* Setup the fixmap mapping only once per-processor */ 470 static inline void setup_fixmap_gdt(int cpu) 471 { 472 #ifdef CONFIG_X86_64 473 /* On 64-bit systems, we use a read-only fixmap GDT. */ 474 pgprot_t prot = PAGE_KERNEL_RO; 475 #else 476 /* 477 * On native 32-bit systems, the GDT cannot be read-only because 478 * our double fault handler uses a task gate, and entering through 479 * a task gate needs to change an available TSS to busy. If the GDT 480 * is read-only, that will triple fault. 481 * 482 * On Xen PV, the GDT must be read-only because the hypervisor requires 483 * it. 484 */ 485 pgprot_t prot = boot_cpu_has(X86_FEATURE_XENPV) ? 486 PAGE_KERNEL_RO : PAGE_KERNEL; 487 #endif 488 489 __set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot); 490 } 491 492 /* Load the original GDT from the per-cpu structure */ 493 void load_direct_gdt(int cpu) 494 { 495 struct desc_ptr gdt_descr; 496 497 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 498 gdt_descr.size = GDT_SIZE - 1; 499 load_gdt(&gdt_descr); 500 } 501 EXPORT_SYMBOL_GPL(load_direct_gdt); 502 503 /* Load a fixmap remapping of the per-cpu GDT */ 504 void load_fixmap_gdt(int cpu) 505 { 506 struct desc_ptr gdt_descr; 507 508 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 509 gdt_descr.size = GDT_SIZE - 1; 510 load_gdt(&gdt_descr); 511 } 512 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 513 514 /* 515 * Current gdt points %fs at the "master" per-cpu area: after this, 516 * it's on the real one. 517 */ 518 void switch_to_new_gdt(int cpu) 519 { 520 /* Load the original GDT */ 521 load_direct_gdt(cpu); 522 /* Reload the per-cpu base */ 523 load_percpu_segment(cpu); 524 } 525 526 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 527 528 static void get_model_name(struct cpuinfo_x86 *c) 529 { 530 unsigned int *v; 531 char *p, *q, *s; 532 533 if (c->extended_cpuid_level < 0x80000004) 534 return; 535 536 v = (unsigned int *)c->x86_model_id; 537 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 538 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 539 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 540 c->x86_model_id[48] = 0; 541 542 /* Trim whitespace */ 543 p = q = s = &c->x86_model_id[0]; 544 545 while (*p == ' ') 546 p++; 547 548 while (*p) { 549 /* Note the last non-whitespace index */ 550 if (!isspace(*p)) 551 s = q; 552 553 *q++ = *p++; 554 } 555 556 *(s + 1) = '\0'; 557 } 558 559 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 560 { 561 unsigned int n, dummy, ebx, ecx, edx, l2size; 562 563 n = c->extended_cpuid_level; 564 565 if (n >= 0x80000005) { 566 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 567 c->x86_cache_size = (ecx>>24) + (edx>>24); 568 #ifdef CONFIG_X86_64 569 /* On K8 L1 TLB is inclusive, so don't count it */ 570 c->x86_tlbsize = 0; 571 #endif 572 } 573 574 if (n < 0x80000006) /* Some chips just has a large L1. */ 575 return; 576 577 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 578 l2size = ecx >> 16; 579 580 #ifdef CONFIG_X86_64 581 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 582 #else 583 /* do processor-specific cache resizing */ 584 if (this_cpu->legacy_cache_size) 585 l2size = this_cpu->legacy_cache_size(c, l2size); 586 587 /* Allow user to override all this if necessary. */ 588 if (cachesize_override != -1) 589 l2size = cachesize_override; 590 591 if (l2size == 0) 592 return; /* Again, no L2 cache is possible */ 593 #endif 594 595 c->x86_cache_size = l2size; 596 } 597 598 u16 __read_mostly tlb_lli_4k[NR_INFO]; 599 u16 __read_mostly tlb_lli_2m[NR_INFO]; 600 u16 __read_mostly tlb_lli_4m[NR_INFO]; 601 u16 __read_mostly tlb_lld_4k[NR_INFO]; 602 u16 __read_mostly tlb_lld_2m[NR_INFO]; 603 u16 __read_mostly tlb_lld_4m[NR_INFO]; 604 u16 __read_mostly tlb_lld_1g[NR_INFO]; 605 606 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 607 { 608 if (this_cpu->c_detect_tlb) 609 this_cpu->c_detect_tlb(c); 610 611 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 612 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 613 tlb_lli_4m[ENTRIES]); 614 615 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 616 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 617 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 618 } 619 620 void detect_ht(struct cpuinfo_x86 *c) 621 { 622 #ifdef CONFIG_SMP 623 u32 eax, ebx, ecx, edx; 624 int index_msb, core_bits; 625 static bool printed; 626 627 if (!cpu_has(c, X86_FEATURE_HT)) 628 return; 629 630 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 631 goto out; 632 633 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 634 return; 635 636 cpuid(1, &eax, &ebx, &ecx, &edx); 637 638 smp_num_siblings = (ebx & 0xff0000) >> 16; 639 640 if (smp_num_siblings == 1) { 641 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 642 goto out; 643 } 644 645 if (smp_num_siblings <= 1) 646 goto out; 647 648 index_msb = get_count_order(smp_num_siblings); 649 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 650 651 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 652 653 index_msb = get_count_order(smp_num_siblings); 654 655 core_bits = get_count_order(c->x86_max_cores); 656 657 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 658 ((1 << core_bits) - 1); 659 660 out: 661 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 662 pr_info("CPU: Physical Processor ID: %d\n", 663 c->phys_proc_id); 664 pr_info("CPU: Processor Core ID: %d\n", 665 c->cpu_core_id); 666 printed = 1; 667 } 668 #endif 669 } 670 671 static void get_cpu_vendor(struct cpuinfo_x86 *c) 672 { 673 char *v = c->x86_vendor_id; 674 int i; 675 676 for (i = 0; i < X86_VENDOR_NUM; i++) { 677 if (!cpu_devs[i]) 678 break; 679 680 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 681 (cpu_devs[i]->c_ident[1] && 682 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 683 684 this_cpu = cpu_devs[i]; 685 c->x86_vendor = this_cpu->c_x86_vendor; 686 return; 687 } 688 } 689 690 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 691 "CPU: Your system may be unstable.\n", v); 692 693 c->x86_vendor = X86_VENDOR_UNKNOWN; 694 this_cpu = &default_cpu; 695 } 696 697 void cpu_detect(struct cpuinfo_x86 *c) 698 { 699 /* Get vendor name */ 700 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 701 (unsigned int *)&c->x86_vendor_id[0], 702 (unsigned int *)&c->x86_vendor_id[8], 703 (unsigned int *)&c->x86_vendor_id[4]); 704 705 c->x86 = 4; 706 /* Intel-defined flags: level 0x00000001 */ 707 if (c->cpuid_level >= 0x00000001) { 708 u32 junk, tfms, cap0, misc; 709 710 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 711 c->x86 = x86_family(tfms); 712 c->x86_model = x86_model(tfms); 713 c->x86_mask = x86_stepping(tfms); 714 715 if (cap0 & (1<<19)) { 716 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 717 c->x86_cache_alignment = c->x86_clflush_size; 718 } 719 } 720 } 721 722 static void apply_forced_caps(struct cpuinfo_x86 *c) 723 { 724 int i; 725 726 for (i = 0; i < NCAPINTS; i++) { 727 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 728 c->x86_capability[i] |= cpu_caps_set[i]; 729 } 730 } 731 732 void get_cpu_cap(struct cpuinfo_x86 *c) 733 { 734 u32 eax, ebx, ecx, edx; 735 736 /* Intel-defined flags: level 0x00000001 */ 737 if (c->cpuid_level >= 0x00000001) { 738 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 739 740 c->x86_capability[CPUID_1_ECX] = ecx; 741 c->x86_capability[CPUID_1_EDX] = edx; 742 } 743 744 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 745 if (c->cpuid_level >= 0x00000006) 746 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 747 748 /* Additional Intel-defined flags: level 0x00000007 */ 749 if (c->cpuid_level >= 0x00000007) { 750 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 751 c->x86_capability[CPUID_7_0_EBX] = ebx; 752 c->x86_capability[CPUID_7_ECX] = ecx; 753 } 754 755 /* Extended state features: level 0x0000000d */ 756 if (c->cpuid_level >= 0x0000000d) { 757 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 758 759 c->x86_capability[CPUID_D_1_EAX] = eax; 760 } 761 762 /* Additional Intel-defined flags: level 0x0000000F */ 763 if (c->cpuid_level >= 0x0000000F) { 764 765 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 766 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 767 c->x86_capability[CPUID_F_0_EDX] = edx; 768 769 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 770 /* will be overridden if occupancy monitoring exists */ 771 c->x86_cache_max_rmid = ebx; 772 773 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 774 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 775 c->x86_capability[CPUID_F_1_EDX] = edx; 776 777 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 778 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 779 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 780 c->x86_cache_max_rmid = ecx; 781 c->x86_cache_occ_scale = ebx; 782 } 783 } else { 784 c->x86_cache_max_rmid = -1; 785 c->x86_cache_occ_scale = -1; 786 } 787 } 788 789 /* AMD-defined flags: level 0x80000001 */ 790 eax = cpuid_eax(0x80000000); 791 c->extended_cpuid_level = eax; 792 793 if ((eax & 0xffff0000) == 0x80000000) { 794 if (eax >= 0x80000001) { 795 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 796 797 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 798 c->x86_capability[CPUID_8000_0001_EDX] = edx; 799 } 800 } 801 802 if (c->extended_cpuid_level >= 0x80000007) { 803 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 804 805 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 806 c->x86_power = edx; 807 } 808 809 if (c->extended_cpuid_level >= 0x80000008) { 810 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 811 812 c->x86_virt_bits = (eax >> 8) & 0xff; 813 c->x86_phys_bits = eax & 0xff; 814 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 815 } 816 #ifdef CONFIG_X86_32 817 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 818 c->x86_phys_bits = 36; 819 #endif 820 821 if (c->extended_cpuid_level >= 0x8000000a) 822 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 823 824 init_scattered_cpuid_features(c); 825 826 /* 827 * Clear/Set all flags overridden by options, after probe. 828 * This needs to happen each time we re-probe, which may happen 829 * several times during CPU initialization. 830 */ 831 apply_forced_caps(c); 832 } 833 834 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 835 { 836 #ifdef CONFIG_X86_32 837 int i; 838 839 /* 840 * First of all, decide if this is a 486 or higher 841 * It's a 486 if we can modify the AC flag 842 */ 843 if (flag_is_changeable_p(X86_EFLAGS_AC)) 844 c->x86 = 4; 845 else 846 c->x86 = 3; 847 848 for (i = 0; i < X86_VENDOR_NUM; i++) 849 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 850 c->x86_vendor_id[0] = 0; 851 cpu_devs[i]->c_identify(c); 852 if (c->x86_vendor_id[0]) { 853 get_cpu_vendor(c); 854 break; 855 } 856 } 857 #endif 858 } 859 860 /* 861 * Do minimum CPU detection early. 862 * Fields really needed: vendor, cpuid_level, family, model, mask, 863 * cache alignment. 864 * The others are not touched to avoid unwanted side effects. 865 * 866 * WARNING: this function is only called on the BP. Don't add code here 867 * that is supposed to run on all CPUs. 868 */ 869 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 870 { 871 #ifdef CONFIG_X86_64 872 c->x86_clflush_size = 64; 873 c->x86_phys_bits = 36; 874 c->x86_virt_bits = 48; 875 #else 876 c->x86_clflush_size = 32; 877 c->x86_phys_bits = 32; 878 c->x86_virt_bits = 32; 879 #endif 880 c->x86_cache_alignment = c->x86_clflush_size; 881 882 memset(&c->x86_capability, 0, sizeof c->x86_capability); 883 c->extended_cpuid_level = 0; 884 885 /* cyrix could have cpuid enabled via c_identify()*/ 886 if (have_cpuid_p()) { 887 cpu_detect(c); 888 get_cpu_vendor(c); 889 get_cpu_cap(c); 890 setup_force_cpu_cap(X86_FEATURE_CPUID); 891 892 if (this_cpu->c_early_init) 893 this_cpu->c_early_init(c); 894 895 c->cpu_index = 0; 896 filter_cpuid_features(c, false); 897 898 if (this_cpu->c_bsp_init) 899 this_cpu->c_bsp_init(c); 900 } else { 901 identify_cpu_without_cpuid(c); 902 setup_clear_cpu_cap(X86_FEATURE_CPUID); 903 } 904 905 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 906 fpu__init_system(c); 907 908 #ifdef CONFIG_X86_32 909 /* 910 * Regardless of whether PCID is enumerated, the SDM says 911 * that it can't be enabled in 32-bit mode. 912 */ 913 setup_clear_cpu_cap(X86_FEATURE_PCID); 914 #endif 915 } 916 917 void __init early_cpu_init(void) 918 { 919 const struct cpu_dev *const *cdev; 920 int count = 0; 921 922 #ifdef CONFIG_PROCESSOR_SELECT 923 pr_info("KERNEL supported cpus:\n"); 924 #endif 925 926 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 927 const struct cpu_dev *cpudev = *cdev; 928 929 if (count >= X86_VENDOR_NUM) 930 break; 931 cpu_devs[count] = cpudev; 932 count++; 933 934 #ifdef CONFIG_PROCESSOR_SELECT 935 { 936 unsigned int j; 937 938 for (j = 0; j < 2; j++) { 939 if (!cpudev->c_ident[j]) 940 continue; 941 pr_info(" %s %s\n", cpudev->c_vendor, 942 cpudev->c_ident[j]); 943 } 944 } 945 #endif 946 } 947 early_identify_cpu(&boot_cpu_data); 948 } 949 950 /* 951 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 952 * unfortunately, that's not true in practice because of early VIA 953 * chips and (more importantly) broken virtualizers that are not easy 954 * to detect. In the latter case it doesn't even *fail* reliably, so 955 * probing for it doesn't even work. Disable it completely on 32-bit 956 * unless we can find a reliable way to detect all the broken cases. 957 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 958 */ 959 static void detect_nopl(struct cpuinfo_x86 *c) 960 { 961 #ifdef CONFIG_X86_32 962 clear_cpu_cap(c, X86_FEATURE_NOPL); 963 #else 964 set_cpu_cap(c, X86_FEATURE_NOPL); 965 #endif 966 } 967 968 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 969 { 970 #ifdef CONFIG_X86_64 971 /* 972 * Empirically, writing zero to a segment selector on AMD does 973 * not clear the base, whereas writing zero to a segment 974 * selector on Intel does clear the base. Intel's behavior 975 * allows slightly faster context switches in the common case 976 * where GS is unused by the prev and next threads. 977 * 978 * Since neither vendor documents this anywhere that I can see, 979 * detect it directly instead of hardcoding the choice by 980 * vendor. 981 * 982 * I've designated AMD's behavior as the "bug" because it's 983 * counterintuitive and less friendly. 984 */ 985 986 unsigned long old_base, tmp; 987 rdmsrl(MSR_FS_BASE, old_base); 988 wrmsrl(MSR_FS_BASE, 1); 989 loadsegment(fs, 0); 990 rdmsrl(MSR_FS_BASE, tmp); 991 if (tmp != 0) 992 set_cpu_bug(c, X86_BUG_NULL_SEG); 993 wrmsrl(MSR_FS_BASE, old_base); 994 #endif 995 } 996 997 static void generic_identify(struct cpuinfo_x86 *c) 998 { 999 c->extended_cpuid_level = 0; 1000 1001 if (!have_cpuid_p()) 1002 identify_cpu_without_cpuid(c); 1003 1004 /* cyrix could have cpuid enabled via c_identify()*/ 1005 if (!have_cpuid_p()) 1006 return; 1007 1008 cpu_detect(c); 1009 1010 get_cpu_vendor(c); 1011 1012 get_cpu_cap(c); 1013 1014 if (c->cpuid_level >= 0x00000001) { 1015 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1016 #ifdef CONFIG_X86_32 1017 # ifdef CONFIG_SMP 1018 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1019 # else 1020 c->apicid = c->initial_apicid; 1021 # endif 1022 #endif 1023 c->phys_proc_id = c->initial_apicid; 1024 } 1025 1026 get_model_name(c); /* Default name */ 1027 1028 detect_nopl(c); 1029 1030 detect_null_seg_behavior(c); 1031 1032 /* 1033 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1034 * systems that run Linux at CPL > 0 may or may not have the 1035 * issue, but, even if they have the issue, there's absolutely 1036 * nothing we can do about it because we can't use the real IRET 1037 * instruction. 1038 * 1039 * NB: For the time being, only 32-bit kernels support 1040 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1041 * whether to apply espfix using paravirt hooks. If any 1042 * non-paravirt system ever shows up that does *not* have the 1043 * ESPFIX issue, we can change this. 1044 */ 1045 #ifdef CONFIG_X86_32 1046 # ifdef CONFIG_PARAVIRT 1047 do { 1048 extern void native_iret(void); 1049 if (pv_cpu_ops.iret == native_iret) 1050 set_cpu_bug(c, X86_BUG_ESPFIX); 1051 } while (0); 1052 # else 1053 set_cpu_bug(c, X86_BUG_ESPFIX); 1054 # endif 1055 #endif 1056 } 1057 1058 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1059 { 1060 /* 1061 * The heavy lifting of max_rmid and cache_occ_scale are handled 1062 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1063 * in case CQM bits really aren't there in this CPU. 1064 */ 1065 if (c != &boot_cpu_data) { 1066 boot_cpu_data.x86_cache_max_rmid = 1067 min(boot_cpu_data.x86_cache_max_rmid, 1068 c->x86_cache_max_rmid); 1069 } 1070 } 1071 1072 /* 1073 * Validate that ACPI/mptables have the same information about the 1074 * effective APIC id and update the package map. 1075 */ 1076 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1077 { 1078 #ifdef CONFIG_SMP 1079 unsigned int apicid, cpu = smp_processor_id(); 1080 1081 apicid = apic->cpu_present_to_apicid(cpu); 1082 1083 if (apicid != c->apicid) { 1084 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1085 cpu, apicid, c->initial_apicid); 1086 } 1087 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1088 #else 1089 c->logical_proc_id = 0; 1090 #endif 1091 } 1092 1093 /* 1094 * This does the hard work of actually picking apart the CPU stuff... 1095 */ 1096 static void identify_cpu(struct cpuinfo_x86 *c) 1097 { 1098 int i; 1099 1100 c->loops_per_jiffy = loops_per_jiffy; 1101 c->x86_cache_size = -1; 1102 c->x86_vendor = X86_VENDOR_UNKNOWN; 1103 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 1104 c->x86_vendor_id[0] = '\0'; /* Unset */ 1105 c->x86_model_id[0] = '\0'; /* Unset */ 1106 c->x86_max_cores = 1; 1107 c->x86_coreid_bits = 0; 1108 c->cu_id = 0xff; 1109 #ifdef CONFIG_X86_64 1110 c->x86_clflush_size = 64; 1111 c->x86_phys_bits = 36; 1112 c->x86_virt_bits = 48; 1113 #else 1114 c->cpuid_level = -1; /* CPUID not detected */ 1115 c->x86_clflush_size = 32; 1116 c->x86_phys_bits = 32; 1117 c->x86_virt_bits = 32; 1118 #endif 1119 c->x86_cache_alignment = c->x86_clflush_size; 1120 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1121 1122 generic_identify(c); 1123 1124 if (this_cpu->c_identify) 1125 this_cpu->c_identify(c); 1126 1127 /* Clear/Set all flags overridden by options, after probe */ 1128 apply_forced_caps(c); 1129 1130 #ifdef CONFIG_X86_64 1131 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1132 #endif 1133 1134 /* 1135 * Vendor-specific initialization. In this section we 1136 * canonicalize the feature flags, meaning if there are 1137 * features a certain CPU supports which CPUID doesn't 1138 * tell us, CPUID claiming incorrect flags, or other bugs, 1139 * we handle them here. 1140 * 1141 * At the end of this section, c->x86_capability better 1142 * indicate the features this CPU genuinely supports! 1143 */ 1144 if (this_cpu->c_init) 1145 this_cpu->c_init(c); 1146 1147 /* Disable the PN if appropriate */ 1148 squash_the_stupid_serial_number(c); 1149 1150 /* Set up SMEP/SMAP */ 1151 setup_smep(c); 1152 setup_smap(c); 1153 1154 /* 1155 * The vendor-specific functions might have changed features. 1156 * Now we do "generic changes." 1157 */ 1158 1159 /* Filter out anything that depends on CPUID levels we don't have */ 1160 filter_cpuid_features(c, true); 1161 1162 /* If the model name is still unset, do table lookup. */ 1163 if (!c->x86_model_id[0]) { 1164 const char *p; 1165 p = table_lookup_model(c); 1166 if (p) 1167 strcpy(c->x86_model_id, p); 1168 else 1169 /* Last resort... */ 1170 sprintf(c->x86_model_id, "%02x/%02x", 1171 c->x86, c->x86_model); 1172 } 1173 1174 #ifdef CONFIG_X86_64 1175 detect_ht(c); 1176 #endif 1177 1178 x86_init_rdrand(c); 1179 x86_init_cache_qos(c); 1180 setup_pku(c); 1181 1182 /* 1183 * Clear/Set all flags overridden by options, need do it 1184 * before following smp all cpus cap AND. 1185 */ 1186 apply_forced_caps(c); 1187 1188 /* 1189 * On SMP, boot_cpu_data holds the common feature set between 1190 * all CPUs; so make sure that we indicate which features are 1191 * common between the CPUs. The first time this routine gets 1192 * executed, c == &boot_cpu_data. 1193 */ 1194 if (c != &boot_cpu_data) { 1195 /* AND the already accumulated flags with these */ 1196 for (i = 0; i < NCAPINTS; i++) 1197 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1198 1199 /* OR, i.e. replicate the bug flags */ 1200 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1201 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1202 } 1203 1204 /* Init Machine Check Exception if available. */ 1205 mcheck_cpu_init(c); 1206 1207 select_idle_routine(c); 1208 1209 #ifdef CONFIG_NUMA 1210 numa_add_cpu(smp_processor_id()); 1211 #endif 1212 } 1213 1214 /* 1215 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1216 * on 32-bit kernels: 1217 */ 1218 #ifdef CONFIG_X86_32 1219 void enable_sep_cpu(void) 1220 { 1221 struct tss_struct *tss; 1222 int cpu; 1223 1224 if (!boot_cpu_has(X86_FEATURE_SEP)) 1225 return; 1226 1227 cpu = get_cpu(); 1228 tss = &per_cpu(cpu_tss, cpu); 1229 1230 /* 1231 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1232 * see the big comment in struct x86_hw_tss's definition. 1233 */ 1234 1235 tss->x86_tss.ss1 = __KERNEL_CS; 1236 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1237 1238 wrmsr(MSR_IA32_SYSENTER_ESP, 1239 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1240 0); 1241 1242 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1243 1244 put_cpu(); 1245 } 1246 #endif 1247 1248 void __init identify_boot_cpu(void) 1249 { 1250 identify_cpu(&boot_cpu_data); 1251 #ifdef CONFIG_X86_32 1252 sysenter_setup(); 1253 enable_sep_cpu(); 1254 #endif 1255 cpu_detect_tlb(&boot_cpu_data); 1256 } 1257 1258 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1259 { 1260 BUG_ON(c == &boot_cpu_data); 1261 identify_cpu(c); 1262 #ifdef CONFIG_X86_32 1263 enable_sep_cpu(); 1264 #endif 1265 mtrr_ap_init(); 1266 validate_apic_and_package_id(c); 1267 } 1268 1269 static __init int setup_noclflush(char *arg) 1270 { 1271 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1272 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1273 return 1; 1274 } 1275 __setup("noclflush", setup_noclflush); 1276 1277 void print_cpu_info(struct cpuinfo_x86 *c) 1278 { 1279 const char *vendor = NULL; 1280 1281 if (c->x86_vendor < X86_VENDOR_NUM) { 1282 vendor = this_cpu->c_vendor; 1283 } else { 1284 if (c->cpuid_level >= 0) 1285 vendor = c->x86_vendor_id; 1286 } 1287 1288 if (vendor && !strstr(c->x86_model_id, vendor)) 1289 pr_cont("%s ", vendor); 1290 1291 if (c->x86_model_id[0]) 1292 pr_cont("%s", c->x86_model_id); 1293 else 1294 pr_cont("%d86", c->x86); 1295 1296 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1297 1298 if (c->x86_mask || c->cpuid_level >= 0) 1299 pr_cont(", stepping: 0x%x)\n", c->x86_mask); 1300 else 1301 pr_cont(")\n"); 1302 } 1303 1304 static __init int setup_disablecpuid(char *arg) 1305 { 1306 int bit; 1307 1308 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32) 1309 setup_clear_cpu_cap(bit); 1310 else 1311 return 0; 1312 1313 return 1; 1314 } 1315 __setup("clearcpuid=", setup_disablecpuid); 1316 1317 #ifdef CONFIG_X86_64 1318 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1319 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1320 1321 /* 1322 * The following percpu variables are hot. Align current_task to 1323 * cacheline size such that they fall in the same cacheline. 1324 */ 1325 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1326 &init_task; 1327 EXPORT_PER_CPU_SYMBOL(current_task); 1328 1329 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1330 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1331 1332 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1333 1334 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1335 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1336 1337 /* 1338 * Special IST stacks which the CPU switches to when it calls 1339 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1340 * limit), all of them are 4K, except the debug stack which 1341 * is 8K. 1342 */ 1343 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1344 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1345 [DEBUG_STACK - 1] = DEBUG_STKSZ 1346 }; 1347 1348 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1349 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1350 1351 /* May not be marked __init: used by software suspend */ 1352 void syscall_init(void) 1353 { 1354 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1355 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1356 1357 #ifdef CONFIG_IA32_EMULATION 1358 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1359 /* 1360 * This only works on Intel CPUs. 1361 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1362 * This does not cause SYSENTER to jump to the wrong location, because 1363 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1364 */ 1365 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1366 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1367 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1368 #else 1369 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1370 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1371 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1372 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1373 #endif 1374 1375 /* Flags to clear on syscall */ 1376 wrmsrl(MSR_SYSCALL_MASK, 1377 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1378 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1379 } 1380 1381 /* 1382 * Copies of the original ist values from the tss are only accessed during 1383 * debugging, no special alignment required. 1384 */ 1385 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1386 1387 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1388 DEFINE_PER_CPU(int, debug_stack_usage); 1389 1390 int is_debug_stack(unsigned long addr) 1391 { 1392 return __this_cpu_read(debug_stack_usage) || 1393 (addr <= __this_cpu_read(debug_stack_addr) && 1394 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1395 } 1396 NOKPROBE_SYMBOL(is_debug_stack); 1397 1398 DEFINE_PER_CPU(u32, debug_idt_ctr); 1399 1400 void debug_stack_set_zero(void) 1401 { 1402 this_cpu_inc(debug_idt_ctr); 1403 load_current_idt(); 1404 } 1405 NOKPROBE_SYMBOL(debug_stack_set_zero); 1406 1407 void debug_stack_reset(void) 1408 { 1409 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1410 return; 1411 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1412 load_current_idt(); 1413 } 1414 NOKPROBE_SYMBOL(debug_stack_reset); 1415 1416 #else /* CONFIG_X86_64 */ 1417 1418 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1419 EXPORT_PER_CPU_SYMBOL(current_task); 1420 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1421 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1422 1423 /* 1424 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1425 * the top of the kernel stack. Use an extra percpu variable to track the 1426 * top of the kernel stack directly. 1427 */ 1428 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1429 (unsigned long)&init_thread_union + THREAD_SIZE; 1430 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1431 1432 #ifdef CONFIG_CC_STACKPROTECTOR 1433 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1434 #endif 1435 1436 #endif /* CONFIG_X86_64 */ 1437 1438 /* 1439 * Clear all 6 debug registers: 1440 */ 1441 static void clear_all_debug_regs(void) 1442 { 1443 int i; 1444 1445 for (i = 0; i < 8; i++) { 1446 /* Ignore db4, db5 */ 1447 if ((i == 4) || (i == 5)) 1448 continue; 1449 1450 set_debugreg(0, i); 1451 } 1452 } 1453 1454 #ifdef CONFIG_KGDB 1455 /* 1456 * Restore debug regs if using kgdbwait and you have a kernel debugger 1457 * connection established. 1458 */ 1459 static void dbg_restore_debug_regs(void) 1460 { 1461 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1462 arch_kgdb_ops.correct_hw_break(); 1463 } 1464 #else /* ! CONFIG_KGDB */ 1465 #define dbg_restore_debug_regs() 1466 #endif /* ! CONFIG_KGDB */ 1467 1468 static void wait_for_master_cpu(int cpu) 1469 { 1470 #ifdef CONFIG_SMP 1471 /* 1472 * wait for ACK from master CPU before continuing 1473 * with AP initialization 1474 */ 1475 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1476 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1477 cpu_relax(); 1478 #endif 1479 } 1480 1481 /* 1482 * cpu_init() initializes state that is per-CPU. Some data is already 1483 * initialized (naturally) in the bootstrap process, such as the GDT 1484 * and IDT. We reload them nevertheless, this function acts as a 1485 * 'CPU state barrier', nothing should get across. 1486 * A lot of state is already set up in PDA init for 64 bit 1487 */ 1488 #ifdef CONFIG_X86_64 1489 1490 void cpu_init(void) 1491 { 1492 struct orig_ist *oist; 1493 struct task_struct *me; 1494 struct tss_struct *t; 1495 unsigned long v; 1496 int cpu = raw_smp_processor_id(); 1497 int i; 1498 1499 wait_for_master_cpu(cpu); 1500 1501 /* 1502 * Initialize the CR4 shadow before doing anything that could 1503 * try to read it. 1504 */ 1505 cr4_init_shadow(); 1506 1507 if (cpu) 1508 load_ucode_ap(); 1509 1510 t = &per_cpu(cpu_tss, cpu); 1511 oist = &per_cpu(orig_ist, cpu); 1512 1513 #ifdef CONFIG_NUMA 1514 if (this_cpu_read(numa_node) == 0 && 1515 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1516 set_numa_node(early_cpu_to_node(cpu)); 1517 #endif 1518 1519 me = current; 1520 1521 pr_debug("Initializing CPU#%d\n", cpu); 1522 1523 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1524 1525 /* 1526 * Initialize the per-CPU GDT with the boot GDT, 1527 * and set up the GDT descriptor: 1528 */ 1529 1530 switch_to_new_gdt(cpu); 1531 loadsegment(fs, 0); 1532 1533 load_current_idt(); 1534 1535 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1536 syscall_init(); 1537 1538 wrmsrl(MSR_FS_BASE, 0); 1539 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1540 barrier(); 1541 1542 x86_configure_nx(); 1543 x2apic_setup(); 1544 1545 /* 1546 * set up and load the per-CPU TSS 1547 */ 1548 if (!oist->ist[0]) { 1549 char *estacks = per_cpu(exception_stacks, cpu); 1550 1551 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1552 estacks += exception_stack_sizes[v]; 1553 oist->ist[v] = t->x86_tss.ist[v] = 1554 (unsigned long)estacks; 1555 if (v == DEBUG_STACK-1) 1556 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1557 } 1558 } 1559 1560 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1561 1562 /* 1563 * <= is required because the CPU will access up to 1564 * 8 bits beyond the end of the IO permission bitmap. 1565 */ 1566 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1567 t->io_bitmap[i] = ~0UL; 1568 1569 mmgrab(&init_mm); 1570 me->active_mm = &init_mm; 1571 BUG_ON(me->mm); 1572 initialize_tlbstate_and_flush(); 1573 enter_lazy_tlb(&init_mm, me); 1574 1575 load_sp0(t, ¤t->thread); 1576 set_tss_desc(cpu, t); 1577 load_TR_desc(); 1578 load_mm_ldt(&init_mm); 1579 1580 clear_all_debug_regs(); 1581 dbg_restore_debug_regs(); 1582 1583 fpu__init_cpu(); 1584 1585 if (is_uv_system()) 1586 uv_cpu_init(); 1587 1588 setup_fixmap_gdt(cpu); 1589 load_fixmap_gdt(cpu); 1590 } 1591 1592 #else 1593 1594 void cpu_init(void) 1595 { 1596 int cpu = smp_processor_id(); 1597 struct task_struct *curr = current; 1598 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1599 struct thread_struct *thread = &curr->thread; 1600 1601 wait_for_master_cpu(cpu); 1602 1603 /* 1604 * Initialize the CR4 shadow before doing anything that could 1605 * try to read it. 1606 */ 1607 cr4_init_shadow(); 1608 1609 show_ucode_info_early(); 1610 1611 pr_info("Initializing CPU#%d\n", cpu); 1612 1613 if (cpu_feature_enabled(X86_FEATURE_VME) || 1614 boot_cpu_has(X86_FEATURE_TSC) || 1615 boot_cpu_has(X86_FEATURE_DE)) 1616 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1617 1618 load_current_idt(); 1619 switch_to_new_gdt(cpu); 1620 1621 /* 1622 * Set up and load the per-CPU TSS and LDT 1623 */ 1624 mmgrab(&init_mm); 1625 curr->active_mm = &init_mm; 1626 BUG_ON(curr->mm); 1627 initialize_tlbstate_and_flush(); 1628 enter_lazy_tlb(&init_mm, curr); 1629 1630 load_sp0(t, thread); 1631 set_tss_desc(cpu, t); 1632 load_TR_desc(); 1633 load_mm_ldt(&init_mm); 1634 1635 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1636 1637 #ifdef CONFIG_DOUBLEFAULT 1638 /* Set up doublefault TSS pointer in the GDT */ 1639 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1640 #endif 1641 1642 clear_all_debug_regs(); 1643 dbg_restore_debug_regs(); 1644 1645 fpu__init_cpu(); 1646 1647 setup_fixmap_gdt(cpu); 1648 load_fixmap_gdt(cpu); 1649 } 1650 #endif 1651 1652 static void bsp_resume(void) 1653 { 1654 if (this_cpu->c_bsp_resume) 1655 this_cpu->c_bsp_resume(&boot_cpu_data); 1656 } 1657 1658 static struct syscore_ops cpu_syscore_ops = { 1659 .resume = bsp_resume, 1660 }; 1661 1662 static int __init init_cpu_syscore(void) 1663 { 1664 register_syscore_ops(&cpu_syscore_ops); 1665 return 0; 1666 } 1667 core_initcall(init_cpu_syscore); 1668