1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 26 #include <asm/cmdline.h> 27 #include <asm/stackprotector.h> 28 #include <asm/perf_event.h> 29 #include <asm/mmu_context.h> 30 #include <asm/doublefault.h> 31 #include <asm/archrandom.h> 32 #include <asm/hypervisor.h> 33 #include <asm/processor.h> 34 #include <asm/tlbflush.h> 35 #include <asm/debugreg.h> 36 #include <asm/sections.h> 37 #include <asm/vsyscall.h> 38 #include <linux/topology.h> 39 #include <linux/cpumask.h> 40 #include <linux/atomic.h> 41 #include <asm/proto.h> 42 #include <asm/setup.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/fpu/api.h> 46 #include <asm/mtrr.h> 47 #include <asm/hwcap2.h> 48 #include <linux/numa.h> 49 #include <asm/numa.h> 50 #include <asm/asm.h> 51 #include <asm/bugs.h> 52 #include <asm/cpu.h> 53 #include <asm/mce.h> 54 #include <asm/msr.h> 55 #include <asm/memtype.h> 56 #include <asm/microcode.h> 57 #include <asm/microcode_intel.h> 58 #include <asm/intel-family.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/uv/uv.h> 61 #include <asm/sigframe.h> 62 63 #include "cpu.h" 64 65 u32 elf_hwcap2 __read_mostly; 66 67 /* all of these masks are initialized in setup_cpu_local_masks() */ 68 cpumask_var_t cpu_initialized_mask; 69 cpumask_var_t cpu_callout_mask; 70 cpumask_var_t cpu_callin_mask; 71 72 /* representing cpus for which sibling maps can be computed */ 73 cpumask_var_t cpu_sibling_setup_mask; 74 75 /* Number of siblings per CPU package */ 76 int smp_num_siblings = 1; 77 EXPORT_SYMBOL(smp_num_siblings); 78 79 /* Last level cache ID of each logical CPU */ 80 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 81 82 u16 get_llc_id(unsigned int cpu) 83 { 84 return per_cpu(cpu_llc_id, cpu); 85 } 86 EXPORT_SYMBOL_GPL(get_llc_id); 87 88 /* L2 cache ID of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 90 91 /* correctly size the local cpu masks */ 92 void __init setup_cpu_local_masks(void) 93 { 94 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 95 alloc_bootmem_cpumask_var(&cpu_callin_mask); 96 alloc_bootmem_cpumask_var(&cpu_callout_mask); 97 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 98 } 99 100 static void default_init(struct cpuinfo_x86 *c) 101 { 102 #ifdef CONFIG_X86_64 103 cpu_detect_cache_sizes(c); 104 #else 105 /* Not much we can do here... */ 106 /* Check if at least it has cpuid */ 107 if (c->cpuid_level == -1) { 108 /* No cpuid. It must be an ancient CPU */ 109 if (c->x86 == 4) 110 strcpy(c->x86_model_id, "486"); 111 else if (c->x86 == 3) 112 strcpy(c->x86_model_id, "386"); 113 } 114 #endif 115 } 116 117 static const struct cpu_dev default_cpu = { 118 .c_init = default_init, 119 .c_vendor = "Unknown", 120 .c_x86_vendor = X86_VENDOR_UNKNOWN, 121 }; 122 123 static const struct cpu_dev *this_cpu = &default_cpu; 124 125 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 126 #ifdef CONFIG_X86_64 127 /* 128 * We need valid kernel segments for data and code in long mode too 129 * IRET will check the segment types kkeil 2000/10/28 130 * Also sysret mandates a special GDT layout 131 * 132 * TLS descriptors are currently at a different place compared to i386. 133 * Hopefully nobody expects them at a fixed place (Wine?) 134 */ 135 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 136 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 137 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 138 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 139 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 140 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 141 #else 142 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 143 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 144 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 145 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 146 /* 147 * Segments used for calling PnP BIOS have byte granularity. 148 * They code segments and data segments have fixed 64k limits, 149 * the transfer segment sizes are set at run time. 150 */ 151 /* 32-bit code */ 152 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 153 /* 16-bit code */ 154 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 155 /* 16-bit data */ 156 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 157 /* 16-bit data */ 158 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 159 /* 16-bit data */ 160 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 161 /* 162 * The APM segments have byte granularity and their bases 163 * are set at run time. All have 64k limits. 164 */ 165 /* 32-bit code */ 166 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 167 /* 16-bit code */ 168 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 169 /* data */ 170 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 171 172 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 173 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 174 #endif 175 } }; 176 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 177 178 #ifdef CONFIG_X86_64 179 static int __init x86_nopcid_setup(char *s) 180 { 181 /* nopcid doesn't accept parameters */ 182 if (s) 183 return -EINVAL; 184 185 /* do not emit a message if the feature is not present */ 186 if (!boot_cpu_has(X86_FEATURE_PCID)) 187 return 0; 188 189 setup_clear_cpu_cap(X86_FEATURE_PCID); 190 pr_info("nopcid: PCID feature disabled\n"); 191 return 0; 192 } 193 early_param("nopcid", x86_nopcid_setup); 194 #endif 195 196 static int __init x86_noinvpcid_setup(char *s) 197 { 198 /* noinvpcid doesn't accept parameters */ 199 if (s) 200 return -EINVAL; 201 202 /* do not emit a message if the feature is not present */ 203 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 204 return 0; 205 206 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 207 pr_info("noinvpcid: INVPCID feature disabled\n"); 208 return 0; 209 } 210 early_param("noinvpcid", x86_noinvpcid_setup); 211 212 #ifdef CONFIG_X86_32 213 static int cachesize_override = -1; 214 static int disable_x86_serial_nr = 1; 215 216 static int __init cachesize_setup(char *str) 217 { 218 get_option(&str, &cachesize_override); 219 return 1; 220 } 221 __setup("cachesize=", cachesize_setup); 222 223 static int __init x86_sep_setup(char *s) 224 { 225 setup_clear_cpu_cap(X86_FEATURE_SEP); 226 return 1; 227 } 228 __setup("nosep", x86_sep_setup); 229 230 /* Standard macro to see if a specific flag is changeable */ 231 static inline int flag_is_changeable_p(u32 flag) 232 { 233 u32 f1, f2; 234 235 /* 236 * Cyrix and IDT cpus allow disabling of CPUID 237 * so the code below may return different results 238 * when it is executed before and after enabling 239 * the CPUID. Add "volatile" to not allow gcc to 240 * optimize the subsequent calls to this function. 241 */ 242 asm volatile ("pushfl \n\t" 243 "pushfl \n\t" 244 "popl %0 \n\t" 245 "movl %0, %1 \n\t" 246 "xorl %2, %0 \n\t" 247 "pushl %0 \n\t" 248 "popfl \n\t" 249 "pushfl \n\t" 250 "popl %0 \n\t" 251 "popfl \n\t" 252 253 : "=&r" (f1), "=&r" (f2) 254 : "ir" (flag)); 255 256 return ((f1^f2) & flag) != 0; 257 } 258 259 /* Probe for the CPUID instruction */ 260 int have_cpuid_p(void) 261 { 262 return flag_is_changeable_p(X86_EFLAGS_ID); 263 } 264 265 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 266 { 267 unsigned long lo, hi; 268 269 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 270 return; 271 272 /* Disable processor serial number: */ 273 274 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 275 lo |= 0x200000; 276 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 277 278 pr_notice("CPU serial number disabled.\n"); 279 clear_cpu_cap(c, X86_FEATURE_PN); 280 281 /* Disabling the serial number may affect the cpuid level */ 282 c->cpuid_level = cpuid_eax(0); 283 } 284 285 static int __init x86_serial_nr_setup(char *s) 286 { 287 disable_x86_serial_nr = 0; 288 return 1; 289 } 290 __setup("serialnumber", x86_serial_nr_setup); 291 #else 292 static inline int flag_is_changeable_p(u32 flag) 293 { 294 return 1; 295 } 296 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 297 { 298 } 299 #endif 300 301 static __init int setup_disable_smep(char *arg) 302 { 303 setup_clear_cpu_cap(X86_FEATURE_SMEP); 304 return 1; 305 } 306 __setup("nosmep", setup_disable_smep); 307 308 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 309 { 310 if (cpu_has(c, X86_FEATURE_SMEP)) 311 cr4_set_bits(X86_CR4_SMEP); 312 } 313 314 static __init int setup_disable_smap(char *arg) 315 { 316 setup_clear_cpu_cap(X86_FEATURE_SMAP); 317 return 1; 318 } 319 __setup("nosmap", setup_disable_smap); 320 321 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 322 { 323 unsigned long eflags = native_save_fl(); 324 325 /* This should have been cleared long ago */ 326 BUG_ON(eflags & X86_EFLAGS_AC); 327 328 if (cpu_has(c, X86_FEATURE_SMAP)) { 329 #ifdef CONFIG_X86_SMAP 330 cr4_set_bits(X86_CR4_SMAP); 331 #else 332 clear_cpu_cap(c, X86_FEATURE_SMAP); 333 cr4_clear_bits(X86_CR4_SMAP); 334 #endif 335 } 336 } 337 338 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 339 { 340 /* Check the boot processor, plus build option for UMIP. */ 341 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 342 goto out; 343 344 /* Check the current processor's cpuid bits. */ 345 if (!cpu_has(c, X86_FEATURE_UMIP)) 346 goto out; 347 348 cr4_set_bits(X86_CR4_UMIP); 349 350 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 351 352 return; 353 354 out: 355 /* 356 * Make sure UMIP is disabled in case it was enabled in a 357 * previous boot (e.g., via kexec). 358 */ 359 cr4_clear_bits(X86_CR4_UMIP); 360 } 361 362 /* These bits should not change their value after CPU init is finished. */ 363 static const unsigned long cr4_pinned_mask = 364 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE; 365 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 366 static unsigned long cr4_pinned_bits __ro_after_init; 367 368 void native_write_cr0(unsigned long val) 369 { 370 unsigned long bits_missing = 0; 371 372 set_register: 373 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 374 375 if (static_branch_likely(&cr_pinning)) { 376 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 377 bits_missing = X86_CR0_WP; 378 val |= bits_missing; 379 goto set_register; 380 } 381 /* Warn after we've set the missing bits. */ 382 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 383 } 384 } 385 EXPORT_SYMBOL(native_write_cr0); 386 387 void native_write_cr4(unsigned long val) 388 { 389 unsigned long bits_changed = 0; 390 391 set_register: 392 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 393 394 if (static_branch_likely(&cr_pinning)) { 395 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 396 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 397 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 398 goto set_register; 399 } 400 /* Warn after we've corrected the changed bits. */ 401 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 402 bits_changed); 403 } 404 } 405 #if IS_MODULE(CONFIG_LKDTM) 406 EXPORT_SYMBOL_GPL(native_write_cr4); 407 #endif 408 409 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 410 { 411 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 412 413 lockdep_assert_irqs_disabled(); 414 415 newval = (cr4 & ~clear) | set; 416 if (newval != cr4) { 417 this_cpu_write(cpu_tlbstate.cr4, newval); 418 __write_cr4(newval); 419 } 420 } 421 EXPORT_SYMBOL(cr4_update_irqsoff); 422 423 /* Read the CR4 shadow. */ 424 unsigned long cr4_read_shadow(void) 425 { 426 return this_cpu_read(cpu_tlbstate.cr4); 427 } 428 EXPORT_SYMBOL_GPL(cr4_read_shadow); 429 430 void cr4_init(void) 431 { 432 unsigned long cr4 = __read_cr4(); 433 434 if (boot_cpu_has(X86_FEATURE_PCID)) 435 cr4 |= X86_CR4_PCIDE; 436 if (static_branch_likely(&cr_pinning)) 437 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 438 439 __write_cr4(cr4); 440 441 /* Initialize cr4 shadow for this CPU. */ 442 this_cpu_write(cpu_tlbstate.cr4, cr4); 443 } 444 445 /* 446 * Once CPU feature detection is finished (and boot params have been 447 * parsed), record any of the sensitive CR bits that are set, and 448 * enable CR pinning. 449 */ 450 static void __init setup_cr_pinning(void) 451 { 452 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 453 static_key_enable(&cr_pinning.key); 454 } 455 456 static __init int x86_nofsgsbase_setup(char *arg) 457 { 458 /* Require an exact match without trailing characters. */ 459 if (strlen(arg)) 460 return 0; 461 462 /* Do not emit a message if the feature is not present. */ 463 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 464 return 1; 465 466 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 467 pr_info("FSGSBASE disabled via kernel command line\n"); 468 return 1; 469 } 470 __setup("nofsgsbase", x86_nofsgsbase_setup); 471 472 /* 473 * Protection Keys are not available in 32-bit mode. 474 */ 475 static bool pku_disabled; 476 477 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 478 { 479 if (c == &boot_cpu_data) { 480 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 481 return; 482 /* 483 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 484 * bit to be set. Enforce it. 485 */ 486 setup_force_cpu_cap(X86_FEATURE_OSPKE); 487 488 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 489 return; 490 } 491 492 cr4_set_bits(X86_CR4_PKE); 493 /* Load the default PKRU value */ 494 pkru_write_default(); 495 } 496 497 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 498 static __init int setup_disable_pku(char *arg) 499 { 500 /* 501 * Do not clear the X86_FEATURE_PKU bit. All of the 502 * runtime checks are against OSPKE so clearing the 503 * bit does nothing. 504 * 505 * This way, we will see "pku" in cpuinfo, but not 506 * "ospke", which is exactly what we want. It shows 507 * that the CPU has PKU, but the OS has not enabled it. 508 * This happens to be exactly how a system would look 509 * if we disabled the config option. 510 */ 511 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 512 pku_disabled = true; 513 return 1; 514 } 515 __setup("nopku", setup_disable_pku); 516 #endif /* CONFIG_X86_64 */ 517 518 /* 519 * Some CPU features depend on higher CPUID levels, which may not always 520 * be available due to CPUID level capping or broken virtualization 521 * software. Add those features to this table to auto-disable them. 522 */ 523 struct cpuid_dependent_feature { 524 u32 feature; 525 u32 level; 526 }; 527 528 static const struct cpuid_dependent_feature 529 cpuid_dependent_features[] = { 530 { X86_FEATURE_MWAIT, 0x00000005 }, 531 { X86_FEATURE_DCA, 0x00000009 }, 532 { X86_FEATURE_XSAVE, 0x0000000d }, 533 { 0, 0 } 534 }; 535 536 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 537 { 538 const struct cpuid_dependent_feature *df; 539 540 for (df = cpuid_dependent_features; df->feature; df++) { 541 542 if (!cpu_has(c, df->feature)) 543 continue; 544 /* 545 * Note: cpuid_level is set to -1 if unavailable, but 546 * extended_extended_level is set to 0 if unavailable 547 * and the legitimate extended levels are all negative 548 * when signed; hence the weird messing around with 549 * signs here... 550 */ 551 if (!((s32)df->level < 0 ? 552 (u32)df->level > (u32)c->extended_cpuid_level : 553 (s32)df->level > (s32)c->cpuid_level)) 554 continue; 555 556 clear_cpu_cap(c, df->feature); 557 if (!warn) 558 continue; 559 560 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 561 x86_cap_flag(df->feature), df->level); 562 } 563 } 564 565 /* 566 * Naming convention should be: <Name> [(<Codename>)] 567 * This table only is used unless init_<vendor>() below doesn't set it; 568 * in particular, if CPUID levels 0x80000002..4 are supported, this 569 * isn't used 570 */ 571 572 /* Look up CPU names by table lookup. */ 573 static const char *table_lookup_model(struct cpuinfo_x86 *c) 574 { 575 #ifdef CONFIG_X86_32 576 const struct legacy_cpu_model_info *info; 577 578 if (c->x86_model >= 16) 579 return NULL; /* Range check */ 580 581 if (!this_cpu) 582 return NULL; 583 584 info = this_cpu->legacy_models; 585 586 while (info->family) { 587 if (info->family == c->x86) 588 return info->model_names[c->x86_model]; 589 info++; 590 } 591 #endif 592 return NULL; /* Not found */ 593 } 594 595 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 596 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 597 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 598 599 void load_percpu_segment(int cpu) 600 { 601 #ifdef CONFIG_X86_32 602 loadsegment(fs, __KERNEL_PERCPU); 603 #else 604 __loadsegment_simple(gs, 0); 605 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 606 #endif 607 } 608 609 #ifdef CONFIG_X86_32 610 /* The 32-bit entry code needs to find cpu_entry_area. */ 611 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 612 #endif 613 614 /* Load the original GDT from the per-cpu structure */ 615 void load_direct_gdt(int cpu) 616 { 617 struct desc_ptr gdt_descr; 618 619 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 620 gdt_descr.size = GDT_SIZE - 1; 621 load_gdt(&gdt_descr); 622 } 623 EXPORT_SYMBOL_GPL(load_direct_gdt); 624 625 /* Load a fixmap remapping of the per-cpu GDT */ 626 void load_fixmap_gdt(int cpu) 627 { 628 struct desc_ptr gdt_descr; 629 630 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 631 gdt_descr.size = GDT_SIZE - 1; 632 load_gdt(&gdt_descr); 633 } 634 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 635 636 /* 637 * Current gdt points %fs at the "master" per-cpu area: after this, 638 * it's on the real one. 639 */ 640 void switch_to_new_gdt(int cpu) 641 { 642 /* Load the original GDT */ 643 load_direct_gdt(cpu); 644 /* Reload the per-cpu base */ 645 load_percpu_segment(cpu); 646 } 647 648 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 649 650 static void get_model_name(struct cpuinfo_x86 *c) 651 { 652 unsigned int *v; 653 char *p, *q, *s; 654 655 if (c->extended_cpuid_level < 0x80000004) 656 return; 657 658 v = (unsigned int *)c->x86_model_id; 659 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 660 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 661 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 662 c->x86_model_id[48] = 0; 663 664 /* Trim whitespace */ 665 p = q = s = &c->x86_model_id[0]; 666 667 while (*p == ' ') 668 p++; 669 670 while (*p) { 671 /* Note the last non-whitespace index */ 672 if (!isspace(*p)) 673 s = q; 674 675 *q++ = *p++; 676 } 677 678 *(s + 1) = '\0'; 679 } 680 681 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 682 { 683 unsigned int eax, ebx, ecx, edx; 684 685 c->x86_max_cores = 1; 686 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 687 return; 688 689 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 690 if (eax & 0x1f) 691 c->x86_max_cores = (eax >> 26) + 1; 692 } 693 694 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 695 { 696 unsigned int n, dummy, ebx, ecx, edx, l2size; 697 698 n = c->extended_cpuid_level; 699 700 if (n >= 0x80000005) { 701 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 702 c->x86_cache_size = (ecx>>24) + (edx>>24); 703 #ifdef CONFIG_X86_64 704 /* On K8 L1 TLB is inclusive, so don't count it */ 705 c->x86_tlbsize = 0; 706 #endif 707 } 708 709 if (n < 0x80000006) /* Some chips just has a large L1. */ 710 return; 711 712 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 713 l2size = ecx >> 16; 714 715 #ifdef CONFIG_X86_64 716 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 717 #else 718 /* do processor-specific cache resizing */ 719 if (this_cpu->legacy_cache_size) 720 l2size = this_cpu->legacy_cache_size(c, l2size); 721 722 /* Allow user to override all this if necessary. */ 723 if (cachesize_override != -1) 724 l2size = cachesize_override; 725 726 if (l2size == 0) 727 return; /* Again, no L2 cache is possible */ 728 #endif 729 730 c->x86_cache_size = l2size; 731 } 732 733 u16 __read_mostly tlb_lli_4k[NR_INFO]; 734 u16 __read_mostly tlb_lli_2m[NR_INFO]; 735 u16 __read_mostly tlb_lli_4m[NR_INFO]; 736 u16 __read_mostly tlb_lld_4k[NR_INFO]; 737 u16 __read_mostly tlb_lld_2m[NR_INFO]; 738 u16 __read_mostly tlb_lld_4m[NR_INFO]; 739 u16 __read_mostly tlb_lld_1g[NR_INFO]; 740 741 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 742 { 743 if (this_cpu->c_detect_tlb) 744 this_cpu->c_detect_tlb(c); 745 746 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 747 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 748 tlb_lli_4m[ENTRIES]); 749 750 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 751 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 752 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 753 } 754 755 int detect_ht_early(struct cpuinfo_x86 *c) 756 { 757 #ifdef CONFIG_SMP 758 u32 eax, ebx, ecx, edx; 759 760 if (!cpu_has(c, X86_FEATURE_HT)) 761 return -1; 762 763 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 764 return -1; 765 766 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 767 return -1; 768 769 cpuid(1, &eax, &ebx, &ecx, &edx); 770 771 smp_num_siblings = (ebx & 0xff0000) >> 16; 772 if (smp_num_siblings == 1) 773 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 774 #endif 775 return 0; 776 } 777 778 void detect_ht(struct cpuinfo_x86 *c) 779 { 780 #ifdef CONFIG_SMP 781 int index_msb, core_bits; 782 783 if (detect_ht_early(c) < 0) 784 return; 785 786 index_msb = get_count_order(smp_num_siblings); 787 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 788 789 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 790 791 index_msb = get_count_order(smp_num_siblings); 792 793 core_bits = get_count_order(c->x86_max_cores); 794 795 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 796 ((1 << core_bits) - 1); 797 #endif 798 } 799 800 static void get_cpu_vendor(struct cpuinfo_x86 *c) 801 { 802 char *v = c->x86_vendor_id; 803 int i; 804 805 for (i = 0; i < X86_VENDOR_NUM; i++) { 806 if (!cpu_devs[i]) 807 break; 808 809 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 810 (cpu_devs[i]->c_ident[1] && 811 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 812 813 this_cpu = cpu_devs[i]; 814 c->x86_vendor = this_cpu->c_x86_vendor; 815 return; 816 } 817 } 818 819 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 820 "CPU: Your system may be unstable.\n", v); 821 822 c->x86_vendor = X86_VENDOR_UNKNOWN; 823 this_cpu = &default_cpu; 824 } 825 826 void cpu_detect(struct cpuinfo_x86 *c) 827 { 828 /* Get vendor name */ 829 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 830 (unsigned int *)&c->x86_vendor_id[0], 831 (unsigned int *)&c->x86_vendor_id[8], 832 (unsigned int *)&c->x86_vendor_id[4]); 833 834 c->x86 = 4; 835 /* Intel-defined flags: level 0x00000001 */ 836 if (c->cpuid_level >= 0x00000001) { 837 u32 junk, tfms, cap0, misc; 838 839 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 840 c->x86 = x86_family(tfms); 841 c->x86_model = x86_model(tfms); 842 c->x86_stepping = x86_stepping(tfms); 843 844 if (cap0 & (1<<19)) { 845 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 846 c->x86_cache_alignment = c->x86_clflush_size; 847 } 848 } 849 } 850 851 static void apply_forced_caps(struct cpuinfo_x86 *c) 852 { 853 int i; 854 855 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 856 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 857 c->x86_capability[i] |= cpu_caps_set[i]; 858 } 859 } 860 861 static void init_speculation_control(struct cpuinfo_x86 *c) 862 { 863 /* 864 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 865 * and they also have a different bit for STIBP support. Also, 866 * a hypervisor might have set the individual AMD bits even on 867 * Intel CPUs, for finer-grained selection of what's available. 868 */ 869 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 870 set_cpu_cap(c, X86_FEATURE_IBRS); 871 set_cpu_cap(c, X86_FEATURE_IBPB); 872 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 873 } 874 875 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 876 set_cpu_cap(c, X86_FEATURE_STIBP); 877 878 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 879 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 880 set_cpu_cap(c, X86_FEATURE_SSBD); 881 882 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 883 set_cpu_cap(c, X86_FEATURE_IBRS); 884 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 885 } 886 887 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 888 set_cpu_cap(c, X86_FEATURE_IBPB); 889 890 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 891 set_cpu_cap(c, X86_FEATURE_STIBP); 892 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 893 } 894 895 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 896 set_cpu_cap(c, X86_FEATURE_SSBD); 897 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 898 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 899 } 900 } 901 902 void get_cpu_cap(struct cpuinfo_x86 *c) 903 { 904 u32 eax, ebx, ecx, edx; 905 906 /* Intel-defined flags: level 0x00000001 */ 907 if (c->cpuid_level >= 0x00000001) { 908 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 909 910 c->x86_capability[CPUID_1_ECX] = ecx; 911 c->x86_capability[CPUID_1_EDX] = edx; 912 } 913 914 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 915 if (c->cpuid_level >= 0x00000006) 916 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 917 918 /* Additional Intel-defined flags: level 0x00000007 */ 919 if (c->cpuid_level >= 0x00000007) { 920 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 921 c->x86_capability[CPUID_7_0_EBX] = ebx; 922 c->x86_capability[CPUID_7_ECX] = ecx; 923 c->x86_capability[CPUID_7_EDX] = edx; 924 925 /* Check valid sub-leaf index before accessing it */ 926 if (eax >= 1) { 927 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 928 c->x86_capability[CPUID_7_1_EAX] = eax; 929 } 930 } 931 932 /* Extended state features: level 0x0000000d */ 933 if (c->cpuid_level >= 0x0000000d) { 934 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 935 936 c->x86_capability[CPUID_D_1_EAX] = eax; 937 } 938 939 /* AMD-defined flags: level 0x80000001 */ 940 eax = cpuid_eax(0x80000000); 941 c->extended_cpuid_level = eax; 942 943 if ((eax & 0xffff0000) == 0x80000000) { 944 if (eax >= 0x80000001) { 945 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 946 947 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 948 c->x86_capability[CPUID_8000_0001_EDX] = edx; 949 } 950 } 951 952 if (c->extended_cpuid_level >= 0x80000007) { 953 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 954 955 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 956 c->x86_power = edx; 957 } 958 959 if (c->extended_cpuid_level >= 0x80000008) { 960 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 961 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 962 } 963 964 if (c->extended_cpuid_level >= 0x8000000a) 965 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 966 967 if (c->extended_cpuid_level >= 0x8000001f) 968 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 969 970 init_scattered_cpuid_features(c); 971 init_speculation_control(c); 972 973 /* 974 * Clear/Set all flags overridden by options, after probe. 975 * This needs to happen each time we re-probe, which may happen 976 * several times during CPU initialization. 977 */ 978 apply_forced_caps(c); 979 } 980 981 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 982 { 983 u32 eax, ebx, ecx, edx; 984 985 if (c->extended_cpuid_level >= 0x80000008) { 986 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 987 988 c->x86_virt_bits = (eax >> 8) & 0xff; 989 c->x86_phys_bits = eax & 0xff; 990 } 991 #ifdef CONFIG_X86_32 992 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 993 c->x86_phys_bits = 36; 994 #endif 995 c->x86_cache_bits = c->x86_phys_bits; 996 } 997 998 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 999 { 1000 #ifdef CONFIG_X86_32 1001 int i; 1002 1003 /* 1004 * First of all, decide if this is a 486 or higher 1005 * It's a 486 if we can modify the AC flag 1006 */ 1007 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1008 c->x86 = 4; 1009 else 1010 c->x86 = 3; 1011 1012 for (i = 0; i < X86_VENDOR_NUM; i++) 1013 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1014 c->x86_vendor_id[0] = 0; 1015 cpu_devs[i]->c_identify(c); 1016 if (c->x86_vendor_id[0]) { 1017 get_cpu_vendor(c); 1018 break; 1019 } 1020 } 1021 #endif 1022 } 1023 1024 #define NO_SPECULATION BIT(0) 1025 #define NO_MELTDOWN BIT(1) 1026 #define NO_SSB BIT(2) 1027 #define NO_L1TF BIT(3) 1028 #define NO_MDS BIT(4) 1029 #define MSBDS_ONLY BIT(5) 1030 #define NO_SWAPGS BIT(6) 1031 #define NO_ITLB_MULTIHIT BIT(7) 1032 #define NO_SPECTRE_V2 BIT(8) 1033 1034 #define VULNWL(vendor, family, model, whitelist) \ 1035 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1036 1037 #define VULNWL_INTEL(model, whitelist) \ 1038 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1039 1040 #define VULNWL_AMD(family, whitelist) \ 1041 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1042 1043 #define VULNWL_HYGON(family, whitelist) \ 1044 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1045 1046 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1047 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1048 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1049 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1050 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1051 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1052 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1053 1054 /* Intel Family 6 */ 1055 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1056 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1057 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1058 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1059 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1060 1061 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1062 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1063 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1064 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1065 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1066 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1067 1068 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1069 1070 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1071 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1072 1073 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1074 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1075 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1076 1077 /* 1078 * Technically, swapgs isn't serializing on AMD (despite it previously 1079 * being documented as such in the APM). But according to AMD, %gs is 1080 * updated non-speculatively, and the issuing of %gs-relative memory 1081 * operands will be blocked until the %gs update completes, which is 1082 * good enough for our purposes. 1083 */ 1084 1085 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1086 1087 /* AMD Family 0xf - 0x12 */ 1088 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1089 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1090 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1091 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1092 1093 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1094 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1095 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1096 1097 /* Zhaoxin Family 7 */ 1098 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1099 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1100 {} 1101 }; 1102 1103 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1104 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1105 INTEL_FAM6_##model, steppings, \ 1106 X86_FEATURE_ANY, issues) 1107 1108 #define SRBDS BIT(0) 1109 1110 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1111 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1112 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1113 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1114 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1115 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1116 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1117 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS), 1118 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS), 1119 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS), 1120 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS), 1121 {} 1122 }; 1123 1124 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1125 { 1126 const struct x86_cpu_id *m = x86_match_cpu(table); 1127 1128 return m && !!(m->driver_data & which); 1129 } 1130 1131 u64 x86_read_arch_cap_msr(void) 1132 { 1133 u64 ia32_cap = 0; 1134 1135 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1136 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1137 1138 return ia32_cap; 1139 } 1140 1141 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1142 { 1143 u64 ia32_cap = x86_read_arch_cap_msr(); 1144 1145 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1146 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1147 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1148 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1149 1150 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1151 return; 1152 1153 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1154 1155 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1156 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1157 1158 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1159 !(ia32_cap & ARCH_CAP_SSB_NO) && 1160 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1161 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1162 1163 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1164 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1165 1166 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1167 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1168 setup_force_cpu_bug(X86_BUG_MDS); 1169 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1170 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1171 } 1172 1173 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1174 setup_force_cpu_bug(X86_BUG_SWAPGS); 1175 1176 /* 1177 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1178 * - TSX is supported or 1179 * - TSX_CTRL is present 1180 * 1181 * TSX_CTRL check is needed for cases when TSX could be disabled before 1182 * the kernel boot e.g. kexec. 1183 * TSX_CTRL check alone is not sufficient for cases when the microcode 1184 * update is not present or running as guest that don't get TSX_CTRL. 1185 */ 1186 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1187 (cpu_has(c, X86_FEATURE_RTM) || 1188 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1189 setup_force_cpu_bug(X86_BUG_TAA); 1190 1191 /* 1192 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1193 * in the vulnerability blacklist. 1194 */ 1195 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1196 cpu_has(c, X86_FEATURE_RDSEED)) && 1197 cpu_matches(cpu_vuln_blacklist, SRBDS)) 1198 setup_force_cpu_bug(X86_BUG_SRBDS); 1199 1200 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1201 return; 1202 1203 /* Rogue Data Cache Load? No! */ 1204 if (ia32_cap & ARCH_CAP_RDCL_NO) 1205 return; 1206 1207 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1208 1209 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1210 return; 1211 1212 setup_force_cpu_bug(X86_BUG_L1TF); 1213 } 1214 1215 /* 1216 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1217 * unfortunately, that's not true in practice because of early VIA 1218 * chips and (more importantly) broken virtualizers that are not easy 1219 * to detect. In the latter case it doesn't even *fail* reliably, so 1220 * probing for it doesn't even work. Disable it completely on 32-bit 1221 * unless we can find a reliable way to detect all the broken cases. 1222 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1223 */ 1224 static void detect_nopl(void) 1225 { 1226 #ifdef CONFIG_X86_32 1227 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1228 #else 1229 setup_force_cpu_cap(X86_FEATURE_NOPL); 1230 #endif 1231 } 1232 1233 /* 1234 * We parse cpu parameters early because fpu__init_system() is executed 1235 * before parse_early_param(). 1236 */ 1237 static void __init cpu_parse_early_param(void) 1238 { 1239 char arg[128]; 1240 char *argptr = arg; 1241 int arglen, res, bit; 1242 1243 #ifdef CONFIG_X86_32 1244 if (cmdline_find_option_bool(boot_command_line, "no387")) 1245 #ifdef CONFIG_MATH_EMULATION 1246 setup_clear_cpu_cap(X86_FEATURE_FPU); 1247 #else 1248 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1249 #endif 1250 1251 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1252 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1253 #endif 1254 1255 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1256 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1257 1258 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1259 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1260 1261 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1262 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1263 1264 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1265 if (arglen <= 0) 1266 return; 1267 1268 pr_info("Clearing CPUID bits:"); 1269 do { 1270 res = get_option(&argptr, &bit); 1271 if (res == 0 || res == 3) 1272 break; 1273 1274 /* If the argument was too long, the last bit may be cut off */ 1275 if (res == 1 && arglen >= sizeof(arg)) 1276 break; 1277 1278 if (bit >= 0 && bit < NCAPINTS * 32) { 1279 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1280 setup_clear_cpu_cap(bit); 1281 } 1282 } while (res == 2); 1283 pr_cont("\n"); 1284 } 1285 1286 /* 1287 * Do minimum CPU detection early. 1288 * Fields really needed: vendor, cpuid_level, family, model, mask, 1289 * cache alignment. 1290 * The others are not touched to avoid unwanted side effects. 1291 * 1292 * WARNING: this function is only called on the boot CPU. Don't add code 1293 * here that is supposed to run on all CPUs. 1294 */ 1295 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1296 { 1297 #ifdef CONFIG_X86_64 1298 c->x86_clflush_size = 64; 1299 c->x86_phys_bits = 36; 1300 c->x86_virt_bits = 48; 1301 #else 1302 c->x86_clflush_size = 32; 1303 c->x86_phys_bits = 32; 1304 c->x86_virt_bits = 32; 1305 #endif 1306 c->x86_cache_alignment = c->x86_clflush_size; 1307 1308 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1309 c->extended_cpuid_level = 0; 1310 1311 if (!have_cpuid_p()) 1312 identify_cpu_without_cpuid(c); 1313 1314 /* cyrix could have cpuid enabled via c_identify()*/ 1315 if (have_cpuid_p()) { 1316 cpu_detect(c); 1317 get_cpu_vendor(c); 1318 get_cpu_cap(c); 1319 get_cpu_address_sizes(c); 1320 setup_force_cpu_cap(X86_FEATURE_CPUID); 1321 cpu_parse_early_param(); 1322 1323 if (this_cpu->c_early_init) 1324 this_cpu->c_early_init(c); 1325 1326 c->cpu_index = 0; 1327 filter_cpuid_features(c, false); 1328 1329 if (this_cpu->c_bsp_init) 1330 this_cpu->c_bsp_init(c); 1331 } else { 1332 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1333 } 1334 1335 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1336 1337 cpu_set_bug_bits(c); 1338 1339 sld_setup(c); 1340 1341 fpu__init_system(c); 1342 1343 init_sigframe_size(); 1344 1345 #ifdef CONFIG_X86_32 1346 /* 1347 * Regardless of whether PCID is enumerated, the SDM says 1348 * that it can't be enabled in 32-bit mode. 1349 */ 1350 setup_clear_cpu_cap(X86_FEATURE_PCID); 1351 #endif 1352 1353 /* 1354 * Later in the boot process pgtable_l5_enabled() relies on 1355 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1356 * enabled by this point we need to clear the feature bit to avoid 1357 * false-positives at the later stage. 1358 * 1359 * pgtable_l5_enabled() can be false here for several reasons: 1360 * - 5-level paging is disabled compile-time; 1361 * - it's 32-bit kernel; 1362 * - machine doesn't support 5-level paging; 1363 * - user specified 'no5lvl' in kernel command line. 1364 */ 1365 if (!pgtable_l5_enabled()) 1366 setup_clear_cpu_cap(X86_FEATURE_LA57); 1367 1368 detect_nopl(); 1369 } 1370 1371 void __init early_cpu_init(void) 1372 { 1373 const struct cpu_dev *const *cdev; 1374 int count = 0; 1375 1376 #ifdef CONFIG_PROCESSOR_SELECT 1377 pr_info("KERNEL supported cpus:\n"); 1378 #endif 1379 1380 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1381 const struct cpu_dev *cpudev = *cdev; 1382 1383 if (count >= X86_VENDOR_NUM) 1384 break; 1385 cpu_devs[count] = cpudev; 1386 count++; 1387 1388 #ifdef CONFIG_PROCESSOR_SELECT 1389 { 1390 unsigned int j; 1391 1392 for (j = 0; j < 2; j++) { 1393 if (!cpudev->c_ident[j]) 1394 continue; 1395 pr_info(" %s %s\n", cpudev->c_vendor, 1396 cpudev->c_ident[j]); 1397 } 1398 } 1399 #endif 1400 } 1401 early_identify_cpu(&boot_cpu_data); 1402 } 1403 1404 static bool detect_null_seg_behavior(void) 1405 { 1406 /* 1407 * Empirically, writing zero to a segment selector on AMD does 1408 * not clear the base, whereas writing zero to a segment 1409 * selector on Intel does clear the base. Intel's behavior 1410 * allows slightly faster context switches in the common case 1411 * where GS is unused by the prev and next threads. 1412 * 1413 * Since neither vendor documents this anywhere that I can see, 1414 * detect it directly instead of hard-coding the choice by 1415 * vendor. 1416 * 1417 * I've designated AMD's behavior as the "bug" because it's 1418 * counterintuitive and less friendly. 1419 */ 1420 1421 unsigned long old_base, tmp; 1422 rdmsrl(MSR_FS_BASE, old_base); 1423 wrmsrl(MSR_FS_BASE, 1); 1424 loadsegment(fs, 0); 1425 rdmsrl(MSR_FS_BASE, tmp); 1426 wrmsrl(MSR_FS_BASE, old_base); 1427 return tmp == 0; 1428 } 1429 1430 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1431 { 1432 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1433 if (!IS_ENABLED(CONFIG_X86_64)) 1434 return; 1435 1436 /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ 1437 if (c->extended_cpuid_level >= 0x80000021 && 1438 cpuid_eax(0x80000021) & BIT(6)) 1439 return; 1440 1441 /* 1442 * CPUID bit above wasn't set. If this kernel is still running 1443 * as a HV guest, then the HV has decided not to advertize 1444 * that CPUID bit for whatever reason. For example, one 1445 * member of the migration pool might be vulnerable. Which 1446 * means, the bug is present: set the BUG flag and return. 1447 */ 1448 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1449 set_cpu_bug(c, X86_BUG_NULL_SEG); 1450 return; 1451 } 1452 1453 /* 1454 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1455 * 0x18 is the respective family for Hygon. 1456 */ 1457 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1458 detect_null_seg_behavior()) 1459 return; 1460 1461 /* All the remaining ones are affected */ 1462 set_cpu_bug(c, X86_BUG_NULL_SEG); 1463 } 1464 1465 static void generic_identify(struct cpuinfo_x86 *c) 1466 { 1467 c->extended_cpuid_level = 0; 1468 1469 if (!have_cpuid_p()) 1470 identify_cpu_without_cpuid(c); 1471 1472 /* cyrix could have cpuid enabled via c_identify()*/ 1473 if (!have_cpuid_p()) 1474 return; 1475 1476 cpu_detect(c); 1477 1478 get_cpu_vendor(c); 1479 1480 get_cpu_cap(c); 1481 1482 get_cpu_address_sizes(c); 1483 1484 if (c->cpuid_level >= 0x00000001) { 1485 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1486 #ifdef CONFIG_X86_32 1487 # ifdef CONFIG_SMP 1488 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1489 # else 1490 c->apicid = c->initial_apicid; 1491 # endif 1492 #endif 1493 c->phys_proc_id = c->initial_apicid; 1494 } 1495 1496 get_model_name(c); /* Default name */ 1497 1498 /* 1499 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1500 * systems that run Linux at CPL > 0 may or may not have the 1501 * issue, but, even if they have the issue, there's absolutely 1502 * nothing we can do about it because we can't use the real IRET 1503 * instruction. 1504 * 1505 * NB: For the time being, only 32-bit kernels support 1506 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1507 * whether to apply espfix using paravirt hooks. If any 1508 * non-paravirt system ever shows up that does *not* have the 1509 * ESPFIX issue, we can change this. 1510 */ 1511 #ifdef CONFIG_X86_32 1512 set_cpu_bug(c, X86_BUG_ESPFIX); 1513 #endif 1514 } 1515 1516 /* 1517 * Validate that ACPI/mptables have the same information about the 1518 * effective APIC id and update the package map. 1519 */ 1520 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1521 { 1522 #ifdef CONFIG_SMP 1523 unsigned int apicid, cpu = smp_processor_id(); 1524 1525 apicid = apic->cpu_present_to_apicid(cpu); 1526 1527 if (apicid != c->apicid) { 1528 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1529 cpu, apicid, c->initial_apicid); 1530 } 1531 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1532 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1533 #else 1534 c->logical_proc_id = 0; 1535 #endif 1536 } 1537 1538 /* 1539 * This does the hard work of actually picking apart the CPU stuff... 1540 */ 1541 static void identify_cpu(struct cpuinfo_x86 *c) 1542 { 1543 int i; 1544 1545 c->loops_per_jiffy = loops_per_jiffy; 1546 c->x86_cache_size = 0; 1547 c->x86_vendor = X86_VENDOR_UNKNOWN; 1548 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1549 c->x86_vendor_id[0] = '\0'; /* Unset */ 1550 c->x86_model_id[0] = '\0'; /* Unset */ 1551 c->x86_max_cores = 1; 1552 c->x86_coreid_bits = 0; 1553 c->cu_id = 0xff; 1554 #ifdef CONFIG_X86_64 1555 c->x86_clflush_size = 64; 1556 c->x86_phys_bits = 36; 1557 c->x86_virt_bits = 48; 1558 #else 1559 c->cpuid_level = -1; /* CPUID not detected */ 1560 c->x86_clflush_size = 32; 1561 c->x86_phys_bits = 32; 1562 c->x86_virt_bits = 32; 1563 #endif 1564 c->x86_cache_alignment = c->x86_clflush_size; 1565 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1566 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1567 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1568 #endif 1569 1570 generic_identify(c); 1571 1572 if (this_cpu->c_identify) 1573 this_cpu->c_identify(c); 1574 1575 /* Clear/Set all flags overridden by options, after probe */ 1576 apply_forced_caps(c); 1577 1578 #ifdef CONFIG_X86_64 1579 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1580 #endif 1581 1582 /* 1583 * Vendor-specific initialization. In this section we 1584 * canonicalize the feature flags, meaning if there are 1585 * features a certain CPU supports which CPUID doesn't 1586 * tell us, CPUID claiming incorrect flags, or other bugs, 1587 * we handle them here. 1588 * 1589 * At the end of this section, c->x86_capability better 1590 * indicate the features this CPU genuinely supports! 1591 */ 1592 if (this_cpu->c_init) 1593 this_cpu->c_init(c); 1594 1595 /* Disable the PN if appropriate */ 1596 squash_the_stupid_serial_number(c); 1597 1598 /* Set up SMEP/SMAP/UMIP */ 1599 setup_smep(c); 1600 setup_smap(c); 1601 setup_umip(c); 1602 1603 /* Enable FSGSBASE instructions if available. */ 1604 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1605 cr4_set_bits(X86_CR4_FSGSBASE); 1606 elf_hwcap2 |= HWCAP2_FSGSBASE; 1607 } 1608 1609 /* 1610 * The vendor-specific functions might have changed features. 1611 * Now we do "generic changes." 1612 */ 1613 1614 /* Filter out anything that depends on CPUID levels we don't have */ 1615 filter_cpuid_features(c, true); 1616 1617 /* If the model name is still unset, do table lookup. */ 1618 if (!c->x86_model_id[0]) { 1619 const char *p; 1620 p = table_lookup_model(c); 1621 if (p) 1622 strcpy(c->x86_model_id, p); 1623 else 1624 /* Last resort... */ 1625 sprintf(c->x86_model_id, "%02x/%02x", 1626 c->x86, c->x86_model); 1627 } 1628 1629 #ifdef CONFIG_X86_64 1630 detect_ht(c); 1631 #endif 1632 1633 x86_init_rdrand(c); 1634 setup_pku(c); 1635 1636 /* 1637 * Clear/Set all flags overridden by options, need do it 1638 * before following smp all cpus cap AND. 1639 */ 1640 apply_forced_caps(c); 1641 1642 /* 1643 * On SMP, boot_cpu_data holds the common feature set between 1644 * all CPUs; so make sure that we indicate which features are 1645 * common between the CPUs. The first time this routine gets 1646 * executed, c == &boot_cpu_data. 1647 */ 1648 if (c != &boot_cpu_data) { 1649 /* AND the already accumulated flags with these */ 1650 for (i = 0; i < NCAPINTS; i++) 1651 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1652 1653 /* OR, i.e. replicate the bug flags */ 1654 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1655 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1656 } 1657 1658 /* Init Machine Check Exception if available. */ 1659 mcheck_cpu_init(c); 1660 1661 select_idle_routine(c); 1662 1663 #ifdef CONFIG_NUMA 1664 numa_add_cpu(smp_processor_id()); 1665 #endif 1666 } 1667 1668 /* 1669 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1670 * on 32-bit kernels: 1671 */ 1672 #ifdef CONFIG_X86_32 1673 void enable_sep_cpu(void) 1674 { 1675 struct tss_struct *tss; 1676 int cpu; 1677 1678 if (!boot_cpu_has(X86_FEATURE_SEP)) 1679 return; 1680 1681 cpu = get_cpu(); 1682 tss = &per_cpu(cpu_tss_rw, cpu); 1683 1684 /* 1685 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1686 * see the big comment in struct x86_hw_tss's definition. 1687 */ 1688 1689 tss->x86_tss.ss1 = __KERNEL_CS; 1690 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1691 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1692 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1693 1694 put_cpu(); 1695 } 1696 #endif 1697 1698 void __init identify_boot_cpu(void) 1699 { 1700 identify_cpu(&boot_cpu_data); 1701 #ifdef CONFIG_X86_32 1702 sysenter_setup(); 1703 enable_sep_cpu(); 1704 #endif 1705 cpu_detect_tlb(&boot_cpu_data); 1706 setup_cr_pinning(); 1707 1708 tsx_init(); 1709 } 1710 1711 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1712 { 1713 BUG_ON(c == &boot_cpu_data); 1714 identify_cpu(c); 1715 #ifdef CONFIG_X86_32 1716 enable_sep_cpu(); 1717 #endif 1718 mtrr_ap_init(); 1719 validate_apic_and_package_id(c); 1720 x86_spec_ctrl_setup_ap(); 1721 update_srbds_msr(); 1722 } 1723 1724 static __init int setup_noclflush(char *arg) 1725 { 1726 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1727 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1728 return 1; 1729 } 1730 __setup("noclflush", setup_noclflush); 1731 1732 void print_cpu_info(struct cpuinfo_x86 *c) 1733 { 1734 const char *vendor = NULL; 1735 1736 if (c->x86_vendor < X86_VENDOR_NUM) { 1737 vendor = this_cpu->c_vendor; 1738 } else { 1739 if (c->cpuid_level >= 0) 1740 vendor = c->x86_vendor_id; 1741 } 1742 1743 if (vendor && !strstr(c->x86_model_id, vendor)) 1744 pr_cont("%s ", vendor); 1745 1746 if (c->x86_model_id[0]) 1747 pr_cont("%s", c->x86_model_id); 1748 else 1749 pr_cont("%d86", c->x86); 1750 1751 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1752 1753 if (c->x86_stepping || c->cpuid_level >= 0) 1754 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1755 else 1756 pr_cont(")\n"); 1757 } 1758 1759 /* 1760 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 1761 * function prevents it from becoming an environment variable for init. 1762 */ 1763 static __init int setup_clearcpuid(char *arg) 1764 { 1765 return 1; 1766 } 1767 __setup("clearcpuid=", setup_clearcpuid); 1768 1769 #ifdef CONFIG_X86_64 1770 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1771 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1772 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1773 1774 /* 1775 * The following percpu variables are hot. Align current_task to 1776 * cacheline size such that they fall in the same cacheline. 1777 */ 1778 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1779 &init_task; 1780 EXPORT_PER_CPU_SYMBOL(current_task); 1781 1782 DEFINE_PER_CPU(void *, hardirq_stack_ptr); 1783 DEFINE_PER_CPU(bool, hardirq_stack_inuse); 1784 1785 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1786 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1787 1788 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 1789 1790 /* May not be marked __init: used by software suspend */ 1791 void syscall_init(void) 1792 { 1793 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1794 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1795 1796 #ifdef CONFIG_IA32_EMULATION 1797 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1798 /* 1799 * This only works on Intel CPUs. 1800 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1801 * This does not cause SYSENTER to jump to the wrong location, because 1802 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1803 */ 1804 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1805 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1806 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1807 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1808 #else 1809 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1810 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1811 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1812 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1813 #endif 1814 1815 /* 1816 * Flags to clear on syscall; clear as much as possible 1817 * to minimize user space-kernel interference. 1818 */ 1819 wrmsrl(MSR_SYSCALL_MASK, 1820 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 1821 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 1822 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 1823 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 1824 X86_EFLAGS_AC|X86_EFLAGS_ID); 1825 } 1826 1827 #else /* CONFIG_X86_64 */ 1828 1829 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1830 EXPORT_PER_CPU_SYMBOL(current_task); 1831 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1832 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1833 1834 /* 1835 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1836 * the top of the kernel stack. Use an extra percpu variable to track the 1837 * top of the kernel stack directly. 1838 */ 1839 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1840 (unsigned long)&init_thread_union + THREAD_SIZE; 1841 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1842 1843 #ifdef CONFIG_STACKPROTECTOR 1844 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 1845 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 1846 #endif 1847 1848 #endif /* CONFIG_X86_64 */ 1849 1850 /* 1851 * Clear all 6 debug registers: 1852 */ 1853 static void clear_all_debug_regs(void) 1854 { 1855 int i; 1856 1857 for (i = 0; i < 8; i++) { 1858 /* Ignore db4, db5 */ 1859 if ((i == 4) || (i == 5)) 1860 continue; 1861 1862 set_debugreg(0, i); 1863 } 1864 } 1865 1866 #ifdef CONFIG_KGDB 1867 /* 1868 * Restore debug regs if using kgdbwait and you have a kernel debugger 1869 * connection established. 1870 */ 1871 static void dbg_restore_debug_regs(void) 1872 { 1873 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1874 arch_kgdb_ops.correct_hw_break(); 1875 } 1876 #else /* ! CONFIG_KGDB */ 1877 #define dbg_restore_debug_regs() 1878 #endif /* ! CONFIG_KGDB */ 1879 1880 static void wait_for_master_cpu(int cpu) 1881 { 1882 #ifdef CONFIG_SMP 1883 /* 1884 * wait for ACK from master CPU before continuing 1885 * with AP initialization 1886 */ 1887 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1888 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1889 cpu_relax(); 1890 #endif 1891 } 1892 1893 #ifdef CONFIG_X86_64 1894 static inline void setup_getcpu(int cpu) 1895 { 1896 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1897 struct desc_struct d = { }; 1898 1899 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 1900 wrmsr(MSR_TSC_AUX, cpudata, 0); 1901 1902 /* Store CPU and node number in limit. */ 1903 d.limit0 = cpudata; 1904 d.limit1 = cpudata >> 16; 1905 1906 d.type = 5; /* RO data, expand down, accessed */ 1907 d.dpl = 3; /* Visible to user code */ 1908 d.s = 1; /* Not a system segment */ 1909 d.p = 1; /* Present */ 1910 d.d = 1; /* 32-bit */ 1911 1912 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1913 } 1914 1915 static inline void ucode_cpu_init(int cpu) 1916 { 1917 if (cpu) 1918 load_ucode_ap(); 1919 } 1920 1921 static inline void tss_setup_ist(struct tss_struct *tss) 1922 { 1923 /* Set up the per-CPU TSS IST stacks */ 1924 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1925 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1926 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1927 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1928 /* Only mapped when SEV-ES is active */ 1929 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 1930 } 1931 1932 #else /* CONFIG_X86_64 */ 1933 1934 static inline void setup_getcpu(int cpu) { } 1935 1936 static inline void ucode_cpu_init(int cpu) 1937 { 1938 show_ucode_info_early(); 1939 } 1940 1941 static inline void tss_setup_ist(struct tss_struct *tss) { } 1942 1943 #endif /* !CONFIG_X86_64 */ 1944 1945 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 1946 { 1947 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 1948 1949 #ifdef CONFIG_X86_IOPL_IOPERM 1950 tss->io_bitmap.prev_max = 0; 1951 tss->io_bitmap.prev_sequence = 0; 1952 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 1953 /* 1954 * Invalidate the extra array entry past the end of the all 1955 * permission bitmap as required by the hardware. 1956 */ 1957 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 1958 #endif 1959 } 1960 1961 /* 1962 * Setup everything needed to handle exceptions from the IDT, including the IST 1963 * exceptions which use paranoid_entry(). 1964 */ 1965 void cpu_init_exception_handling(void) 1966 { 1967 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1968 int cpu = raw_smp_processor_id(); 1969 1970 /* paranoid_entry() gets the CPU number from the GDT */ 1971 setup_getcpu(cpu); 1972 1973 /* IST vectors need TSS to be set up. */ 1974 tss_setup_ist(tss); 1975 tss_setup_io_bitmap(tss); 1976 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1977 1978 load_TR_desc(); 1979 1980 /* Finally load the IDT */ 1981 load_current_idt(); 1982 } 1983 1984 /* 1985 * cpu_init() initializes state that is per-CPU. Some data is already 1986 * initialized (naturally) in the bootstrap process, such as the GDT. We 1987 * reload it nevertheless, this function acts as a 'CPU state barrier', 1988 * nothing should get across. 1989 */ 1990 void cpu_init(void) 1991 { 1992 struct task_struct *cur = current; 1993 int cpu = raw_smp_processor_id(); 1994 1995 wait_for_master_cpu(cpu); 1996 1997 ucode_cpu_init(cpu); 1998 1999 #ifdef CONFIG_NUMA 2000 if (this_cpu_read(numa_node) == 0 && 2001 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2002 set_numa_node(early_cpu_to_node(cpu)); 2003 #endif 2004 pr_debug("Initializing CPU#%d\n", cpu); 2005 2006 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2007 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2008 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2009 2010 /* 2011 * Initialize the per-CPU GDT with the boot GDT, 2012 * and set up the GDT descriptor: 2013 */ 2014 switch_to_new_gdt(cpu); 2015 2016 if (IS_ENABLED(CONFIG_X86_64)) { 2017 loadsegment(fs, 0); 2018 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2019 syscall_init(); 2020 2021 wrmsrl(MSR_FS_BASE, 0); 2022 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2023 barrier(); 2024 2025 x2apic_setup(); 2026 } 2027 2028 mmgrab(&init_mm); 2029 cur->active_mm = &init_mm; 2030 BUG_ON(cur->mm); 2031 initialize_tlbstate_and_flush(); 2032 enter_lazy_tlb(&init_mm, cur); 2033 2034 /* 2035 * sp0 points to the entry trampoline stack regardless of what task 2036 * is running. 2037 */ 2038 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2039 2040 load_mm_ldt(&init_mm); 2041 2042 clear_all_debug_regs(); 2043 dbg_restore_debug_regs(); 2044 2045 doublefault_init_cpu_tss(); 2046 2047 fpu__init_cpu(); 2048 2049 if (is_uv_system()) 2050 uv_cpu_init(); 2051 2052 load_fixmap_gdt(cpu); 2053 } 2054 2055 #ifdef CONFIG_SMP 2056 void cpu_init_secondary(void) 2057 { 2058 /* 2059 * Relies on the BP having set-up the IDT tables, which are loaded 2060 * on this CPU in cpu_init_exception_handling(). 2061 */ 2062 cpu_init_exception_handling(); 2063 cpu_init(); 2064 } 2065 #endif 2066 2067 /* 2068 * The microcode loader calls this upon late microcode load to recheck features, 2069 * only when microcode has been updated. Caller holds microcode_mutex and CPU 2070 * hotplug lock. 2071 */ 2072 void microcode_check(void) 2073 { 2074 struct cpuinfo_x86 info; 2075 2076 perf_check_microcode(); 2077 2078 /* Reload CPUID max function as it might've changed. */ 2079 info.cpuid_level = cpuid_eax(0); 2080 2081 /* 2082 * Copy all capability leafs to pick up the synthetic ones so that 2083 * memcmp() below doesn't fail on that. The ones coming from CPUID will 2084 * get overwritten in get_cpu_cap(). 2085 */ 2086 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 2087 2088 get_cpu_cap(&info); 2089 2090 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 2091 return; 2092 2093 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2094 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2095 } 2096 2097 /* 2098 * Invoked from core CPU hotplug code after hotplug operations 2099 */ 2100 void arch_smt_update(void) 2101 { 2102 /* Handle the speculative execution misfeatures */ 2103 cpu_bugs_smt_update(); 2104 /* Check whether IPI broadcasting can be enabled */ 2105 apic_smt_update(); 2106 } 2107