1 /* cpu_feature_enabled() cannot be used this early */ 2 #define USE_EARLY_PGTABLE_L5 3 4 #include <linux/bootmem.h> 5 #include <linux/linkage.h> 6 #include <linux/bitops.h> 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/percpu.h> 10 #include <linux/string.h> 11 #include <linux/ctype.h> 12 #include <linux/delay.h> 13 #include <linux/sched/mm.h> 14 #include <linux/sched/clock.h> 15 #include <linux/sched/task.h> 16 #include <linux/init.h> 17 #include <linux/kprobes.h> 18 #include <linux/kgdb.h> 19 #include <linux/smp.h> 20 #include <linux/io.h> 21 #include <linux/syscore_ops.h> 22 23 #include <asm/stackprotector.h> 24 #include <asm/perf_event.h> 25 #include <asm/mmu_context.h> 26 #include <asm/archrandom.h> 27 #include <asm/hypervisor.h> 28 #include <asm/processor.h> 29 #include <asm/tlbflush.h> 30 #include <asm/debugreg.h> 31 #include <asm/sections.h> 32 #include <asm/vsyscall.h> 33 #include <linux/topology.h> 34 #include <linux/cpumask.h> 35 #include <asm/pgtable.h> 36 #include <linux/atomic.h> 37 #include <asm/proto.h> 38 #include <asm/setup.h> 39 #include <asm/apic.h> 40 #include <asm/desc.h> 41 #include <asm/fpu/internal.h> 42 #include <asm/mtrr.h> 43 #include <asm/hwcap2.h> 44 #include <linux/numa.h> 45 #include <asm/asm.h> 46 #include <asm/bugs.h> 47 #include <asm/cpu.h> 48 #include <asm/mce.h> 49 #include <asm/msr.h> 50 #include <asm/pat.h> 51 #include <asm/microcode.h> 52 #include <asm/microcode_intel.h> 53 #include <asm/intel-family.h> 54 #include <asm/cpu_device_id.h> 55 56 #ifdef CONFIG_X86_LOCAL_APIC 57 #include <asm/uv/uv.h> 58 #endif 59 60 #include "cpu.h" 61 62 u32 elf_hwcap2 __read_mostly; 63 64 /* all of these masks are initialized in setup_cpu_local_masks() */ 65 cpumask_var_t cpu_initialized_mask; 66 cpumask_var_t cpu_callout_mask; 67 cpumask_var_t cpu_callin_mask; 68 69 /* representing cpus for which sibling maps can be computed */ 70 cpumask_var_t cpu_sibling_setup_mask; 71 72 /* Number of siblings per CPU package */ 73 int smp_num_siblings = 1; 74 EXPORT_SYMBOL(smp_num_siblings); 75 76 /* Last level cache ID of each logical CPU */ 77 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 78 79 /* correctly size the local cpu masks */ 80 void __init setup_cpu_local_masks(void) 81 { 82 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 83 alloc_bootmem_cpumask_var(&cpu_callin_mask); 84 alloc_bootmem_cpumask_var(&cpu_callout_mask); 85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 86 } 87 88 static void default_init(struct cpuinfo_x86 *c) 89 { 90 #ifdef CONFIG_X86_64 91 cpu_detect_cache_sizes(c); 92 #else 93 /* Not much we can do here... */ 94 /* Check if at least it has cpuid */ 95 if (c->cpuid_level == -1) { 96 /* No cpuid. It must be an ancient CPU */ 97 if (c->x86 == 4) 98 strcpy(c->x86_model_id, "486"); 99 else if (c->x86 == 3) 100 strcpy(c->x86_model_id, "386"); 101 } 102 #endif 103 } 104 105 static const struct cpu_dev default_cpu = { 106 .c_init = default_init, 107 .c_vendor = "Unknown", 108 .c_x86_vendor = X86_VENDOR_UNKNOWN, 109 }; 110 111 static const struct cpu_dev *this_cpu = &default_cpu; 112 113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 114 #ifdef CONFIG_X86_64 115 /* 116 * We need valid kernel segments for data and code in long mode too 117 * IRET will check the segment types kkeil 2000/10/28 118 * Also sysret mandates a special GDT layout 119 * 120 * TLS descriptors are currently at a different place compared to i386. 121 * Hopefully nobody expects them at a fixed place (Wine?) 122 */ 123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 129 #else 130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 134 /* 135 * Segments used for calling PnP BIOS have byte granularity. 136 * They code segments and data segments have fixed 64k limits, 137 * the transfer segment sizes are set at run time. 138 */ 139 /* 32-bit code */ 140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 141 /* 16-bit code */ 142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 143 /* 16-bit data */ 144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 145 /* 16-bit data */ 146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 147 /* 16-bit data */ 148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 149 /* 150 * The APM segments have byte granularity and their bases 151 * are set at run time. All have 64k limits. 152 */ 153 /* 32-bit code */ 154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 155 /* 16-bit code */ 156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 157 /* data */ 158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 159 160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 162 GDT_STACK_CANARY_INIT 163 #endif 164 } }; 165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 166 167 static int __init x86_mpx_setup(char *s) 168 { 169 /* require an exact match without trailing characters */ 170 if (strlen(s)) 171 return 0; 172 173 /* do not emit a message if the feature is not present */ 174 if (!boot_cpu_has(X86_FEATURE_MPX)) 175 return 1; 176 177 setup_clear_cpu_cap(X86_FEATURE_MPX); 178 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 179 return 1; 180 } 181 __setup("nompx", x86_mpx_setup); 182 183 #ifdef CONFIG_X86_64 184 static int __init x86_nopcid_setup(char *s) 185 { 186 /* nopcid doesn't accept parameters */ 187 if (s) 188 return -EINVAL; 189 190 /* do not emit a message if the feature is not present */ 191 if (!boot_cpu_has(X86_FEATURE_PCID)) 192 return 0; 193 194 setup_clear_cpu_cap(X86_FEATURE_PCID); 195 pr_info("nopcid: PCID feature disabled\n"); 196 return 0; 197 } 198 early_param("nopcid", x86_nopcid_setup); 199 #endif 200 201 static int __init x86_noinvpcid_setup(char *s) 202 { 203 /* noinvpcid doesn't accept parameters */ 204 if (s) 205 return -EINVAL; 206 207 /* do not emit a message if the feature is not present */ 208 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 209 return 0; 210 211 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 212 pr_info("noinvpcid: INVPCID feature disabled\n"); 213 return 0; 214 } 215 early_param("noinvpcid", x86_noinvpcid_setup); 216 217 #ifdef CONFIG_X86_32 218 static int cachesize_override = -1; 219 static int disable_x86_serial_nr = 1; 220 221 static int __init cachesize_setup(char *str) 222 { 223 get_option(&str, &cachesize_override); 224 return 1; 225 } 226 __setup("cachesize=", cachesize_setup); 227 228 static int __init x86_sep_setup(char *s) 229 { 230 setup_clear_cpu_cap(X86_FEATURE_SEP); 231 return 1; 232 } 233 __setup("nosep", x86_sep_setup); 234 235 /* Standard macro to see if a specific flag is changeable */ 236 static inline int flag_is_changeable_p(u32 flag) 237 { 238 u32 f1, f2; 239 240 /* 241 * Cyrix and IDT cpus allow disabling of CPUID 242 * so the code below may return different results 243 * when it is executed before and after enabling 244 * the CPUID. Add "volatile" to not allow gcc to 245 * optimize the subsequent calls to this function. 246 */ 247 asm volatile ("pushfl \n\t" 248 "pushfl \n\t" 249 "popl %0 \n\t" 250 "movl %0, %1 \n\t" 251 "xorl %2, %0 \n\t" 252 "pushl %0 \n\t" 253 "popfl \n\t" 254 "pushfl \n\t" 255 "popl %0 \n\t" 256 "popfl \n\t" 257 258 : "=&r" (f1), "=&r" (f2) 259 : "ir" (flag)); 260 261 return ((f1^f2) & flag) != 0; 262 } 263 264 /* Probe for the CPUID instruction */ 265 int have_cpuid_p(void) 266 { 267 return flag_is_changeable_p(X86_EFLAGS_ID); 268 } 269 270 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 271 { 272 unsigned long lo, hi; 273 274 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 275 return; 276 277 /* Disable processor serial number: */ 278 279 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 280 lo |= 0x200000; 281 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 282 283 pr_notice("CPU serial number disabled.\n"); 284 clear_cpu_cap(c, X86_FEATURE_PN); 285 286 /* Disabling the serial number may affect the cpuid level */ 287 c->cpuid_level = cpuid_eax(0); 288 } 289 290 static int __init x86_serial_nr_setup(char *s) 291 { 292 disable_x86_serial_nr = 0; 293 return 1; 294 } 295 __setup("serialnumber", x86_serial_nr_setup); 296 #else 297 static inline int flag_is_changeable_p(u32 flag) 298 { 299 return 1; 300 } 301 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 302 { 303 } 304 #endif 305 306 static __init int setup_disable_smep(char *arg) 307 { 308 setup_clear_cpu_cap(X86_FEATURE_SMEP); 309 /* Check for things that depend on SMEP being enabled: */ 310 check_mpx_erratum(&boot_cpu_data); 311 return 1; 312 } 313 __setup("nosmep", setup_disable_smep); 314 315 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 316 { 317 if (cpu_has(c, X86_FEATURE_SMEP)) 318 cr4_set_bits(X86_CR4_SMEP); 319 } 320 321 static __init int setup_disable_smap(char *arg) 322 { 323 setup_clear_cpu_cap(X86_FEATURE_SMAP); 324 return 1; 325 } 326 __setup("nosmap", setup_disable_smap); 327 328 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 329 { 330 unsigned long eflags = native_save_fl(); 331 332 /* This should have been cleared long ago */ 333 BUG_ON(eflags & X86_EFLAGS_AC); 334 335 if (cpu_has(c, X86_FEATURE_SMAP)) { 336 #ifdef CONFIG_X86_SMAP 337 cr4_set_bits(X86_CR4_SMAP); 338 #else 339 cr4_clear_bits(X86_CR4_SMAP); 340 #endif 341 } 342 } 343 344 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 345 { 346 /* Check the boot processor, plus build option for UMIP. */ 347 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 348 goto out; 349 350 /* Check the current processor's cpuid bits. */ 351 if (!cpu_has(c, X86_FEATURE_UMIP)) 352 goto out; 353 354 cr4_set_bits(X86_CR4_UMIP); 355 356 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); 357 358 return; 359 360 out: 361 /* 362 * Make sure UMIP is disabled in case it was enabled in a 363 * previous boot (e.g., via kexec). 364 */ 365 cr4_clear_bits(X86_CR4_UMIP); 366 } 367 368 /* 369 * Protection Keys are not available in 32-bit mode. 370 */ 371 static bool pku_disabled; 372 373 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 374 { 375 /* check the boot processor, plus compile options for PKU: */ 376 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 377 return; 378 /* checks the actual processor's cpuid bits: */ 379 if (!cpu_has(c, X86_FEATURE_PKU)) 380 return; 381 if (pku_disabled) 382 return; 383 384 cr4_set_bits(X86_CR4_PKE); 385 /* 386 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 387 * cpuid bit to be set. We need to ensure that we 388 * update that bit in this CPU's "cpu_info". 389 */ 390 get_cpu_cap(c); 391 } 392 393 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 394 static __init int setup_disable_pku(char *arg) 395 { 396 /* 397 * Do not clear the X86_FEATURE_PKU bit. All of the 398 * runtime checks are against OSPKE so clearing the 399 * bit does nothing. 400 * 401 * This way, we will see "pku" in cpuinfo, but not 402 * "ospke", which is exactly what we want. It shows 403 * that the CPU has PKU, but the OS has not enabled it. 404 * This happens to be exactly how a system would look 405 * if we disabled the config option. 406 */ 407 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 408 pku_disabled = true; 409 return 1; 410 } 411 __setup("nopku", setup_disable_pku); 412 #endif /* CONFIG_X86_64 */ 413 414 /* 415 * Some CPU features depend on higher CPUID levels, which may not always 416 * be available due to CPUID level capping or broken virtualization 417 * software. Add those features to this table to auto-disable them. 418 */ 419 struct cpuid_dependent_feature { 420 u32 feature; 421 u32 level; 422 }; 423 424 static const struct cpuid_dependent_feature 425 cpuid_dependent_features[] = { 426 { X86_FEATURE_MWAIT, 0x00000005 }, 427 { X86_FEATURE_DCA, 0x00000009 }, 428 { X86_FEATURE_XSAVE, 0x0000000d }, 429 { 0, 0 } 430 }; 431 432 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 433 { 434 const struct cpuid_dependent_feature *df; 435 436 for (df = cpuid_dependent_features; df->feature; df++) { 437 438 if (!cpu_has(c, df->feature)) 439 continue; 440 /* 441 * Note: cpuid_level is set to -1 if unavailable, but 442 * extended_extended_level is set to 0 if unavailable 443 * and the legitimate extended levels are all negative 444 * when signed; hence the weird messing around with 445 * signs here... 446 */ 447 if (!((s32)df->level < 0 ? 448 (u32)df->level > (u32)c->extended_cpuid_level : 449 (s32)df->level > (s32)c->cpuid_level)) 450 continue; 451 452 clear_cpu_cap(c, df->feature); 453 if (!warn) 454 continue; 455 456 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 457 x86_cap_flag(df->feature), df->level); 458 } 459 } 460 461 /* 462 * Naming convention should be: <Name> [(<Codename>)] 463 * This table only is used unless init_<vendor>() below doesn't set it; 464 * in particular, if CPUID levels 0x80000002..4 are supported, this 465 * isn't used 466 */ 467 468 /* Look up CPU names by table lookup. */ 469 static const char *table_lookup_model(struct cpuinfo_x86 *c) 470 { 471 #ifdef CONFIG_X86_32 472 const struct legacy_cpu_model_info *info; 473 474 if (c->x86_model >= 16) 475 return NULL; /* Range check */ 476 477 if (!this_cpu) 478 return NULL; 479 480 info = this_cpu->legacy_models; 481 482 while (info->family) { 483 if (info->family == c->x86) 484 return info->model_names[c->x86_model]; 485 info++; 486 } 487 #endif 488 return NULL; /* Not found */ 489 } 490 491 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 492 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 493 494 void load_percpu_segment(int cpu) 495 { 496 #ifdef CONFIG_X86_32 497 loadsegment(fs, __KERNEL_PERCPU); 498 #else 499 __loadsegment_simple(gs, 0); 500 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 501 #endif 502 load_stack_canary_segment(); 503 } 504 505 #ifdef CONFIG_X86_32 506 /* The 32-bit entry code needs to find cpu_entry_area. */ 507 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 508 #endif 509 510 #ifdef CONFIG_X86_64 511 /* 512 * Special IST stacks which the CPU switches to when it calls 513 * an IST-marked descriptor entry. Up to 7 stacks (hardware 514 * limit), all of them are 4K, except the debug stack which 515 * is 8K. 516 */ 517 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 518 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 519 [DEBUG_STACK - 1] = DEBUG_STKSZ 520 }; 521 #endif 522 523 /* Load the original GDT from the per-cpu structure */ 524 void load_direct_gdt(int cpu) 525 { 526 struct desc_ptr gdt_descr; 527 528 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 529 gdt_descr.size = GDT_SIZE - 1; 530 load_gdt(&gdt_descr); 531 } 532 EXPORT_SYMBOL_GPL(load_direct_gdt); 533 534 /* Load a fixmap remapping of the per-cpu GDT */ 535 void load_fixmap_gdt(int cpu) 536 { 537 struct desc_ptr gdt_descr; 538 539 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 540 gdt_descr.size = GDT_SIZE - 1; 541 load_gdt(&gdt_descr); 542 } 543 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 544 545 /* 546 * Current gdt points %fs at the "master" per-cpu area: after this, 547 * it's on the real one. 548 */ 549 void switch_to_new_gdt(int cpu) 550 { 551 /* Load the original GDT */ 552 load_direct_gdt(cpu); 553 /* Reload the per-cpu base */ 554 load_percpu_segment(cpu); 555 } 556 557 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 558 559 static void get_model_name(struct cpuinfo_x86 *c) 560 { 561 unsigned int *v; 562 char *p, *q, *s; 563 564 if (c->extended_cpuid_level < 0x80000004) 565 return; 566 567 v = (unsigned int *)c->x86_model_id; 568 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 569 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 570 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 571 c->x86_model_id[48] = 0; 572 573 /* Trim whitespace */ 574 p = q = s = &c->x86_model_id[0]; 575 576 while (*p == ' ') 577 p++; 578 579 while (*p) { 580 /* Note the last non-whitespace index */ 581 if (!isspace(*p)) 582 s = q; 583 584 *q++ = *p++; 585 } 586 587 *(s + 1) = '\0'; 588 } 589 590 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 591 { 592 unsigned int eax, ebx, ecx, edx; 593 594 c->x86_max_cores = 1; 595 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 596 return; 597 598 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 599 if (eax & 0x1f) 600 c->x86_max_cores = (eax >> 26) + 1; 601 } 602 603 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 604 { 605 unsigned int n, dummy, ebx, ecx, edx, l2size; 606 607 n = c->extended_cpuid_level; 608 609 if (n >= 0x80000005) { 610 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 611 c->x86_cache_size = (ecx>>24) + (edx>>24); 612 #ifdef CONFIG_X86_64 613 /* On K8 L1 TLB is inclusive, so don't count it */ 614 c->x86_tlbsize = 0; 615 #endif 616 } 617 618 if (n < 0x80000006) /* Some chips just has a large L1. */ 619 return; 620 621 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 622 l2size = ecx >> 16; 623 624 #ifdef CONFIG_X86_64 625 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 626 #else 627 /* do processor-specific cache resizing */ 628 if (this_cpu->legacy_cache_size) 629 l2size = this_cpu->legacy_cache_size(c, l2size); 630 631 /* Allow user to override all this if necessary. */ 632 if (cachesize_override != -1) 633 l2size = cachesize_override; 634 635 if (l2size == 0) 636 return; /* Again, no L2 cache is possible */ 637 #endif 638 639 c->x86_cache_size = l2size; 640 } 641 642 u16 __read_mostly tlb_lli_4k[NR_INFO]; 643 u16 __read_mostly tlb_lli_2m[NR_INFO]; 644 u16 __read_mostly tlb_lli_4m[NR_INFO]; 645 u16 __read_mostly tlb_lld_4k[NR_INFO]; 646 u16 __read_mostly tlb_lld_2m[NR_INFO]; 647 u16 __read_mostly tlb_lld_4m[NR_INFO]; 648 u16 __read_mostly tlb_lld_1g[NR_INFO]; 649 650 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 651 { 652 if (this_cpu->c_detect_tlb) 653 this_cpu->c_detect_tlb(c); 654 655 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 656 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 657 tlb_lli_4m[ENTRIES]); 658 659 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 660 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 661 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 662 } 663 664 void detect_ht(struct cpuinfo_x86 *c) 665 { 666 #ifdef CONFIG_SMP 667 u32 eax, ebx, ecx, edx; 668 int index_msb, core_bits; 669 static bool printed; 670 671 if (!cpu_has(c, X86_FEATURE_HT)) 672 return; 673 674 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 675 goto out; 676 677 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 678 return; 679 680 cpuid(1, &eax, &ebx, &ecx, &edx); 681 682 smp_num_siblings = (ebx & 0xff0000) >> 16; 683 684 if (smp_num_siblings == 1) { 685 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 686 goto out; 687 } 688 689 if (smp_num_siblings <= 1) 690 goto out; 691 692 index_msb = get_count_order(smp_num_siblings); 693 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 694 695 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 696 697 index_msb = get_count_order(smp_num_siblings); 698 699 core_bits = get_count_order(c->x86_max_cores); 700 701 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 702 ((1 << core_bits) - 1); 703 704 out: 705 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 706 pr_info("CPU: Physical Processor ID: %d\n", 707 c->phys_proc_id); 708 pr_info("CPU: Processor Core ID: %d\n", 709 c->cpu_core_id); 710 printed = 1; 711 } 712 #endif 713 } 714 715 static void get_cpu_vendor(struct cpuinfo_x86 *c) 716 { 717 char *v = c->x86_vendor_id; 718 int i; 719 720 for (i = 0; i < X86_VENDOR_NUM; i++) { 721 if (!cpu_devs[i]) 722 break; 723 724 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 725 (cpu_devs[i]->c_ident[1] && 726 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 727 728 this_cpu = cpu_devs[i]; 729 c->x86_vendor = this_cpu->c_x86_vendor; 730 return; 731 } 732 } 733 734 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 735 "CPU: Your system may be unstable.\n", v); 736 737 c->x86_vendor = X86_VENDOR_UNKNOWN; 738 this_cpu = &default_cpu; 739 } 740 741 void cpu_detect(struct cpuinfo_x86 *c) 742 { 743 /* Get vendor name */ 744 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 745 (unsigned int *)&c->x86_vendor_id[0], 746 (unsigned int *)&c->x86_vendor_id[8], 747 (unsigned int *)&c->x86_vendor_id[4]); 748 749 c->x86 = 4; 750 /* Intel-defined flags: level 0x00000001 */ 751 if (c->cpuid_level >= 0x00000001) { 752 u32 junk, tfms, cap0, misc; 753 754 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 755 c->x86 = x86_family(tfms); 756 c->x86_model = x86_model(tfms); 757 c->x86_stepping = x86_stepping(tfms); 758 759 if (cap0 & (1<<19)) { 760 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 761 c->x86_cache_alignment = c->x86_clflush_size; 762 } 763 } 764 } 765 766 static void apply_forced_caps(struct cpuinfo_x86 *c) 767 { 768 int i; 769 770 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 771 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 772 c->x86_capability[i] |= cpu_caps_set[i]; 773 } 774 } 775 776 static void init_speculation_control(struct cpuinfo_x86 *c) 777 { 778 /* 779 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 780 * and they also have a different bit for STIBP support. Also, 781 * a hypervisor might have set the individual AMD bits even on 782 * Intel CPUs, for finer-grained selection of what's available. 783 */ 784 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 785 set_cpu_cap(c, X86_FEATURE_IBRS); 786 set_cpu_cap(c, X86_FEATURE_IBPB); 787 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 788 } 789 790 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 791 set_cpu_cap(c, X86_FEATURE_STIBP); 792 793 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 794 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 795 set_cpu_cap(c, X86_FEATURE_SSBD); 796 797 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 798 set_cpu_cap(c, X86_FEATURE_IBRS); 799 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 800 } 801 802 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 803 set_cpu_cap(c, X86_FEATURE_IBPB); 804 805 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 806 set_cpu_cap(c, X86_FEATURE_STIBP); 807 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 808 } 809 810 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 811 set_cpu_cap(c, X86_FEATURE_SSBD); 812 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 813 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 814 } 815 } 816 817 void get_cpu_cap(struct cpuinfo_x86 *c) 818 { 819 u32 eax, ebx, ecx, edx; 820 821 /* Intel-defined flags: level 0x00000001 */ 822 if (c->cpuid_level >= 0x00000001) { 823 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 824 825 c->x86_capability[CPUID_1_ECX] = ecx; 826 c->x86_capability[CPUID_1_EDX] = edx; 827 } 828 829 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 830 if (c->cpuid_level >= 0x00000006) 831 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 832 833 /* Additional Intel-defined flags: level 0x00000007 */ 834 if (c->cpuid_level >= 0x00000007) { 835 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 836 c->x86_capability[CPUID_7_0_EBX] = ebx; 837 c->x86_capability[CPUID_7_ECX] = ecx; 838 c->x86_capability[CPUID_7_EDX] = edx; 839 } 840 841 /* Extended state features: level 0x0000000d */ 842 if (c->cpuid_level >= 0x0000000d) { 843 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 844 845 c->x86_capability[CPUID_D_1_EAX] = eax; 846 } 847 848 /* Additional Intel-defined flags: level 0x0000000F */ 849 if (c->cpuid_level >= 0x0000000F) { 850 851 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 852 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 853 c->x86_capability[CPUID_F_0_EDX] = edx; 854 855 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 856 /* will be overridden if occupancy monitoring exists */ 857 c->x86_cache_max_rmid = ebx; 858 859 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 860 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 861 c->x86_capability[CPUID_F_1_EDX] = edx; 862 863 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 864 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 865 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 866 c->x86_cache_max_rmid = ecx; 867 c->x86_cache_occ_scale = ebx; 868 } 869 } else { 870 c->x86_cache_max_rmid = -1; 871 c->x86_cache_occ_scale = -1; 872 } 873 } 874 875 /* AMD-defined flags: level 0x80000001 */ 876 eax = cpuid_eax(0x80000000); 877 c->extended_cpuid_level = eax; 878 879 if ((eax & 0xffff0000) == 0x80000000) { 880 if (eax >= 0x80000001) { 881 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 882 883 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 884 c->x86_capability[CPUID_8000_0001_EDX] = edx; 885 } 886 } 887 888 if (c->extended_cpuid_level >= 0x80000007) { 889 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 890 891 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 892 c->x86_power = edx; 893 } 894 895 if (c->extended_cpuid_level >= 0x80000008) { 896 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 897 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 898 } 899 900 if (c->extended_cpuid_level >= 0x8000000a) 901 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 902 903 init_scattered_cpuid_features(c); 904 init_speculation_control(c); 905 906 /* 907 * Clear/Set all flags overridden by options, after probe. 908 * This needs to happen each time we re-probe, which may happen 909 * several times during CPU initialization. 910 */ 911 apply_forced_caps(c); 912 } 913 914 static void get_cpu_address_sizes(struct cpuinfo_x86 *c) 915 { 916 u32 eax, ebx, ecx, edx; 917 918 if (c->extended_cpuid_level >= 0x80000008) { 919 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 920 921 c->x86_virt_bits = (eax >> 8) & 0xff; 922 c->x86_phys_bits = eax & 0xff; 923 } 924 #ifdef CONFIG_X86_32 925 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 926 c->x86_phys_bits = 36; 927 #endif 928 } 929 930 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 931 { 932 #ifdef CONFIG_X86_32 933 int i; 934 935 /* 936 * First of all, decide if this is a 486 or higher 937 * It's a 486 if we can modify the AC flag 938 */ 939 if (flag_is_changeable_p(X86_EFLAGS_AC)) 940 c->x86 = 4; 941 else 942 c->x86 = 3; 943 944 for (i = 0; i < X86_VENDOR_NUM; i++) 945 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 946 c->x86_vendor_id[0] = 0; 947 cpu_devs[i]->c_identify(c); 948 if (c->x86_vendor_id[0]) { 949 get_cpu_vendor(c); 950 break; 951 } 952 } 953 #endif 954 } 955 956 static const __initconst struct x86_cpu_id cpu_no_speculation[] = { 957 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, 958 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, 959 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, 960 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, 961 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, 962 { X86_VENDOR_CENTAUR, 5 }, 963 { X86_VENDOR_INTEL, 5 }, 964 { X86_VENDOR_NSC, 5 }, 965 { X86_VENDOR_ANY, 4 }, 966 {} 967 }; 968 969 static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { 970 { X86_VENDOR_AMD }, 971 {} 972 }; 973 974 /* Only list CPUs which speculate but are non susceptible to SSB */ 975 static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = { 976 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, 977 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, 978 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, 979 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, 980 { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH }, 981 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, 982 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, 983 { X86_VENDOR_AMD, 0x12, }, 984 { X86_VENDOR_AMD, 0x11, }, 985 { X86_VENDOR_AMD, 0x10, }, 986 { X86_VENDOR_AMD, 0xf, }, 987 {} 988 }; 989 990 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 991 { 992 u64 ia32_cap = 0; 993 994 if (x86_match_cpu(cpu_no_speculation)) 995 return; 996 997 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 998 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 999 1000 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) 1001 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1002 1003 if (!x86_match_cpu(cpu_no_spec_store_bypass) && 1004 !(ia32_cap & ARCH_CAP_SSB_NO) && 1005 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1006 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1007 1008 if (x86_match_cpu(cpu_no_meltdown)) 1009 return; 1010 1011 /* Rogue Data Cache Load? No! */ 1012 if (ia32_cap & ARCH_CAP_RDCL_NO) 1013 return; 1014 1015 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1016 } 1017 1018 /* 1019 * Do minimum CPU detection early. 1020 * Fields really needed: vendor, cpuid_level, family, model, mask, 1021 * cache alignment. 1022 * The others are not touched to avoid unwanted side effects. 1023 * 1024 * WARNING: this function is only called on the boot CPU. Don't add code 1025 * here that is supposed to run on all CPUs. 1026 */ 1027 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1028 { 1029 #ifdef CONFIG_X86_64 1030 c->x86_clflush_size = 64; 1031 c->x86_phys_bits = 36; 1032 c->x86_virt_bits = 48; 1033 #else 1034 c->x86_clflush_size = 32; 1035 c->x86_phys_bits = 32; 1036 c->x86_virt_bits = 32; 1037 #endif 1038 c->x86_cache_alignment = c->x86_clflush_size; 1039 1040 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1041 c->extended_cpuid_level = 0; 1042 1043 /* cyrix could have cpuid enabled via c_identify()*/ 1044 if (have_cpuid_p()) { 1045 cpu_detect(c); 1046 get_cpu_vendor(c); 1047 get_cpu_cap(c); 1048 get_cpu_address_sizes(c); 1049 setup_force_cpu_cap(X86_FEATURE_CPUID); 1050 1051 if (this_cpu->c_early_init) 1052 this_cpu->c_early_init(c); 1053 1054 c->cpu_index = 0; 1055 filter_cpuid_features(c, false); 1056 1057 if (this_cpu->c_bsp_init) 1058 this_cpu->c_bsp_init(c); 1059 } else { 1060 identify_cpu_without_cpuid(c); 1061 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1062 } 1063 1064 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1065 1066 cpu_set_bug_bits(c); 1067 1068 fpu__init_system(c); 1069 1070 #ifdef CONFIG_X86_32 1071 /* 1072 * Regardless of whether PCID is enumerated, the SDM says 1073 * that it can't be enabled in 32-bit mode. 1074 */ 1075 setup_clear_cpu_cap(X86_FEATURE_PCID); 1076 #endif 1077 1078 /* 1079 * Later in the boot process pgtable_l5_enabled() relies on 1080 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1081 * enabled by this point we need to clear the feature bit to avoid 1082 * false-positives at the later stage. 1083 * 1084 * pgtable_l5_enabled() can be false here for several reasons: 1085 * - 5-level paging is disabled compile-time; 1086 * - it's 32-bit kernel; 1087 * - machine doesn't support 5-level paging; 1088 * - user specified 'no5lvl' in kernel command line. 1089 */ 1090 if (!pgtable_l5_enabled()) 1091 setup_clear_cpu_cap(X86_FEATURE_LA57); 1092 } 1093 1094 void __init early_cpu_init(void) 1095 { 1096 const struct cpu_dev *const *cdev; 1097 int count = 0; 1098 1099 #ifdef CONFIG_PROCESSOR_SELECT 1100 pr_info("KERNEL supported cpus:\n"); 1101 #endif 1102 1103 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1104 const struct cpu_dev *cpudev = *cdev; 1105 1106 if (count >= X86_VENDOR_NUM) 1107 break; 1108 cpu_devs[count] = cpudev; 1109 count++; 1110 1111 #ifdef CONFIG_PROCESSOR_SELECT 1112 { 1113 unsigned int j; 1114 1115 for (j = 0; j < 2; j++) { 1116 if (!cpudev->c_ident[j]) 1117 continue; 1118 pr_info(" %s %s\n", cpudev->c_vendor, 1119 cpudev->c_ident[j]); 1120 } 1121 } 1122 #endif 1123 } 1124 early_identify_cpu(&boot_cpu_data); 1125 } 1126 1127 /* 1128 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1129 * unfortunately, that's not true in practice because of early VIA 1130 * chips and (more importantly) broken virtualizers that are not easy 1131 * to detect. In the latter case it doesn't even *fail* reliably, so 1132 * probing for it doesn't even work. Disable it completely on 32-bit 1133 * unless we can find a reliable way to detect all the broken cases. 1134 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1135 */ 1136 static void detect_nopl(struct cpuinfo_x86 *c) 1137 { 1138 #ifdef CONFIG_X86_32 1139 clear_cpu_cap(c, X86_FEATURE_NOPL); 1140 #else 1141 set_cpu_cap(c, X86_FEATURE_NOPL); 1142 #endif 1143 } 1144 1145 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1146 { 1147 #ifdef CONFIG_X86_64 1148 /* 1149 * Empirically, writing zero to a segment selector on AMD does 1150 * not clear the base, whereas writing zero to a segment 1151 * selector on Intel does clear the base. Intel's behavior 1152 * allows slightly faster context switches in the common case 1153 * where GS is unused by the prev and next threads. 1154 * 1155 * Since neither vendor documents this anywhere that I can see, 1156 * detect it directly instead of hardcoding the choice by 1157 * vendor. 1158 * 1159 * I've designated AMD's behavior as the "bug" because it's 1160 * counterintuitive and less friendly. 1161 */ 1162 1163 unsigned long old_base, tmp; 1164 rdmsrl(MSR_FS_BASE, old_base); 1165 wrmsrl(MSR_FS_BASE, 1); 1166 loadsegment(fs, 0); 1167 rdmsrl(MSR_FS_BASE, tmp); 1168 if (tmp != 0) 1169 set_cpu_bug(c, X86_BUG_NULL_SEG); 1170 wrmsrl(MSR_FS_BASE, old_base); 1171 #endif 1172 } 1173 1174 static void generic_identify(struct cpuinfo_x86 *c) 1175 { 1176 c->extended_cpuid_level = 0; 1177 1178 if (!have_cpuid_p()) 1179 identify_cpu_without_cpuid(c); 1180 1181 /* cyrix could have cpuid enabled via c_identify()*/ 1182 if (!have_cpuid_p()) 1183 return; 1184 1185 cpu_detect(c); 1186 1187 get_cpu_vendor(c); 1188 1189 get_cpu_cap(c); 1190 1191 get_cpu_address_sizes(c); 1192 1193 if (c->cpuid_level >= 0x00000001) { 1194 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1195 #ifdef CONFIG_X86_32 1196 # ifdef CONFIG_SMP 1197 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1198 # else 1199 c->apicid = c->initial_apicid; 1200 # endif 1201 #endif 1202 c->phys_proc_id = c->initial_apicid; 1203 } 1204 1205 get_model_name(c); /* Default name */ 1206 1207 detect_nopl(c); 1208 1209 detect_null_seg_behavior(c); 1210 1211 /* 1212 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1213 * systems that run Linux at CPL > 0 may or may not have the 1214 * issue, but, even if they have the issue, there's absolutely 1215 * nothing we can do about it because we can't use the real IRET 1216 * instruction. 1217 * 1218 * NB: For the time being, only 32-bit kernels support 1219 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1220 * whether to apply espfix using paravirt hooks. If any 1221 * non-paravirt system ever shows up that does *not* have the 1222 * ESPFIX issue, we can change this. 1223 */ 1224 #ifdef CONFIG_X86_32 1225 # ifdef CONFIG_PARAVIRT 1226 do { 1227 extern void native_iret(void); 1228 if (pv_cpu_ops.iret == native_iret) 1229 set_cpu_bug(c, X86_BUG_ESPFIX); 1230 } while (0); 1231 # else 1232 set_cpu_bug(c, X86_BUG_ESPFIX); 1233 # endif 1234 #endif 1235 } 1236 1237 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1238 { 1239 /* 1240 * The heavy lifting of max_rmid and cache_occ_scale are handled 1241 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1242 * in case CQM bits really aren't there in this CPU. 1243 */ 1244 if (c != &boot_cpu_data) { 1245 boot_cpu_data.x86_cache_max_rmid = 1246 min(boot_cpu_data.x86_cache_max_rmid, 1247 c->x86_cache_max_rmid); 1248 } 1249 } 1250 1251 /* 1252 * Validate that ACPI/mptables have the same information about the 1253 * effective APIC id and update the package map. 1254 */ 1255 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1256 { 1257 #ifdef CONFIG_SMP 1258 unsigned int apicid, cpu = smp_processor_id(); 1259 1260 apicid = apic->cpu_present_to_apicid(cpu); 1261 1262 if (apicid != c->apicid) { 1263 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1264 cpu, apicid, c->initial_apicid); 1265 } 1266 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1267 #else 1268 c->logical_proc_id = 0; 1269 #endif 1270 } 1271 1272 /* 1273 * This does the hard work of actually picking apart the CPU stuff... 1274 */ 1275 static void identify_cpu(struct cpuinfo_x86 *c) 1276 { 1277 int i; 1278 1279 c->loops_per_jiffy = loops_per_jiffy; 1280 c->x86_cache_size = 0; 1281 c->x86_vendor = X86_VENDOR_UNKNOWN; 1282 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1283 c->x86_vendor_id[0] = '\0'; /* Unset */ 1284 c->x86_model_id[0] = '\0'; /* Unset */ 1285 c->x86_max_cores = 1; 1286 c->x86_coreid_bits = 0; 1287 c->cu_id = 0xff; 1288 #ifdef CONFIG_X86_64 1289 c->x86_clflush_size = 64; 1290 c->x86_phys_bits = 36; 1291 c->x86_virt_bits = 48; 1292 #else 1293 c->cpuid_level = -1; /* CPUID not detected */ 1294 c->x86_clflush_size = 32; 1295 c->x86_phys_bits = 32; 1296 c->x86_virt_bits = 32; 1297 #endif 1298 c->x86_cache_alignment = c->x86_clflush_size; 1299 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1300 1301 generic_identify(c); 1302 1303 if (this_cpu->c_identify) 1304 this_cpu->c_identify(c); 1305 1306 /* Clear/Set all flags overridden by options, after probe */ 1307 apply_forced_caps(c); 1308 1309 #ifdef CONFIG_X86_64 1310 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1311 #endif 1312 1313 /* 1314 * Vendor-specific initialization. In this section we 1315 * canonicalize the feature flags, meaning if there are 1316 * features a certain CPU supports which CPUID doesn't 1317 * tell us, CPUID claiming incorrect flags, or other bugs, 1318 * we handle them here. 1319 * 1320 * At the end of this section, c->x86_capability better 1321 * indicate the features this CPU genuinely supports! 1322 */ 1323 if (this_cpu->c_init) 1324 this_cpu->c_init(c); 1325 1326 /* Disable the PN if appropriate */ 1327 squash_the_stupid_serial_number(c); 1328 1329 /* Set up SMEP/SMAP/UMIP */ 1330 setup_smep(c); 1331 setup_smap(c); 1332 setup_umip(c); 1333 1334 /* 1335 * The vendor-specific functions might have changed features. 1336 * Now we do "generic changes." 1337 */ 1338 1339 /* Filter out anything that depends on CPUID levels we don't have */ 1340 filter_cpuid_features(c, true); 1341 1342 /* If the model name is still unset, do table lookup. */ 1343 if (!c->x86_model_id[0]) { 1344 const char *p; 1345 p = table_lookup_model(c); 1346 if (p) 1347 strcpy(c->x86_model_id, p); 1348 else 1349 /* Last resort... */ 1350 sprintf(c->x86_model_id, "%02x/%02x", 1351 c->x86, c->x86_model); 1352 } 1353 1354 #ifdef CONFIG_X86_64 1355 detect_ht(c); 1356 #endif 1357 1358 x86_init_rdrand(c); 1359 x86_init_cache_qos(c); 1360 setup_pku(c); 1361 1362 /* 1363 * Clear/Set all flags overridden by options, need do it 1364 * before following smp all cpus cap AND. 1365 */ 1366 apply_forced_caps(c); 1367 1368 /* 1369 * On SMP, boot_cpu_data holds the common feature set between 1370 * all CPUs; so make sure that we indicate which features are 1371 * common between the CPUs. The first time this routine gets 1372 * executed, c == &boot_cpu_data. 1373 */ 1374 if (c != &boot_cpu_data) { 1375 /* AND the already accumulated flags with these */ 1376 for (i = 0; i < NCAPINTS; i++) 1377 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1378 1379 /* OR, i.e. replicate the bug flags */ 1380 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1381 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1382 } 1383 1384 /* Init Machine Check Exception if available. */ 1385 mcheck_cpu_init(c); 1386 1387 select_idle_routine(c); 1388 1389 #ifdef CONFIG_NUMA 1390 numa_add_cpu(smp_processor_id()); 1391 #endif 1392 } 1393 1394 /* 1395 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1396 * on 32-bit kernels: 1397 */ 1398 #ifdef CONFIG_X86_32 1399 void enable_sep_cpu(void) 1400 { 1401 struct tss_struct *tss; 1402 int cpu; 1403 1404 if (!boot_cpu_has(X86_FEATURE_SEP)) 1405 return; 1406 1407 cpu = get_cpu(); 1408 tss = &per_cpu(cpu_tss_rw, cpu); 1409 1410 /* 1411 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1412 * see the big comment in struct x86_hw_tss's definition. 1413 */ 1414 1415 tss->x86_tss.ss1 = __KERNEL_CS; 1416 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1417 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1418 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1419 1420 put_cpu(); 1421 } 1422 #endif 1423 1424 void __init identify_boot_cpu(void) 1425 { 1426 identify_cpu(&boot_cpu_data); 1427 #ifdef CONFIG_X86_32 1428 sysenter_setup(); 1429 enable_sep_cpu(); 1430 #endif 1431 cpu_detect_tlb(&boot_cpu_data); 1432 } 1433 1434 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1435 { 1436 BUG_ON(c == &boot_cpu_data); 1437 identify_cpu(c); 1438 #ifdef CONFIG_X86_32 1439 enable_sep_cpu(); 1440 #endif 1441 mtrr_ap_init(); 1442 validate_apic_and_package_id(c); 1443 x86_spec_ctrl_setup_ap(); 1444 } 1445 1446 static __init int setup_noclflush(char *arg) 1447 { 1448 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1449 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1450 return 1; 1451 } 1452 __setup("noclflush", setup_noclflush); 1453 1454 void print_cpu_info(struct cpuinfo_x86 *c) 1455 { 1456 const char *vendor = NULL; 1457 1458 if (c->x86_vendor < X86_VENDOR_NUM) { 1459 vendor = this_cpu->c_vendor; 1460 } else { 1461 if (c->cpuid_level >= 0) 1462 vendor = c->x86_vendor_id; 1463 } 1464 1465 if (vendor && !strstr(c->x86_model_id, vendor)) 1466 pr_cont("%s ", vendor); 1467 1468 if (c->x86_model_id[0]) 1469 pr_cont("%s", c->x86_model_id); 1470 else 1471 pr_cont("%d86", c->x86); 1472 1473 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1474 1475 if (c->x86_stepping || c->cpuid_level >= 0) 1476 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1477 else 1478 pr_cont(")\n"); 1479 } 1480 1481 /* 1482 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1483 * But we need to keep a dummy __setup around otherwise it would 1484 * show up as an environment variable for init. 1485 */ 1486 static __init int setup_clearcpuid(char *arg) 1487 { 1488 return 1; 1489 } 1490 __setup("clearcpuid=", setup_clearcpuid); 1491 1492 #ifdef CONFIG_X86_64 1493 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1494 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1495 EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union); 1496 1497 /* 1498 * The following percpu variables are hot. Align current_task to 1499 * cacheline size such that they fall in the same cacheline. 1500 */ 1501 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1502 &init_task; 1503 EXPORT_PER_CPU_SYMBOL(current_task); 1504 1505 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1506 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1507 1508 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1509 1510 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1511 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1512 1513 /* May not be marked __init: used by software suspend */ 1514 void syscall_init(void) 1515 { 1516 extern char _entry_trampoline[]; 1517 extern char entry_SYSCALL_64_trampoline[]; 1518 1519 int cpu = smp_processor_id(); 1520 unsigned long SYSCALL64_entry_trampoline = 1521 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + 1522 (entry_SYSCALL_64_trampoline - _entry_trampoline); 1523 1524 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1525 if (static_cpu_has(X86_FEATURE_PTI)) 1526 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); 1527 else 1528 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1529 1530 #ifdef CONFIG_IA32_EMULATION 1531 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1532 /* 1533 * This only works on Intel CPUs. 1534 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1535 * This does not cause SYSENTER to jump to the wrong location, because 1536 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1537 */ 1538 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1539 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 1540 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1541 #else 1542 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1543 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1544 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1545 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1546 #endif 1547 1548 /* Flags to clear on syscall */ 1549 wrmsrl(MSR_SYSCALL_MASK, 1550 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1551 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1552 } 1553 1554 /* 1555 * Copies of the original ist values from the tss are only accessed during 1556 * debugging, no special alignment required. 1557 */ 1558 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1559 1560 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1561 DEFINE_PER_CPU(int, debug_stack_usage); 1562 1563 int is_debug_stack(unsigned long addr) 1564 { 1565 return __this_cpu_read(debug_stack_usage) || 1566 (addr <= __this_cpu_read(debug_stack_addr) && 1567 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1568 } 1569 NOKPROBE_SYMBOL(is_debug_stack); 1570 1571 DEFINE_PER_CPU(u32, debug_idt_ctr); 1572 1573 void debug_stack_set_zero(void) 1574 { 1575 this_cpu_inc(debug_idt_ctr); 1576 load_current_idt(); 1577 } 1578 NOKPROBE_SYMBOL(debug_stack_set_zero); 1579 1580 void debug_stack_reset(void) 1581 { 1582 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1583 return; 1584 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1585 load_current_idt(); 1586 } 1587 NOKPROBE_SYMBOL(debug_stack_reset); 1588 1589 #else /* CONFIG_X86_64 */ 1590 1591 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1592 EXPORT_PER_CPU_SYMBOL(current_task); 1593 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1594 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1595 1596 /* 1597 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1598 * the top of the kernel stack. Use an extra percpu variable to track the 1599 * top of the kernel stack directly. 1600 */ 1601 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1602 (unsigned long)&init_thread_union + THREAD_SIZE; 1603 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1604 1605 #ifdef CONFIG_STACKPROTECTOR 1606 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1607 #endif 1608 1609 #endif /* CONFIG_X86_64 */ 1610 1611 /* 1612 * Clear all 6 debug registers: 1613 */ 1614 static void clear_all_debug_regs(void) 1615 { 1616 int i; 1617 1618 for (i = 0; i < 8; i++) { 1619 /* Ignore db4, db5 */ 1620 if ((i == 4) || (i == 5)) 1621 continue; 1622 1623 set_debugreg(0, i); 1624 } 1625 } 1626 1627 #ifdef CONFIG_KGDB 1628 /* 1629 * Restore debug regs if using kgdbwait and you have a kernel debugger 1630 * connection established. 1631 */ 1632 static void dbg_restore_debug_regs(void) 1633 { 1634 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1635 arch_kgdb_ops.correct_hw_break(); 1636 } 1637 #else /* ! CONFIG_KGDB */ 1638 #define dbg_restore_debug_regs() 1639 #endif /* ! CONFIG_KGDB */ 1640 1641 static void wait_for_master_cpu(int cpu) 1642 { 1643 #ifdef CONFIG_SMP 1644 /* 1645 * wait for ACK from master CPU before continuing 1646 * with AP initialization 1647 */ 1648 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1649 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1650 cpu_relax(); 1651 #endif 1652 } 1653 1654 /* 1655 * cpu_init() initializes state that is per-CPU. Some data is already 1656 * initialized (naturally) in the bootstrap process, such as the GDT 1657 * and IDT. We reload them nevertheless, this function acts as a 1658 * 'CPU state barrier', nothing should get across. 1659 * A lot of state is already set up in PDA init for 64 bit 1660 */ 1661 #ifdef CONFIG_X86_64 1662 1663 void cpu_init(void) 1664 { 1665 struct orig_ist *oist; 1666 struct task_struct *me; 1667 struct tss_struct *t; 1668 unsigned long v; 1669 int cpu = raw_smp_processor_id(); 1670 int i; 1671 1672 wait_for_master_cpu(cpu); 1673 1674 /* 1675 * Initialize the CR4 shadow before doing anything that could 1676 * try to read it. 1677 */ 1678 cr4_init_shadow(); 1679 1680 if (cpu) 1681 load_ucode_ap(); 1682 1683 t = &per_cpu(cpu_tss_rw, cpu); 1684 oist = &per_cpu(orig_ist, cpu); 1685 1686 #ifdef CONFIG_NUMA 1687 if (this_cpu_read(numa_node) == 0 && 1688 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1689 set_numa_node(early_cpu_to_node(cpu)); 1690 #endif 1691 1692 me = current; 1693 1694 pr_debug("Initializing CPU#%d\n", cpu); 1695 1696 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1697 1698 /* 1699 * Initialize the per-CPU GDT with the boot GDT, 1700 * and set up the GDT descriptor: 1701 */ 1702 1703 switch_to_new_gdt(cpu); 1704 loadsegment(fs, 0); 1705 1706 load_current_idt(); 1707 1708 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1709 syscall_init(); 1710 1711 wrmsrl(MSR_FS_BASE, 0); 1712 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1713 barrier(); 1714 1715 x86_configure_nx(); 1716 x2apic_setup(); 1717 1718 /* 1719 * set up and load the per-CPU TSS 1720 */ 1721 if (!oist->ist[0]) { 1722 char *estacks = get_cpu_entry_area(cpu)->exception_stacks; 1723 1724 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1725 estacks += exception_stack_sizes[v]; 1726 oist->ist[v] = t->x86_tss.ist[v] = 1727 (unsigned long)estacks; 1728 if (v == DEBUG_STACK-1) 1729 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1730 } 1731 } 1732 1733 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1734 1735 /* 1736 * <= is required because the CPU will access up to 1737 * 8 bits beyond the end of the IO permission bitmap. 1738 */ 1739 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1740 t->io_bitmap[i] = ~0UL; 1741 1742 mmgrab(&init_mm); 1743 me->active_mm = &init_mm; 1744 BUG_ON(me->mm); 1745 initialize_tlbstate_and_flush(); 1746 enter_lazy_tlb(&init_mm, me); 1747 1748 /* 1749 * Initialize the TSS. sp0 points to the entry trampoline stack 1750 * regardless of what task is running. 1751 */ 1752 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1753 load_TR_desc(); 1754 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1755 1756 load_mm_ldt(&init_mm); 1757 1758 clear_all_debug_regs(); 1759 dbg_restore_debug_regs(); 1760 1761 fpu__init_cpu(); 1762 1763 if (is_uv_system()) 1764 uv_cpu_init(); 1765 1766 load_fixmap_gdt(cpu); 1767 } 1768 1769 #else 1770 1771 void cpu_init(void) 1772 { 1773 int cpu = smp_processor_id(); 1774 struct task_struct *curr = current; 1775 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1776 1777 wait_for_master_cpu(cpu); 1778 1779 /* 1780 * Initialize the CR4 shadow before doing anything that could 1781 * try to read it. 1782 */ 1783 cr4_init_shadow(); 1784 1785 show_ucode_info_early(); 1786 1787 pr_info("Initializing CPU#%d\n", cpu); 1788 1789 if (cpu_feature_enabled(X86_FEATURE_VME) || 1790 boot_cpu_has(X86_FEATURE_TSC) || 1791 boot_cpu_has(X86_FEATURE_DE)) 1792 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1793 1794 load_current_idt(); 1795 switch_to_new_gdt(cpu); 1796 1797 /* 1798 * Set up and load the per-CPU TSS and LDT 1799 */ 1800 mmgrab(&init_mm); 1801 curr->active_mm = &init_mm; 1802 BUG_ON(curr->mm); 1803 initialize_tlbstate_and_flush(); 1804 enter_lazy_tlb(&init_mm, curr); 1805 1806 /* 1807 * Initialize the TSS. Don't bother initializing sp0, as the initial 1808 * task never enters user mode. 1809 */ 1810 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1811 load_TR_desc(); 1812 1813 load_mm_ldt(&init_mm); 1814 1815 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1816 1817 #ifdef CONFIG_DOUBLEFAULT 1818 /* Set up doublefault TSS pointer in the GDT */ 1819 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1820 #endif 1821 1822 clear_all_debug_regs(); 1823 dbg_restore_debug_regs(); 1824 1825 fpu__init_cpu(); 1826 1827 load_fixmap_gdt(cpu); 1828 } 1829 #endif 1830 1831 static void bsp_resume(void) 1832 { 1833 if (this_cpu->c_bsp_resume) 1834 this_cpu->c_bsp_resume(&boot_cpu_data); 1835 } 1836 1837 static struct syscore_ops cpu_syscore_ops = { 1838 .resume = bsp_resume, 1839 }; 1840 1841 static int __init init_cpu_syscore(void) 1842 { 1843 register_syscore_ops(&cpu_syscore_ops); 1844 return 0; 1845 } 1846 core_initcall(init_cpu_syscore); 1847 1848 /* 1849 * The microcode loader calls this upon late microcode load to recheck features, 1850 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1851 * hotplug lock. 1852 */ 1853 void microcode_check(void) 1854 { 1855 struct cpuinfo_x86 info; 1856 1857 perf_check_microcode(); 1858 1859 /* Reload CPUID max function as it might've changed. */ 1860 info.cpuid_level = cpuid_eax(0); 1861 1862 /* 1863 * Copy all capability leafs to pick up the synthetic ones so that 1864 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1865 * get overwritten in get_cpu_cap(). 1866 */ 1867 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1868 1869 get_cpu_cap(&info); 1870 1871 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1872 return; 1873 1874 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1875 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1876 } 1877