1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 25 #include <asm/stackprotector.h> 26 #include <asm/perf_event.h> 27 #include <asm/mmu_context.h> 28 #include <asm/doublefault.h> 29 #include <asm/archrandom.h> 30 #include <asm/hypervisor.h> 31 #include <asm/processor.h> 32 #include <asm/tlbflush.h> 33 #include <asm/debugreg.h> 34 #include <asm/sections.h> 35 #include <asm/vsyscall.h> 36 #include <linux/topology.h> 37 #include <linux/cpumask.h> 38 #include <asm/pgtable.h> 39 #include <linux/atomic.h> 40 #include <asm/proto.h> 41 #include <asm/setup.h> 42 #include <asm/apic.h> 43 #include <asm/desc.h> 44 #include <asm/fpu/internal.h> 45 #include <asm/mtrr.h> 46 #include <asm/hwcap2.h> 47 #include <linux/numa.h> 48 #include <asm/asm.h> 49 #include <asm/bugs.h> 50 #include <asm/cpu.h> 51 #include <asm/mce.h> 52 #include <asm/msr.h> 53 #include <asm/memtype.h> 54 #include <asm/microcode.h> 55 #include <asm/microcode_intel.h> 56 #include <asm/intel-family.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/uv/uv.h> 59 60 #include "cpu.h" 61 62 u32 elf_hwcap2 __read_mostly; 63 64 /* all of these masks are initialized in setup_cpu_local_masks() */ 65 cpumask_var_t cpu_initialized_mask; 66 cpumask_var_t cpu_callout_mask; 67 cpumask_var_t cpu_callin_mask; 68 69 /* representing cpus for which sibling maps can be computed */ 70 cpumask_var_t cpu_sibling_setup_mask; 71 72 /* Number of siblings per CPU package */ 73 int smp_num_siblings = 1; 74 EXPORT_SYMBOL(smp_num_siblings); 75 76 /* Last level cache ID of each logical CPU */ 77 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 78 79 /* correctly size the local cpu masks */ 80 void __init setup_cpu_local_masks(void) 81 { 82 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 83 alloc_bootmem_cpumask_var(&cpu_callin_mask); 84 alloc_bootmem_cpumask_var(&cpu_callout_mask); 85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 86 } 87 88 static void default_init(struct cpuinfo_x86 *c) 89 { 90 #ifdef CONFIG_X86_64 91 cpu_detect_cache_sizes(c); 92 #else 93 /* Not much we can do here... */ 94 /* Check if at least it has cpuid */ 95 if (c->cpuid_level == -1) { 96 /* No cpuid. It must be an ancient CPU */ 97 if (c->x86 == 4) 98 strcpy(c->x86_model_id, "486"); 99 else if (c->x86 == 3) 100 strcpy(c->x86_model_id, "386"); 101 } 102 #endif 103 } 104 105 static const struct cpu_dev default_cpu = { 106 .c_init = default_init, 107 .c_vendor = "Unknown", 108 .c_x86_vendor = X86_VENDOR_UNKNOWN, 109 }; 110 111 static const struct cpu_dev *this_cpu = &default_cpu; 112 113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 114 #ifdef CONFIG_X86_64 115 /* 116 * We need valid kernel segments for data and code in long mode too 117 * IRET will check the segment types kkeil 2000/10/28 118 * Also sysret mandates a special GDT layout 119 * 120 * TLS descriptors are currently at a different place compared to i386. 121 * Hopefully nobody expects them at a fixed place (Wine?) 122 */ 123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 129 #else 130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 134 /* 135 * Segments used for calling PnP BIOS have byte granularity. 136 * They code segments and data segments have fixed 64k limits, 137 * the transfer segment sizes are set at run time. 138 */ 139 /* 32-bit code */ 140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 141 /* 16-bit code */ 142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 143 /* 16-bit data */ 144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 145 /* 16-bit data */ 146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 147 /* 16-bit data */ 148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 149 /* 150 * The APM segments have byte granularity and their bases 151 * are set at run time. All have 64k limits. 152 */ 153 /* 32-bit code */ 154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 155 /* 16-bit code */ 156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 157 /* data */ 158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 159 160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 162 GDT_STACK_CANARY_INIT 163 #endif 164 } }; 165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 166 167 #ifdef CONFIG_X86_64 168 static int __init x86_nopcid_setup(char *s) 169 { 170 /* nopcid doesn't accept parameters */ 171 if (s) 172 return -EINVAL; 173 174 /* do not emit a message if the feature is not present */ 175 if (!boot_cpu_has(X86_FEATURE_PCID)) 176 return 0; 177 178 setup_clear_cpu_cap(X86_FEATURE_PCID); 179 pr_info("nopcid: PCID feature disabled\n"); 180 return 0; 181 } 182 early_param("nopcid", x86_nopcid_setup); 183 #endif 184 185 static int __init x86_noinvpcid_setup(char *s) 186 { 187 /* noinvpcid doesn't accept parameters */ 188 if (s) 189 return -EINVAL; 190 191 /* do not emit a message if the feature is not present */ 192 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 193 return 0; 194 195 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 196 pr_info("noinvpcid: INVPCID feature disabled\n"); 197 return 0; 198 } 199 early_param("noinvpcid", x86_noinvpcid_setup); 200 201 #ifdef CONFIG_X86_32 202 static int cachesize_override = -1; 203 static int disable_x86_serial_nr = 1; 204 205 static int __init cachesize_setup(char *str) 206 { 207 get_option(&str, &cachesize_override); 208 return 1; 209 } 210 __setup("cachesize=", cachesize_setup); 211 212 static int __init x86_sep_setup(char *s) 213 { 214 setup_clear_cpu_cap(X86_FEATURE_SEP); 215 return 1; 216 } 217 __setup("nosep", x86_sep_setup); 218 219 /* Standard macro to see if a specific flag is changeable */ 220 static inline int flag_is_changeable_p(u32 flag) 221 { 222 u32 f1, f2; 223 224 /* 225 * Cyrix and IDT cpus allow disabling of CPUID 226 * so the code below may return different results 227 * when it is executed before and after enabling 228 * the CPUID. Add "volatile" to not allow gcc to 229 * optimize the subsequent calls to this function. 230 */ 231 asm volatile ("pushfl \n\t" 232 "pushfl \n\t" 233 "popl %0 \n\t" 234 "movl %0, %1 \n\t" 235 "xorl %2, %0 \n\t" 236 "pushl %0 \n\t" 237 "popfl \n\t" 238 "pushfl \n\t" 239 "popl %0 \n\t" 240 "popfl \n\t" 241 242 : "=&r" (f1), "=&r" (f2) 243 : "ir" (flag)); 244 245 return ((f1^f2) & flag) != 0; 246 } 247 248 /* Probe for the CPUID instruction */ 249 int have_cpuid_p(void) 250 { 251 return flag_is_changeable_p(X86_EFLAGS_ID); 252 } 253 254 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 255 { 256 unsigned long lo, hi; 257 258 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 259 return; 260 261 /* Disable processor serial number: */ 262 263 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 264 lo |= 0x200000; 265 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 266 267 pr_notice("CPU serial number disabled.\n"); 268 clear_cpu_cap(c, X86_FEATURE_PN); 269 270 /* Disabling the serial number may affect the cpuid level */ 271 c->cpuid_level = cpuid_eax(0); 272 } 273 274 static int __init x86_serial_nr_setup(char *s) 275 { 276 disable_x86_serial_nr = 0; 277 return 1; 278 } 279 __setup("serialnumber", x86_serial_nr_setup); 280 #else 281 static inline int flag_is_changeable_p(u32 flag) 282 { 283 return 1; 284 } 285 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 286 { 287 } 288 #endif 289 290 static __init int setup_disable_smep(char *arg) 291 { 292 setup_clear_cpu_cap(X86_FEATURE_SMEP); 293 return 1; 294 } 295 __setup("nosmep", setup_disable_smep); 296 297 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 298 { 299 if (cpu_has(c, X86_FEATURE_SMEP)) 300 cr4_set_bits(X86_CR4_SMEP); 301 } 302 303 static __init int setup_disable_smap(char *arg) 304 { 305 setup_clear_cpu_cap(X86_FEATURE_SMAP); 306 return 1; 307 } 308 __setup("nosmap", setup_disable_smap); 309 310 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 311 { 312 unsigned long eflags = native_save_fl(); 313 314 /* This should have been cleared long ago */ 315 BUG_ON(eflags & X86_EFLAGS_AC); 316 317 if (cpu_has(c, X86_FEATURE_SMAP)) { 318 #ifdef CONFIG_X86_SMAP 319 cr4_set_bits(X86_CR4_SMAP); 320 #else 321 cr4_clear_bits(X86_CR4_SMAP); 322 #endif 323 } 324 } 325 326 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 327 { 328 /* Check the boot processor, plus build option for UMIP. */ 329 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 330 goto out; 331 332 /* Check the current processor's cpuid bits. */ 333 if (!cpu_has(c, X86_FEATURE_UMIP)) 334 goto out; 335 336 cr4_set_bits(X86_CR4_UMIP); 337 338 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 339 340 return; 341 342 out: 343 /* 344 * Make sure UMIP is disabled in case it was enabled in a 345 * previous boot (e.g., via kexec). 346 */ 347 cr4_clear_bits(X86_CR4_UMIP); 348 } 349 350 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 351 static unsigned long cr4_pinned_bits __ro_after_init; 352 353 void native_write_cr0(unsigned long val) 354 { 355 unsigned long bits_missing = 0; 356 357 set_register: 358 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); 359 360 if (static_branch_likely(&cr_pinning)) { 361 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 362 bits_missing = X86_CR0_WP; 363 val |= bits_missing; 364 goto set_register; 365 } 366 /* Warn after we've set the missing bits. */ 367 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 368 } 369 } 370 EXPORT_SYMBOL(native_write_cr0); 371 372 void native_write_cr4(unsigned long val) 373 { 374 unsigned long bits_missing = 0; 375 376 set_register: 377 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); 378 379 if (static_branch_likely(&cr_pinning)) { 380 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { 381 bits_missing = ~val & cr4_pinned_bits; 382 val |= bits_missing; 383 goto set_register; 384 } 385 /* Warn after we've set the missing bits. */ 386 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n", 387 bits_missing); 388 } 389 } 390 EXPORT_SYMBOL(native_write_cr4); 391 392 void cr4_init(void) 393 { 394 unsigned long cr4 = __read_cr4(); 395 396 if (boot_cpu_has(X86_FEATURE_PCID)) 397 cr4 |= X86_CR4_PCIDE; 398 if (static_branch_likely(&cr_pinning)) 399 cr4 |= cr4_pinned_bits; 400 401 __write_cr4(cr4); 402 403 /* Initialize cr4 shadow for this CPU. */ 404 this_cpu_write(cpu_tlbstate.cr4, cr4); 405 } 406 407 /* 408 * Once CPU feature detection is finished (and boot params have been 409 * parsed), record any of the sensitive CR bits that are set, and 410 * enable CR pinning. 411 */ 412 static void __init setup_cr_pinning(void) 413 { 414 unsigned long mask; 415 416 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); 417 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; 418 static_key_enable(&cr_pinning.key); 419 } 420 421 /* 422 * Protection Keys are not available in 32-bit mode. 423 */ 424 static bool pku_disabled; 425 426 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 427 { 428 struct pkru_state *pk; 429 430 /* check the boot processor, plus compile options for PKU: */ 431 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 432 return; 433 /* checks the actual processor's cpuid bits: */ 434 if (!cpu_has(c, X86_FEATURE_PKU)) 435 return; 436 if (pku_disabled) 437 return; 438 439 cr4_set_bits(X86_CR4_PKE); 440 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 441 if (pk) 442 pk->pkru = init_pkru_value; 443 /* 444 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 445 * cpuid bit to be set. We need to ensure that we 446 * update that bit in this CPU's "cpu_info". 447 */ 448 set_cpu_cap(c, X86_FEATURE_OSPKE); 449 } 450 451 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 452 static __init int setup_disable_pku(char *arg) 453 { 454 /* 455 * Do not clear the X86_FEATURE_PKU bit. All of the 456 * runtime checks are against OSPKE so clearing the 457 * bit does nothing. 458 * 459 * This way, we will see "pku" in cpuinfo, but not 460 * "ospke", which is exactly what we want. It shows 461 * that the CPU has PKU, but the OS has not enabled it. 462 * This happens to be exactly how a system would look 463 * if we disabled the config option. 464 */ 465 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 466 pku_disabled = true; 467 return 1; 468 } 469 __setup("nopku", setup_disable_pku); 470 #endif /* CONFIG_X86_64 */ 471 472 /* 473 * Some CPU features depend on higher CPUID levels, which may not always 474 * be available due to CPUID level capping or broken virtualization 475 * software. Add those features to this table to auto-disable them. 476 */ 477 struct cpuid_dependent_feature { 478 u32 feature; 479 u32 level; 480 }; 481 482 static const struct cpuid_dependent_feature 483 cpuid_dependent_features[] = { 484 { X86_FEATURE_MWAIT, 0x00000005 }, 485 { X86_FEATURE_DCA, 0x00000009 }, 486 { X86_FEATURE_XSAVE, 0x0000000d }, 487 { 0, 0 } 488 }; 489 490 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 491 { 492 const struct cpuid_dependent_feature *df; 493 494 for (df = cpuid_dependent_features; df->feature; df++) { 495 496 if (!cpu_has(c, df->feature)) 497 continue; 498 /* 499 * Note: cpuid_level is set to -1 if unavailable, but 500 * extended_extended_level is set to 0 if unavailable 501 * and the legitimate extended levels are all negative 502 * when signed; hence the weird messing around with 503 * signs here... 504 */ 505 if (!((s32)df->level < 0 ? 506 (u32)df->level > (u32)c->extended_cpuid_level : 507 (s32)df->level > (s32)c->cpuid_level)) 508 continue; 509 510 clear_cpu_cap(c, df->feature); 511 if (!warn) 512 continue; 513 514 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 515 x86_cap_flag(df->feature), df->level); 516 } 517 } 518 519 /* 520 * Naming convention should be: <Name> [(<Codename>)] 521 * This table only is used unless init_<vendor>() below doesn't set it; 522 * in particular, if CPUID levels 0x80000002..4 are supported, this 523 * isn't used 524 */ 525 526 /* Look up CPU names by table lookup. */ 527 static const char *table_lookup_model(struct cpuinfo_x86 *c) 528 { 529 #ifdef CONFIG_X86_32 530 const struct legacy_cpu_model_info *info; 531 532 if (c->x86_model >= 16) 533 return NULL; /* Range check */ 534 535 if (!this_cpu) 536 return NULL; 537 538 info = this_cpu->legacy_models; 539 540 while (info->family) { 541 if (info->family == c->x86) 542 return info->model_names[c->x86_model]; 543 info++; 544 } 545 #endif 546 return NULL; /* Not found */ 547 } 548 549 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 550 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 551 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 552 553 void load_percpu_segment(int cpu) 554 { 555 #ifdef CONFIG_X86_32 556 loadsegment(fs, __KERNEL_PERCPU); 557 #else 558 __loadsegment_simple(gs, 0); 559 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 560 #endif 561 load_stack_canary_segment(); 562 } 563 564 #ifdef CONFIG_X86_32 565 /* The 32-bit entry code needs to find cpu_entry_area. */ 566 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 567 #endif 568 569 /* Load the original GDT from the per-cpu structure */ 570 void load_direct_gdt(int cpu) 571 { 572 struct desc_ptr gdt_descr; 573 574 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 575 gdt_descr.size = GDT_SIZE - 1; 576 load_gdt(&gdt_descr); 577 } 578 EXPORT_SYMBOL_GPL(load_direct_gdt); 579 580 /* Load a fixmap remapping of the per-cpu GDT */ 581 void load_fixmap_gdt(int cpu) 582 { 583 struct desc_ptr gdt_descr; 584 585 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 586 gdt_descr.size = GDT_SIZE - 1; 587 load_gdt(&gdt_descr); 588 } 589 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 590 591 /* 592 * Current gdt points %fs at the "master" per-cpu area: after this, 593 * it's on the real one. 594 */ 595 void switch_to_new_gdt(int cpu) 596 { 597 /* Load the original GDT */ 598 load_direct_gdt(cpu); 599 /* Reload the per-cpu base */ 600 load_percpu_segment(cpu); 601 } 602 603 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 604 605 static void get_model_name(struct cpuinfo_x86 *c) 606 { 607 unsigned int *v; 608 char *p, *q, *s; 609 610 if (c->extended_cpuid_level < 0x80000004) 611 return; 612 613 v = (unsigned int *)c->x86_model_id; 614 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 615 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 616 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 617 c->x86_model_id[48] = 0; 618 619 /* Trim whitespace */ 620 p = q = s = &c->x86_model_id[0]; 621 622 while (*p == ' ') 623 p++; 624 625 while (*p) { 626 /* Note the last non-whitespace index */ 627 if (!isspace(*p)) 628 s = q; 629 630 *q++ = *p++; 631 } 632 633 *(s + 1) = '\0'; 634 } 635 636 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 637 { 638 unsigned int eax, ebx, ecx, edx; 639 640 c->x86_max_cores = 1; 641 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 642 return; 643 644 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 645 if (eax & 0x1f) 646 c->x86_max_cores = (eax >> 26) + 1; 647 } 648 649 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 650 { 651 unsigned int n, dummy, ebx, ecx, edx, l2size; 652 653 n = c->extended_cpuid_level; 654 655 if (n >= 0x80000005) { 656 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 657 c->x86_cache_size = (ecx>>24) + (edx>>24); 658 #ifdef CONFIG_X86_64 659 /* On K8 L1 TLB is inclusive, so don't count it */ 660 c->x86_tlbsize = 0; 661 #endif 662 } 663 664 if (n < 0x80000006) /* Some chips just has a large L1. */ 665 return; 666 667 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 668 l2size = ecx >> 16; 669 670 #ifdef CONFIG_X86_64 671 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 672 #else 673 /* do processor-specific cache resizing */ 674 if (this_cpu->legacy_cache_size) 675 l2size = this_cpu->legacy_cache_size(c, l2size); 676 677 /* Allow user to override all this if necessary. */ 678 if (cachesize_override != -1) 679 l2size = cachesize_override; 680 681 if (l2size == 0) 682 return; /* Again, no L2 cache is possible */ 683 #endif 684 685 c->x86_cache_size = l2size; 686 } 687 688 u16 __read_mostly tlb_lli_4k[NR_INFO]; 689 u16 __read_mostly tlb_lli_2m[NR_INFO]; 690 u16 __read_mostly tlb_lli_4m[NR_INFO]; 691 u16 __read_mostly tlb_lld_4k[NR_INFO]; 692 u16 __read_mostly tlb_lld_2m[NR_INFO]; 693 u16 __read_mostly tlb_lld_4m[NR_INFO]; 694 u16 __read_mostly tlb_lld_1g[NR_INFO]; 695 696 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 697 { 698 if (this_cpu->c_detect_tlb) 699 this_cpu->c_detect_tlb(c); 700 701 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 702 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 703 tlb_lli_4m[ENTRIES]); 704 705 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 706 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 707 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 708 } 709 710 int detect_ht_early(struct cpuinfo_x86 *c) 711 { 712 #ifdef CONFIG_SMP 713 u32 eax, ebx, ecx, edx; 714 715 if (!cpu_has(c, X86_FEATURE_HT)) 716 return -1; 717 718 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 719 return -1; 720 721 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 722 return -1; 723 724 cpuid(1, &eax, &ebx, &ecx, &edx); 725 726 smp_num_siblings = (ebx & 0xff0000) >> 16; 727 if (smp_num_siblings == 1) 728 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 729 #endif 730 return 0; 731 } 732 733 void detect_ht(struct cpuinfo_x86 *c) 734 { 735 #ifdef CONFIG_SMP 736 int index_msb, core_bits; 737 738 if (detect_ht_early(c) < 0) 739 return; 740 741 index_msb = get_count_order(smp_num_siblings); 742 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 743 744 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 745 746 index_msb = get_count_order(smp_num_siblings); 747 748 core_bits = get_count_order(c->x86_max_cores); 749 750 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 751 ((1 << core_bits) - 1); 752 #endif 753 } 754 755 static void get_cpu_vendor(struct cpuinfo_x86 *c) 756 { 757 char *v = c->x86_vendor_id; 758 int i; 759 760 for (i = 0; i < X86_VENDOR_NUM; i++) { 761 if (!cpu_devs[i]) 762 break; 763 764 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 765 (cpu_devs[i]->c_ident[1] && 766 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 767 768 this_cpu = cpu_devs[i]; 769 c->x86_vendor = this_cpu->c_x86_vendor; 770 return; 771 } 772 } 773 774 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 775 "CPU: Your system may be unstable.\n", v); 776 777 c->x86_vendor = X86_VENDOR_UNKNOWN; 778 this_cpu = &default_cpu; 779 } 780 781 void cpu_detect(struct cpuinfo_x86 *c) 782 { 783 /* Get vendor name */ 784 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 785 (unsigned int *)&c->x86_vendor_id[0], 786 (unsigned int *)&c->x86_vendor_id[8], 787 (unsigned int *)&c->x86_vendor_id[4]); 788 789 c->x86 = 4; 790 /* Intel-defined flags: level 0x00000001 */ 791 if (c->cpuid_level >= 0x00000001) { 792 u32 junk, tfms, cap0, misc; 793 794 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 795 c->x86 = x86_family(tfms); 796 c->x86_model = x86_model(tfms); 797 c->x86_stepping = x86_stepping(tfms); 798 799 if (cap0 & (1<<19)) { 800 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 801 c->x86_cache_alignment = c->x86_clflush_size; 802 } 803 } 804 } 805 806 static void apply_forced_caps(struct cpuinfo_x86 *c) 807 { 808 int i; 809 810 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 811 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 812 c->x86_capability[i] |= cpu_caps_set[i]; 813 } 814 } 815 816 static void init_speculation_control(struct cpuinfo_x86 *c) 817 { 818 /* 819 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 820 * and they also have a different bit for STIBP support. Also, 821 * a hypervisor might have set the individual AMD bits even on 822 * Intel CPUs, for finer-grained selection of what's available. 823 */ 824 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 825 set_cpu_cap(c, X86_FEATURE_IBRS); 826 set_cpu_cap(c, X86_FEATURE_IBPB); 827 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 828 } 829 830 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 831 set_cpu_cap(c, X86_FEATURE_STIBP); 832 833 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 834 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 835 set_cpu_cap(c, X86_FEATURE_SSBD); 836 837 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 838 set_cpu_cap(c, X86_FEATURE_IBRS); 839 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 840 } 841 842 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 843 set_cpu_cap(c, X86_FEATURE_IBPB); 844 845 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 846 set_cpu_cap(c, X86_FEATURE_STIBP); 847 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 848 } 849 850 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 851 set_cpu_cap(c, X86_FEATURE_SSBD); 852 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 853 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 854 } 855 } 856 857 static void init_cqm(struct cpuinfo_x86 *c) 858 { 859 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 860 c->x86_cache_max_rmid = -1; 861 c->x86_cache_occ_scale = -1; 862 return; 863 } 864 865 /* will be overridden if occupancy monitoring exists */ 866 c->x86_cache_max_rmid = cpuid_ebx(0xf); 867 868 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 869 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 870 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 871 u32 eax, ebx, ecx, edx; 872 873 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 874 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 875 876 c->x86_cache_max_rmid = ecx; 877 c->x86_cache_occ_scale = ebx; 878 } 879 } 880 881 void get_cpu_cap(struct cpuinfo_x86 *c) 882 { 883 u32 eax, ebx, ecx, edx; 884 885 /* Intel-defined flags: level 0x00000001 */ 886 if (c->cpuid_level >= 0x00000001) { 887 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 888 889 c->x86_capability[CPUID_1_ECX] = ecx; 890 c->x86_capability[CPUID_1_EDX] = edx; 891 } 892 893 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 894 if (c->cpuid_level >= 0x00000006) 895 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 896 897 /* Additional Intel-defined flags: level 0x00000007 */ 898 if (c->cpuid_level >= 0x00000007) { 899 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 900 c->x86_capability[CPUID_7_0_EBX] = ebx; 901 c->x86_capability[CPUID_7_ECX] = ecx; 902 c->x86_capability[CPUID_7_EDX] = edx; 903 904 /* Check valid sub-leaf index before accessing it */ 905 if (eax >= 1) { 906 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 907 c->x86_capability[CPUID_7_1_EAX] = eax; 908 } 909 } 910 911 /* Extended state features: level 0x0000000d */ 912 if (c->cpuid_level >= 0x0000000d) { 913 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 914 915 c->x86_capability[CPUID_D_1_EAX] = eax; 916 } 917 918 /* AMD-defined flags: level 0x80000001 */ 919 eax = cpuid_eax(0x80000000); 920 c->extended_cpuid_level = eax; 921 922 if ((eax & 0xffff0000) == 0x80000000) { 923 if (eax >= 0x80000001) { 924 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 925 926 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 927 c->x86_capability[CPUID_8000_0001_EDX] = edx; 928 } 929 } 930 931 if (c->extended_cpuid_level >= 0x80000007) { 932 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 933 934 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 935 c->x86_power = edx; 936 } 937 938 if (c->extended_cpuid_level >= 0x80000008) { 939 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 940 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 941 } 942 943 if (c->extended_cpuid_level >= 0x8000000a) 944 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 945 946 init_scattered_cpuid_features(c); 947 init_speculation_control(c); 948 init_cqm(c); 949 950 /* 951 * Clear/Set all flags overridden by options, after probe. 952 * This needs to happen each time we re-probe, which may happen 953 * several times during CPU initialization. 954 */ 955 apply_forced_caps(c); 956 } 957 958 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 959 { 960 u32 eax, ebx, ecx, edx; 961 962 if (c->extended_cpuid_level >= 0x80000008) { 963 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 964 965 c->x86_virt_bits = (eax >> 8) & 0xff; 966 c->x86_phys_bits = eax & 0xff; 967 } 968 #ifdef CONFIG_X86_32 969 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 970 c->x86_phys_bits = 36; 971 #endif 972 c->x86_cache_bits = c->x86_phys_bits; 973 } 974 975 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 976 { 977 #ifdef CONFIG_X86_32 978 int i; 979 980 /* 981 * First of all, decide if this is a 486 or higher 982 * It's a 486 if we can modify the AC flag 983 */ 984 if (flag_is_changeable_p(X86_EFLAGS_AC)) 985 c->x86 = 4; 986 else 987 c->x86 = 3; 988 989 for (i = 0; i < X86_VENDOR_NUM; i++) 990 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 991 c->x86_vendor_id[0] = 0; 992 cpu_devs[i]->c_identify(c); 993 if (c->x86_vendor_id[0]) { 994 get_cpu_vendor(c); 995 break; 996 } 997 } 998 #endif 999 } 1000 1001 #define NO_SPECULATION BIT(0) 1002 #define NO_MELTDOWN BIT(1) 1003 #define NO_SSB BIT(2) 1004 #define NO_L1TF BIT(3) 1005 #define NO_MDS BIT(4) 1006 #define MSBDS_ONLY BIT(5) 1007 #define NO_SWAPGS BIT(6) 1008 #define NO_ITLB_MULTIHIT BIT(7) 1009 #define NO_SPECTRE_V2 BIT(8) 1010 1011 #define VULNWL(vendor, family, model, whitelist) \ 1012 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1013 1014 #define VULNWL_INTEL(model, whitelist) \ 1015 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1016 1017 #define VULNWL_AMD(family, whitelist) \ 1018 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1019 1020 #define VULNWL_HYGON(family, whitelist) \ 1021 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1022 1023 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1024 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1025 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1026 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1027 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1028 1029 /* Intel Family 6 */ 1030 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1031 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1032 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1033 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1034 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1035 1036 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1037 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1038 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1039 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1040 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1041 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1042 1043 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1044 1045 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1046 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1047 1048 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1049 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1050 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1051 1052 /* 1053 * Technically, swapgs isn't serializing on AMD (despite it previously 1054 * being documented as such in the APM). But according to AMD, %gs is 1055 * updated non-speculatively, and the issuing of %gs-relative memory 1056 * operands will be blocked until the %gs update completes, which is 1057 * good enough for our purposes. 1058 */ 1059 1060 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1061 1062 /* AMD Family 0xf - 0x12 */ 1063 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1064 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1065 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1066 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1067 1068 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1069 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1070 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1071 1072 /* Zhaoxin Family 7 */ 1073 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1074 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1075 {} 1076 }; 1077 1078 static bool __init cpu_matches(unsigned long which) 1079 { 1080 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 1081 1082 return m && !!(m->driver_data & which); 1083 } 1084 1085 u64 x86_read_arch_cap_msr(void) 1086 { 1087 u64 ia32_cap = 0; 1088 1089 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1090 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1091 1092 return ia32_cap; 1093 } 1094 1095 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1096 { 1097 u64 ia32_cap = x86_read_arch_cap_msr(); 1098 1099 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1100 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1101 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1102 1103 if (cpu_matches(NO_SPECULATION)) 1104 return; 1105 1106 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1107 1108 if (!cpu_matches(NO_SPECTRE_V2)) 1109 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1110 1111 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 1112 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1113 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1114 1115 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1116 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1117 1118 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1119 setup_force_cpu_bug(X86_BUG_MDS); 1120 if (cpu_matches(MSBDS_ONLY)) 1121 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1122 } 1123 1124 if (!cpu_matches(NO_SWAPGS)) 1125 setup_force_cpu_bug(X86_BUG_SWAPGS); 1126 1127 /* 1128 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1129 * - TSX is supported or 1130 * - TSX_CTRL is present 1131 * 1132 * TSX_CTRL check is needed for cases when TSX could be disabled before 1133 * the kernel boot e.g. kexec. 1134 * TSX_CTRL check alone is not sufficient for cases when the microcode 1135 * update is not present or running as guest that don't get TSX_CTRL. 1136 */ 1137 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1138 (cpu_has(c, X86_FEATURE_RTM) || 1139 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1140 setup_force_cpu_bug(X86_BUG_TAA); 1141 1142 if (cpu_matches(NO_MELTDOWN)) 1143 return; 1144 1145 /* Rogue Data Cache Load? No! */ 1146 if (ia32_cap & ARCH_CAP_RDCL_NO) 1147 return; 1148 1149 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1150 1151 if (cpu_matches(NO_L1TF)) 1152 return; 1153 1154 setup_force_cpu_bug(X86_BUG_L1TF); 1155 } 1156 1157 /* 1158 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1159 * unfortunately, that's not true in practice because of early VIA 1160 * chips and (more importantly) broken virtualizers that are not easy 1161 * to detect. In the latter case it doesn't even *fail* reliably, so 1162 * probing for it doesn't even work. Disable it completely on 32-bit 1163 * unless we can find a reliable way to detect all the broken cases. 1164 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1165 */ 1166 static void detect_nopl(void) 1167 { 1168 #ifdef CONFIG_X86_32 1169 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1170 #else 1171 setup_force_cpu_cap(X86_FEATURE_NOPL); 1172 #endif 1173 } 1174 1175 /* 1176 * Do minimum CPU detection early. 1177 * Fields really needed: vendor, cpuid_level, family, model, mask, 1178 * cache alignment. 1179 * The others are not touched to avoid unwanted side effects. 1180 * 1181 * WARNING: this function is only called on the boot CPU. Don't add code 1182 * here that is supposed to run on all CPUs. 1183 */ 1184 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1185 { 1186 #ifdef CONFIG_X86_64 1187 c->x86_clflush_size = 64; 1188 c->x86_phys_bits = 36; 1189 c->x86_virt_bits = 48; 1190 #else 1191 c->x86_clflush_size = 32; 1192 c->x86_phys_bits = 32; 1193 c->x86_virt_bits = 32; 1194 #endif 1195 c->x86_cache_alignment = c->x86_clflush_size; 1196 1197 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1198 c->extended_cpuid_level = 0; 1199 1200 if (!have_cpuid_p()) 1201 identify_cpu_without_cpuid(c); 1202 1203 /* cyrix could have cpuid enabled via c_identify()*/ 1204 if (have_cpuid_p()) { 1205 cpu_detect(c); 1206 get_cpu_vendor(c); 1207 get_cpu_cap(c); 1208 get_cpu_address_sizes(c); 1209 setup_force_cpu_cap(X86_FEATURE_CPUID); 1210 1211 if (this_cpu->c_early_init) 1212 this_cpu->c_early_init(c); 1213 1214 c->cpu_index = 0; 1215 filter_cpuid_features(c, false); 1216 1217 if (this_cpu->c_bsp_init) 1218 this_cpu->c_bsp_init(c); 1219 } else { 1220 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1221 } 1222 1223 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1224 1225 cpu_set_bug_bits(c); 1226 1227 cpu_set_core_cap_bits(c); 1228 1229 fpu__init_system(c); 1230 1231 #ifdef CONFIG_X86_32 1232 /* 1233 * Regardless of whether PCID is enumerated, the SDM says 1234 * that it can't be enabled in 32-bit mode. 1235 */ 1236 setup_clear_cpu_cap(X86_FEATURE_PCID); 1237 #endif 1238 1239 /* 1240 * Later in the boot process pgtable_l5_enabled() relies on 1241 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1242 * enabled by this point we need to clear the feature bit to avoid 1243 * false-positives at the later stage. 1244 * 1245 * pgtable_l5_enabled() can be false here for several reasons: 1246 * - 5-level paging is disabled compile-time; 1247 * - it's 32-bit kernel; 1248 * - machine doesn't support 5-level paging; 1249 * - user specified 'no5lvl' in kernel command line. 1250 */ 1251 if (!pgtable_l5_enabled()) 1252 setup_clear_cpu_cap(X86_FEATURE_LA57); 1253 1254 detect_nopl(); 1255 } 1256 1257 void __init early_cpu_init(void) 1258 { 1259 const struct cpu_dev *const *cdev; 1260 int count = 0; 1261 1262 #ifdef CONFIG_PROCESSOR_SELECT 1263 pr_info("KERNEL supported cpus:\n"); 1264 #endif 1265 1266 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1267 const struct cpu_dev *cpudev = *cdev; 1268 1269 if (count >= X86_VENDOR_NUM) 1270 break; 1271 cpu_devs[count] = cpudev; 1272 count++; 1273 1274 #ifdef CONFIG_PROCESSOR_SELECT 1275 { 1276 unsigned int j; 1277 1278 for (j = 0; j < 2; j++) { 1279 if (!cpudev->c_ident[j]) 1280 continue; 1281 pr_info(" %s %s\n", cpudev->c_vendor, 1282 cpudev->c_ident[j]); 1283 } 1284 } 1285 #endif 1286 } 1287 early_identify_cpu(&boot_cpu_data); 1288 } 1289 1290 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1291 { 1292 #ifdef CONFIG_X86_64 1293 /* 1294 * Empirically, writing zero to a segment selector on AMD does 1295 * not clear the base, whereas writing zero to a segment 1296 * selector on Intel does clear the base. Intel's behavior 1297 * allows slightly faster context switches in the common case 1298 * where GS is unused by the prev and next threads. 1299 * 1300 * Since neither vendor documents this anywhere that I can see, 1301 * detect it directly instead of hardcoding the choice by 1302 * vendor. 1303 * 1304 * I've designated AMD's behavior as the "bug" because it's 1305 * counterintuitive and less friendly. 1306 */ 1307 1308 unsigned long old_base, tmp; 1309 rdmsrl(MSR_FS_BASE, old_base); 1310 wrmsrl(MSR_FS_BASE, 1); 1311 loadsegment(fs, 0); 1312 rdmsrl(MSR_FS_BASE, tmp); 1313 if (tmp != 0) 1314 set_cpu_bug(c, X86_BUG_NULL_SEG); 1315 wrmsrl(MSR_FS_BASE, old_base); 1316 #endif 1317 } 1318 1319 static void generic_identify(struct cpuinfo_x86 *c) 1320 { 1321 c->extended_cpuid_level = 0; 1322 1323 if (!have_cpuid_p()) 1324 identify_cpu_without_cpuid(c); 1325 1326 /* cyrix could have cpuid enabled via c_identify()*/ 1327 if (!have_cpuid_p()) 1328 return; 1329 1330 cpu_detect(c); 1331 1332 get_cpu_vendor(c); 1333 1334 get_cpu_cap(c); 1335 1336 get_cpu_address_sizes(c); 1337 1338 if (c->cpuid_level >= 0x00000001) { 1339 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1340 #ifdef CONFIG_X86_32 1341 # ifdef CONFIG_SMP 1342 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1343 # else 1344 c->apicid = c->initial_apicid; 1345 # endif 1346 #endif 1347 c->phys_proc_id = c->initial_apicid; 1348 } 1349 1350 get_model_name(c); /* Default name */ 1351 1352 detect_null_seg_behavior(c); 1353 1354 /* 1355 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1356 * systems that run Linux at CPL > 0 may or may not have the 1357 * issue, but, even if they have the issue, there's absolutely 1358 * nothing we can do about it because we can't use the real IRET 1359 * instruction. 1360 * 1361 * NB: For the time being, only 32-bit kernels support 1362 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1363 * whether to apply espfix using paravirt hooks. If any 1364 * non-paravirt system ever shows up that does *not* have the 1365 * ESPFIX issue, we can change this. 1366 */ 1367 #ifdef CONFIG_X86_32 1368 # ifdef CONFIG_PARAVIRT_XXL 1369 do { 1370 extern void native_iret(void); 1371 if (pv_ops.cpu.iret == native_iret) 1372 set_cpu_bug(c, X86_BUG_ESPFIX); 1373 } while (0); 1374 # else 1375 set_cpu_bug(c, X86_BUG_ESPFIX); 1376 # endif 1377 #endif 1378 } 1379 1380 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1381 { 1382 /* 1383 * The heavy lifting of max_rmid and cache_occ_scale are handled 1384 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1385 * in case CQM bits really aren't there in this CPU. 1386 */ 1387 if (c != &boot_cpu_data) { 1388 boot_cpu_data.x86_cache_max_rmid = 1389 min(boot_cpu_data.x86_cache_max_rmid, 1390 c->x86_cache_max_rmid); 1391 } 1392 } 1393 1394 /* 1395 * Validate that ACPI/mptables have the same information about the 1396 * effective APIC id and update the package map. 1397 */ 1398 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1399 { 1400 #ifdef CONFIG_SMP 1401 unsigned int apicid, cpu = smp_processor_id(); 1402 1403 apicid = apic->cpu_present_to_apicid(cpu); 1404 1405 if (apicid != c->apicid) { 1406 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1407 cpu, apicid, c->initial_apicid); 1408 } 1409 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1410 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1411 #else 1412 c->logical_proc_id = 0; 1413 #endif 1414 } 1415 1416 /* 1417 * This does the hard work of actually picking apart the CPU stuff... 1418 */ 1419 static void identify_cpu(struct cpuinfo_x86 *c) 1420 { 1421 int i; 1422 1423 c->loops_per_jiffy = loops_per_jiffy; 1424 c->x86_cache_size = 0; 1425 c->x86_vendor = X86_VENDOR_UNKNOWN; 1426 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1427 c->x86_vendor_id[0] = '\0'; /* Unset */ 1428 c->x86_model_id[0] = '\0'; /* Unset */ 1429 c->x86_max_cores = 1; 1430 c->x86_coreid_bits = 0; 1431 c->cu_id = 0xff; 1432 #ifdef CONFIG_X86_64 1433 c->x86_clflush_size = 64; 1434 c->x86_phys_bits = 36; 1435 c->x86_virt_bits = 48; 1436 #else 1437 c->cpuid_level = -1; /* CPUID not detected */ 1438 c->x86_clflush_size = 32; 1439 c->x86_phys_bits = 32; 1440 c->x86_virt_bits = 32; 1441 #endif 1442 c->x86_cache_alignment = c->x86_clflush_size; 1443 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1444 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1445 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1446 #endif 1447 1448 generic_identify(c); 1449 1450 if (this_cpu->c_identify) 1451 this_cpu->c_identify(c); 1452 1453 /* Clear/Set all flags overridden by options, after probe */ 1454 apply_forced_caps(c); 1455 1456 #ifdef CONFIG_X86_64 1457 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1458 #endif 1459 1460 /* 1461 * Vendor-specific initialization. In this section we 1462 * canonicalize the feature flags, meaning if there are 1463 * features a certain CPU supports which CPUID doesn't 1464 * tell us, CPUID claiming incorrect flags, or other bugs, 1465 * we handle them here. 1466 * 1467 * At the end of this section, c->x86_capability better 1468 * indicate the features this CPU genuinely supports! 1469 */ 1470 if (this_cpu->c_init) 1471 this_cpu->c_init(c); 1472 1473 /* Disable the PN if appropriate */ 1474 squash_the_stupid_serial_number(c); 1475 1476 /* Set up SMEP/SMAP/UMIP */ 1477 setup_smep(c); 1478 setup_smap(c); 1479 setup_umip(c); 1480 1481 /* 1482 * The vendor-specific functions might have changed features. 1483 * Now we do "generic changes." 1484 */ 1485 1486 /* Filter out anything that depends on CPUID levels we don't have */ 1487 filter_cpuid_features(c, true); 1488 1489 /* If the model name is still unset, do table lookup. */ 1490 if (!c->x86_model_id[0]) { 1491 const char *p; 1492 p = table_lookup_model(c); 1493 if (p) 1494 strcpy(c->x86_model_id, p); 1495 else 1496 /* Last resort... */ 1497 sprintf(c->x86_model_id, "%02x/%02x", 1498 c->x86, c->x86_model); 1499 } 1500 1501 #ifdef CONFIG_X86_64 1502 detect_ht(c); 1503 #endif 1504 1505 x86_init_rdrand(c); 1506 x86_init_cache_qos(c); 1507 setup_pku(c); 1508 1509 /* 1510 * Clear/Set all flags overridden by options, need do it 1511 * before following smp all cpus cap AND. 1512 */ 1513 apply_forced_caps(c); 1514 1515 /* 1516 * On SMP, boot_cpu_data holds the common feature set between 1517 * all CPUs; so make sure that we indicate which features are 1518 * common between the CPUs. The first time this routine gets 1519 * executed, c == &boot_cpu_data. 1520 */ 1521 if (c != &boot_cpu_data) { 1522 /* AND the already accumulated flags with these */ 1523 for (i = 0; i < NCAPINTS; i++) 1524 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1525 1526 /* OR, i.e. replicate the bug flags */ 1527 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1528 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1529 } 1530 1531 /* Init Machine Check Exception if available. */ 1532 mcheck_cpu_init(c); 1533 1534 select_idle_routine(c); 1535 1536 #ifdef CONFIG_NUMA 1537 numa_add_cpu(smp_processor_id()); 1538 #endif 1539 } 1540 1541 /* 1542 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1543 * on 32-bit kernels: 1544 */ 1545 #ifdef CONFIG_X86_32 1546 void enable_sep_cpu(void) 1547 { 1548 struct tss_struct *tss; 1549 int cpu; 1550 1551 if (!boot_cpu_has(X86_FEATURE_SEP)) 1552 return; 1553 1554 cpu = get_cpu(); 1555 tss = &per_cpu(cpu_tss_rw, cpu); 1556 1557 /* 1558 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1559 * see the big comment in struct x86_hw_tss's definition. 1560 */ 1561 1562 tss->x86_tss.ss1 = __KERNEL_CS; 1563 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1564 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1565 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1566 1567 put_cpu(); 1568 } 1569 #endif 1570 1571 void __init identify_boot_cpu(void) 1572 { 1573 identify_cpu(&boot_cpu_data); 1574 #ifdef CONFIG_X86_32 1575 sysenter_setup(); 1576 enable_sep_cpu(); 1577 #endif 1578 cpu_detect_tlb(&boot_cpu_data); 1579 setup_cr_pinning(); 1580 1581 tsx_init(); 1582 } 1583 1584 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1585 { 1586 BUG_ON(c == &boot_cpu_data); 1587 identify_cpu(c); 1588 #ifdef CONFIG_X86_32 1589 enable_sep_cpu(); 1590 #endif 1591 mtrr_ap_init(); 1592 validate_apic_and_package_id(c); 1593 x86_spec_ctrl_setup_ap(); 1594 } 1595 1596 static __init int setup_noclflush(char *arg) 1597 { 1598 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1599 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1600 return 1; 1601 } 1602 __setup("noclflush", setup_noclflush); 1603 1604 void print_cpu_info(struct cpuinfo_x86 *c) 1605 { 1606 const char *vendor = NULL; 1607 1608 if (c->x86_vendor < X86_VENDOR_NUM) { 1609 vendor = this_cpu->c_vendor; 1610 } else { 1611 if (c->cpuid_level >= 0) 1612 vendor = c->x86_vendor_id; 1613 } 1614 1615 if (vendor && !strstr(c->x86_model_id, vendor)) 1616 pr_cont("%s ", vendor); 1617 1618 if (c->x86_model_id[0]) 1619 pr_cont("%s", c->x86_model_id); 1620 else 1621 pr_cont("%d86", c->x86); 1622 1623 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1624 1625 if (c->x86_stepping || c->cpuid_level >= 0) 1626 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1627 else 1628 pr_cont(")\n"); 1629 } 1630 1631 /* 1632 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1633 * But we need to keep a dummy __setup around otherwise it would 1634 * show up as an environment variable for init. 1635 */ 1636 static __init int setup_clearcpuid(char *arg) 1637 { 1638 return 1; 1639 } 1640 __setup("clearcpuid=", setup_clearcpuid); 1641 1642 #ifdef CONFIG_X86_64 1643 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1644 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1645 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1646 1647 /* 1648 * The following percpu variables are hot. Align current_task to 1649 * cacheline size such that they fall in the same cacheline. 1650 */ 1651 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1652 &init_task; 1653 EXPORT_PER_CPU_SYMBOL(current_task); 1654 1655 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1656 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1657 1658 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1659 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1660 1661 /* May not be marked __init: used by software suspend */ 1662 void syscall_init(void) 1663 { 1664 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1665 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1666 1667 #ifdef CONFIG_IA32_EMULATION 1668 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1669 /* 1670 * This only works on Intel CPUs. 1671 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1672 * This does not cause SYSENTER to jump to the wrong location, because 1673 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1674 */ 1675 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1676 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1677 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1678 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1679 #else 1680 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1681 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1682 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1683 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1684 #endif 1685 1686 /* Flags to clear on syscall */ 1687 wrmsrl(MSR_SYSCALL_MASK, 1688 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1689 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1690 } 1691 1692 DEFINE_PER_CPU(int, debug_stack_usage); 1693 DEFINE_PER_CPU(u32, debug_idt_ctr); 1694 1695 void debug_stack_set_zero(void) 1696 { 1697 this_cpu_inc(debug_idt_ctr); 1698 load_current_idt(); 1699 } 1700 NOKPROBE_SYMBOL(debug_stack_set_zero); 1701 1702 void debug_stack_reset(void) 1703 { 1704 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1705 return; 1706 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1707 load_current_idt(); 1708 } 1709 NOKPROBE_SYMBOL(debug_stack_reset); 1710 1711 #else /* CONFIG_X86_64 */ 1712 1713 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1714 EXPORT_PER_CPU_SYMBOL(current_task); 1715 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1716 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1717 1718 /* 1719 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1720 * the top of the kernel stack. Use an extra percpu variable to track the 1721 * top of the kernel stack directly. 1722 */ 1723 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1724 (unsigned long)&init_thread_union + THREAD_SIZE; 1725 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1726 1727 #ifdef CONFIG_STACKPROTECTOR 1728 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1729 #endif 1730 1731 #endif /* CONFIG_X86_64 */ 1732 1733 /* 1734 * Clear all 6 debug registers: 1735 */ 1736 static void clear_all_debug_regs(void) 1737 { 1738 int i; 1739 1740 for (i = 0; i < 8; i++) { 1741 /* Ignore db4, db5 */ 1742 if ((i == 4) || (i == 5)) 1743 continue; 1744 1745 set_debugreg(0, i); 1746 } 1747 } 1748 1749 #ifdef CONFIG_KGDB 1750 /* 1751 * Restore debug regs if using kgdbwait and you have a kernel debugger 1752 * connection established. 1753 */ 1754 static void dbg_restore_debug_regs(void) 1755 { 1756 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1757 arch_kgdb_ops.correct_hw_break(); 1758 } 1759 #else /* ! CONFIG_KGDB */ 1760 #define dbg_restore_debug_regs() 1761 #endif /* ! CONFIG_KGDB */ 1762 1763 static void wait_for_master_cpu(int cpu) 1764 { 1765 #ifdef CONFIG_SMP 1766 /* 1767 * wait for ACK from master CPU before continuing 1768 * with AP initialization 1769 */ 1770 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1771 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1772 cpu_relax(); 1773 #endif 1774 } 1775 1776 #ifdef CONFIG_X86_64 1777 static inline void setup_getcpu(int cpu) 1778 { 1779 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1780 struct desc_struct d = { }; 1781 1782 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1783 write_rdtscp_aux(cpudata); 1784 1785 /* Store CPU and node number in limit. */ 1786 d.limit0 = cpudata; 1787 d.limit1 = cpudata >> 16; 1788 1789 d.type = 5; /* RO data, expand down, accessed */ 1790 d.dpl = 3; /* Visible to user code */ 1791 d.s = 1; /* Not a system segment */ 1792 d.p = 1; /* Present */ 1793 d.d = 1; /* 32-bit */ 1794 1795 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1796 } 1797 1798 static inline void ucode_cpu_init(int cpu) 1799 { 1800 if (cpu) 1801 load_ucode_ap(); 1802 } 1803 1804 static inline void tss_setup_ist(struct tss_struct *tss) 1805 { 1806 /* Set up the per-CPU TSS IST stacks */ 1807 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1808 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1809 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1810 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1811 } 1812 1813 #else /* CONFIG_X86_64 */ 1814 1815 static inline void setup_getcpu(int cpu) { } 1816 1817 static inline void ucode_cpu_init(int cpu) 1818 { 1819 show_ucode_info_early(); 1820 } 1821 1822 static inline void tss_setup_ist(struct tss_struct *tss) { } 1823 1824 #endif /* !CONFIG_X86_64 */ 1825 1826 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 1827 { 1828 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 1829 1830 #ifdef CONFIG_X86_IOPL_IOPERM 1831 tss->io_bitmap.prev_max = 0; 1832 tss->io_bitmap.prev_sequence = 0; 1833 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 1834 /* 1835 * Invalidate the extra array entry past the end of the all 1836 * permission bitmap as required by the hardware. 1837 */ 1838 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 1839 #endif 1840 } 1841 1842 /* 1843 * cpu_init() initializes state that is per-CPU. Some data is already 1844 * initialized (naturally) in the bootstrap process, such as the GDT 1845 * and IDT. We reload them nevertheless, this function acts as a 1846 * 'CPU state barrier', nothing should get across. 1847 */ 1848 void cpu_init(void) 1849 { 1850 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1851 struct task_struct *cur = current; 1852 int cpu = raw_smp_processor_id(); 1853 1854 wait_for_master_cpu(cpu); 1855 1856 ucode_cpu_init(cpu); 1857 1858 #ifdef CONFIG_NUMA 1859 if (this_cpu_read(numa_node) == 0 && 1860 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1861 set_numa_node(early_cpu_to_node(cpu)); 1862 #endif 1863 setup_getcpu(cpu); 1864 1865 pr_debug("Initializing CPU#%d\n", cpu); 1866 1867 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 1868 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 1869 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1870 1871 /* 1872 * Initialize the per-CPU GDT with the boot GDT, 1873 * and set up the GDT descriptor: 1874 */ 1875 switch_to_new_gdt(cpu); 1876 load_current_idt(); 1877 1878 if (IS_ENABLED(CONFIG_X86_64)) { 1879 loadsegment(fs, 0); 1880 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1881 syscall_init(); 1882 1883 wrmsrl(MSR_FS_BASE, 0); 1884 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1885 barrier(); 1886 1887 x2apic_setup(); 1888 } 1889 1890 mmgrab(&init_mm); 1891 cur->active_mm = &init_mm; 1892 BUG_ON(cur->mm); 1893 initialize_tlbstate_and_flush(); 1894 enter_lazy_tlb(&init_mm, cur); 1895 1896 /* Initialize the TSS. */ 1897 tss_setup_ist(tss); 1898 tss_setup_io_bitmap(tss); 1899 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1900 1901 load_TR_desc(); 1902 /* 1903 * sp0 points to the entry trampoline stack regardless of what task 1904 * is running. 1905 */ 1906 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1907 1908 load_mm_ldt(&init_mm); 1909 1910 clear_all_debug_regs(); 1911 dbg_restore_debug_regs(); 1912 1913 doublefault_init_cpu_tss(); 1914 1915 fpu__init_cpu(); 1916 1917 if (is_uv_system()) 1918 uv_cpu_init(); 1919 1920 load_fixmap_gdt(cpu); 1921 } 1922 1923 /* 1924 * The microcode loader calls this upon late microcode load to recheck features, 1925 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1926 * hotplug lock. 1927 */ 1928 void microcode_check(void) 1929 { 1930 struct cpuinfo_x86 info; 1931 1932 perf_check_microcode(); 1933 1934 /* Reload CPUID max function as it might've changed. */ 1935 info.cpuid_level = cpuid_eax(0); 1936 1937 /* 1938 * Copy all capability leafs to pick up the synthetic ones so that 1939 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1940 * get overwritten in get_cpu_cap(). 1941 */ 1942 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1943 1944 get_cpu_cap(&info); 1945 1946 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1947 return; 1948 1949 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1950 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1951 } 1952 1953 /* 1954 * Invoked from core CPU hotplug code after hotplug operations 1955 */ 1956 void arch_smt_update(void) 1957 { 1958 /* Handle the speculative execution misfeatures */ 1959 cpu_bugs_smt_update(); 1960 /* Check whether IPI broadcasting can be enabled */ 1961 apic_smt_update(); 1962 } 1963