1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/mmu_context.h> 17 #include <asm/hypervisor.h> 18 #include <asm/processor.h> 19 #include <asm/sections.h> 20 #include <asm/topology.h> 21 #include <asm/cpumask.h> 22 #include <asm/pgtable.h> 23 #include <asm/atomic.h> 24 #include <asm/proto.h> 25 #include <asm/setup.h> 26 #include <asm/apic.h> 27 #include <asm/desc.h> 28 #include <asm/i387.h> 29 #include <asm/mtrr.h> 30 #include <asm/numa.h> 31 #include <asm/asm.h> 32 #include <asm/cpu.h> 33 #include <asm/mce.h> 34 #include <asm/msr.h> 35 #include <asm/pat.h> 36 #include <asm/smp.h> 37 38 #ifdef CONFIG_X86_LOCAL_APIC 39 #include <asm/uv/uv.h> 40 #endif 41 42 #include "cpu.h" 43 44 /* all of these masks are initialized in setup_cpu_local_masks() */ 45 cpumask_var_t cpu_initialized_mask; 46 cpumask_var_t cpu_callout_mask; 47 cpumask_var_t cpu_callin_mask; 48 49 /* representing cpus for which sibling maps can be computed */ 50 cpumask_var_t cpu_sibling_setup_mask; 51 52 /* correctly size the local cpu masks */ 53 void __init setup_cpu_local_masks(void) 54 { 55 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 56 alloc_bootmem_cpumask_var(&cpu_callin_mask); 57 alloc_bootmem_cpumask_var(&cpu_callout_mask); 58 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 59 } 60 61 static const struct cpu_dev *this_cpu __cpuinitdata; 62 63 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 64 #ifdef CONFIG_X86_64 65 /* 66 * We need valid kernel segments for data and code in long mode too 67 * IRET will check the segment types kkeil 2000/10/28 68 * Also sysret mandates a special GDT layout 69 * 70 * TLS descriptors are currently at a different place compared to i386. 71 * Hopefully nobody expects them at a fixed place (Wine?) 72 */ 73 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, 74 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, 75 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, 76 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, 77 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, 78 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, 79 #else 80 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 81 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 82 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 83 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 84 /* 85 * Segments used for calling PnP BIOS have byte granularity. 86 * They code segments and data segments have fixed 64k limits, 87 * the transfer segment sizes are set at run time. 88 */ 89 /* 32-bit code */ 90 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 91 /* 16-bit code */ 92 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 93 /* 16-bit data */ 94 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 95 /* 16-bit data */ 96 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 97 /* 16-bit data */ 98 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 99 /* 100 * The APM segments have byte granularity and their bases 101 * are set at run time. All have 64k limits. 102 */ 103 /* 32-bit code */ 104 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 105 /* 16-bit code */ 106 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 107 /* data */ 108 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 109 110 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, 111 [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, 112 GDT_STACK_CANARY_INIT 113 #endif 114 } }; 115 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 116 117 #ifdef CONFIG_X86_32 118 static int cachesize_override __cpuinitdata = -1; 119 static int disable_x86_serial_nr __cpuinitdata = 1; 120 121 static int __init cachesize_setup(char *str) 122 { 123 get_option(&str, &cachesize_override); 124 return 1; 125 } 126 __setup("cachesize=", cachesize_setup); 127 128 static int __init x86_fxsr_setup(char *s) 129 { 130 setup_clear_cpu_cap(X86_FEATURE_FXSR); 131 setup_clear_cpu_cap(X86_FEATURE_XMM); 132 return 1; 133 } 134 __setup("nofxsr", x86_fxsr_setup); 135 136 static int __init x86_sep_setup(char *s) 137 { 138 setup_clear_cpu_cap(X86_FEATURE_SEP); 139 return 1; 140 } 141 __setup("nosep", x86_sep_setup); 142 143 /* Standard macro to see if a specific flag is changeable */ 144 static inline int flag_is_changeable_p(u32 flag) 145 { 146 u32 f1, f2; 147 148 /* 149 * Cyrix and IDT cpus allow disabling of CPUID 150 * so the code below may return different results 151 * when it is executed before and after enabling 152 * the CPUID. Add "volatile" to not allow gcc to 153 * optimize the subsequent calls to this function. 154 */ 155 asm volatile ("pushfl \n\t" 156 "pushfl \n\t" 157 "popl %0 \n\t" 158 "movl %0, %1 \n\t" 159 "xorl %2, %0 \n\t" 160 "pushl %0 \n\t" 161 "popfl \n\t" 162 "pushfl \n\t" 163 "popl %0 \n\t" 164 "popfl \n\t" 165 166 : "=&r" (f1), "=&r" (f2) 167 : "ir" (flag)); 168 169 return ((f1^f2) & flag) != 0; 170 } 171 172 /* Probe for the CPUID instruction */ 173 static int __cpuinit have_cpuid_p(void) 174 { 175 return flag_is_changeable_p(X86_EFLAGS_ID); 176 } 177 178 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 179 { 180 unsigned long lo, hi; 181 182 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 183 return; 184 185 /* Disable processor serial number: */ 186 187 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 188 lo |= 0x200000; 189 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 190 191 printk(KERN_NOTICE "CPU serial number disabled.\n"); 192 clear_cpu_cap(c, X86_FEATURE_PN); 193 194 /* Disabling the serial number may affect the cpuid level */ 195 c->cpuid_level = cpuid_eax(0); 196 } 197 198 static int __init x86_serial_nr_setup(char *s) 199 { 200 disable_x86_serial_nr = 0; 201 return 1; 202 } 203 __setup("serialnumber", x86_serial_nr_setup); 204 #else 205 static inline int flag_is_changeable_p(u32 flag) 206 { 207 return 1; 208 } 209 /* Probe for the CPUID instruction */ 210 static inline int have_cpuid_p(void) 211 { 212 return 1; 213 } 214 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 215 { 216 } 217 #endif 218 219 /* 220 * Some CPU features depend on higher CPUID levels, which may not always 221 * be available due to CPUID level capping or broken virtualization 222 * software. Add those features to this table to auto-disable them. 223 */ 224 struct cpuid_dependent_feature { 225 u32 feature; 226 u32 level; 227 }; 228 229 static const struct cpuid_dependent_feature __cpuinitconst 230 cpuid_dependent_features[] = { 231 { X86_FEATURE_MWAIT, 0x00000005 }, 232 { X86_FEATURE_DCA, 0x00000009 }, 233 { X86_FEATURE_XSAVE, 0x0000000d }, 234 { 0, 0 } 235 }; 236 237 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 238 { 239 const struct cpuid_dependent_feature *df; 240 241 for (df = cpuid_dependent_features; df->feature; df++) { 242 243 if (!cpu_has(c, df->feature)) 244 continue; 245 /* 246 * Note: cpuid_level is set to -1 if unavailable, but 247 * extended_extended_level is set to 0 if unavailable 248 * and the legitimate extended levels are all negative 249 * when signed; hence the weird messing around with 250 * signs here... 251 */ 252 if (!((s32)df->level < 0 ? 253 (u32)df->level > (u32)c->extended_cpuid_level : 254 (s32)df->level > (s32)c->cpuid_level)) 255 continue; 256 257 clear_cpu_cap(c, df->feature); 258 if (!warn) 259 continue; 260 261 printk(KERN_WARNING 262 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 263 x86_cap_flags[df->feature], df->level); 264 } 265 } 266 267 /* 268 * Naming convention should be: <Name> [(<Codename>)] 269 * This table only is used unless init_<vendor>() below doesn't set it; 270 * in particular, if CPUID levels 0x80000002..4 are supported, this 271 * isn't used 272 */ 273 274 /* Look up CPU names by table lookup. */ 275 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 276 { 277 const struct cpu_model_info *info; 278 279 if (c->x86_model >= 16) 280 return NULL; /* Range check */ 281 282 if (!this_cpu) 283 return NULL; 284 285 info = this_cpu->c_models; 286 287 while (info && info->family) { 288 if (info->family == c->x86) 289 return info->model_names[c->x86_model]; 290 info++; 291 } 292 return NULL; /* Not found */ 293 } 294 295 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; 296 297 void load_percpu_segment(int cpu) 298 { 299 #ifdef CONFIG_X86_32 300 loadsegment(fs, __KERNEL_PERCPU); 301 #else 302 loadsegment(gs, 0); 303 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 304 #endif 305 load_stack_canary_segment(); 306 } 307 308 /* 309 * Current gdt points %fs at the "master" per-cpu area: after this, 310 * it's on the real one. 311 */ 312 void switch_to_new_gdt(int cpu) 313 { 314 struct desc_ptr gdt_descr; 315 316 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 317 gdt_descr.size = GDT_SIZE - 1; 318 load_gdt(&gdt_descr); 319 /* Reload the per-cpu base */ 320 321 load_percpu_segment(cpu); 322 } 323 324 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 325 326 static void __cpuinit default_init(struct cpuinfo_x86 *c) 327 { 328 #ifdef CONFIG_X86_64 329 display_cacheinfo(c); 330 #else 331 /* Not much we can do here... */ 332 /* Check if at least it has cpuid */ 333 if (c->cpuid_level == -1) { 334 /* No cpuid. It must be an ancient CPU */ 335 if (c->x86 == 4) 336 strcpy(c->x86_model_id, "486"); 337 else if (c->x86 == 3) 338 strcpy(c->x86_model_id, "386"); 339 } 340 #endif 341 } 342 343 static const struct cpu_dev __cpuinitconst default_cpu = { 344 .c_init = default_init, 345 .c_vendor = "Unknown", 346 .c_x86_vendor = X86_VENDOR_UNKNOWN, 347 }; 348 349 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 350 { 351 unsigned int *v; 352 char *p, *q; 353 354 if (c->extended_cpuid_level < 0x80000004) 355 return; 356 357 v = (unsigned int *)c->x86_model_id; 358 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 359 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 360 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 361 c->x86_model_id[48] = 0; 362 363 /* 364 * Intel chips right-justify this string for some dumb reason; 365 * undo that brain damage: 366 */ 367 p = q = &c->x86_model_id[0]; 368 while (*p == ' ') 369 p++; 370 if (p != q) { 371 while (*p) 372 *q++ = *p++; 373 while (q <= &c->x86_model_id[48]) 374 *q++ = '\0'; /* Zero-pad the rest */ 375 } 376 } 377 378 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 379 { 380 unsigned int n, dummy, ebx, ecx, edx, l2size; 381 382 n = c->extended_cpuid_level; 383 384 if (n >= 0x80000005) { 385 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 386 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 387 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 388 c->x86_cache_size = (ecx>>24) + (edx>>24); 389 #ifdef CONFIG_X86_64 390 /* On K8 L1 TLB is inclusive, so don't count it */ 391 c->x86_tlbsize = 0; 392 #endif 393 } 394 395 if (n < 0x80000006) /* Some chips just has a large L1. */ 396 return; 397 398 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 399 l2size = ecx >> 16; 400 401 #ifdef CONFIG_X86_64 402 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 403 #else 404 /* do processor-specific cache resizing */ 405 if (this_cpu->c_size_cache) 406 l2size = this_cpu->c_size_cache(c, l2size); 407 408 /* Allow user to override all this if necessary. */ 409 if (cachesize_override != -1) 410 l2size = cachesize_override; 411 412 if (l2size == 0) 413 return; /* Again, no L2 cache is possible */ 414 #endif 415 416 c->x86_cache_size = l2size; 417 418 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 419 l2size, ecx & 0xFF); 420 } 421 422 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 423 { 424 #ifdef CONFIG_X86_HT 425 u32 eax, ebx, ecx, edx; 426 int index_msb, core_bits; 427 428 if (!cpu_has(c, X86_FEATURE_HT)) 429 return; 430 431 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 432 goto out; 433 434 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 435 return; 436 437 cpuid(1, &eax, &ebx, &ecx, &edx); 438 439 smp_num_siblings = (ebx & 0xff0000) >> 16; 440 441 if (smp_num_siblings == 1) { 442 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 443 goto out; 444 } 445 446 if (smp_num_siblings <= 1) 447 goto out; 448 449 if (smp_num_siblings > nr_cpu_ids) { 450 pr_warning("CPU: Unsupported number of siblings %d", 451 smp_num_siblings); 452 smp_num_siblings = 1; 453 return; 454 } 455 456 index_msb = get_count_order(smp_num_siblings); 457 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 458 459 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 460 461 index_msb = get_count_order(smp_num_siblings); 462 463 core_bits = get_count_order(c->x86_max_cores); 464 465 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 466 ((1 << core_bits) - 1); 467 468 out: 469 if ((c->x86_max_cores * smp_num_siblings) > 1) { 470 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 471 c->phys_proc_id); 472 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 473 c->cpu_core_id); 474 } 475 #endif 476 } 477 478 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 479 { 480 char *v = c->x86_vendor_id; 481 static int printed; 482 int i; 483 484 for (i = 0; i < X86_VENDOR_NUM; i++) { 485 if (!cpu_devs[i]) 486 break; 487 488 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 489 (cpu_devs[i]->c_ident[1] && 490 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 491 492 this_cpu = cpu_devs[i]; 493 c->x86_vendor = this_cpu->c_x86_vendor; 494 return; 495 } 496 } 497 498 if (!printed) { 499 printed++; 500 printk(KERN_ERR 501 "CPU: vendor_id '%s' unknown, using generic init.\n", v); 502 503 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 504 } 505 506 c->x86_vendor = X86_VENDOR_UNKNOWN; 507 this_cpu = &default_cpu; 508 } 509 510 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 511 { 512 /* Get vendor name */ 513 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 514 (unsigned int *)&c->x86_vendor_id[0], 515 (unsigned int *)&c->x86_vendor_id[8], 516 (unsigned int *)&c->x86_vendor_id[4]); 517 518 c->x86 = 4; 519 /* Intel-defined flags: level 0x00000001 */ 520 if (c->cpuid_level >= 0x00000001) { 521 u32 junk, tfms, cap0, misc; 522 523 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 524 c->x86 = (tfms >> 8) & 0xf; 525 c->x86_model = (tfms >> 4) & 0xf; 526 c->x86_mask = tfms & 0xf; 527 528 if (c->x86 == 0xf) 529 c->x86 += (tfms >> 20) & 0xff; 530 if (c->x86 >= 0x6) 531 c->x86_model += ((tfms >> 16) & 0xf) << 4; 532 533 if (cap0 & (1<<19)) { 534 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 535 c->x86_cache_alignment = c->x86_clflush_size; 536 } 537 } 538 } 539 540 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 541 { 542 u32 tfms, xlvl; 543 u32 ebx; 544 545 /* Intel-defined flags: level 0x00000001 */ 546 if (c->cpuid_level >= 0x00000001) { 547 u32 capability, excap; 548 549 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 550 c->x86_capability[0] = capability; 551 c->x86_capability[4] = excap; 552 } 553 554 /* AMD-defined flags: level 0x80000001 */ 555 xlvl = cpuid_eax(0x80000000); 556 c->extended_cpuid_level = xlvl; 557 558 if ((xlvl & 0xffff0000) == 0x80000000) { 559 if (xlvl >= 0x80000001) { 560 c->x86_capability[1] = cpuid_edx(0x80000001); 561 c->x86_capability[6] = cpuid_ecx(0x80000001); 562 } 563 } 564 565 if (c->extended_cpuid_level >= 0x80000008) { 566 u32 eax = cpuid_eax(0x80000008); 567 568 c->x86_virt_bits = (eax >> 8) & 0xff; 569 c->x86_phys_bits = eax & 0xff; 570 } 571 #ifdef CONFIG_X86_32 572 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 573 c->x86_phys_bits = 36; 574 #endif 575 576 if (c->extended_cpuid_level >= 0x80000007) 577 c->x86_power = cpuid_edx(0x80000007); 578 579 } 580 581 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 582 { 583 #ifdef CONFIG_X86_32 584 int i; 585 586 /* 587 * First of all, decide if this is a 486 or higher 588 * It's a 486 if we can modify the AC flag 589 */ 590 if (flag_is_changeable_p(X86_EFLAGS_AC)) 591 c->x86 = 4; 592 else 593 c->x86 = 3; 594 595 for (i = 0; i < X86_VENDOR_NUM; i++) 596 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 597 c->x86_vendor_id[0] = 0; 598 cpu_devs[i]->c_identify(c); 599 if (c->x86_vendor_id[0]) { 600 get_cpu_vendor(c); 601 break; 602 } 603 } 604 #endif 605 } 606 607 /* 608 * Do minimum CPU detection early. 609 * Fields really needed: vendor, cpuid_level, family, model, mask, 610 * cache alignment. 611 * The others are not touched to avoid unwanted side effects. 612 * 613 * WARNING: this function is only called on the BP. Don't add code here 614 * that is supposed to run on all CPUs. 615 */ 616 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 617 { 618 #ifdef CONFIG_X86_64 619 c->x86_clflush_size = 64; 620 c->x86_phys_bits = 36; 621 c->x86_virt_bits = 48; 622 #else 623 c->x86_clflush_size = 32; 624 c->x86_phys_bits = 32; 625 c->x86_virt_bits = 32; 626 #endif 627 c->x86_cache_alignment = c->x86_clflush_size; 628 629 memset(&c->x86_capability, 0, sizeof c->x86_capability); 630 c->extended_cpuid_level = 0; 631 632 if (!have_cpuid_p()) 633 identify_cpu_without_cpuid(c); 634 635 /* cyrix could have cpuid enabled via c_identify()*/ 636 if (!have_cpuid_p()) 637 return; 638 639 cpu_detect(c); 640 641 get_cpu_vendor(c); 642 643 get_cpu_cap(c); 644 645 if (this_cpu->c_early_init) 646 this_cpu->c_early_init(c); 647 648 #ifdef CONFIG_SMP 649 c->cpu_index = boot_cpu_id; 650 #endif 651 filter_cpuid_features(c, false); 652 } 653 654 void __init early_cpu_init(void) 655 { 656 const struct cpu_dev *const *cdev; 657 int count = 0; 658 659 printk(KERN_INFO "KERNEL supported cpus:\n"); 660 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 661 const struct cpu_dev *cpudev = *cdev; 662 unsigned int j; 663 664 if (count >= X86_VENDOR_NUM) 665 break; 666 cpu_devs[count] = cpudev; 667 count++; 668 669 for (j = 0; j < 2; j++) { 670 if (!cpudev->c_ident[j]) 671 continue; 672 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 673 cpudev->c_ident[j]); 674 } 675 } 676 677 early_identify_cpu(&boot_cpu_data); 678 } 679 680 /* 681 * The NOPL instruction is supposed to exist on all CPUs with 682 * family >= 6; unfortunately, that's not true in practice because 683 * of early VIA chips and (more importantly) broken virtualizers that 684 * are not easy to detect. In the latter case it doesn't even *fail* 685 * reliably, so probing for it doesn't even work. Disable it completely 686 * unless we can find a reliable way to detect all the broken cases. 687 */ 688 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 689 { 690 clear_cpu_cap(c, X86_FEATURE_NOPL); 691 } 692 693 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 694 { 695 c->extended_cpuid_level = 0; 696 697 if (!have_cpuid_p()) 698 identify_cpu_without_cpuid(c); 699 700 /* cyrix could have cpuid enabled via c_identify()*/ 701 if (!have_cpuid_p()) 702 return; 703 704 cpu_detect(c); 705 706 get_cpu_vendor(c); 707 708 get_cpu_cap(c); 709 710 if (c->cpuid_level >= 0x00000001) { 711 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 712 #ifdef CONFIG_X86_32 713 # ifdef CONFIG_X86_HT 714 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 715 # else 716 c->apicid = c->initial_apicid; 717 # endif 718 #endif 719 720 #ifdef CONFIG_X86_HT 721 c->phys_proc_id = c->initial_apicid; 722 #endif 723 } 724 725 get_model_name(c); /* Default name */ 726 727 init_scattered_cpuid_features(c); 728 detect_nopl(c); 729 } 730 731 /* 732 * This does the hard work of actually picking apart the CPU stuff... 733 */ 734 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 735 { 736 int i; 737 738 c->loops_per_jiffy = loops_per_jiffy; 739 c->x86_cache_size = -1; 740 c->x86_vendor = X86_VENDOR_UNKNOWN; 741 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 742 c->x86_vendor_id[0] = '\0'; /* Unset */ 743 c->x86_model_id[0] = '\0'; /* Unset */ 744 c->x86_max_cores = 1; 745 c->x86_coreid_bits = 0; 746 #ifdef CONFIG_X86_64 747 c->x86_clflush_size = 64; 748 c->x86_phys_bits = 36; 749 c->x86_virt_bits = 48; 750 #else 751 c->cpuid_level = -1; /* CPUID not detected */ 752 c->x86_clflush_size = 32; 753 c->x86_phys_bits = 32; 754 c->x86_virt_bits = 32; 755 #endif 756 c->x86_cache_alignment = c->x86_clflush_size; 757 memset(&c->x86_capability, 0, sizeof c->x86_capability); 758 759 generic_identify(c); 760 761 if (this_cpu->c_identify) 762 this_cpu->c_identify(c); 763 764 #ifdef CONFIG_X86_64 765 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 766 #endif 767 768 /* 769 * Vendor-specific initialization. In this section we 770 * canonicalize the feature flags, meaning if there are 771 * features a certain CPU supports which CPUID doesn't 772 * tell us, CPUID claiming incorrect flags, or other bugs, 773 * we handle them here. 774 * 775 * At the end of this section, c->x86_capability better 776 * indicate the features this CPU genuinely supports! 777 */ 778 if (this_cpu->c_init) 779 this_cpu->c_init(c); 780 781 /* Disable the PN if appropriate */ 782 squash_the_stupid_serial_number(c); 783 784 /* 785 * The vendor-specific functions might have changed features. 786 * Now we do "generic changes." 787 */ 788 789 /* Filter out anything that depends on CPUID levels we don't have */ 790 filter_cpuid_features(c, true); 791 792 /* If the model name is still unset, do table lookup. */ 793 if (!c->x86_model_id[0]) { 794 const char *p; 795 p = table_lookup_model(c); 796 if (p) 797 strcpy(c->x86_model_id, p); 798 else 799 /* Last resort... */ 800 sprintf(c->x86_model_id, "%02x/%02x", 801 c->x86, c->x86_model); 802 } 803 804 #ifdef CONFIG_X86_64 805 detect_ht(c); 806 #endif 807 808 init_hypervisor(c); 809 /* 810 * On SMP, boot_cpu_data holds the common feature set between 811 * all CPUs; so make sure that we indicate which features are 812 * common between the CPUs. The first time this routine gets 813 * executed, c == &boot_cpu_data. 814 */ 815 if (c != &boot_cpu_data) { 816 /* AND the already accumulated flags with these */ 817 for (i = 0; i < NCAPINTS; i++) 818 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 819 } 820 821 /* Clear all flags overriden by options */ 822 for (i = 0; i < NCAPINTS; i++) 823 c->x86_capability[i] &= ~cleared_cpu_caps[i]; 824 825 #ifdef CONFIG_X86_MCE 826 /* Init Machine Check Exception if available. */ 827 mcheck_init(c); 828 #endif 829 830 select_idle_routine(c); 831 832 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 833 numa_add_cpu(smp_processor_id()); 834 #endif 835 } 836 837 #ifdef CONFIG_X86_64 838 static void vgetcpu_set_mode(void) 839 { 840 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 841 vgetcpu_mode = VGETCPU_RDTSCP; 842 else 843 vgetcpu_mode = VGETCPU_LSL; 844 } 845 #endif 846 847 void __init identify_boot_cpu(void) 848 { 849 identify_cpu(&boot_cpu_data); 850 init_c1e_mask(); 851 #ifdef CONFIG_X86_32 852 sysenter_setup(); 853 enable_sep_cpu(); 854 #else 855 vgetcpu_set_mode(); 856 #endif 857 } 858 859 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 860 { 861 BUG_ON(c == &boot_cpu_data); 862 identify_cpu(c); 863 #ifdef CONFIG_X86_32 864 enable_sep_cpu(); 865 #endif 866 mtrr_ap_init(); 867 } 868 869 struct msr_range { 870 unsigned min; 871 unsigned max; 872 }; 873 874 static const struct msr_range msr_range_array[] __cpuinitconst = { 875 { 0x00000000, 0x00000418}, 876 { 0xc0000000, 0xc000040b}, 877 { 0xc0010000, 0xc0010142}, 878 { 0xc0011000, 0xc001103b}, 879 }; 880 881 static void __cpuinit print_cpu_msr(void) 882 { 883 unsigned index_min, index_max; 884 unsigned index; 885 u64 val; 886 int i; 887 888 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 889 index_min = msr_range_array[i].min; 890 index_max = msr_range_array[i].max; 891 892 for (index = index_min; index < index_max; index++) { 893 if (rdmsrl_amd_safe(index, &val)) 894 continue; 895 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 896 } 897 } 898 } 899 900 static int show_msr __cpuinitdata; 901 902 static __init int setup_show_msr(char *arg) 903 { 904 int num; 905 906 get_option(&arg, &num); 907 908 if (num > 0) 909 show_msr = num; 910 return 1; 911 } 912 __setup("show_msr=", setup_show_msr); 913 914 static __init int setup_noclflush(char *arg) 915 { 916 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 917 return 1; 918 } 919 __setup("noclflush", setup_noclflush); 920 921 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 922 { 923 const char *vendor = NULL; 924 925 if (c->x86_vendor < X86_VENDOR_NUM) { 926 vendor = this_cpu->c_vendor; 927 } else { 928 if (c->cpuid_level >= 0) 929 vendor = c->x86_vendor_id; 930 } 931 932 if (vendor && !strstr(c->x86_model_id, vendor)) 933 printk(KERN_CONT "%s ", vendor); 934 935 if (c->x86_model_id[0]) 936 printk(KERN_CONT "%s", c->x86_model_id); 937 else 938 printk(KERN_CONT "%d86", c->x86); 939 940 if (c->x86_mask || c->cpuid_level >= 0) 941 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 942 else 943 printk(KERN_CONT "\n"); 944 945 #ifdef CONFIG_SMP 946 if (c->cpu_index < show_msr) 947 print_cpu_msr(); 948 #else 949 if (show_msr) 950 print_cpu_msr(); 951 #endif 952 } 953 954 static __init int setup_disablecpuid(char *arg) 955 { 956 int bit; 957 958 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 959 setup_clear_cpu_cap(bit); 960 else 961 return 0; 962 963 return 1; 964 } 965 __setup("clearcpuid=", setup_disablecpuid); 966 967 #ifdef CONFIG_X86_64 968 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; 969 970 DEFINE_PER_CPU_FIRST(union irq_stack_union, 971 irq_stack_union) __aligned(PAGE_SIZE); 972 973 DEFINE_PER_CPU(char *, irq_stack_ptr) = 974 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 975 976 DEFINE_PER_CPU(unsigned long, kernel_stack) = 977 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 978 EXPORT_PER_CPU_SYMBOL(kernel_stack); 979 980 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 981 982 /* 983 * Special IST stacks which the CPU switches to when it calls 984 * an IST-marked descriptor entry. Up to 7 stacks (hardware 985 * limit), all of them are 4K, except the debug stack which 986 * is 8K. 987 */ 988 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 989 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 990 [DEBUG_STACK - 1] = DEBUG_STKSZ 991 }; 992 993 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 994 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) 995 __aligned(PAGE_SIZE); 996 997 /* May not be marked __init: used by software suspend */ 998 void syscall_init(void) 999 { 1000 /* 1001 * LSTAR and STAR live in a bit strange symbiosis. 1002 * They both write to the same internal register. STAR allows to 1003 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1004 */ 1005 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1006 wrmsrl(MSR_LSTAR, system_call); 1007 wrmsrl(MSR_CSTAR, ignore_sysret); 1008 1009 #ifdef CONFIG_IA32_EMULATION 1010 syscall32_cpu_init(); 1011 #endif 1012 1013 /* Flags to clear on syscall */ 1014 wrmsrl(MSR_SYSCALL_MASK, 1015 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 1016 } 1017 1018 unsigned long kernel_eflags; 1019 1020 /* 1021 * Copies of the original ist values from the tss are only accessed during 1022 * debugging, no special alignment required. 1023 */ 1024 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1025 1026 #else /* CONFIG_X86_64 */ 1027 1028 #ifdef CONFIG_CC_STACKPROTECTOR 1029 DEFINE_PER_CPU(unsigned long, stack_canary); 1030 #endif 1031 1032 /* Make sure %fs and %gs are initialized properly in idle threads */ 1033 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 1034 { 1035 memset(regs, 0, sizeof(struct pt_regs)); 1036 regs->fs = __KERNEL_PERCPU; 1037 regs->gs = __KERNEL_STACK_CANARY; 1038 1039 return regs; 1040 } 1041 #endif /* CONFIG_X86_64 */ 1042 1043 /* 1044 * Clear all 6 debug registers: 1045 */ 1046 static void clear_all_debug_regs(void) 1047 { 1048 int i; 1049 1050 for (i = 0; i < 8; i++) { 1051 /* Ignore db4, db5 */ 1052 if ((i == 4) || (i == 5)) 1053 continue; 1054 1055 set_debugreg(0, i); 1056 } 1057 } 1058 1059 /* 1060 * cpu_init() initializes state that is per-CPU. Some data is already 1061 * initialized (naturally) in the bootstrap process, such as the GDT 1062 * and IDT. We reload them nevertheless, this function acts as a 1063 * 'CPU state barrier', nothing should get across. 1064 * A lot of state is already set up in PDA init for 64 bit 1065 */ 1066 #ifdef CONFIG_X86_64 1067 1068 void __cpuinit cpu_init(void) 1069 { 1070 struct orig_ist *orig_ist; 1071 struct task_struct *me; 1072 struct tss_struct *t; 1073 unsigned long v; 1074 int cpu; 1075 int i; 1076 1077 cpu = stack_smp_processor_id(); 1078 t = &per_cpu(init_tss, cpu); 1079 orig_ist = &per_cpu(orig_ist, cpu); 1080 1081 #ifdef CONFIG_NUMA 1082 if (cpu != 0 && percpu_read(node_number) == 0 && 1083 cpu_to_node(cpu) != NUMA_NO_NODE) 1084 percpu_write(node_number, cpu_to_node(cpu)); 1085 #endif 1086 1087 me = current; 1088 1089 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1090 panic("CPU#%d already initialized!\n", cpu); 1091 1092 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1093 1094 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1095 1096 /* 1097 * Initialize the per-CPU GDT with the boot GDT, 1098 * and set up the GDT descriptor: 1099 */ 1100 1101 switch_to_new_gdt(cpu); 1102 loadsegment(fs, 0); 1103 1104 load_idt((const struct desc_ptr *)&idt_descr); 1105 1106 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1107 syscall_init(); 1108 1109 wrmsrl(MSR_FS_BASE, 0); 1110 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1111 barrier(); 1112 1113 check_efer(); 1114 if (cpu != 0) 1115 enable_x2apic(); 1116 1117 /* 1118 * set up and load the per-CPU TSS 1119 */ 1120 if (!orig_ist->ist[0]) { 1121 char *estacks = per_cpu(exception_stacks, cpu); 1122 1123 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1124 estacks += exception_stack_sizes[v]; 1125 orig_ist->ist[v] = t->x86_tss.ist[v] = 1126 (unsigned long)estacks; 1127 } 1128 } 1129 1130 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1131 1132 /* 1133 * <= is required because the CPU will access up to 1134 * 8 bits beyond the end of the IO permission bitmap. 1135 */ 1136 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1137 t->io_bitmap[i] = ~0UL; 1138 1139 atomic_inc(&init_mm.mm_count); 1140 me->active_mm = &init_mm; 1141 BUG_ON(me->mm); 1142 enter_lazy_tlb(&init_mm, me); 1143 1144 load_sp0(t, ¤t->thread); 1145 set_tss_desc(cpu, t); 1146 load_TR_desc(); 1147 load_LDT(&init_mm.context); 1148 1149 #ifdef CONFIG_KGDB 1150 /* 1151 * If the kgdb is connected no debug regs should be altered. This 1152 * is only applicable when KGDB and a KGDB I/O module are built 1153 * into the kernel and you are using early debugging with 1154 * kgdbwait. KGDB will control the kernel HW breakpoint registers. 1155 */ 1156 if (kgdb_connected && arch_kgdb_ops.correct_hw_break) 1157 arch_kgdb_ops.correct_hw_break(); 1158 else 1159 #endif 1160 clear_all_debug_regs(); 1161 1162 fpu_init(); 1163 1164 raw_local_save_flags(kernel_eflags); 1165 1166 if (is_uv_system()) 1167 uv_cpu_init(); 1168 } 1169 1170 #else 1171 1172 void __cpuinit cpu_init(void) 1173 { 1174 int cpu = smp_processor_id(); 1175 struct task_struct *curr = current; 1176 struct tss_struct *t = &per_cpu(init_tss, cpu); 1177 struct thread_struct *thread = &curr->thread; 1178 1179 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1180 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1181 for (;;) 1182 local_irq_enable(); 1183 } 1184 1185 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1186 1187 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1188 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1189 1190 load_idt(&idt_descr); 1191 switch_to_new_gdt(cpu); 1192 1193 /* 1194 * Set up and load the per-CPU TSS and LDT 1195 */ 1196 atomic_inc(&init_mm.mm_count); 1197 curr->active_mm = &init_mm; 1198 BUG_ON(curr->mm); 1199 enter_lazy_tlb(&init_mm, curr); 1200 1201 load_sp0(t, thread); 1202 set_tss_desc(cpu, t); 1203 load_TR_desc(); 1204 load_LDT(&init_mm.context); 1205 1206 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1207 1208 #ifdef CONFIG_DOUBLEFAULT 1209 /* Set up doublefault TSS pointer in the GDT */ 1210 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1211 #endif 1212 1213 clear_all_debug_regs(); 1214 1215 /* 1216 * Force FPU initialization: 1217 */ 1218 if (cpu_has_xsave) 1219 current_thread_info()->status = TS_XSAVE; 1220 else 1221 current_thread_info()->status = 0; 1222 clear_used_math(); 1223 mxcsr_feature_mask_init(); 1224 1225 /* 1226 * Boot processor to setup the FP and extended state context info. 1227 */ 1228 if (smp_processor_id() == boot_cpu_id) 1229 init_thread_xstate(); 1230 1231 xsave_init(); 1232 } 1233 #endif 1234