1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 26 #include <asm/cmdline.h> 27 #include <asm/stackprotector.h> 28 #include <asm/perf_event.h> 29 #include <asm/mmu_context.h> 30 #include <asm/doublefault.h> 31 #include <asm/archrandom.h> 32 #include <asm/hypervisor.h> 33 #include <asm/processor.h> 34 #include <asm/tlbflush.h> 35 #include <asm/debugreg.h> 36 #include <asm/sections.h> 37 #include <asm/vsyscall.h> 38 #include <linux/topology.h> 39 #include <linux/cpumask.h> 40 #include <linux/atomic.h> 41 #include <asm/proto.h> 42 #include <asm/setup.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/fpu/internal.h> 46 #include <asm/mtrr.h> 47 #include <asm/hwcap2.h> 48 #include <linux/numa.h> 49 #include <asm/numa.h> 50 #include <asm/asm.h> 51 #include <asm/bugs.h> 52 #include <asm/cpu.h> 53 #include <asm/mce.h> 54 #include <asm/msr.h> 55 #include <asm/memtype.h> 56 #include <asm/microcode.h> 57 #include <asm/microcode_intel.h> 58 #include <asm/intel-family.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/uv/uv.h> 61 #include <asm/sigframe.h> 62 63 #include "cpu.h" 64 65 u32 elf_hwcap2 __read_mostly; 66 67 /* all of these masks are initialized in setup_cpu_local_masks() */ 68 cpumask_var_t cpu_initialized_mask; 69 cpumask_var_t cpu_callout_mask; 70 cpumask_var_t cpu_callin_mask; 71 72 /* representing cpus for which sibling maps can be computed */ 73 cpumask_var_t cpu_sibling_setup_mask; 74 75 /* Number of siblings per CPU package */ 76 int smp_num_siblings = 1; 77 EXPORT_SYMBOL(smp_num_siblings); 78 79 /* Last level cache ID of each logical CPU */ 80 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 81 82 /* correctly size the local cpu masks */ 83 void __init setup_cpu_local_masks(void) 84 { 85 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 86 alloc_bootmem_cpumask_var(&cpu_callin_mask); 87 alloc_bootmem_cpumask_var(&cpu_callout_mask); 88 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 89 } 90 91 static void default_init(struct cpuinfo_x86 *c) 92 { 93 #ifdef CONFIG_X86_64 94 cpu_detect_cache_sizes(c); 95 #else 96 /* Not much we can do here... */ 97 /* Check if at least it has cpuid */ 98 if (c->cpuid_level == -1) { 99 /* No cpuid. It must be an ancient CPU */ 100 if (c->x86 == 4) 101 strcpy(c->x86_model_id, "486"); 102 else if (c->x86 == 3) 103 strcpy(c->x86_model_id, "386"); 104 } 105 #endif 106 } 107 108 static const struct cpu_dev default_cpu = { 109 .c_init = default_init, 110 .c_vendor = "Unknown", 111 .c_x86_vendor = X86_VENDOR_UNKNOWN, 112 }; 113 114 static const struct cpu_dev *this_cpu = &default_cpu; 115 116 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 117 #ifdef CONFIG_X86_64 118 /* 119 * We need valid kernel segments for data and code in long mode too 120 * IRET will check the segment types kkeil 2000/10/28 121 * Also sysret mandates a special GDT layout 122 * 123 * TLS descriptors are currently at a different place compared to i386. 124 * Hopefully nobody expects them at a fixed place (Wine?) 125 */ 126 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 127 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 128 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 129 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 130 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 131 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 132 #else 133 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 134 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 135 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 136 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 137 /* 138 * Segments used for calling PnP BIOS have byte granularity. 139 * They code segments and data segments have fixed 64k limits, 140 * the transfer segment sizes are set at run time. 141 */ 142 /* 32-bit code */ 143 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 144 /* 16-bit code */ 145 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 146 /* 16-bit data */ 147 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 148 /* 16-bit data */ 149 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 150 /* 16-bit data */ 151 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 152 /* 153 * The APM segments have byte granularity and their bases 154 * are set at run time. All have 64k limits. 155 */ 156 /* 32-bit code */ 157 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 158 /* 16-bit code */ 159 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 160 /* data */ 161 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 162 163 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 164 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 165 #endif 166 } }; 167 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 168 169 #ifdef CONFIG_X86_64 170 static int __init x86_nopcid_setup(char *s) 171 { 172 /* nopcid doesn't accept parameters */ 173 if (s) 174 return -EINVAL; 175 176 /* do not emit a message if the feature is not present */ 177 if (!boot_cpu_has(X86_FEATURE_PCID)) 178 return 0; 179 180 setup_clear_cpu_cap(X86_FEATURE_PCID); 181 pr_info("nopcid: PCID feature disabled\n"); 182 return 0; 183 } 184 early_param("nopcid", x86_nopcid_setup); 185 #endif 186 187 static int __init x86_noinvpcid_setup(char *s) 188 { 189 /* noinvpcid doesn't accept parameters */ 190 if (s) 191 return -EINVAL; 192 193 /* do not emit a message if the feature is not present */ 194 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 195 return 0; 196 197 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 198 pr_info("noinvpcid: INVPCID feature disabled\n"); 199 return 0; 200 } 201 early_param("noinvpcid", x86_noinvpcid_setup); 202 203 #ifdef CONFIG_X86_32 204 static int cachesize_override = -1; 205 static int disable_x86_serial_nr = 1; 206 207 static int __init cachesize_setup(char *str) 208 { 209 get_option(&str, &cachesize_override); 210 return 1; 211 } 212 __setup("cachesize=", cachesize_setup); 213 214 static int __init x86_sep_setup(char *s) 215 { 216 setup_clear_cpu_cap(X86_FEATURE_SEP); 217 return 1; 218 } 219 __setup("nosep", x86_sep_setup); 220 221 /* Standard macro to see if a specific flag is changeable */ 222 static inline int flag_is_changeable_p(u32 flag) 223 { 224 u32 f1, f2; 225 226 /* 227 * Cyrix and IDT cpus allow disabling of CPUID 228 * so the code below may return different results 229 * when it is executed before and after enabling 230 * the CPUID. Add "volatile" to not allow gcc to 231 * optimize the subsequent calls to this function. 232 */ 233 asm volatile ("pushfl \n\t" 234 "pushfl \n\t" 235 "popl %0 \n\t" 236 "movl %0, %1 \n\t" 237 "xorl %2, %0 \n\t" 238 "pushl %0 \n\t" 239 "popfl \n\t" 240 "pushfl \n\t" 241 "popl %0 \n\t" 242 "popfl \n\t" 243 244 : "=&r" (f1), "=&r" (f2) 245 : "ir" (flag)); 246 247 return ((f1^f2) & flag) != 0; 248 } 249 250 /* Probe for the CPUID instruction */ 251 int have_cpuid_p(void) 252 { 253 return flag_is_changeable_p(X86_EFLAGS_ID); 254 } 255 256 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 257 { 258 unsigned long lo, hi; 259 260 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 261 return; 262 263 /* Disable processor serial number: */ 264 265 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 266 lo |= 0x200000; 267 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 268 269 pr_notice("CPU serial number disabled.\n"); 270 clear_cpu_cap(c, X86_FEATURE_PN); 271 272 /* Disabling the serial number may affect the cpuid level */ 273 c->cpuid_level = cpuid_eax(0); 274 } 275 276 static int __init x86_serial_nr_setup(char *s) 277 { 278 disable_x86_serial_nr = 0; 279 return 1; 280 } 281 __setup("serialnumber", x86_serial_nr_setup); 282 #else 283 static inline int flag_is_changeable_p(u32 flag) 284 { 285 return 1; 286 } 287 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 288 { 289 } 290 #endif 291 292 static __init int setup_disable_smep(char *arg) 293 { 294 setup_clear_cpu_cap(X86_FEATURE_SMEP); 295 return 1; 296 } 297 __setup("nosmep", setup_disable_smep); 298 299 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 300 { 301 if (cpu_has(c, X86_FEATURE_SMEP)) 302 cr4_set_bits(X86_CR4_SMEP); 303 } 304 305 static __init int setup_disable_smap(char *arg) 306 { 307 setup_clear_cpu_cap(X86_FEATURE_SMAP); 308 return 1; 309 } 310 __setup("nosmap", setup_disable_smap); 311 312 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 313 { 314 unsigned long eflags = native_save_fl(); 315 316 /* This should have been cleared long ago */ 317 BUG_ON(eflags & X86_EFLAGS_AC); 318 319 if (cpu_has(c, X86_FEATURE_SMAP)) { 320 #ifdef CONFIG_X86_SMAP 321 cr4_set_bits(X86_CR4_SMAP); 322 #else 323 cr4_clear_bits(X86_CR4_SMAP); 324 #endif 325 } 326 } 327 328 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 329 { 330 /* Check the boot processor, plus build option for UMIP. */ 331 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 332 goto out; 333 334 /* Check the current processor's cpuid bits. */ 335 if (!cpu_has(c, X86_FEATURE_UMIP)) 336 goto out; 337 338 cr4_set_bits(X86_CR4_UMIP); 339 340 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 341 342 return; 343 344 out: 345 /* 346 * Make sure UMIP is disabled in case it was enabled in a 347 * previous boot (e.g., via kexec). 348 */ 349 cr4_clear_bits(X86_CR4_UMIP); 350 } 351 352 /* These bits should not change their value after CPU init is finished. */ 353 static const unsigned long cr4_pinned_mask = 354 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE; 355 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 356 static unsigned long cr4_pinned_bits __ro_after_init; 357 358 void native_write_cr0(unsigned long val) 359 { 360 unsigned long bits_missing = 0; 361 362 set_register: 363 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 364 365 if (static_branch_likely(&cr_pinning)) { 366 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 367 bits_missing = X86_CR0_WP; 368 val |= bits_missing; 369 goto set_register; 370 } 371 /* Warn after we've set the missing bits. */ 372 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 373 } 374 } 375 EXPORT_SYMBOL(native_write_cr0); 376 377 void native_write_cr4(unsigned long val) 378 { 379 unsigned long bits_changed = 0; 380 381 set_register: 382 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 383 384 if (static_branch_likely(&cr_pinning)) { 385 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 386 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 387 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 388 goto set_register; 389 } 390 /* Warn after we've corrected the changed bits. */ 391 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 392 bits_changed); 393 } 394 } 395 #if IS_MODULE(CONFIG_LKDTM) 396 EXPORT_SYMBOL_GPL(native_write_cr4); 397 #endif 398 399 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 400 { 401 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 402 403 lockdep_assert_irqs_disabled(); 404 405 newval = (cr4 & ~clear) | set; 406 if (newval != cr4) { 407 this_cpu_write(cpu_tlbstate.cr4, newval); 408 __write_cr4(newval); 409 } 410 } 411 EXPORT_SYMBOL(cr4_update_irqsoff); 412 413 /* Read the CR4 shadow. */ 414 unsigned long cr4_read_shadow(void) 415 { 416 return this_cpu_read(cpu_tlbstate.cr4); 417 } 418 EXPORT_SYMBOL_GPL(cr4_read_shadow); 419 420 void cr4_init(void) 421 { 422 unsigned long cr4 = __read_cr4(); 423 424 if (boot_cpu_has(X86_FEATURE_PCID)) 425 cr4 |= X86_CR4_PCIDE; 426 if (static_branch_likely(&cr_pinning)) 427 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 428 429 __write_cr4(cr4); 430 431 /* Initialize cr4 shadow for this CPU. */ 432 this_cpu_write(cpu_tlbstate.cr4, cr4); 433 } 434 435 /* 436 * Once CPU feature detection is finished (and boot params have been 437 * parsed), record any of the sensitive CR bits that are set, and 438 * enable CR pinning. 439 */ 440 static void __init setup_cr_pinning(void) 441 { 442 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 443 static_key_enable(&cr_pinning.key); 444 } 445 446 static __init int x86_nofsgsbase_setup(char *arg) 447 { 448 /* Require an exact match without trailing characters. */ 449 if (strlen(arg)) 450 return 0; 451 452 /* Do not emit a message if the feature is not present. */ 453 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 454 return 1; 455 456 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 457 pr_info("FSGSBASE disabled via kernel command line\n"); 458 return 1; 459 } 460 __setup("nofsgsbase", x86_nofsgsbase_setup); 461 462 /* 463 * Protection Keys are not available in 32-bit mode. 464 */ 465 static bool pku_disabled; 466 467 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 468 { 469 if (c == &boot_cpu_data) { 470 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 471 return; 472 /* 473 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 474 * bit to be set. Enforce it. 475 */ 476 setup_force_cpu_cap(X86_FEATURE_OSPKE); 477 478 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 479 return; 480 } 481 482 cr4_set_bits(X86_CR4_PKE); 483 /* Load the default PKRU value */ 484 pkru_write_default(); 485 } 486 487 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 488 static __init int setup_disable_pku(char *arg) 489 { 490 /* 491 * Do not clear the X86_FEATURE_PKU bit. All of the 492 * runtime checks are against OSPKE so clearing the 493 * bit does nothing. 494 * 495 * This way, we will see "pku" in cpuinfo, but not 496 * "ospke", which is exactly what we want. It shows 497 * that the CPU has PKU, but the OS has not enabled it. 498 * This happens to be exactly how a system would look 499 * if we disabled the config option. 500 */ 501 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 502 pku_disabled = true; 503 return 1; 504 } 505 __setup("nopku", setup_disable_pku); 506 #endif /* CONFIG_X86_64 */ 507 508 /* 509 * Some CPU features depend on higher CPUID levels, which may not always 510 * be available due to CPUID level capping or broken virtualization 511 * software. Add those features to this table to auto-disable them. 512 */ 513 struct cpuid_dependent_feature { 514 u32 feature; 515 u32 level; 516 }; 517 518 static const struct cpuid_dependent_feature 519 cpuid_dependent_features[] = { 520 { X86_FEATURE_MWAIT, 0x00000005 }, 521 { X86_FEATURE_DCA, 0x00000009 }, 522 { X86_FEATURE_XSAVE, 0x0000000d }, 523 { 0, 0 } 524 }; 525 526 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 527 { 528 const struct cpuid_dependent_feature *df; 529 530 for (df = cpuid_dependent_features; df->feature; df++) { 531 532 if (!cpu_has(c, df->feature)) 533 continue; 534 /* 535 * Note: cpuid_level is set to -1 if unavailable, but 536 * extended_extended_level is set to 0 if unavailable 537 * and the legitimate extended levels are all negative 538 * when signed; hence the weird messing around with 539 * signs here... 540 */ 541 if (!((s32)df->level < 0 ? 542 (u32)df->level > (u32)c->extended_cpuid_level : 543 (s32)df->level > (s32)c->cpuid_level)) 544 continue; 545 546 clear_cpu_cap(c, df->feature); 547 if (!warn) 548 continue; 549 550 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 551 x86_cap_flag(df->feature), df->level); 552 } 553 } 554 555 /* 556 * Naming convention should be: <Name> [(<Codename>)] 557 * This table only is used unless init_<vendor>() below doesn't set it; 558 * in particular, if CPUID levels 0x80000002..4 are supported, this 559 * isn't used 560 */ 561 562 /* Look up CPU names by table lookup. */ 563 static const char *table_lookup_model(struct cpuinfo_x86 *c) 564 { 565 #ifdef CONFIG_X86_32 566 const struct legacy_cpu_model_info *info; 567 568 if (c->x86_model >= 16) 569 return NULL; /* Range check */ 570 571 if (!this_cpu) 572 return NULL; 573 574 info = this_cpu->legacy_models; 575 576 while (info->family) { 577 if (info->family == c->x86) 578 return info->model_names[c->x86_model]; 579 info++; 580 } 581 #endif 582 return NULL; /* Not found */ 583 } 584 585 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 586 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 587 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 588 589 void load_percpu_segment(int cpu) 590 { 591 #ifdef CONFIG_X86_32 592 loadsegment(fs, __KERNEL_PERCPU); 593 #else 594 __loadsegment_simple(gs, 0); 595 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 596 #endif 597 } 598 599 #ifdef CONFIG_X86_32 600 /* The 32-bit entry code needs to find cpu_entry_area. */ 601 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 602 #endif 603 604 /* Load the original GDT from the per-cpu structure */ 605 void load_direct_gdt(int cpu) 606 { 607 struct desc_ptr gdt_descr; 608 609 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 610 gdt_descr.size = GDT_SIZE - 1; 611 load_gdt(&gdt_descr); 612 } 613 EXPORT_SYMBOL_GPL(load_direct_gdt); 614 615 /* Load a fixmap remapping of the per-cpu GDT */ 616 void load_fixmap_gdt(int cpu) 617 { 618 struct desc_ptr gdt_descr; 619 620 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 621 gdt_descr.size = GDT_SIZE - 1; 622 load_gdt(&gdt_descr); 623 } 624 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 625 626 /* 627 * Current gdt points %fs at the "master" per-cpu area: after this, 628 * it's on the real one. 629 */ 630 void switch_to_new_gdt(int cpu) 631 { 632 /* Load the original GDT */ 633 load_direct_gdt(cpu); 634 /* Reload the per-cpu base */ 635 load_percpu_segment(cpu); 636 } 637 638 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 639 640 static void get_model_name(struct cpuinfo_x86 *c) 641 { 642 unsigned int *v; 643 char *p, *q, *s; 644 645 if (c->extended_cpuid_level < 0x80000004) 646 return; 647 648 v = (unsigned int *)c->x86_model_id; 649 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 650 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 651 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 652 c->x86_model_id[48] = 0; 653 654 /* Trim whitespace */ 655 p = q = s = &c->x86_model_id[0]; 656 657 while (*p == ' ') 658 p++; 659 660 while (*p) { 661 /* Note the last non-whitespace index */ 662 if (!isspace(*p)) 663 s = q; 664 665 *q++ = *p++; 666 } 667 668 *(s + 1) = '\0'; 669 } 670 671 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 672 { 673 unsigned int eax, ebx, ecx, edx; 674 675 c->x86_max_cores = 1; 676 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 677 return; 678 679 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 680 if (eax & 0x1f) 681 c->x86_max_cores = (eax >> 26) + 1; 682 } 683 684 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 685 { 686 unsigned int n, dummy, ebx, ecx, edx, l2size; 687 688 n = c->extended_cpuid_level; 689 690 if (n >= 0x80000005) { 691 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 692 c->x86_cache_size = (ecx>>24) + (edx>>24); 693 #ifdef CONFIG_X86_64 694 /* On K8 L1 TLB is inclusive, so don't count it */ 695 c->x86_tlbsize = 0; 696 #endif 697 } 698 699 if (n < 0x80000006) /* Some chips just has a large L1. */ 700 return; 701 702 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 703 l2size = ecx >> 16; 704 705 #ifdef CONFIG_X86_64 706 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 707 #else 708 /* do processor-specific cache resizing */ 709 if (this_cpu->legacy_cache_size) 710 l2size = this_cpu->legacy_cache_size(c, l2size); 711 712 /* Allow user to override all this if necessary. */ 713 if (cachesize_override != -1) 714 l2size = cachesize_override; 715 716 if (l2size == 0) 717 return; /* Again, no L2 cache is possible */ 718 #endif 719 720 c->x86_cache_size = l2size; 721 } 722 723 u16 __read_mostly tlb_lli_4k[NR_INFO]; 724 u16 __read_mostly tlb_lli_2m[NR_INFO]; 725 u16 __read_mostly tlb_lli_4m[NR_INFO]; 726 u16 __read_mostly tlb_lld_4k[NR_INFO]; 727 u16 __read_mostly tlb_lld_2m[NR_INFO]; 728 u16 __read_mostly tlb_lld_4m[NR_INFO]; 729 u16 __read_mostly tlb_lld_1g[NR_INFO]; 730 731 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 732 { 733 if (this_cpu->c_detect_tlb) 734 this_cpu->c_detect_tlb(c); 735 736 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 737 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 738 tlb_lli_4m[ENTRIES]); 739 740 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 741 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 742 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 743 } 744 745 int detect_ht_early(struct cpuinfo_x86 *c) 746 { 747 #ifdef CONFIG_SMP 748 u32 eax, ebx, ecx, edx; 749 750 if (!cpu_has(c, X86_FEATURE_HT)) 751 return -1; 752 753 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 754 return -1; 755 756 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 757 return -1; 758 759 cpuid(1, &eax, &ebx, &ecx, &edx); 760 761 smp_num_siblings = (ebx & 0xff0000) >> 16; 762 if (smp_num_siblings == 1) 763 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 764 #endif 765 return 0; 766 } 767 768 void detect_ht(struct cpuinfo_x86 *c) 769 { 770 #ifdef CONFIG_SMP 771 int index_msb, core_bits; 772 773 if (detect_ht_early(c) < 0) 774 return; 775 776 index_msb = get_count_order(smp_num_siblings); 777 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 778 779 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 780 781 index_msb = get_count_order(smp_num_siblings); 782 783 core_bits = get_count_order(c->x86_max_cores); 784 785 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 786 ((1 << core_bits) - 1); 787 #endif 788 } 789 790 static void get_cpu_vendor(struct cpuinfo_x86 *c) 791 { 792 char *v = c->x86_vendor_id; 793 int i; 794 795 for (i = 0; i < X86_VENDOR_NUM; i++) { 796 if (!cpu_devs[i]) 797 break; 798 799 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 800 (cpu_devs[i]->c_ident[1] && 801 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 802 803 this_cpu = cpu_devs[i]; 804 c->x86_vendor = this_cpu->c_x86_vendor; 805 return; 806 } 807 } 808 809 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 810 "CPU: Your system may be unstable.\n", v); 811 812 c->x86_vendor = X86_VENDOR_UNKNOWN; 813 this_cpu = &default_cpu; 814 } 815 816 void cpu_detect(struct cpuinfo_x86 *c) 817 { 818 /* Get vendor name */ 819 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 820 (unsigned int *)&c->x86_vendor_id[0], 821 (unsigned int *)&c->x86_vendor_id[8], 822 (unsigned int *)&c->x86_vendor_id[4]); 823 824 c->x86 = 4; 825 /* Intel-defined flags: level 0x00000001 */ 826 if (c->cpuid_level >= 0x00000001) { 827 u32 junk, tfms, cap0, misc; 828 829 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 830 c->x86 = x86_family(tfms); 831 c->x86_model = x86_model(tfms); 832 c->x86_stepping = x86_stepping(tfms); 833 834 if (cap0 & (1<<19)) { 835 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 836 c->x86_cache_alignment = c->x86_clflush_size; 837 } 838 } 839 } 840 841 static void apply_forced_caps(struct cpuinfo_x86 *c) 842 { 843 int i; 844 845 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 846 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 847 c->x86_capability[i] |= cpu_caps_set[i]; 848 } 849 } 850 851 static void init_speculation_control(struct cpuinfo_x86 *c) 852 { 853 /* 854 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 855 * and they also have a different bit for STIBP support. Also, 856 * a hypervisor might have set the individual AMD bits even on 857 * Intel CPUs, for finer-grained selection of what's available. 858 */ 859 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 860 set_cpu_cap(c, X86_FEATURE_IBRS); 861 set_cpu_cap(c, X86_FEATURE_IBPB); 862 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 863 } 864 865 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 866 set_cpu_cap(c, X86_FEATURE_STIBP); 867 868 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 869 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 870 set_cpu_cap(c, X86_FEATURE_SSBD); 871 872 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 873 set_cpu_cap(c, X86_FEATURE_IBRS); 874 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 875 } 876 877 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 878 set_cpu_cap(c, X86_FEATURE_IBPB); 879 880 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 881 set_cpu_cap(c, X86_FEATURE_STIBP); 882 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 883 } 884 885 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 886 set_cpu_cap(c, X86_FEATURE_SSBD); 887 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 888 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 889 } 890 } 891 892 void get_cpu_cap(struct cpuinfo_x86 *c) 893 { 894 u32 eax, ebx, ecx, edx; 895 896 /* Intel-defined flags: level 0x00000001 */ 897 if (c->cpuid_level >= 0x00000001) { 898 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 899 900 c->x86_capability[CPUID_1_ECX] = ecx; 901 c->x86_capability[CPUID_1_EDX] = edx; 902 } 903 904 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 905 if (c->cpuid_level >= 0x00000006) 906 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 907 908 /* Additional Intel-defined flags: level 0x00000007 */ 909 if (c->cpuid_level >= 0x00000007) { 910 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 911 c->x86_capability[CPUID_7_0_EBX] = ebx; 912 c->x86_capability[CPUID_7_ECX] = ecx; 913 c->x86_capability[CPUID_7_EDX] = edx; 914 915 /* Check valid sub-leaf index before accessing it */ 916 if (eax >= 1) { 917 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 918 c->x86_capability[CPUID_7_1_EAX] = eax; 919 } 920 } 921 922 /* Extended state features: level 0x0000000d */ 923 if (c->cpuid_level >= 0x0000000d) { 924 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 925 926 c->x86_capability[CPUID_D_1_EAX] = eax; 927 } 928 929 /* AMD-defined flags: level 0x80000001 */ 930 eax = cpuid_eax(0x80000000); 931 c->extended_cpuid_level = eax; 932 933 if ((eax & 0xffff0000) == 0x80000000) { 934 if (eax >= 0x80000001) { 935 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 936 937 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 938 c->x86_capability[CPUID_8000_0001_EDX] = edx; 939 } 940 } 941 942 if (c->extended_cpuid_level >= 0x80000007) { 943 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 944 945 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 946 c->x86_power = edx; 947 } 948 949 if (c->extended_cpuid_level >= 0x80000008) { 950 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 951 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 952 } 953 954 if (c->extended_cpuid_level >= 0x8000000a) 955 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 956 957 if (c->extended_cpuid_level >= 0x8000001f) 958 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 959 960 init_scattered_cpuid_features(c); 961 init_speculation_control(c); 962 963 /* 964 * Clear/Set all flags overridden by options, after probe. 965 * This needs to happen each time we re-probe, which may happen 966 * several times during CPU initialization. 967 */ 968 apply_forced_caps(c); 969 } 970 971 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 972 { 973 u32 eax, ebx, ecx, edx; 974 975 if (c->extended_cpuid_level >= 0x80000008) { 976 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 977 978 c->x86_virt_bits = (eax >> 8) & 0xff; 979 c->x86_phys_bits = eax & 0xff; 980 } 981 #ifdef CONFIG_X86_32 982 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 983 c->x86_phys_bits = 36; 984 #endif 985 c->x86_cache_bits = c->x86_phys_bits; 986 } 987 988 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 989 { 990 #ifdef CONFIG_X86_32 991 int i; 992 993 /* 994 * First of all, decide if this is a 486 or higher 995 * It's a 486 if we can modify the AC flag 996 */ 997 if (flag_is_changeable_p(X86_EFLAGS_AC)) 998 c->x86 = 4; 999 else 1000 c->x86 = 3; 1001 1002 for (i = 0; i < X86_VENDOR_NUM; i++) 1003 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1004 c->x86_vendor_id[0] = 0; 1005 cpu_devs[i]->c_identify(c); 1006 if (c->x86_vendor_id[0]) { 1007 get_cpu_vendor(c); 1008 break; 1009 } 1010 } 1011 #endif 1012 } 1013 1014 #define NO_SPECULATION BIT(0) 1015 #define NO_MELTDOWN BIT(1) 1016 #define NO_SSB BIT(2) 1017 #define NO_L1TF BIT(3) 1018 #define NO_MDS BIT(4) 1019 #define MSBDS_ONLY BIT(5) 1020 #define NO_SWAPGS BIT(6) 1021 #define NO_ITLB_MULTIHIT BIT(7) 1022 #define NO_SPECTRE_V2 BIT(8) 1023 1024 #define VULNWL(vendor, family, model, whitelist) \ 1025 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1026 1027 #define VULNWL_INTEL(model, whitelist) \ 1028 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1029 1030 #define VULNWL_AMD(family, whitelist) \ 1031 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1032 1033 #define VULNWL_HYGON(family, whitelist) \ 1034 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1035 1036 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1037 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1038 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1039 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1040 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1041 1042 /* Intel Family 6 */ 1043 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1044 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1045 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1046 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1047 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1048 1049 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1050 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1051 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1052 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1053 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1054 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1055 1056 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1057 1058 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1059 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1060 1061 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1062 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1063 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1064 1065 /* 1066 * Technically, swapgs isn't serializing on AMD (despite it previously 1067 * being documented as such in the APM). But according to AMD, %gs is 1068 * updated non-speculatively, and the issuing of %gs-relative memory 1069 * operands will be blocked until the %gs update completes, which is 1070 * good enough for our purposes. 1071 */ 1072 1073 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1074 1075 /* AMD Family 0xf - 0x12 */ 1076 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1077 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1078 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1079 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1080 1081 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1082 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1083 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1084 1085 /* Zhaoxin Family 7 */ 1086 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1087 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1088 {} 1089 }; 1090 1091 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1092 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1093 INTEL_FAM6_##model, steppings, \ 1094 X86_FEATURE_ANY, issues) 1095 1096 #define SRBDS BIT(0) 1097 1098 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1099 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1100 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1101 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1102 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1103 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1104 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1105 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS), 1106 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS), 1107 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS), 1108 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS), 1109 {} 1110 }; 1111 1112 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1113 { 1114 const struct x86_cpu_id *m = x86_match_cpu(table); 1115 1116 return m && !!(m->driver_data & which); 1117 } 1118 1119 u64 x86_read_arch_cap_msr(void) 1120 { 1121 u64 ia32_cap = 0; 1122 1123 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1124 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1125 1126 return ia32_cap; 1127 } 1128 1129 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1130 { 1131 u64 ia32_cap = x86_read_arch_cap_msr(); 1132 1133 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1134 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1135 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1136 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1137 1138 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1139 return; 1140 1141 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1142 1143 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1144 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1145 1146 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1147 !(ia32_cap & ARCH_CAP_SSB_NO) && 1148 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1149 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1150 1151 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1152 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1153 1154 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1155 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1156 setup_force_cpu_bug(X86_BUG_MDS); 1157 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1158 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1159 } 1160 1161 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1162 setup_force_cpu_bug(X86_BUG_SWAPGS); 1163 1164 /* 1165 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1166 * - TSX is supported or 1167 * - TSX_CTRL is present 1168 * 1169 * TSX_CTRL check is needed for cases when TSX could be disabled before 1170 * the kernel boot e.g. kexec. 1171 * TSX_CTRL check alone is not sufficient for cases when the microcode 1172 * update is not present or running as guest that don't get TSX_CTRL. 1173 */ 1174 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1175 (cpu_has(c, X86_FEATURE_RTM) || 1176 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1177 setup_force_cpu_bug(X86_BUG_TAA); 1178 1179 /* 1180 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1181 * in the vulnerability blacklist. 1182 */ 1183 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1184 cpu_has(c, X86_FEATURE_RDSEED)) && 1185 cpu_matches(cpu_vuln_blacklist, SRBDS)) 1186 setup_force_cpu_bug(X86_BUG_SRBDS); 1187 1188 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1189 return; 1190 1191 /* Rogue Data Cache Load? No! */ 1192 if (ia32_cap & ARCH_CAP_RDCL_NO) 1193 return; 1194 1195 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1196 1197 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1198 return; 1199 1200 setup_force_cpu_bug(X86_BUG_L1TF); 1201 } 1202 1203 /* 1204 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1205 * unfortunately, that's not true in practice because of early VIA 1206 * chips and (more importantly) broken virtualizers that are not easy 1207 * to detect. In the latter case it doesn't even *fail* reliably, so 1208 * probing for it doesn't even work. Disable it completely on 32-bit 1209 * unless we can find a reliable way to detect all the broken cases. 1210 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1211 */ 1212 static void detect_nopl(void) 1213 { 1214 #ifdef CONFIG_X86_32 1215 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1216 #else 1217 setup_force_cpu_cap(X86_FEATURE_NOPL); 1218 #endif 1219 } 1220 1221 /* 1222 * We parse cpu parameters early because fpu__init_system() is executed 1223 * before parse_early_param(). 1224 */ 1225 static void __init cpu_parse_early_param(void) 1226 { 1227 char arg[128]; 1228 char *argptr = arg; 1229 int arglen, res, bit; 1230 1231 #ifdef CONFIG_X86_32 1232 if (cmdline_find_option_bool(boot_command_line, "no387")) 1233 #ifdef CONFIG_MATH_EMULATION 1234 setup_clear_cpu_cap(X86_FEATURE_FPU); 1235 #else 1236 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1237 #endif 1238 1239 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1240 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1241 #endif 1242 1243 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1244 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1245 1246 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1247 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1248 1249 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1250 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1251 1252 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1253 if (arglen <= 0) 1254 return; 1255 1256 pr_info("Clearing CPUID bits:"); 1257 do { 1258 res = get_option(&argptr, &bit); 1259 if (res == 0 || res == 3) 1260 break; 1261 1262 /* If the argument was too long, the last bit may be cut off */ 1263 if (res == 1 && arglen >= sizeof(arg)) 1264 break; 1265 1266 if (bit >= 0 && bit < NCAPINTS * 32) { 1267 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1268 setup_clear_cpu_cap(bit); 1269 } 1270 } while (res == 2); 1271 pr_cont("\n"); 1272 } 1273 1274 /* 1275 * Do minimum CPU detection early. 1276 * Fields really needed: vendor, cpuid_level, family, model, mask, 1277 * cache alignment. 1278 * The others are not touched to avoid unwanted side effects. 1279 * 1280 * WARNING: this function is only called on the boot CPU. Don't add code 1281 * here that is supposed to run on all CPUs. 1282 */ 1283 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1284 { 1285 #ifdef CONFIG_X86_64 1286 c->x86_clflush_size = 64; 1287 c->x86_phys_bits = 36; 1288 c->x86_virt_bits = 48; 1289 #else 1290 c->x86_clflush_size = 32; 1291 c->x86_phys_bits = 32; 1292 c->x86_virt_bits = 32; 1293 #endif 1294 c->x86_cache_alignment = c->x86_clflush_size; 1295 1296 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1297 c->extended_cpuid_level = 0; 1298 1299 if (!have_cpuid_p()) 1300 identify_cpu_without_cpuid(c); 1301 1302 /* cyrix could have cpuid enabled via c_identify()*/ 1303 if (have_cpuid_p()) { 1304 cpu_detect(c); 1305 get_cpu_vendor(c); 1306 get_cpu_cap(c); 1307 get_cpu_address_sizes(c); 1308 setup_force_cpu_cap(X86_FEATURE_CPUID); 1309 cpu_parse_early_param(); 1310 1311 if (this_cpu->c_early_init) 1312 this_cpu->c_early_init(c); 1313 1314 c->cpu_index = 0; 1315 filter_cpuid_features(c, false); 1316 1317 if (this_cpu->c_bsp_init) 1318 this_cpu->c_bsp_init(c); 1319 } else { 1320 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1321 } 1322 1323 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1324 1325 cpu_set_bug_bits(c); 1326 1327 sld_setup(c); 1328 1329 fpu__init_system(c); 1330 1331 init_sigframe_size(); 1332 1333 #ifdef CONFIG_X86_32 1334 /* 1335 * Regardless of whether PCID is enumerated, the SDM says 1336 * that it can't be enabled in 32-bit mode. 1337 */ 1338 setup_clear_cpu_cap(X86_FEATURE_PCID); 1339 #endif 1340 1341 /* 1342 * Later in the boot process pgtable_l5_enabled() relies on 1343 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1344 * enabled by this point we need to clear the feature bit to avoid 1345 * false-positives at the later stage. 1346 * 1347 * pgtable_l5_enabled() can be false here for several reasons: 1348 * - 5-level paging is disabled compile-time; 1349 * - it's 32-bit kernel; 1350 * - machine doesn't support 5-level paging; 1351 * - user specified 'no5lvl' in kernel command line. 1352 */ 1353 if (!pgtable_l5_enabled()) 1354 setup_clear_cpu_cap(X86_FEATURE_LA57); 1355 1356 detect_nopl(); 1357 } 1358 1359 void __init early_cpu_init(void) 1360 { 1361 const struct cpu_dev *const *cdev; 1362 int count = 0; 1363 1364 #ifdef CONFIG_PROCESSOR_SELECT 1365 pr_info("KERNEL supported cpus:\n"); 1366 #endif 1367 1368 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1369 const struct cpu_dev *cpudev = *cdev; 1370 1371 if (count >= X86_VENDOR_NUM) 1372 break; 1373 cpu_devs[count] = cpudev; 1374 count++; 1375 1376 #ifdef CONFIG_PROCESSOR_SELECT 1377 { 1378 unsigned int j; 1379 1380 for (j = 0; j < 2; j++) { 1381 if (!cpudev->c_ident[j]) 1382 continue; 1383 pr_info(" %s %s\n", cpudev->c_vendor, 1384 cpudev->c_ident[j]); 1385 } 1386 } 1387 #endif 1388 } 1389 early_identify_cpu(&boot_cpu_data); 1390 } 1391 1392 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1393 { 1394 #ifdef CONFIG_X86_64 1395 /* 1396 * Empirically, writing zero to a segment selector on AMD does 1397 * not clear the base, whereas writing zero to a segment 1398 * selector on Intel does clear the base. Intel's behavior 1399 * allows slightly faster context switches in the common case 1400 * where GS is unused by the prev and next threads. 1401 * 1402 * Since neither vendor documents this anywhere that I can see, 1403 * detect it directly instead of hard-coding the choice by 1404 * vendor. 1405 * 1406 * I've designated AMD's behavior as the "bug" because it's 1407 * counterintuitive and less friendly. 1408 */ 1409 1410 unsigned long old_base, tmp; 1411 rdmsrl(MSR_FS_BASE, old_base); 1412 wrmsrl(MSR_FS_BASE, 1); 1413 loadsegment(fs, 0); 1414 rdmsrl(MSR_FS_BASE, tmp); 1415 if (tmp != 0) 1416 set_cpu_bug(c, X86_BUG_NULL_SEG); 1417 wrmsrl(MSR_FS_BASE, old_base); 1418 #endif 1419 } 1420 1421 static void generic_identify(struct cpuinfo_x86 *c) 1422 { 1423 c->extended_cpuid_level = 0; 1424 1425 if (!have_cpuid_p()) 1426 identify_cpu_without_cpuid(c); 1427 1428 /* cyrix could have cpuid enabled via c_identify()*/ 1429 if (!have_cpuid_p()) 1430 return; 1431 1432 cpu_detect(c); 1433 1434 get_cpu_vendor(c); 1435 1436 get_cpu_cap(c); 1437 1438 get_cpu_address_sizes(c); 1439 1440 if (c->cpuid_level >= 0x00000001) { 1441 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1442 #ifdef CONFIG_X86_32 1443 # ifdef CONFIG_SMP 1444 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1445 # else 1446 c->apicid = c->initial_apicid; 1447 # endif 1448 #endif 1449 c->phys_proc_id = c->initial_apicid; 1450 } 1451 1452 get_model_name(c); /* Default name */ 1453 1454 detect_null_seg_behavior(c); 1455 1456 /* 1457 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1458 * systems that run Linux at CPL > 0 may or may not have the 1459 * issue, but, even if they have the issue, there's absolutely 1460 * nothing we can do about it because we can't use the real IRET 1461 * instruction. 1462 * 1463 * NB: For the time being, only 32-bit kernels support 1464 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1465 * whether to apply espfix using paravirt hooks. If any 1466 * non-paravirt system ever shows up that does *not* have the 1467 * ESPFIX issue, we can change this. 1468 */ 1469 #ifdef CONFIG_X86_32 1470 set_cpu_bug(c, X86_BUG_ESPFIX); 1471 #endif 1472 } 1473 1474 /* 1475 * Validate that ACPI/mptables have the same information about the 1476 * effective APIC id and update the package map. 1477 */ 1478 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1479 { 1480 #ifdef CONFIG_SMP 1481 unsigned int apicid, cpu = smp_processor_id(); 1482 1483 apicid = apic->cpu_present_to_apicid(cpu); 1484 1485 if (apicid != c->apicid) { 1486 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1487 cpu, apicid, c->initial_apicid); 1488 } 1489 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1490 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1491 #else 1492 c->logical_proc_id = 0; 1493 #endif 1494 } 1495 1496 /* 1497 * This does the hard work of actually picking apart the CPU stuff... 1498 */ 1499 static void identify_cpu(struct cpuinfo_x86 *c) 1500 { 1501 int i; 1502 1503 c->loops_per_jiffy = loops_per_jiffy; 1504 c->x86_cache_size = 0; 1505 c->x86_vendor = X86_VENDOR_UNKNOWN; 1506 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1507 c->x86_vendor_id[0] = '\0'; /* Unset */ 1508 c->x86_model_id[0] = '\0'; /* Unset */ 1509 c->x86_max_cores = 1; 1510 c->x86_coreid_bits = 0; 1511 c->cu_id = 0xff; 1512 #ifdef CONFIG_X86_64 1513 c->x86_clflush_size = 64; 1514 c->x86_phys_bits = 36; 1515 c->x86_virt_bits = 48; 1516 #else 1517 c->cpuid_level = -1; /* CPUID not detected */ 1518 c->x86_clflush_size = 32; 1519 c->x86_phys_bits = 32; 1520 c->x86_virt_bits = 32; 1521 #endif 1522 c->x86_cache_alignment = c->x86_clflush_size; 1523 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1524 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1525 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1526 #endif 1527 1528 generic_identify(c); 1529 1530 if (this_cpu->c_identify) 1531 this_cpu->c_identify(c); 1532 1533 /* Clear/Set all flags overridden by options, after probe */ 1534 apply_forced_caps(c); 1535 1536 #ifdef CONFIG_X86_64 1537 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1538 #endif 1539 1540 /* 1541 * Vendor-specific initialization. In this section we 1542 * canonicalize the feature flags, meaning if there are 1543 * features a certain CPU supports which CPUID doesn't 1544 * tell us, CPUID claiming incorrect flags, or other bugs, 1545 * we handle them here. 1546 * 1547 * At the end of this section, c->x86_capability better 1548 * indicate the features this CPU genuinely supports! 1549 */ 1550 if (this_cpu->c_init) 1551 this_cpu->c_init(c); 1552 1553 /* Disable the PN if appropriate */ 1554 squash_the_stupid_serial_number(c); 1555 1556 /* Set up SMEP/SMAP/UMIP */ 1557 setup_smep(c); 1558 setup_smap(c); 1559 setup_umip(c); 1560 1561 /* Enable FSGSBASE instructions if available. */ 1562 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1563 cr4_set_bits(X86_CR4_FSGSBASE); 1564 elf_hwcap2 |= HWCAP2_FSGSBASE; 1565 } 1566 1567 /* 1568 * The vendor-specific functions might have changed features. 1569 * Now we do "generic changes." 1570 */ 1571 1572 /* Filter out anything that depends on CPUID levels we don't have */ 1573 filter_cpuid_features(c, true); 1574 1575 /* If the model name is still unset, do table lookup. */ 1576 if (!c->x86_model_id[0]) { 1577 const char *p; 1578 p = table_lookup_model(c); 1579 if (p) 1580 strcpy(c->x86_model_id, p); 1581 else 1582 /* Last resort... */ 1583 sprintf(c->x86_model_id, "%02x/%02x", 1584 c->x86, c->x86_model); 1585 } 1586 1587 #ifdef CONFIG_X86_64 1588 detect_ht(c); 1589 #endif 1590 1591 x86_init_rdrand(c); 1592 setup_pku(c); 1593 1594 /* 1595 * Clear/Set all flags overridden by options, need do it 1596 * before following smp all cpus cap AND. 1597 */ 1598 apply_forced_caps(c); 1599 1600 /* 1601 * On SMP, boot_cpu_data holds the common feature set between 1602 * all CPUs; so make sure that we indicate which features are 1603 * common between the CPUs. The first time this routine gets 1604 * executed, c == &boot_cpu_data. 1605 */ 1606 if (c != &boot_cpu_data) { 1607 /* AND the already accumulated flags with these */ 1608 for (i = 0; i < NCAPINTS; i++) 1609 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1610 1611 /* OR, i.e. replicate the bug flags */ 1612 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1613 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1614 } 1615 1616 /* Init Machine Check Exception if available. */ 1617 mcheck_cpu_init(c); 1618 1619 select_idle_routine(c); 1620 1621 #ifdef CONFIG_NUMA 1622 numa_add_cpu(smp_processor_id()); 1623 #endif 1624 } 1625 1626 /* 1627 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1628 * on 32-bit kernels: 1629 */ 1630 #ifdef CONFIG_X86_32 1631 void enable_sep_cpu(void) 1632 { 1633 struct tss_struct *tss; 1634 int cpu; 1635 1636 if (!boot_cpu_has(X86_FEATURE_SEP)) 1637 return; 1638 1639 cpu = get_cpu(); 1640 tss = &per_cpu(cpu_tss_rw, cpu); 1641 1642 /* 1643 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1644 * see the big comment in struct x86_hw_tss's definition. 1645 */ 1646 1647 tss->x86_tss.ss1 = __KERNEL_CS; 1648 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1649 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1650 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1651 1652 put_cpu(); 1653 } 1654 #endif 1655 1656 void __init identify_boot_cpu(void) 1657 { 1658 identify_cpu(&boot_cpu_data); 1659 #ifdef CONFIG_X86_32 1660 sysenter_setup(); 1661 enable_sep_cpu(); 1662 #endif 1663 cpu_detect_tlb(&boot_cpu_data); 1664 setup_cr_pinning(); 1665 1666 tsx_init(); 1667 } 1668 1669 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1670 { 1671 BUG_ON(c == &boot_cpu_data); 1672 identify_cpu(c); 1673 #ifdef CONFIG_X86_32 1674 enable_sep_cpu(); 1675 #endif 1676 mtrr_ap_init(); 1677 validate_apic_and_package_id(c); 1678 x86_spec_ctrl_setup_ap(); 1679 update_srbds_msr(); 1680 } 1681 1682 static __init int setup_noclflush(char *arg) 1683 { 1684 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1685 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1686 return 1; 1687 } 1688 __setup("noclflush", setup_noclflush); 1689 1690 void print_cpu_info(struct cpuinfo_x86 *c) 1691 { 1692 const char *vendor = NULL; 1693 1694 if (c->x86_vendor < X86_VENDOR_NUM) { 1695 vendor = this_cpu->c_vendor; 1696 } else { 1697 if (c->cpuid_level >= 0) 1698 vendor = c->x86_vendor_id; 1699 } 1700 1701 if (vendor && !strstr(c->x86_model_id, vendor)) 1702 pr_cont("%s ", vendor); 1703 1704 if (c->x86_model_id[0]) 1705 pr_cont("%s", c->x86_model_id); 1706 else 1707 pr_cont("%d86", c->x86); 1708 1709 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1710 1711 if (c->x86_stepping || c->cpuid_level >= 0) 1712 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1713 else 1714 pr_cont(")\n"); 1715 } 1716 1717 /* 1718 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 1719 * function prevents it from becoming an environment variable for init. 1720 */ 1721 static __init int setup_clearcpuid(char *arg) 1722 { 1723 return 1; 1724 } 1725 __setup("clearcpuid=", setup_clearcpuid); 1726 1727 #ifdef CONFIG_X86_64 1728 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1729 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1730 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1731 1732 /* 1733 * The following percpu variables are hot. Align current_task to 1734 * cacheline size such that they fall in the same cacheline. 1735 */ 1736 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1737 &init_task; 1738 EXPORT_PER_CPU_SYMBOL(current_task); 1739 1740 DEFINE_PER_CPU(void *, hardirq_stack_ptr); 1741 DEFINE_PER_CPU(bool, hardirq_stack_inuse); 1742 1743 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1744 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1745 1746 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 1747 1748 /* May not be marked __init: used by software suspend */ 1749 void syscall_init(void) 1750 { 1751 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1752 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1753 1754 #ifdef CONFIG_IA32_EMULATION 1755 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1756 /* 1757 * This only works on Intel CPUs. 1758 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1759 * This does not cause SYSENTER to jump to the wrong location, because 1760 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1761 */ 1762 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1763 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1764 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1765 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1766 #else 1767 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1768 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1769 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1770 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1771 #endif 1772 1773 /* 1774 * Flags to clear on syscall; clear as much as possible 1775 * to minimize user space-kernel interference. 1776 */ 1777 wrmsrl(MSR_SYSCALL_MASK, 1778 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 1779 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 1780 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 1781 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 1782 X86_EFLAGS_AC|X86_EFLAGS_ID); 1783 } 1784 1785 #else /* CONFIG_X86_64 */ 1786 1787 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1788 EXPORT_PER_CPU_SYMBOL(current_task); 1789 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1790 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1791 1792 /* 1793 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1794 * the top of the kernel stack. Use an extra percpu variable to track the 1795 * top of the kernel stack directly. 1796 */ 1797 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1798 (unsigned long)&init_thread_union + THREAD_SIZE; 1799 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1800 1801 #ifdef CONFIG_STACKPROTECTOR 1802 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 1803 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 1804 #endif 1805 1806 #endif /* CONFIG_X86_64 */ 1807 1808 /* 1809 * Clear all 6 debug registers: 1810 */ 1811 static void clear_all_debug_regs(void) 1812 { 1813 int i; 1814 1815 for (i = 0; i < 8; i++) { 1816 /* Ignore db4, db5 */ 1817 if ((i == 4) || (i == 5)) 1818 continue; 1819 1820 set_debugreg(0, i); 1821 } 1822 } 1823 1824 #ifdef CONFIG_KGDB 1825 /* 1826 * Restore debug regs if using kgdbwait and you have a kernel debugger 1827 * connection established. 1828 */ 1829 static void dbg_restore_debug_regs(void) 1830 { 1831 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1832 arch_kgdb_ops.correct_hw_break(); 1833 } 1834 #else /* ! CONFIG_KGDB */ 1835 #define dbg_restore_debug_regs() 1836 #endif /* ! CONFIG_KGDB */ 1837 1838 static void wait_for_master_cpu(int cpu) 1839 { 1840 #ifdef CONFIG_SMP 1841 /* 1842 * wait for ACK from master CPU before continuing 1843 * with AP initialization 1844 */ 1845 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1846 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1847 cpu_relax(); 1848 #endif 1849 } 1850 1851 #ifdef CONFIG_X86_64 1852 static inline void setup_getcpu(int cpu) 1853 { 1854 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1855 struct desc_struct d = { }; 1856 1857 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 1858 wrmsr(MSR_TSC_AUX, cpudata, 0); 1859 1860 /* Store CPU and node number in limit. */ 1861 d.limit0 = cpudata; 1862 d.limit1 = cpudata >> 16; 1863 1864 d.type = 5; /* RO data, expand down, accessed */ 1865 d.dpl = 3; /* Visible to user code */ 1866 d.s = 1; /* Not a system segment */ 1867 d.p = 1; /* Present */ 1868 d.d = 1; /* 32-bit */ 1869 1870 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1871 } 1872 1873 static inline void ucode_cpu_init(int cpu) 1874 { 1875 if (cpu) 1876 load_ucode_ap(); 1877 } 1878 1879 static inline void tss_setup_ist(struct tss_struct *tss) 1880 { 1881 /* Set up the per-CPU TSS IST stacks */ 1882 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1883 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1884 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1885 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1886 /* Only mapped when SEV-ES is active */ 1887 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 1888 } 1889 1890 #else /* CONFIG_X86_64 */ 1891 1892 static inline void setup_getcpu(int cpu) { } 1893 1894 static inline void ucode_cpu_init(int cpu) 1895 { 1896 show_ucode_info_early(); 1897 } 1898 1899 static inline void tss_setup_ist(struct tss_struct *tss) { } 1900 1901 #endif /* !CONFIG_X86_64 */ 1902 1903 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 1904 { 1905 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 1906 1907 #ifdef CONFIG_X86_IOPL_IOPERM 1908 tss->io_bitmap.prev_max = 0; 1909 tss->io_bitmap.prev_sequence = 0; 1910 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 1911 /* 1912 * Invalidate the extra array entry past the end of the all 1913 * permission bitmap as required by the hardware. 1914 */ 1915 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 1916 #endif 1917 } 1918 1919 /* 1920 * Setup everything needed to handle exceptions from the IDT, including the IST 1921 * exceptions which use paranoid_entry(). 1922 */ 1923 void cpu_init_exception_handling(void) 1924 { 1925 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1926 int cpu = raw_smp_processor_id(); 1927 1928 /* paranoid_entry() gets the CPU number from the GDT */ 1929 setup_getcpu(cpu); 1930 1931 /* IST vectors need TSS to be set up. */ 1932 tss_setup_ist(tss); 1933 tss_setup_io_bitmap(tss); 1934 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1935 1936 load_TR_desc(); 1937 1938 /* Finally load the IDT */ 1939 load_current_idt(); 1940 } 1941 1942 /* 1943 * cpu_init() initializes state that is per-CPU. Some data is already 1944 * initialized (naturally) in the bootstrap process, such as the GDT. We 1945 * reload it nevertheless, this function acts as a 'CPU state barrier', 1946 * nothing should get across. 1947 */ 1948 void cpu_init(void) 1949 { 1950 struct task_struct *cur = current; 1951 int cpu = raw_smp_processor_id(); 1952 1953 wait_for_master_cpu(cpu); 1954 1955 ucode_cpu_init(cpu); 1956 1957 #ifdef CONFIG_NUMA 1958 if (this_cpu_read(numa_node) == 0 && 1959 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1960 set_numa_node(early_cpu_to_node(cpu)); 1961 #endif 1962 pr_debug("Initializing CPU#%d\n", cpu); 1963 1964 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 1965 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 1966 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1967 1968 /* 1969 * Initialize the per-CPU GDT with the boot GDT, 1970 * and set up the GDT descriptor: 1971 */ 1972 switch_to_new_gdt(cpu); 1973 1974 if (IS_ENABLED(CONFIG_X86_64)) { 1975 loadsegment(fs, 0); 1976 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1977 syscall_init(); 1978 1979 wrmsrl(MSR_FS_BASE, 0); 1980 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1981 barrier(); 1982 1983 x2apic_setup(); 1984 } 1985 1986 mmgrab(&init_mm); 1987 cur->active_mm = &init_mm; 1988 BUG_ON(cur->mm); 1989 initialize_tlbstate_and_flush(); 1990 enter_lazy_tlb(&init_mm, cur); 1991 1992 /* 1993 * sp0 points to the entry trampoline stack regardless of what task 1994 * is running. 1995 */ 1996 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1997 1998 load_mm_ldt(&init_mm); 1999 2000 clear_all_debug_regs(); 2001 dbg_restore_debug_regs(); 2002 2003 doublefault_init_cpu_tss(); 2004 2005 fpu__init_cpu(); 2006 2007 if (is_uv_system()) 2008 uv_cpu_init(); 2009 2010 load_fixmap_gdt(cpu); 2011 } 2012 2013 #ifdef CONFIG_SMP 2014 void cpu_init_secondary(void) 2015 { 2016 /* 2017 * Relies on the BP having set-up the IDT tables, which are loaded 2018 * on this CPU in cpu_init_exception_handling(). 2019 */ 2020 cpu_init_exception_handling(); 2021 cpu_init(); 2022 } 2023 #endif 2024 2025 /* 2026 * The microcode loader calls this upon late microcode load to recheck features, 2027 * only when microcode has been updated. Caller holds microcode_mutex and CPU 2028 * hotplug lock. 2029 */ 2030 void microcode_check(void) 2031 { 2032 struct cpuinfo_x86 info; 2033 2034 perf_check_microcode(); 2035 2036 /* Reload CPUID max function as it might've changed. */ 2037 info.cpuid_level = cpuid_eax(0); 2038 2039 /* 2040 * Copy all capability leafs to pick up the synthetic ones so that 2041 * memcmp() below doesn't fail on that. The ones coming from CPUID will 2042 * get overwritten in get_cpu_cap(). 2043 */ 2044 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 2045 2046 get_cpu_cap(&info); 2047 2048 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 2049 return; 2050 2051 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2052 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2053 } 2054 2055 /* 2056 * Invoked from core CPU hotplug code after hotplug operations 2057 */ 2058 void arch_smt_update(void) 2059 { 2060 /* Handle the speculative execution misfeatures */ 2061 cpu_bugs_smt_update(); 2062 /* Check whether IPI broadcasting can be enabled */ 2063 apic_smt_update(); 2064 } 2065