1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_event.h> 17 #include <asm/mmu_context.h> 18 #include <asm/archrandom.h> 19 #include <asm/hypervisor.h> 20 #include <asm/processor.h> 21 #include <asm/debugreg.h> 22 #include <asm/sections.h> 23 #include <linux/topology.h> 24 #include <linux/cpumask.h> 25 #include <asm/pgtable.h> 26 #include <linux/atomic.h> 27 #include <asm/proto.h> 28 #include <asm/setup.h> 29 #include <asm/apic.h> 30 #include <asm/desc.h> 31 #include <asm/i387.h> 32 #include <asm/fpu-internal.h> 33 #include <asm/mtrr.h> 34 #include <linux/numa.h> 35 #include <asm/asm.h> 36 #include <asm/cpu.h> 37 #include <asm/mce.h> 38 #include <asm/msr.h> 39 #include <asm/pat.h> 40 41 #ifdef CONFIG_X86_LOCAL_APIC 42 #include <asm/uv/uv.h> 43 #endif 44 45 #include "cpu.h" 46 47 /* all of these masks are initialized in setup_cpu_local_masks() */ 48 cpumask_var_t cpu_initialized_mask; 49 cpumask_var_t cpu_callout_mask; 50 cpumask_var_t cpu_callin_mask; 51 52 /* representing cpus for which sibling maps can be computed */ 53 cpumask_var_t cpu_sibling_setup_mask; 54 55 /* correctly size the local cpu masks */ 56 void __init setup_cpu_local_masks(void) 57 { 58 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 59 alloc_bootmem_cpumask_var(&cpu_callin_mask); 60 alloc_bootmem_cpumask_var(&cpu_callout_mask); 61 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 62 } 63 64 static void __cpuinit default_init(struct cpuinfo_x86 *c) 65 { 66 #ifdef CONFIG_X86_64 67 cpu_detect_cache_sizes(c); 68 #else 69 /* Not much we can do here... */ 70 /* Check if at least it has cpuid */ 71 if (c->cpuid_level == -1) { 72 /* No cpuid. It must be an ancient CPU */ 73 if (c->x86 == 4) 74 strcpy(c->x86_model_id, "486"); 75 else if (c->x86 == 3) 76 strcpy(c->x86_model_id, "386"); 77 } 78 #endif 79 } 80 81 static const struct cpu_dev __cpuinitconst default_cpu = { 82 .c_init = default_init, 83 .c_vendor = "Unknown", 84 .c_x86_vendor = X86_VENDOR_UNKNOWN, 85 }; 86 87 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; 88 89 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 90 #ifdef CONFIG_X86_64 91 /* 92 * We need valid kernel segments for data and code in long mode too 93 * IRET will check the segment types kkeil 2000/10/28 94 * Also sysret mandates a special GDT layout 95 * 96 * TLS descriptors are currently at a different place compared to i386. 97 * Hopefully nobody expects them at a fixed place (Wine?) 98 */ 99 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 100 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 101 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 102 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 103 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 104 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 105 #else 106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 110 /* 111 * Segments used for calling PnP BIOS have byte granularity. 112 * They code segments and data segments have fixed 64k limits, 113 * the transfer segment sizes are set at run time. 114 */ 115 /* 32-bit code */ 116 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 117 /* 16-bit code */ 118 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 119 /* 16-bit data */ 120 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 121 /* 16-bit data */ 122 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 123 /* 16-bit data */ 124 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 125 /* 126 * The APM segments have byte granularity and their bases 127 * are set at run time. All have 64k limits. 128 */ 129 /* 32-bit code */ 130 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 131 /* 16-bit code */ 132 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 133 /* data */ 134 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 135 136 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 137 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 138 GDT_STACK_CANARY_INIT 139 #endif 140 } }; 141 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 142 143 static int __init x86_xsave_setup(char *s) 144 { 145 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 146 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 147 setup_clear_cpu_cap(X86_FEATURE_AVX); 148 setup_clear_cpu_cap(X86_FEATURE_AVX2); 149 return 1; 150 } 151 __setup("noxsave", x86_xsave_setup); 152 153 static int __init x86_xsaveopt_setup(char *s) 154 { 155 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 156 return 1; 157 } 158 __setup("noxsaveopt", x86_xsaveopt_setup); 159 160 #ifdef CONFIG_X86_32 161 static int cachesize_override __cpuinitdata = -1; 162 static int disable_x86_serial_nr __cpuinitdata = 1; 163 164 static int __init cachesize_setup(char *str) 165 { 166 get_option(&str, &cachesize_override); 167 return 1; 168 } 169 __setup("cachesize=", cachesize_setup); 170 171 static int __init x86_fxsr_setup(char *s) 172 { 173 setup_clear_cpu_cap(X86_FEATURE_FXSR); 174 setup_clear_cpu_cap(X86_FEATURE_XMM); 175 return 1; 176 } 177 __setup("nofxsr", x86_fxsr_setup); 178 179 static int __init x86_sep_setup(char *s) 180 { 181 setup_clear_cpu_cap(X86_FEATURE_SEP); 182 return 1; 183 } 184 __setup("nosep", x86_sep_setup); 185 186 /* Standard macro to see if a specific flag is changeable */ 187 static inline int flag_is_changeable_p(u32 flag) 188 { 189 u32 f1, f2; 190 191 /* 192 * Cyrix and IDT cpus allow disabling of CPUID 193 * so the code below may return different results 194 * when it is executed before and after enabling 195 * the CPUID. Add "volatile" to not allow gcc to 196 * optimize the subsequent calls to this function. 197 */ 198 asm volatile ("pushfl \n\t" 199 "pushfl \n\t" 200 "popl %0 \n\t" 201 "movl %0, %1 \n\t" 202 "xorl %2, %0 \n\t" 203 "pushl %0 \n\t" 204 "popfl \n\t" 205 "pushfl \n\t" 206 "popl %0 \n\t" 207 "popfl \n\t" 208 209 : "=&r" (f1), "=&r" (f2) 210 : "ir" (flag)); 211 212 return ((f1^f2) & flag) != 0; 213 } 214 215 /* Probe for the CPUID instruction */ 216 static int __cpuinit have_cpuid_p(void) 217 { 218 return flag_is_changeable_p(X86_EFLAGS_ID); 219 } 220 221 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 222 { 223 unsigned long lo, hi; 224 225 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 226 return; 227 228 /* Disable processor serial number: */ 229 230 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 231 lo |= 0x200000; 232 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 233 234 printk(KERN_NOTICE "CPU serial number disabled.\n"); 235 clear_cpu_cap(c, X86_FEATURE_PN); 236 237 /* Disabling the serial number may affect the cpuid level */ 238 c->cpuid_level = cpuid_eax(0); 239 } 240 241 static int __init x86_serial_nr_setup(char *s) 242 { 243 disable_x86_serial_nr = 0; 244 return 1; 245 } 246 __setup("serialnumber", x86_serial_nr_setup); 247 #else 248 static inline int flag_is_changeable_p(u32 flag) 249 { 250 return 1; 251 } 252 /* Probe for the CPUID instruction */ 253 static inline int have_cpuid_p(void) 254 { 255 return 1; 256 } 257 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 258 { 259 } 260 #endif 261 262 static int disable_smep __cpuinitdata; 263 static __init int setup_disable_smep(char *arg) 264 { 265 disable_smep = 1; 266 return 1; 267 } 268 __setup("nosmep", setup_disable_smep); 269 270 static __cpuinit void setup_smep(struct cpuinfo_x86 *c) 271 { 272 if (cpu_has(c, X86_FEATURE_SMEP)) { 273 if (unlikely(disable_smep)) { 274 setup_clear_cpu_cap(X86_FEATURE_SMEP); 275 clear_in_cr4(X86_CR4_SMEP); 276 } else 277 set_in_cr4(X86_CR4_SMEP); 278 } 279 } 280 281 /* 282 * Some CPU features depend on higher CPUID levels, which may not always 283 * be available due to CPUID level capping or broken virtualization 284 * software. Add those features to this table to auto-disable them. 285 */ 286 struct cpuid_dependent_feature { 287 u32 feature; 288 u32 level; 289 }; 290 291 static const struct cpuid_dependent_feature __cpuinitconst 292 cpuid_dependent_features[] = { 293 { X86_FEATURE_MWAIT, 0x00000005 }, 294 { X86_FEATURE_DCA, 0x00000009 }, 295 { X86_FEATURE_XSAVE, 0x0000000d }, 296 { 0, 0 } 297 }; 298 299 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 300 { 301 const struct cpuid_dependent_feature *df; 302 303 for (df = cpuid_dependent_features; df->feature; df++) { 304 305 if (!cpu_has(c, df->feature)) 306 continue; 307 /* 308 * Note: cpuid_level is set to -1 if unavailable, but 309 * extended_extended_level is set to 0 if unavailable 310 * and the legitimate extended levels are all negative 311 * when signed; hence the weird messing around with 312 * signs here... 313 */ 314 if (!((s32)df->level < 0 ? 315 (u32)df->level > (u32)c->extended_cpuid_level : 316 (s32)df->level > (s32)c->cpuid_level)) 317 continue; 318 319 clear_cpu_cap(c, df->feature); 320 if (!warn) 321 continue; 322 323 printk(KERN_WARNING 324 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 325 x86_cap_flags[df->feature], df->level); 326 } 327 } 328 329 /* 330 * Naming convention should be: <Name> [(<Codename>)] 331 * This table only is used unless init_<vendor>() below doesn't set it; 332 * in particular, if CPUID levels 0x80000002..4 are supported, this 333 * isn't used 334 */ 335 336 /* Look up CPU names by table lookup. */ 337 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 338 { 339 const struct cpu_model_info *info; 340 341 if (c->x86_model >= 16) 342 return NULL; /* Range check */ 343 344 if (!this_cpu) 345 return NULL; 346 347 info = this_cpu->c_models; 348 349 while (info && info->family) { 350 if (info->family == c->x86) 351 return info->model_names[c->x86_model]; 352 info++; 353 } 354 return NULL; /* Not found */ 355 } 356 357 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; 358 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; 359 360 void load_percpu_segment(int cpu) 361 { 362 #ifdef CONFIG_X86_32 363 loadsegment(fs, __KERNEL_PERCPU); 364 #else 365 loadsegment(gs, 0); 366 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 367 #endif 368 load_stack_canary_segment(); 369 } 370 371 /* 372 * Current gdt points %fs at the "master" per-cpu area: after this, 373 * it's on the real one. 374 */ 375 void switch_to_new_gdt(int cpu) 376 { 377 struct desc_ptr gdt_descr; 378 379 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 380 gdt_descr.size = GDT_SIZE - 1; 381 load_gdt(&gdt_descr); 382 /* Reload the per-cpu base */ 383 384 load_percpu_segment(cpu); 385 } 386 387 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 388 389 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 390 { 391 unsigned int *v; 392 char *p, *q; 393 394 if (c->extended_cpuid_level < 0x80000004) 395 return; 396 397 v = (unsigned int *)c->x86_model_id; 398 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 399 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 400 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 401 c->x86_model_id[48] = 0; 402 403 /* 404 * Intel chips right-justify this string for some dumb reason; 405 * undo that brain damage: 406 */ 407 p = q = &c->x86_model_id[0]; 408 while (*p == ' ') 409 p++; 410 if (p != q) { 411 while (*p) 412 *q++ = *p++; 413 while (q <= &c->x86_model_id[48]) 414 *q++ = '\0'; /* Zero-pad the rest */ 415 } 416 } 417 418 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 419 { 420 unsigned int n, dummy, ebx, ecx, edx, l2size; 421 422 n = c->extended_cpuid_level; 423 424 if (n >= 0x80000005) { 425 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 426 c->x86_cache_size = (ecx>>24) + (edx>>24); 427 #ifdef CONFIG_X86_64 428 /* On K8 L1 TLB is inclusive, so don't count it */ 429 c->x86_tlbsize = 0; 430 #endif 431 } 432 433 if (n < 0x80000006) /* Some chips just has a large L1. */ 434 return; 435 436 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 437 l2size = ecx >> 16; 438 439 #ifdef CONFIG_X86_64 440 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 441 #else 442 /* do processor-specific cache resizing */ 443 if (this_cpu->c_size_cache) 444 l2size = this_cpu->c_size_cache(c, l2size); 445 446 /* Allow user to override all this if necessary. */ 447 if (cachesize_override != -1) 448 l2size = cachesize_override; 449 450 if (l2size == 0) 451 return; /* Again, no L2 cache is possible */ 452 #endif 453 454 c->x86_cache_size = l2size; 455 } 456 457 u16 __read_mostly tlb_lli_4k[NR_INFO]; 458 u16 __read_mostly tlb_lli_2m[NR_INFO]; 459 u16 __read_mostly tlb_lli_4m[NR_INFO]; 460 u16 __read_mostly tlb_lld_4k[NR_INFO]; 461 u16 __read_mostly tlb_lld_2m[NR_INFO]; 462 u16 __read_mostly tlb_lld_4m[NR_INFO]; 463 464 /* 465 * tlb_flushall_shift shows the balance point in replacing cr3 write 466 * with multiple 'invlpg'. It will do this replacement when 467 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. 468 * If tlb_flushall_shift is -1, means the replacement will be disabled. 469 */ 470 s8 __read_mostly tlb_flushall_shift = -1; 471 472 void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c) 473 { 474 if (this_cpu->c_detect_tlb) 475 this_cpu->c_detect_tlb(c); 476 477 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 478 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 479 "tlb_flushall_shift is 0x%x\n", 480 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 481 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], 482 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], 483 tlb_flushall_shift); 484 } 485 486 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 487 { 488 #ifdef CONFIG_X86_HT 489 u32 eax, ebx, ecx, edx; 490 int index_msb, core_bits; 491 static bool printed; 492 493 if (!cpu_has(c, X86_FEATURE_HT)) 494 return; 495 496 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 497 goto out; 498 499 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 500 return; 501 502 cpuid(1, &eax, &ebx, &ecx, &edx); 503 504 smp_num_siblings = (ebx & 0xff0000) >> 16; 505 506 if (smp_num_siblings == 1) { 507 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 508 goto out; 509 } 510 511 if (smp_num_siblings <= 1) 512 goto out; 513 514 index_msb = get_count_order(smp_num_siblings); 515 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 516 517 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 518 519 index_msb = get_count_order(smp_num_siblings); 520 521 core_bits = get_count_order(c->x86_max_cores); 522 523 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 524 ((1 << core_bits) - 1); 525 526 out: 527 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 528 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 529 c->phys_proc_id); 530 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 531 c->cpu_core_id); 532 printed = 1; 533 } 534 #endif 535 } 536 537 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 538 { 539 char *v = c->x86_vendor_id; 540 int i; 541 542 for (i = 0; i < X86_VENDOR_NUM; i++) { 543 if (!cpu_devs[i]) 544 break; 545 546 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 547 (cpu_devs[i]->c_ident[1] && 548 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 549 550 this_cpu = cpu_devs[i]; 551 c->x86_vendor = this_cpu->c_x86_vendor; 552 return; 553 } 554 } 555 556 printk_once(KERN_ERR 557 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 558 "CPU: Your system may be unstable.\n", v); 559 560 c->x86_vendor = X86_VENDOR_UNKNOWN; 561 this_cpu = &default_cpu; 562 } 563 564 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 565 { 566 /* Get vendor name */ 567 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 568 (unsigned int *)&c->x86_vendor_id[0], 569 (unsigned int *)&c->x86_vendor_id[8], 570 (unsigned int *)&c->x86_vendor_id[4]); 571 572 c->x86 = 4; 573 /* Intel-defined flags: level 0x00000001 */ 574 if (c->cpuid_level >= 0x00000001) { 575 u32 junk, tfms, cap0, misc; 576 577 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 578 c->x86 = (tfms >> 8) & 0xf; 579 c->x86_model = (tfms >> 4) & 0xf; 580 c->x86_mask = tfms & 0xf; 581 582 if (c->x86 == 0xf) 583 c->x86 += (tfms >> 20) & 0xff; 584 if (c->x86 >= 0x6) 585 c->x86_model += ((tfms >> 16) & 0xf) << 4; 586 587 if (cap0 & (1<<19)) { 588 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 589 c->x86_cache_alignment = c->x86_clflush_size; 590 } 591 } 592 } 593 594 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 595 { 596 u32 tfms, xlvl; 597 u32 ebx; 598 599 /* Intel-defined flags: level 0x00000001 */ 600 if (c->cpuid_level >= 0x00000001) { 601 u32 capability, excap; 602 603 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 604 c->x86_capability[0] = capability; 605 c->x86_capability[4] = excap; 606 } 607 608 /* Additional Intel-defined flags: level 0x00000007 */ 609 if (c->cpuid_level >= 0x00000007) { 610 u32 eax, ebx, ecx, edx; 611 612 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 613 614 c->x86_capability[9] = ebx; 615 } 616 617 /* AMD-defined flags: level 0x80000001 */ 618 xlvl = cpuid_eax(0x80000000); 619 c->extended_cpuid_level = xlvl; 620 621 if ((xlvl & 0xffff0000) == 0x80000000) { 622 if (xlvl >= 0x80000001) { 623 c->x86_capability[1] = cpuid_edx(0x80000001); 624 c->x86_capability[6] = cpuid_ecx(0x80000001); 625 } 626 } 627 628 if (c->extended_cpuid_level >= 0x80000008) { 629 u32 eax = cpuid_eax(0x80000008); 630 631 c->x86_virt_bits = (eax >> 8) & 0xff; 632 c->x86_phys_bits = eax & 0xff; 633 } 634 #ifdef CONFIG_X86_32 635 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 636 c->x86_phys_bits = 36; 637 #endif 638 639 if (c->extended_cpuid_level >= 0x80000007) 640 c->x86_power = cpuid_edx(0x80000007); 641 642 init_scattered_cpuid_features(c); 643 } 644 645 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 646 { 647 #ifdef CONFIG_X86_32 648 int i; 649 650 /* 651 * First of all, decide if this is a 486 or higher 652 * It's a 486 if we can modify the AC flag 653 */ 654 if (flag_is_changeable_p(X86_EFLAGS_AC)) 655 c->x86 = 4; 656 else 657 c->x86 = 3; 658 659 for (i = 0; i < X86_VENDOR_NUM; i++) 660 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 661 c->x86_vendor_id[0] = 0; 662 cpu_devs[i]->c_identify(c); 663 if (c->x86_vendor_id[0]) { 664 get_cpu_vendor(c); 665 break; 666 } 667 } 668 #endif 669 } 670 671 /* 672 * Do minimum CPU detection early. 673 * Fields really needed: vendor, cpuid_level, family, model, mask, 674 * cache alignment. 675 * The others are not touched to avoid unwanted side effects. 676 * 677 * WARNING: this function is only called on the BP. Don't add code here 678 * that is supposed to run on all CPUs. 679 */ 680 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 681 { 682 #ifdef CONFIG_X86_64 683 c->x86_clflush_size = 64; 684 c->x86_phys_bits = 36; 685 c->x86_virt_bits = 48; 686 #else 687 c->x86_clflush_size = 32; 688 c->x86_phys_bits = 32; 689 c->x86_virt_bits = 32; 690 #endif 691 c->x86_cache_alignment = c->x86_clflush_size; 692 693 memset(&c->x86_capability, 0, sizeof c->x86_capability); 694 c->extended_cpuid_level = 0; 695 696 if (!have_cpuid_p()) 697 identify_cpu_without_cpuid(c); 698 699 /* cyrix could have cpuid enabled via c_identify()*/ 700 if (!have_cpuid_p()) 701 return; 702 703 cpu_detect(c); 704 705 get_cpu_vendor(c); 706 707 get_cpu_cap(c); 708 709 if (this_cpu->c_early_init) 710 this_cpu->c_early_init(c); 711 712 c->cpu_index = 0; 713 filter_cpuid_features(c, false); 714 715 setup_smep(c); 716 717 if (this_cpu->c_bsp_init) 718 this_cpu->c_bsp_init(c); 719 } 720 721 void __init early_cpu_init(void) 722 { 723 const struct cpu_dev *const *cdev; 724 int count = 0; 725 726 #ifdef CONFIG_PROCESSOR_SELECT 727 printk(KERN_INFO "KERNEL supported cpus:\n"); 728 #endif 729 730 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 731 const struct cpu_dev *cpudev = *cdev; 732 733 if (count >= X86_VENDOR_NUM) 734 break; 735 cpu_devs[count] = cpudev; 736 count++; 737 738 #ifdef CONFIG_PROCESSOR_SELECT 739 { 740 unsigned int j; 741 742 for (j = 0; j < 2; j++) { 743 if (!cpudev->c_ident[j]) 744 continue; 745 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 746 cpudev->c_ident[j]); 747 } 748 } 749 #endif 750 } 751 early_identify_cpu(&boot_cpu_data); 752 } 753 754 /* 755 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 756 * unfortunately, that's not true in practice because of early VIA 757 * chips and (more importantly) broken virtualizers that are not easy 758 * to detect. In the latter case it doesn't even *fail* reliably, so 759 * probing for it doesn't even work. Disable it completely on 32-bit 760 * unless we can find a reliable way to detect all the broken cases. 761 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 762 */ 763 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 764 { 765 #ifdef CONFIG_X86_32 766 clear_cpu_cap(c, X86_FEATURE_NOPL); 767 #else 768 set_cpu_cap(c, X86_FEATURE_NOPL); 769 #endif 770 } 771 772 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 773 { 774 c->extended_cpuid_level = 0; 775 776 if (!have_cpuid_p()) 777 identify_cpu_without_cpuid(c); 778 779 /* cyrix could have cpuid enabled via c_identify()*/ 780 if (!have_cpuid_p()) 781 return; 782 783 cpu_detect(c); 784 785 get_cpu_vendor(c); 786 787 get_cpu_cap(c); 788 789 if (c->cpuid_level >= 0x00000001) { 790 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 791 #ifdef CONFIG_X86_32 792 # ifdef CONFIG_X86_HT 793 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 794 # else 795 c->apicid = c->initial_apicid; 796 # endif 797 #endif 798 c->phys_proc_id = c->initial_apicid; 799 } 800 801 setup_smep(c); 802 803 get_model_name(c); /* Default name */ 804 805 detect_nopl(c); 806 } 807 808 /* 809 * This does the hard work of actually picking apart the CPU stuff... 810 */ 811 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 812 { 813 int i; 814 815 c->loops_per_jiffy = loops_per_jiffy; 816 c->x86_cache_size = -1; 817 c->x86_vendor = X86_VENDOR_UNKNOWN; 818 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 819 c->x86_vendor_id[0] = '\0'; /* Unset */ 820 c->x86_model_id[0] = '\0'; /* Unset */ 821 c->x86_max_cores = 1; 822 c->x86_coreid_bits = 0; 823 #ifdef CONFIG_X86_64 824 c->x86_clflush_size = 64; 825 c->x86_phys_bits = 36; 826 c->x86_virt_bits = 48; 827 #else 828 c->cpuid_level = -1; /* CPUID not detected */ 829 c->x86_clflush_size = 32; 830 c->x86_phys_bits = 32; 831 c->x86_virt_bits = 32; 832 #endif 833 c->x86_cache_alignment = c->x86_clflush_size; 834 memset(&c->x86_capability, 0, sizeof c->x86_capability); 835 836 generic_identify(c); 837 838 if (this_cpu->c_identify) 839 this_cpu->c_identify(c); 840 841 /* Clear/Set all flags overriden by options, after probe */ 842 for (i = 0; i < NCAPINTS; i++) { 843 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 844 c->x86_capability[i] |= cpu_caps_set[i]; 845 } 846 847 #ifdef CONFIG_X86_64 848 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 849 #endif 850 851 /* 852 * Vendor-specific initialization. In this section we 853 * canonicalize the feature flags, meaning if there are 854 * features a certain CPU supports which CPUID doesn't 855 * tell us, CPUID claiming incorrect flags, or other bugs, 856 * we handle them here. 857 * 858 * At the end of this section, c->x86_capability better 859 * indicate the features this CPU genuinely supports! 860 */ 861 if (this_cpu->c_init) 862 this_cpu->c_init(c); 863 864 /* Disable the PN if appropriate */ 865 squash_the_stupid_serial_number(c); 866 867 /* 868 * The vendor-specific functions might have changed features. 869 * Now we do "generic changes." 870 */ 871 872 /* Filter out anything that depends on CPUID levels we don't have */ 873 filter_cpuid_features(c, true); 874 875 /* If the model name is still unset, do table lookup. */ 876 if (!c->x86_model_id[0]) { 877 const char *p; 878 p = table_lookup_model(c); 879 if (p) 880 strcpy(c->x86_model_id, p); 881 else 882 /* Last resort... */ 883 sprintf(c->x86_model_id, "%02x/%02x", 884 c->x86, c->x86_model); 885 } 886 887 #ifdef CONFIG_X86_64 888 detect_ht(c); 889 #endif 890 891 init_hypervisor(c); 892 x86_init_rdrand(c); 893 894 /* 895 * Clear/Set all flags overriden by options, need do it 896 * before following smp all cpus cap AND. 897 */ 898 for (i = 0; i < NCAPINTS; i++) { 899 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 900 c->x86_capability[i] |= cpu_caps_set[i]; 901 } 902 903 /* 904 * On SMP, boot_cpu_data holds the common feature set between 905 * all CPUs; so make sure that we indicate which features are 906 * common between the CPUs. The first time this routine gets 907 * executed, c == &boot_cpu_data. 908 */ 909 if (c != &boot_cpu_data) { 910 /* AND the already accumulated flags with these */ 911 for (i = 0; i < NCAPINTS; i++) 912 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 913 } 914 915 /* Init Machine Check Exception if available. */ 916 mcheck_cpu_init(c); 917 918 select_idle_routine(c); 919 920 #ifdef CONFIG_NUMA 921 numa_add_cpu(smp_processor_id()); 922 #endif 923 } 924 925 #ifdef CONFIG_X86_64 926 static void vgetcpu_set_mode(void) 927 { 928 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 929 vgetcpu_mode = VGETCPU_RDTSCP; 930 else 931 vgetcpu_mode = VGETCPU_LSL; 932 } 933 #endif 934 935 void __init identify_boot_cpu(void) 936 { 937 identify_cpu(&boot_cpu_data); 938 init_amd_e400_c1e_mask(); 939 #ifdef CONFIG_X86_32 940 sysenter_setup(); 941 enable_sep_cpu(); 942 #else 943 vgetcpu_set_mode(); 944 #endif 945 if (boot_cpu_data.cpuid_level >= 2) 946 cpu_detect_tlb(&boot_cpu_data); 947 } 948 949 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 950 { 951 BUG_ON(c == &boot_cpu_data); 952 identify_cpu(c); 953 #ifdef CONFIG_X86_32 954 enable_sep_cpu(); 955 #endif 956 mtrr_ap_init(); 957 } 958 959 struct msr_range { 960 unsigned min; 961 unsigned max; 962 }; 963 964 static const struct msr_range msr_range_array[] __cpuinitconst = { 965 { 0x00000000, 0x00000418}, 966 { 0xc0000000, 0xc000040b}, 967 { 0xc0010000, 0xc0010142}, 968 { 0xc0011000, 0xc001103b}, 969 }; 970 971 static void __cpuinit __print_cpu_msr(void) 972 { 973 unsigned index_min, index_max; 974 unsigned index; 975 u64 val; 976 int i; 977 978 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 979 index_min = msr_range_array[i].min; 980 index_max = msr_range_array[i].max; 981 982 for (index = index_min; index < index_max; index++) { 983 if (rdmsrl_safe(index, &val)) 984 continue; 985 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 986 } 987 } 988 } 989 990 static int show_msr __cpuinitdata; 991 992 static __init int setup_show_msr(char *arg) 993 { 994 int num; 995 996 get_option(&arg, &num); 997 998 if (num > 0) 999 show_msr = num; 1000 return 1; 1001 } 1002 __setup("show_msr=", setup_show_msr); 1003 1004 static __init int setup_noclflush(char *arg) 1005 { 1006 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 1007 return 1; 1008 } 1009 __setup("noclflush", setup_noclflush); 1010 1011 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 1012 { 1013 const char *vendor = NULL; 1014 1015 if (c->x86_vendor < X86_VENDOR_NUM) { 1016 vendor = this_cpu->c_vendor; 1017 } else { 1018 if (c->cpuid_level >= 0) 1019 vendor = c->x86_vendor_id; 1020 } 1021 1022 if (vendor && !strstr(c->x86_model_id, vendor)) 1023 printk(KERN_CONT "%s ", vendor); 1024 1025 if (c->x86_model_id[0]) 1026 printk(KERN_CONT "%s", c->x86_model_id); 1027 else 1028 printk(KERN_CONT "%d86", c->x86); 1029 1030 if (c->x86_mask || c->cpuid_level >= 0) 1031 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 1032 else 1033 printk(KERN_CONT "\n"); 1034 1035 print_cpu_msr(c); 1036 } 1037 1038 void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c) 1039 { 1040 if (c->cpu_index < show_msr) 1041 __print_cpu_msr(); 1042 } 1043 1044 static __init int setup_disablecpuid(char *arg) 1045 { 1046 int bit; 1047 1048 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1049 setup_clear_cpu_cap(bit); 1050 else 1051 return 0; 1052 1053 return 1; 1054 } 1055 __setup("clearcpuid=", setup_disablecpuid); 1056 1057 #ifdef CONFIG_X86_64 1058 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1059 struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1, 1060 (unsigned long) nmi_idt_table }; 1061 1062 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1063 irq_stack_union) __aligned(PAGE_SIZE); 1064 1065 /* 1066 * The following four percpu variables are hot. Align current_task to 1067 * cacheline size such that all four fall in the same cacheline. 1068 */ 1069 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1070 &init_task; 1071 EXPORT_PER_CPU_SYMBOL(current_task); 1072 1073 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1074 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1075 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1076 1077 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1078 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1079 1080 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 1081 1082 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1083 1084 /* 1085 * Special IST stacks which the CPU switches to when it calls 1086 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1087 * limit), all of them are 4K, except the debug stack which 1088 * is 8K. 1089 */ 1090 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1091 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1092 [DEBUG_STACK - 1] = DEBUG_STKSZ 1093 }; 1094 1095 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1096 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1097 1098 /* May not be marked __init: used by software suspend */ 1099 void syscall_init(void) 1100 { 1101 /* 1102 * LSTAR and STAR live in a bit strange symbiosis. 1103 * They both write to the same internal register. STAR allows to 1104 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1105 */ 1106 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1107 wrmsrl(MSR_LSTAR, system_call); 1108 wrmsrl(MSR_CSTAR, ignore_sysret); 1109 1110 #ifdef CONFIG_IA32_EMULATION 1111 syscall32_cpu_init(); 1112 #endif 1113 1114 /* Flags to clear on syscall */ 1115 wrmsrl(MSR_SYSCALL_MASK, 1116 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 1117 } 1118 1119 unsigned long kernel_eflags; 1120 1121 /* 1122 * Copies of the original ist values from the tss are only accessed during 1123 * debugging, no special alignment required. 1124 */ 1125 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1126 1127 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1128 DEFINE_PER_CPU(int, debug_stack_usage); 1129 1130 int is_debug_stack(unsigned long addr) 1131 { 1132 return __get_cpu_var(debug_stack_usage) || 1133 (addr <= __get_cpu_var(debug_stack_addr) && 1134 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); 1135 } 1136 1137 static DEFINE_PER_CPU(u32, debug_stack_use_ctr); 1138 1139 void debug_stack_set_zero(void) 1140 { 1141 this_cpu_inc(debug_stack_use_ctr); 1142 load_idt((const struct desc_ptr *)&nmi_idt_descr); 1143 } 1144 1145 void debug_stack_reset(void) 1146 { 1147 if (WARN_ON(!this_cpu_read(debug_stack_use_ctr))) 1148 return; 1149 if (this_cpu_dec_return(debug_stack_use_ctr) == 0) 1150 load_idt((const struct desc_ptr *)&idt_descr); 1151 } 1152 1153 #else /* CONFIG_X86_64 */ 1154 1155 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1156 EXPORT_PER_CPU_SYMBOL(current_task); 1157 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1158 1159 #ifdef CONFIG_CC_STACKPROTECTOR 1160 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1161 #endif 1162 1163 /* Make sure %fs and %gs are initialized properly in idle threads */ 1164 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 1165 { 1166 memset(regs, 0, sizeof(struct pt_regs)); 1167 regs->fs = __KERNEL_PERCPU; 1168 regs->gs = __KERNEL_STACK_CANARY; 1169 1170 return regs; 1171 } 1172 #endif /* CONFIG_X86_64 */ 1173 1174 /* 1175 * Clear all 6 debug registers: 1176 */ 1177 static void clear_all_debug_regs(void) 1178 { 1179 int i; 1180 1181 for (i = 0; i < 8; i++) { 1182 /* Ignore db4, db5 */ 1183 if ((i == 4) || (i == 5)) 1184 continue; 1185 1186 set_debugreg(0, i); 1187 } 1188 } 1189 1190 #ifdef CONFIG_KGDB 1191 /* 1192 * Restore debug regs if using kgdbwait and you have a kernel debugger 1193 * connection established. 1194 */ 1195 static void dbg_restore_debug_regs(void) 1196 { 1197 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1198 arch_kgdb_ops.correct_hw_break(); 1199 } 1200 #else /* ! CONFIG_KGDB */ 1201 #define dbg_restore_debug_regs() 1202 #endif /* ! CONFIG_KGDB */ 1203 1204 /* 1205 * cpu_init() initializes state that is per-CPU. Some data is already 1206 * initialized (naturally) in the bootstrap process, such as the GDT 1207 * and IDT. We reload them nevertheless, this function acts as a 1208 * 'CPU state barrier', nothing should get across. 1209 * A lot of state is already set up in PDA init for 64 bit 1210 */ 1211 #ifdef CONFIG_X86_64 1212 1213 void __cpuinit cpu_init(void) 1214 { 1215 struct orig_ist *oist; 1216 struct task_struct *me; 1217 struct tss_struct *t; 1218 unsigned long v; 1219 int cpu; 1220 int i; 1221 1222 cpu = stack_smp_processor_id(); 1223 t = &per_cpu(init_tss, cpu); 1224 oist = &per_cpu(orig_ist, cpu); 1225 1226 #ifdef CONFIG_NUMA 1227 if (cpu != 0 && this_cpu_read(numa_node) == 0 && 1228 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1229 set_numa_node(early_cpu_to_node(cpu)); 1230 #endif 1231 1232 me = current; 1233 1234 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1235 panic("CPU#%d already initialized!\n", cpu); 1236 1237 pr_debug("Initializing CPU#%d\n", cpu); 1238 1239 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1240 1241 /* 1242 * Initialize the per-CPU GDT with the boot GDT, 1243 * and set up the GDT descriptor: 1244 */ 1245 1246 switch_to_new_gdt(cpu); 1247 loadsegment(fs, 0); 1248 1249 load_idt((const struct desc_ptr *)&idt_descr); 1250 1251 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1252 syscall_init(); 1253 1254 wrmsrl(MSR_FS_BASE, 0); 1255 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1256 barrier(); 1257 1258 x86_configure_nx(); 1259 if (cpu != 0) 1260 enable_x2apic(); 1261 1262 /* 1263 * set up and load the per-CPU TSS 1264 */ 1265 if (!oist->ist[0]) { 1266 char *estacks = per_cpu(exception_stacks, cpu); 1267 1268 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1269 estacks += exception_stack_sizes[v]; 1270 oist->ist[v] = t->x86_tss.ist[v] = 1271 (unsigned long)estacks; 1272 if (v == DEBUG_STACK-1) 1273 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1274 } 1275 } 1276 1277 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1278 1279 /* 1280 * <= is required because the CPU will access up to 1281 * 8 bits beyond the end of the IO permission bitmap. 1282 */ 1283 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1284 t->io_bitmap[i] = ~0UL; 1285 1286 atomic_inc(&init_mm.mm_count); 1287 me->active_mm = &init_mm; 1288 BUG_ON(me->mm); 1289 enter_lazy_tlb(&init_mm, me); 1290 1291 load_sp0(t, ¤t->thread); 1292 set_tss_desc(cpu, t); 1293 load_TR_desc(); 1294 load_LDT(&init_mm.context); 1295 1296 clear_all_debug_regs(); 1297 dbg_restore_debug_regs(); 1298 1299 fpu_init(); 1300 xsave_init(); 1301 1302 raw_local_save_flags(kernel_eflags); 1303 1304 if (is_uv_system()) 1305 uv_cpu_init(); 1306 } 1307 1308 #else 1309 1310 void __cpuinit cpu_init(void) 1311 { 1312 int cpu = smp_processor_id(); 1313 struct task_struct *curr = current; 1314 struct tss_struct *t = &per_cpu(init_tss, cpu); 1315 struct thread_struct *thread = &curr->thread; 1316 1317 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1318 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1319 for (;;) 1320 local_irq_enable(); 1321 } 1322 1323 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1324 1325 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1326 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1327 1328 load_idt(&idt_descr); 1329 switch_to_new_gdt(cpu); 1330 1331 /* 1332 * Set up and load the per-CPU TSS and LDT 1333 */ 1334 atomic_inc(&init_mm.mm_count); 1335 curr->active_mm = &init_mm; 1336 BUG_ON(curr->mm); 1337 enter_lazy_tlb(&init_mm, curr); 1338 1339 load_sp0(t, thread); 1340 set_tss_desc(cpu, t); 1341 load_TR_desc(); 1342 load_LDT(&init_mm.context); 1343 1344 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1345 1346 #ifdef CONFIG_DOUBLEFAULT 1347 /* Set up doublefault TSS pointer in the GDT */ 1348 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1349 #endif 1350 1351 clear_all_debug_regs(); 1352 dbg_restore_debug_regs(); 1353 1354 fpu_init(); 1355 xsave_init(); 1356 } 1357 #endif 1358