1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_event.h> 17 #include <asm/mmu_context.h> 18 #include <asm/archrandom.h> 19 #include <asm/hypervisor.h> 20 #include <asm/processor.h> 21 #include <asm/debugreg.h> 22 #include <asm/sections.h> 23 #include <linux/topology.h> 24 #include <linux/cpumask.h> 25 #include <asm/pgtable.h> 26 #include <linux/atomic.h> 27 #include <asm/proto.h> 28 #include <asm/setup.h> 29 #include <asm/apic.h> 30 #include <asm/desc.h> 31 #include <asm/i387.h> 32 #include <asm/fpu-internal.h> 33 #include <asm/mtrr.h> 34 #include <linux/numa.h> 35 #include <asm/asm.h> 36 #include <asm/cpu.h> 37 #include <asm/mce.h> 38 #include <asm/msr.h> 39 #include <asm/pat.h> 40 #include <asm/microcode.h> 41 #include <asm/microcode_intel.h> 42 43 #ifdef CONFIG_X86_LOCAL_APIC 44 #include <asm/uv/uv.h> 45 #endif 46 47 #include "cpu.h" 48 49 /* all of these masks are initialized in setup_cpu_local_masks() */ 50 cpumask_var_t cpu_initialized_mask; 51 cpumask_var_t cpu_callout_mask; 52 cpumask_var_t cpu_callin_mask; 53 54 /* representing cpus for which sibling maps can be computed */ 55 cpumask_var_t cpu_sibling_setup_mask; 56 57 /* correctly size the local cpu masks */ 58 void __init setup_cpu_local_masks(void) 59 { 60 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 61 alloc_bootmem_cpumask_var(&cpu_callin_mask); 62 alloc_bootmem_cpumask_var(&cpu_callout_mask); 63 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 64 } 65 66 static void default_init(struct cpuinfo_x86 *c) 67 { 68 #ifdef CONFIG_X86_64 69 cpu_detect_cache_sizes(c); 70 #else 71 /* Not much we can do here... */ 72 /* Check if at least it has cpuid */ 73 if (c->cpuid_level == -1) { 74 /* No cpuid. It must be an ancient CPU */ 75 if (c->x86 == 4) 76 strcpy(c->x86_model_id, "486"); 77 else if (c->x86 == 3) 78 strcpy(c->x86_model_id, "386"); 79 } 80 #endif 81 } 82 83 static const struct cpu_dev default_cpu = { 84 .c_init = default_init, 85 .c_vendor = "Unknown", 86 .c_x86_vendor = X86_VENDOR_UNKNOWN, 87 }; 88 89 static const struct cpu_dev *this_cpu = &default_cpu; 90 91 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 92 #ifdef CONFIG_X86_64 93 /* 94 * We need valid kernel segments for data and code in long mode too 95 * IRET will check the segment types kkeil 2000/10/28 96 * Also sysret mandates a special GDT layout 97 * 98 * TLS descriptors are currently at a different place compared to i386. 99 * Hopefully nobody expects them at a fixed place (Wine?) 100 */ 101 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 102 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 103 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 104 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 105 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 107 #else 108 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 109 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 111 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 112 /* 113 * Segments used for calling PnP BIOS have byte granularity. 114 * They code segments and data segments have fixed 64k limits, 115 * the transfer segment sizes are set at run time. 116 */ 117 /* 32-bit code */ 118 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 119 /* 16-bit code */ 120 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 121 /* 16-bit data */ 122 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 123 /* 16-bit data */ 124 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 125 /* 16-bit data */ 126 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 127 /* 128 * The APM segments have byte granularity and their bases 129 * are set at run time. All have 64k limits. 130 */ 131 /* 32-bit code */ 132 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 133 /* 16-bit code */ 134 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 135 /* data */ 136 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 137 138 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 139 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 140 GDT_STACK_CANARY_INIT 141 #endif 142 } }; 143 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 144 145 static int __init x86_xsave_setup(char *s) 146 { 147 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 148 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 149 setup_clear_cpu_cap(X86_FEATURE_AVX); 150 setup_clear_cpu_cap(X86_FEATURE_AVX2); 151 return 1; 152 } 153 __setup("noxsave", x86_xsave_setup); 154 155 static int __init x86_xsaveopt_setup(char *s) 156 { 157 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 158 return 1; 159 } 160 __setup("noxsaveopt", x86_xsaveopt_setup); 161 162 #ifdef CONFIG_X86_32 163 static int cachesize_override = -1; 164 static int disable_x86_serial_nr = 1; 165 166 static int __init cachesize_setup(char *str) 167 { 168 get_option(&str, &cachesize_override); 169 return 1; 170 } 171 __setup("cachesize=", cachesize_setup); 172 173 static int __init x86_fxsr_setup(char *s) 174 { 175 setup_clear_cpu_cap(X86_FEATURE_FXSR); 176 setup_clear_cpu_cap(X86_FEATURE_XMM); 177 return 1; 178 } 179 __setup("nofxsr", x86_fxsr_setup); 180 181 static int __init x86_sep_setup(char *s) 182 { 183 setup_clear_cpu_cap(X86_FEATURE_SEP); 184 return 1; 185 } 186 __setup("nosep", x86_sep_setup); 187 188 /* Standard macro to see if a specific flag is changeable */ 189 static inline int flag_is_changeable_p(u32 flag) 190 { 191 u32 f1, f2; 192 193 /* 194 * Cyrix and IDT cpus allow disabling of CPUID 195 * so the code below may return different results 196 * when it is executed before and after enabling 197 * the CPUID. Add "volatile" to not allow gcc to 198 * optimize the subsequent calls to this function. 199 */ 200 asm volatile ("pushfl \n\t" 201 "pushfl \n\t" 202 "popl %0 \n\t" 203 "movl %0, %1 \n\t" 204 "xorl %2, %0 \n\t" 205 "pushl %0 \n\t" 206 "popfl \n\t" 207 "pushfl \n\t" 208 "popl %0 \n\t" 209 "popfl \n\t" 210 211 : "=&r" (f1), "=&r" (f2) 212 : "ir" (flag)); 213 214 return ((f1^f2) & flag) != 0; 215 } 216 217 /* Probe for the CPUID instruction */ 218 int have_cpuid_p(void) 219 { 220 return flag_is_changeable_p(X86_EFLAGS_ID); 221 } 222 223 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 224 { 225 unsigned long lo, hi; 226 227 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 228 return; 229 230 /* Disable processor serial number: */ 231 232 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 233 lo |= 0x200000; 234 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 235 236 printk(KERN_NOTICE "CPU serial number disabled.\n"); 237 clear_cpu_cap(c, X86_FEATURE_PN); 238 239 /* Disabling the serial number may affect the cpuid level */ 240 c->cpuid_level = cpuid_eax(0); 241 } 242 243 static int __init x86_serial_nr_setup(char *s) 244 { 245 disable_x86_serial_nr = 0; 246 return 1; 247 } 248 __setup("serialnumber", x86_serial_nr_setup); 249 #else 250 static inline int flag_is_changeable_p(u32 flag) 251 { 252 return 1; 253 } 254 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 255 { 256 } 257 #endif 258 259 static __init int setup_disable_smep(char *arg) 260 { 261 setup_clear_cpu_cap(X86_FEATURE_SMEP); 262 return 1; 263 } 264 __setup("nosmep", setup_disable_smep); 265 266 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 267 { 268 if (cpu_has(c, X86_FEATURE_SMEP)) 269 set_in_cr4(X86_CR4_SMEP); 270 } 271 272 static __init int setup_disable_smap(char *arg) 273 { 274 setup_clear_cpu_cap(X86_FEATURE_SMAP); 275 return 1; 276 } 277 __setup("nosmap", setup_disable_smap); 278 279 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 280 { 281 unsigned long eflags; 282 283 /* This should have been cleared long ago */ 284 raw_local_save_flags(eflags); 285 BUG_ON(eflags & X86_EFLAGS_AC); 286 287 if (cpu_has(c, X86_FEATURE_SMAP)) 288 set_in_cr4(X86_CR4_SMAP); 289 } 290 291 /* 292 * Some CPU features depend on higher CPUID levels, which may not always 293 * be available due to CPUID level capping or broken virtualization 294 * software. Add those features to this table to auto-disable them. 295 */ 296 struct cpuid_dependent_feature { 297 u32 feature; 298 u32 level; 299 }; 300 301 static const struct cpuid_dependent_feature 302 cpuid_dependent_features[] = { 303 { X86_FEATURE_MWAIT, 0x00000005 }, 304 { X86_FEATURE_DCA, 0x00000009 }, 305 { X86_FEATURE_XSAVE, 0x0000000d }, 306 { 0, 0 } 307 }; 308 309 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 310 { 311 const struct cpuid_dependent_feature *df; 312 313 for (df = cpuid_dependent_features; df->feature; df++) { 314 315 if (!cpu_has(c, df->feature)) 316 continue; 317 /* 318 * Note: cpuid_level is set to -1 if unavailable, but 319 * extended_extended_level is set to 0 if unavailable 320 * and the legitimate extended levels are all negative 321 * when signed; hence the weird messing around with 322 * signs here... 323 */ 324 if (!((s32)df->level < 0 ? 325 (u32)df->level > (u32)c->extended_cpuid_level : 326 (s32)df->level > (s32)c->cpuid_level)) 327 continue; 328 329 clear_cpu_cap(c, df->feature); 330 if (!warn) 331 continue; 332 333 printk(KERN_WARNING 334 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 335 x86_cap_flags[df->feature], df->level); 336 } 337 } 338 339 /* 340 * Naming convention should be: <Name> [(<Codename>)] 341 * This table only is used unless init_<vendor>() below doesn't set it; 342 * in particular, if CPUID levels 0x80000002..4 are supported, this 343 * isn't used 344 */ 345 346 /* Look up CPU names by table lookup. */ 347 static const char *table_lookup_model(struct cpuinfo_x86 *c) 348 { 349 #ifdef CONFIG_X86_32 350 const struct legacy_cpu_model_info *info; 351 352 if (c->x86_model >= 16) 353 return NULL; /* Range check */ 354 355 if (!this_cpu) 356 return NULL; 357 358 info = this_cpu->legacy_models; 359 360 while (info->family) { 361 if (info->family == c->x86) 362 return info->model_names[c->x86_model]; 363 info++; 364 } 365 #endif 366 return NULL; /* Not found */ 367 } 368 369 __u32 cpu_caps_cleared[NCAPINTS]; 370 __u32 cpu_caps_set[NCAPINTS]; 371 372 void load_percpu_segment(int cpu) 373 { 374 #ifdef CONFIG_X86_32 375 loadsegment(fs, __KERNEL_PERCPU); 376 #else 377 loadsegment(gs, 0); 378 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 379 #endif 380 load_stack_canary_segment(); 381 } 382 383 /* 384 * Current gdt points %fs at the "master" per-cpu area: after this, 385 * it's on the real one. 386 */ 387 void switch_to_new_gdt(int cpu) 388 { 389 struct desc_ptr gdt_descr; 390 391 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 392 gdt_descr.size = GDT_SIZE - 1; 393 load_gdt(&gdt_descr); 394 /* Reload the per-cpu base */ 395 396 load_percpu_segment(cpu); 397 } 398 399 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 400 401 static void get_model_name(struct cpuinfo_x86 *c) 402 { 403 unsigned int *v; 404 char *p, *q; 405 406 if (c->extended_cpuid_level < 0x80000004) 407 return; 408 409 v = (unsigned int *)c->x86_model_id; 410 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 411 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 412 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 413 c->x86_model_id[48] = 0; 414 415 /* 416 * Intel chips right-justify this string for some dumb reason; 417 * undo that brain damage: 418 */ 419 p = q = &c->x86_model_id[0]; 420 while (*p == ' ') 421 p++; 422 if (p != q) { 423 while (*p) 424 *q++ = *p++; 425 while (q <= &c->x86_model_id[48]) 426 *q++ = '\0'; /* Zero-pad the rest */ 427 } 428 } 429 430 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 431 { 432 unsigned int n, dummy, ebx, ecx, edx, l2size; 433 434 n = c->extended_cpuid_level; 435 436 if (n >= 0x80000005) { 437 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 438 c->x86_cache_size = (ecx>>24) + (edx>>24); 439 #ifdef CONFIG_X86_64 440 /* On K8 L1 TLB is inclusive, so don't count it */ 441 c->x86_tlbsize = 0; 442 #endif 443 } 444 445 if (n < 0x80000006) /* Some chips just has a large L1. */ 446 return; 447 448 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 449 l2size = ecx >> 16; 450 451 #ifdef CONFIG_X86_64 452 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 453 #else 454 /* do processor-specific cache resizing */ 455 if (this_cpu->legacy_cache_size) 456 l2size = this_cpu->legacy_cache_size(c, l2size); 457 458 /* Allow user to override all this if necessary. */ 459 if (cachesize_override != -1) 460 l2size = cachesize_override; 461 462 if (l2size == 0) 463 return; /* Again, no L2 cache is possible */ 464 #endif 465 466 c->x86_cache_size = l2size; 467 } 468 469 u16 __read_mostly tlb_lli_4k[NR_INFO]; 470 u16 __read_mostly tlb_lli_2m[NR_INFO]; 471 u16 __read_mostly tlb_lli_4m[NR_INFO]; 472 u16 __read_mostly tlb_lld_4k[NR_INFO]; 473 u16 __read_mostly tlb_lld_2m[NR_INFO]; 474 u16 __read_mostly tlb_lld_4m[NR_INFO]; 475 u16 __read_mostly tlb_lld_1g[NR_INFO]; 476 477 /* 478 * tlb_flushall_shift shows the balance point in replacing cr3 write 479 * with multiple 'invlpg'. It will do this replacement when 480 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. 481 * If tlb_flushall_shift is -1, means the replacement will be disabled. 482 */ 483 s8 __read_mostly tlb_flushall_shift = -1; 484 485 void cpu_detect_tlb(struct cpuinfo_x86 *c) 486 { 487 if (this_cpu->c_detect_tlb) 488 this_cpu->c_detect_tlb(c); 489 490 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" 491 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n" 492 "tlb_flushall_shift: %d\n", 493 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 494 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], 495 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], 496 tlb_lld_1g[ENTRIES], tlb_flushall_shift); 497 } 498 499 void detect_ht(struct cpuinfo_x86 *c) 500 { 501 #ifdef CONFIG_X86_HT 502 u32 eax, ebx, ecx, edx; 503 int index_msb, core_bits; 504 static bool printed; 505 506 if (!cpu_has(c, X86_FEATURE_HT)) 507 return; 508 509 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 510 goto out; 511 512 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 513 return; 514 515 cpuid(1, &eax, &ebx, &ecx, &edx); 516 517 smp_num_siblings = (ebx & 0xff0000) >> 16; 518 519 if (smp_num_siblings == 1) { 520 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 521 goto out; 522 } 523 524 if (smp_num_siblings <= 1) 525 goto out; 526 527 index_msb = get_count_order(smp_num_siblings); 528 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 529 530 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 531 532 index_msb = get_count_order(smp_num_siblings); 533 534 core_bits = get_count_order(c->x86_max_cores); 535 536 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 537 ((1 << core_bits) - 1); 538 539 out: 540 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 541 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 542 c->phys_proc_id); 543 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 544 c->cpu_core_id); 545 printed = 1; 546 } 547 #endif 548 } 549 550 static void get_cpu_vendor(struct cpuinfo_x86 *c) 551 { 552 char *v = c->x86_vendor_id; 553 int i; 554 555 for (i = 0; i < X86_VENDOR_NUM; i++) { 556 if (!cpu_devs[i]) 557 break; 558 559 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 560 (cpu_devs[i]->c_ident[1] && 561 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 562 563 this_cpu = cpu_devs[i]; 564 c->x86_vendor = this_cpu->c_x86_vendor; 565 return; 566 } 567 } 568 569 printk_once(KERN_ERR 570 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 571 "CPU: Your system may be unstable.\n", v); 572 573 c->x86_vendor = X86_VENDOR_UNKNOWN; 574 this_cpu = &default_cpu; 575 } 576 577 void cpu_detect(struct cpuinfo_x86 *c) 578 { 579 /* Get vendor name */ 580 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 581 (unsigned int *)&c->x86_vendor_id[0], 582 (unsigned int *)&c->x86_vendor_id[8], 583 (unsigned int *)&c->x86_vendor_id[4]); 584 585 c->x86 = 4; 586 /* Intel-defined flags: level 0x00000001 */ 587 if (c->cpuid_level >= 0x00000001) { 588 u32 junk, tfms, cap0, misc; 589 590 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 591 c->x86 = (tfms >> 8) & 0xf; 592 c->x86_model = (tfms >> 4) & 0xf; 593 c->x86_mask = tfms & 0xf; 594 595 if (c->x86 == 0xf) 596 c->x86 += (tfms >> 20) & 0xff; 597 if (c->x86 >= 0x6) 598 c->x86_model += ((tfms >> 16) & 0xf) << 4; 599 600 if (cap0 & (1<<19)) { 601 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 602 c->x86_cache_alignment = c->x86_clflush_size; 603 } 604 } 605 } 606 607 void get_cpu_cap(struct cpuinfo_x86 *c) 608 { 609 u32 tfms, xlvl; 610 u32 ebx; 611 612 /* Intel-defined flags: level 0x00000001 */ 613 if (c->cpuid_level >= 0x00000001) { 614 u32 capability, excap; 615 616 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 617 c->x86_capability[0] = capability; 618 c->x86_capability[4] = excap; 619 } 620 621 /* Additional Intel-defined flags: level 0x00000007 */ 622 if (c->cpuid_level >= 0x00000007) { 623 u32 eax, ebx, ecx, edx; 624 625 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 626 627 c->x86_capability[9] = ebx; 628 } 629 630 /* AMD-defined flags: level 0x80000001 */ 631 xlvl = cpuid_eax(0x80000000); 632 c->extended_cpuid_level = xlvl; 633 634 if ((xlvl & 0xffff0000) == 0x80000000) { 635 if (xlvl >= 0x80000001) { 636 c->x86_capability[1] = cpuid_edx(0x80000001); 637 c->x86_capability[6] = cpuid_ecx(0x80000001); 638 } 639 } 640 641 if (c->extended_cpuid_level >= 0x80000008) { 642 u32 eax = cpuid_eax(0x80000008); 643 644 c->x86_virt_bits = (eax >> 8) & 0xff; 645 c->x86_phys_bits = eax & 0xff; 646 } 647 #ifdef CONFIG_X86_32 648 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 649 c->x86_phys_bits = 36; 650 #endif 651 652 if (c->extended_cpuid_level >= 0x80000007) 653 c->x86_power = cpuid_edx(0x80000007); 654 655 init_scattered_cpuid_features(c); 656 } 657 658 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 659 { 660 #ifdef CONFIG_X86_32 661 int i; 662 663 /* 664 * First of all, decide if this is a 486 or higher 665 * It's a 486 if we can modify the AC flag 666 */ 667 if (flag_is_changeable_p(X86_EFLAGS_AC)) 668 c->x86 = 4; 669 else 670 c->x86 = 3; 671 672 for (i = 0; i < X86_VENDOR_NUM; i++) 673 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 674 c->x86_vendor_id[0] = 0; 675 cpu_devs[i]->c_identify(c); 676 if (c->x86_vendor_id[0]) { 677 get_cpu_vendor(c); 678 break; 679 } 680 } 681 #endif 682 } 683 684 /* 685 * Do minimum CPU detection early. 686 * Fields really needed: vendor, cpuid_level, family, model, mask, 687 * cache alignment. 688 * The others are not touched to avoid unwanted side effects. 689 * 690 * WARNING: this function is only called on the BP. Don't add code here 691 * that is supposed to run on all CPUs. 692 */ 693 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 694 { 695 #ifdef CONFIG_X86_64 696 c->x86_clflush_size = 64; 697 c->x86_phys_bits = 36; 698 c->x86_virt_bits = 48; 699 #else 700 c->x86_clflush_size = 32; 701 c->x86_phys_bits = 32; 702 c->x86_virt_bits = 32; 703 #endif 704 c->x86_cache_alignment = c->x86_clflush_size; 705 706 memset(&c->x86_capability, 0, sizeof c->x86_capability); 707 c->extended_cpuid_level = 0; 708 709 if (!have_cpuid_p()) 710 identify_cpu_without_cpuid(c); 711 712 /* cyrix could have cpuid enabled via c_identify()*/ 713 if (!have_cpuid_p()) 714 return; 715 716 cpu_detect(c); 717 get_cpu_vendor(c); 718 get_cpu_cap(c); 719 fpu_detect(c); 720 721 if (this_cpu->c_early_init) 722 this_cpu->c_early_init(c); 723 724 c->cpu_index = 0; 725 filter_cpuid_features(c, false); 726 727 if (this_cpu->c_bsp_init) 728 this_cpu->c_bsp_init(c); 729 730 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 731 } 732 733 void __init early_cpu_init(void) 734 { 735 const struct cpu_dev *const *cdev; 736 int count = 0; 737 738 #ifdef CONFIG_PROCESSOR_SELECT 739 printk(KERN_INFO "KERNEL supported cpus:\n"); 740 #endif 741 742 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 743 const struct cpu_dev *cpudev = *cdev; 744 745 if (count >= X86_VENDOR_NUM) 746 break; 747 cpu_devs[count] = cpudev; 748 count++; 749 750 #ifdef CONFIG_PROCESSOR_SELECT 751 { 752 unsigned int j; 753 754 for (j = 0; j < 2; j++) { 755 if (!cpudev->c_ident[j]) 756 continue; 757 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 758 cpudev->c_ident[j]); 759 } 760 } 761 #endif 762 } 763 early_identify_cpu(&boot_cpu_data); 764 } 765 766 /* 767 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 768 * unfortunately, that's not true in practice because of early VIA 769 * chips and (more importantly) broken virtualizers that are not easy 770 * to detect. In the latter case it doesn't even *fail* reliably, so 771 * probing for it doesn't even work. Disable it completely on 32-bit 772 * unless we can find a reliable way to detect all the broken cases. 773 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 774 */ 775 static void detect_nopl(struct cpuinfo_x86 *c) 776 { 777 #ifdef CONFIG_X86_32 778 clear_cpu_cap(c, X86_FEATURE_NOPL); 779 #else 780 set_cpu_cap(c, X86_FEATURE_NOPL); 781 #endif 782 } 783 784 static void generic_identify(struct cpuinfo_x86 *c) 785 { 786 c->extended_cpuid_level = 0; 787 788 if (!have_cpuid_p()) 789 identify_cpu_without_cpuid(c); 790 791 /* cyrix could have cpuid enabled via c_identify()*/ 792 if (!have_cpuid_p()) 793 return; 794 795 cpu_detect(c); 796 797 get_cpu_vendor(c); 798 799 get_cpu_cap(c); 800 801 if (c->cpuid_level >= 0x00000001) { 802 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 803 #ifdef CONFIG_X86_32 804 # ifdef CONFIG_X86_HT 805 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 806 # else 807 c->apicid = c->initial_apicid; 808 # endif 809 #endif 810 c->phys_proc_id = c->initial_apicid; 811 } 812 813 get_model_name(c); /* Default name */ 814 815 detect_nopl(c); 816 } 817 818 /* 819 * This does the hard work of actually picking apart the CPU stuff... 820 */ 821 static void identify_cpu(struct cpuinfo_x86 *c) 822 { 823 int i; 824 825 c->loops_per_jiffy = loops_per_jiffy; 826 c->x86_cache_size = -1; 827 c->x86_vendor = X86_VENDOR_UNKNOWN; 828 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 829 c->x86_vendor_id[0] = '\0'; /* Unset */ 830 c->x86_model_id[0] = '\0'; /* Unset */ 831 c->x86_max_cores = 1; 832 c->x86_coreid_bits = 0; 833 #ifdef CONFIG_X86_64 834 c->x86_clflush_size = 64; 835 c->x86_phys_bits = 36; 836 c->x86_virt_bits = 48; 837 #else 838 c->cpuid_level = -1; /* CPUID not detected */ 839 c->x86_clflush_size = 32; 840 c->x86_phys_bits = 32; 841 c->x86_virt_bits = 32; 842 #endif 843 c->x86_cache_alignment = c->x86_clflush_size; 844 memset(&c->x86_capability, 0, sizeof c->x86_capability); 845 846 generic_identify(c); 847 848 if (this_cpu->c_identify) 849 this_cpu->c_identify(c); 850 851 /* Clear/Set all flags overriden by options, after probe */ 852 for (i = 0; i < NCAPINTS; i++) { 853 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 854 c->x86_capability[i] |= cpu_caps_set[i]; 855 } 856 857 #ifdef CONFIG_X86_64 858 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 859 #endif 860 861 /* 862 * Vendor-specific initialization. In this section we 863 * canonicalize the feature flags, meaning if there are 864 * features a certain CPU supports which CPUID doesn't 865 * tell us, CPUID claiming incorrect flags, or other bugs, 866 * we handle them here. 867 * 868 * At the end of this section, c->x86_capability better 869 * indicate the features this CPU genuinely supports! 870 */ 871 if (this_cpu->c_init) 872 this_cpu->c_init(c); 873 874 /* Disable the PN if appropriate */ 875 squash_the_stupid_serial_number(c); 876 877 /* Set up SMEP/SMAP */ 878 setup_smep(c); 879 setup_smap(c); 880 881 /* 882 * The vendor-specific functions might have changed features. 883 * Now we do "generic changes." 884 */ 885 886 /* Filter out anything that depends on CPUID levels we don't have */ 887 filter_cpuid_features(c, true); 888 889 /* If the model name is still unset, do table lookup. */ 890 if (!c->x86_model_id[0]) { 891 const char *p; 892 p = table_lookup_model(c); 893 if (p) 894 strcpy(c->x86_model_id, p); 895 else 896 /* Last resort... */ 897 sprintf(c->x86_model_id, "%02x/%02x", 898 c->x86, c->x86_model); 899 } 900 901 #ifdef CONFIG_X86_64 902 detect_ht(c); 903 #endif 904 905 init_hypervisor(c); 906 x86_init_rdrand(c); 907 908 /* 909 * Clear/Set all flags overriden by options, need do it 910 * before following smp all cpus cap AND. 911 */ 912 for (i = 0; i < NCAPINTS; i++) { 913 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 914 c->x86_capability[i] |= cpu_caps_set[i]; 915 } 916 917 /* 918 * On SMP, boot_cpu_data holds the common feature set between 919 * all CPUs; so make sure that we indicate which features are 920 * common between the CPUs. The first time this routine gets 921 * executed, c == &boot_cpu_data. 922 */ 923 if (c != &boot_cpu_data) { 924 /* AND the already accumulated flags with these */ 925 for (i = 0; i < NCAPINTS; i++) 926 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 927 928 /* OR, i.e. replicate the bug flags */ 929 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 930 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 931 } 932 933 /* Init Machine Check Exception if available. */ 934 mcheck_cpu_init(c); 935 936 select_idle_routine(c); 937 938 #ifdef CONFIG_NUMA 939 numa_add_cpu(smp_processor_id()); 940 #endif 941 } 942 943 #ifdef CONFIG_X86_64 944 static void vgetcpu_set_mode(void) 945 { 946 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 947 vgetcpu_mode = VGETCPU_RDTSCP; 948 else 949 vgetcpu_mode = VGETCPU_LSL; 950 } 951 #endif 952 953 void __init identify_boot_cpu(void) 954 { 955 identify_cpu(&boot_cpu_data); 956 init_amd_e400_c1e_mask(); 957 #ifdef CONFIG_X86_32 958 sysenter_setup(); 959 enable_sep_cpu(); 960 #else 961 vgetcpu_set_mode(); 962 #endif 963 cpu_detect_tlb(&boot_cpu_data); 964 } 965 966 void identify_secondary_cpu(struct cpuinfo_x86 *c) 967 { 968 BUG_ON(c == &boot_cpu_data); 969 identify_cpu(c); 970 #ifdef CONFIG_X86_32 971 enable_sep_cpu(); 972 #endif 973 mtrr_ap_init(); 974 } 975 976 struct msr_range { 977 unsigned min; 978 unsigned max; 979 }; 980 981 static const struct msr_range msr_range_array[] = { 982 { 0x00000000, 0x00000418}, 983 { 0xc0000000, 0xc000040b}, 984 { 0xc0010000, 0xc0010142}, 985 { 0xc0011000, 0xc001103b}, 986 }; 987 988 static void __print_cpu_msr(void) 989 { 990 unsigned index_min, index_max; 991 unsigned index; 992 u64 val; 993 int i; 994 995 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 996 index_min = msr_range_array[i].min; 997 index_max = msr_range_array[i].max; 998 999 for (index = index_min; index < index_max; index++) { 1000 if (rdmsrl_safe(index, &val)) 1001 continue; 1002 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 1003 } 1004 } 1005 } 1006 1007 static int show_msr; 1008 1009 static __init int setup_show_msr(char *arg) 1010 { 1011 int num; 1012 1013 get_option(&arg, &num); 1014 1015 if (num > 0) 1016 show_msr = num; 1017 return 1; 1018 } 1019 __setup("show_msr=", setup_show_msr); 1020 1021 static __init int setup_noclflush(char *arg) 1022 { 1023 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 1024 return 1; 1025 } 1026 __setup("noclflush", setup_noclflush); 1027 1028 void print_cpu_info(struct cpuinfo_x86 *c) 1029 { 1030 const char *vendor = NULL; 1031 1032 if (c->x86_vendor < X86_VENDOR_NUM) { 1033 vendor = this_cpu->c_vendor; 1034 } else { 1035 if (c->cpuid_level >= 0) 1036 vendor = c->x86_vendor_id; 1037 } 1038 1039 if (vendor && !strstr(c->x86_model_id, vendor)) 1040 printk(KERN_CONT "%s ", vendor); 1041 1042 if (c->x86_model_id[0]) 1043 printk(KERN_CONT "%s", strim(c->x86_model_id)); 1044 else 1045 printk(KERN_CONT "%d86", c->x86); 1046 1047 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); 1048 1049 if (c->x86_mask || c->cpuid_level >= 0) 1050 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); 1051 else 1052 printk(KERN_CONT ")\n"); 1053 1054 print_cpu_msr(c); 1055 } 1056 1057 void print_cpu_msr(struct cpuinfo_x86 *c) 1058 { 1059 if (c->cpu_index < show_msr) 1060 __print_cpu_msr(); 1061 } 1062 1063 static __init int setup_disablecpuid(char *arg) 1064 { 1065 int bit; 1066 1067 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1068 setup_clear_cpu_cap(bit); 1069 else 1070 return 0; 1071 1072 return 1; 1073 } 1074 __setup("clearcpuid=", setup_disablecpuid); 1075 1076 #ifdef CONFIG_X86_64 1077 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1078 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1079 (unsigned long) debug_idt_table }; 1080 1081 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1082 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1083 1084 /* 1085 * The following four percpu variables are hot. Align current_task to 1086 * cacheline size such that all four fall in the same cacheline. 1087 */ 1088 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1089 &init_task; 1090 EXPORT_PER_CPU_SYMBOL(current_task); 1091 1092 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1093 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1094 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1095 1096 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1097 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1098 1099 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1100 1101 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1102 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1103 1104 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1105 1106 /* 1107 * Special IST stacks which the CPU switches to when it calls 1108 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1109 * limit), all of them are 4K, except the debug stack which 1110 * is 8K. 1111 */ 1112 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1113 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1114 [DEBUG_STACK - 1] = DEBUG_STKSZ 1115 }; 1116 1117 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1118 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1119 1120 /* May not be marked __init: used by software suspend */ 1121 void syscall_init(void) 1122 { 1123 /* 1124 * LSTAR and STAR live in a bit strange symbiosis. 1125 * They both write to the same internal register. STAR allows to 1126 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1127 */ 1128 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1129 wrmsrl(MSR_LSTAR, system_call); 1130 wrmsrl(MSR_CSTAR, ignore_sysret); 1131 1132 #ifdef CONFIG_IA32_EMULATION 1133 syscall32_cpu_init(); 1134 #endif 1135 1136 /* Flags to clear on syscall */ 1137 wrmsrl(MSR_SYSCALL_MASK, 1138 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1139 X86_EFLAGS_IOPL|X86_EFLAGS_AC); 1140 } 1141 1142 /* 1143 * Copies of the original ist values from the tss are only accessed during 1144 * debugging, no special alignment required. 1145 */ 1146 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1147 1148 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1149 DEFINE_PER_CPU(int, debug_stack_usage); 1150 1151 int is_debug_stack(unsigned long addr) 1152 { 1153 return __get_cpu_var(debug_stack_usage) || 1154 (addr <= __get_cpu_var(debug_stack_addr) && 1155 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); 1156 } 1157 1158 DEFINE_PER_CPU(u32, debug_idt_ctr); 1159 1160 void debug_stack_set_zero(void) 1161 { 1162 this_cpu_inc(debug_idt_ctr); 1163 load_current_idt(); 1164 } 1165 1166 void debug_stack_reset(void) 1167 { 1168 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1169 return; 1170 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1171 load_current_idt(); 1172 } 1173 1174 #else /* CONFIG_X86_64 */ 1175 1176 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1177 EXPORT_PER_CPU_SYMBOL(current_task); 1178 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1179 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1180 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1181 1182 #ifdef CONFIG_CC_STACKPROTECTOR 1183 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1184 #endif 1185 1186 #endif /* CONFIG_X86_64 */ 1187 1188 /* 1189 * Clear all 6 debug registers: 1190 */ 1191 static void clear_all_debug_regs(void) 1192 { 1193 int i; 1194 1195 for (i = 0; i < 8; i++) { 1196 /* Ignore db4, db5 */ 1197 if ((i == 4) || (i == 5)) 1198 continue; 1199 1200 set_debugreg(0, i); 1201 } 1202 } 1203 1204 #ifdef CONFIG_KGDB 1205 /* 1206 * Restore debug regs if using kgdbwait and you have a kernel debugger 1207 * connection established. 1208 */ 1209 static void dbg_restore_debug_regs(void) 1210 { 1211 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1212 arch_kgdb_ops.correct_hw_break(); 1213 } 1214 #else /* ! CONFIG_KGDB */ 1215 #define dbg_restore_debug_regs() 1216 #endif /* ! CONFIG_KGDB */ 1217 1218 /* 1219 * cpu_init() initializes state that is per-CPU. Some data is already 1220 * initialized (naturally) in the bootstrap process, such as the GDT 1221 * and IDT. We reload them nevertheless, this function acts as a 1222 * 'CPU state barrier', nothing should get across. 1223 * A lot of state is already set up in PDA init for 64 bit 1224 */ 1225 #ifdef CONFIG_X86_64 1226 1227 void cpu_init(void) 1228 { 1229 struct orig_ist *oist; 1230 struct task_struct *me; 1231 struct tss_struct *t; 1232 unsigned long v; 1233 int cpu; 1234 int i; 1235 1236 /* 1237 * Load microcode on this cpu if a valid microcode is available. 1238 * This is early microcode loading procedure. 1239 */ 1240 load_ucode_ap(); 1241 1242 cpu = stack_smp_processor_id(); 1243 t = &per_cpu(init_tss, cpu); 1244 oist = &per_cpu(orig_ist, cpu); 1245 1246 #ifdef CONFIG_NUMA 1247 if (this_cpu_read(numa_node) == 0 && 1248 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1249 set_numa_node(early_cpu_to_node(cpu)); 1250 #endif 1251 1252 me = current; 1253 1254 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1255 panic("CPU#%d already initialized!\n", cpu); 1256 1257 pr_debug("Initializing CPU#%d\n", cpu); 1258 1259 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1260 1261 /* 1262 * Initialize the per-CPU GDT with the boot GDT, 1263 * and set up the GDT descriptor: 1264 */ 1265 1266 switch_to_new_gdt(cpu); 1267 loadsegment(fs, 0); 1268 1269 load_current_idt(); 1270 1271 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1272 syscall_init(); 1273 1274 wrmsrl(MSR_FS_BASE, 0); 1275 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1276 barrier(); 1277 1278 x86_configure_nx(); 1279 enable_x2apic(); 1280 1281 /* 1282 * set up and load the per-CPU TSS 1283 */ 1284 if (!oist->ist[0]) { 1285 char *estacks = per_cpu(exception_stacks, cpu); 1286 1287 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1288 estacks += exception_stack_sizes[v]; 1289 oist->ist[v] = t->x86_tss.ist[v] = 1290 (unsigned long)estacks; 1291 if (v == DEBUG_STACK-1) 1292 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1293 } 1294 } 1295 1296 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1297 1298 /* 1299 * <= is required because the CPU will access up to 1300 * 8 bits beyond the end of the IO permission bitmap. 1301 */ 1302 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1303 t->io_bitmap[i] = ~0UL; 1304 1305 atomic_inc(&init_mm.mm_count); 1306 me->active_mm = &init_mm; 1307 BUG_ON(me->mm); 1308 enter_lazy_tlb(&init_mm, me); 1309 1310 load_sp0(t, ¤t->thread); 1311 set_tss_desc(cpu, t); 1312 load_TR_desc(); 1313 load_LDT(&init_mm.context); 1314 1315 clear_all_debug_regs(); 1316 dbg_restore_debug_regs(); 1317 1318 fpu_init(); 1319 1320 if (is_uv_system()) 1321 uv_cpu_init(); 1322 } 1323 1324 #else 1325 1326 void cpu_init(void) 1327 { 1328 int cpu = smp_processor_id(); 1329 struct task_struct *curr = current; 1330 struct tss_struct *t = &per_cpu(init_tss, cpu); 1331 struct thread_struct *thread = &curr->thread; 1332 1333 show_ucode_info_early(); 1334 1335 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1336 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1337 for (;;) 1338 local_irq_enable(); 1339 } 1340 1341 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1342 1343 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1344 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1345 1346 load_current_idt(); 1347 switch_to_new_gdt(cpu); 1348 1349 /* 1350 * Set up and load the per-CPU TSS and LDT 1351 */ 1352 atomic_inc(&init_mm.mm_count); 1353 curr->active_mm = &init_mm; 1354 BUG_ON(curr->mm); 1355 enter_lazy_tlb(&init_mm, curr); 1356 1357 load_sp0(t, thread); 1358 set_tss_desc(cpu, t); 1359 load_TR_desc(); 1360 load_LDT(&init_mm.context); 1361 1362 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1363 1364 #ifdef CONFIG_DOUBLEFAULT 1365 /* Set up doublefault TSS pointer in the GDT */ 1366 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1367 #endif 1368 1369 clear_all_debug_regs(); 1370 dbg_restore_debug_regs(); 1371 1372 fpu_init(); 1373 } 1374 #endif 1375 1376 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 1377 void warn_pre_alternatives(void) 1378 { 1379 WARN(1, "You're using static_cpu_has before alternatives have run!\n"); 1380 } 1381 EXPORT_SYMBOL_GPL(warn_pre_alternatives); 1382 #endif 1383 1384 inline bool __static_cpu_has_safe(u16 bit) 1385 { 1386 return boot_cpu_has(bit); 1387 } 1388 EXPORT_SYMBOL_GPL(__static_cpu_has_safe); 1389