1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 #include <linux/stackprotector.h> 26 27 #include <asm/cmdline.h> 28 #include <asm/perf_event.h> 29 #include <asm/mmu_context.h> 30 #include <asm/doublefault.h> 31 #include <asm/archrandom.h> 32 #include <asm/hypervisor.h> 33 #include <asm/processor.h> 34 #include <asm/tlbflush.h> 35 #include <asm/debugreg.h> 36 #include <asm/sections.h> 37 #include <asm/vsyscall.h> 38 #include <linux/topology.h> 39 #include <linux/cpumask.h> 40 #include <linux/atomic.h> 41 #include <asm/proto.h> 42 #include <asm/setup.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/fpu/api.h> 46 #include <asm/mtrr.h> 47 #include <asm/hwcap2.h> 48 #include <linux/numa.h> 49 #include <asm/numa.h> 50 #include <asm/asm.h> 51 #include <asm/bugs.h> 52 #include <asm/cpu.h> 53 #include <asm/mce.h> 54 #include <asm/msr.h> 55 #include <asm/cacheinfo.h> 56 #include <asm/memtype.h> 57 #include <asm/microcode.h> 58 #include <asm/microcode_intel.h> 59 #include <asm/intel-family.h> 60 #include <asm/cpu_device_id.h> 61 #include <asm/uv/uv.h> 62 #include <asm/sigframe.h> 63 #include <asm/traps.h> 64 #include <asm/sev.h> 65 66 #include "cpu.h" 67 68 u32 elf_hwcap2 __read_mostly; 69 70 /* all of these masks are initialized in setup_cpu_local_masks() */ 71 cpumask_var_t cpu_initialized_mask; 72 cpumask_var_t cpu_callout_mask; 73 cpumask_var_t cpu_callin_mask; 74 75 /* representing cpus for which sibling maps can be computed */ 76 cpumask_var_t cpu_sibling_setup_mask; 77 78 /* Number of siblings per CPU package */ 79 int smp_num_siblings = 1; 80 EXPORT_SYMBOL(smp_num_siblings); 81 82 /* Last level cache ID of each logical CPU */ 83 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 84 85 u16 get_llc_id(unsigned int cpu) 86 { 87 return per_cpu(cpu_llc_id, cpu); 88 } 89 EXPORT_SYMBOL_GPL(get_llc_id); 90 91 /* L2 cache ID of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 93 94 static struct ppin_info { 95 int feature; 96 int msr_ppin_ctl; 97 int msr_ppin; 98 } ppin_info[] = { 99 [X86_VENDOR_INTEL] = { 100 .feature = X86_FEATURE_INTEL_PPIN, 101 .msr_ppin_ctl = MSR_PPIN_CTL, 102 .msr_ppin = MSR_PPIN 103 }, 104 [X86_VENDOR_AMD] = { 105 .feature = X86_FEATURE_AMD_PPIN, 106 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 107 .msr_ppin = MSR_AMD_PPIN 108 }, 109 }; 110 111 static const struct x86_cpu_id ppin_cpuids[] = { 112 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 113 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 114 115 /* Legacy models without CPUID enumeration */ 116 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 117 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 125 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 126 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 127 128 {} 129 }; 130 131 static void ppin_init(struct cpuinfo_x86 *c) 132 { 133 const struct x86_cpu_id *id; 134 unsigned long long val; 135 struct ppin_info *info; 136 137 id = x86_match_cpu(ppin_cpuids); 138 if (!id) 139 return; 140 141 /* 142 * Testing the presence of the MSR is not enough. Need to check 143 * that the PPIN_CTL allows reading of the PPIN. 144 */ 145 info = (struct ppin_info *)id->driver_data; 146 147 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 148 goto clear_ppin; 149 150 if ((val & 3UL) == 1UL) { 151 /* PPIN locked in disabled mode */ 152 goto clear_ppin; 153 } 154 155 /* If PPIN is disabled, try to enable */ 156 if (!(val & 2UL)) { 157 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 158 rdmsrl_safe(info->msr_ppin_ctl, &val); 159 } 160 161 /* Is the enable bit set? */ 162 if (val & 2UL) { 163 c->ppin = __rdmsr(info->msr_ppin); 164 set_cpu_cap(c, info->feature); 165 return; 166 } 167 168 clear_ppin: 169 clear_cpu_cap(c, info->feature); 170 } 171 172 /* correctly size the local cpu masks */ 173 void __init setup_cpu_local_masks(void) 174 { 175 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 176 alloc_bootmem_cpumask_var(&cpu_callin_mask); 177 alloc_bootmem_cpumask_var(&cpu_callout_mask); 178 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 179 } 180 181 static void default_init(struct cpuinfo_x86 *c) 182 { 183 #ifdef CONFIG_X86_64 184 cpu_detect_cache_sizes(c); 185 #else 186 /* Not much we can do here... */ 187 /* Check if at least it has cpuid */ 188 if (c->cpuid_level == -1) { 189 /* No cpuid. It must be an ancient CPU */ 190 if (c->x86 == 4) 191 strcpy(c->x86_model_id, "486"); 192 else if (c->x86 == 3) 193 strcpy(c->x86_model_id, "386"); 194 } 195 #endif 196 } 197 198 static const struct cpu_dev default_cpu = { 199 .c_init = default_init, 200 .c_vendor = "Unknown", 201 .c_x86_vendor = X86_VENDOR_UNKNOWN, 202 }; 203 204 static const struct cpu_dev *this_cpu = &default_cpu; 205 206 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 207 #ifdef CONFIG_X86_64 208 /* 209 * We need valid kernel segments for data and code in long mode too 210 * IRET will check the segment types kkeil 2000/10/28 211 * Also sysret mandates a special GDT layout 212 * 213 * TLS descriptors are currently at a different place compared to i386. 214 * Hopefully nobody expects them at a fixed place (Wine?) 215 */ 216 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 217 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 218 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 219 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 220 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 221 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 222 #else 223 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 224 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 225 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 226 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 227 /* 228 * Segments used for calling PnP BIOS have byte granularity. 229 * They code segments and data segments have fixed 64k limits, 230 * the transfer segment sizes are set at run time. 231 */ 232 /* 32-bit code */ 233 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 234 /* 16-bit code */ 235 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 236 /* 16-bit data */ 237 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 238 /* 16-bit data */ 239 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 240 /* 16-bit data */ 241 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 242 /* 243 * The APM segments have byte granularity and their bases 244 * are set at run time. All have 64k limits. 245 */ 246 /* 32-bit code */ 247 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 248 /* 16-bit code */ 249 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 250 /* data */ 251 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 252 253 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 254 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 255 #endif 256 } }; 257 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 258 259 #ifdef CONFIG_X86_64 260 static int __init x86_nopcid_setup(char *s) 261 { 262 /* nopcid doesn't accept parameters */ 263 if (s) 264 return -EINVAL; 265 266 /* do not emit a message if the feature is not present */ 267 if (!boot_cpu_has(X86_FEATURE_PCID)) 268 return 0; 269 270 setup_clear_cpu_cap(X86_FEATURE_PCID); 271 pr_info("nopcid: PCID feature disabled\n"); 272 return 0; 273 } 274 early_param("nopcid", x86_nopcid_setup); 275 #endif 276 277 static int __init x86_noinvpcid_setup(char *s) 278 { 279 /* noinvpcid doesn't accept parameters */ 280 if (s) 281 return -EINVAL; 282 283 /* do not emit a message if the feature is not present */ 284 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 285 return 0; 286 287 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 288 pr_info("noinvpcid: INVPCID feature disabled\n"); 289 return 0; 290 } 291 early_param("noinvpcid", x86_noinvpcid_setup); 292 293 #ifdef CONFIG_X86_32 294 static int cachesize_override = -1; 295 static int disable_x86_serial_nr = 1; 296 297 static int __init cachesize_setup(char *str) 298 { 299 get_option(&str, &cachesize_override); 300 return 1; 301 } 302 __setup("cachesize=", cachesize_setup); 303 304 /* Standard macro to see if a specific flag is changeable */ 305 static inline int flag_is_changeable_p(u32 flag) 306 { 307 u32 f1, f2; 308 309 /* 310 * Cyrix and IDT cpus allow disabling of CPUID 311 * so the code below may return different results 312 * when it is executed before and after enabling 313 * the CPUID. Add "volatile" to not allow gcc to 314 * optimize the subsequent calls to this function. 315 */ 316 asm volatile ("pushfl \n\t" 317 "pushfl \n\t" 318 "popl %0 \n\t" 319 "movl %0, %1 \n\t" 320 "xorl %2, %0 \n\t" 321 "pushl %0 \n\t" 322 "popfl \n\t" 323 "pushfl \n\t" 324 "popl %0 \n\t" 325 "popfl \n\t" 326 327 : "=&r" (f1), "=&r" (f2) 328 : "ir" (flag)); 329 330 return ((f1^f2) & flag) != 0; 331 } 332 333 /* Probe for the CPUID instruction */ 334 int have_cpuid_p(void) 335 { 336 return flag_is_changeable_p(X86_EFLAGS_ID); 337 } 338 339 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 340 { 341 unsigned long lo, hi; 342 343 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 344 return; 345 346 /* Disable processor serial number: */ 347 348 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 349 lo |= 0x200000; 350 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 351 352 pr_notice("CPU serial number disabled.\n"); 353 clear_cpu_cap(c, X86_FEATURE_PN); 354 355 /* Disabling the serial number may affect the cpuid level */ 356 c->cpuid_level = cpuid_eax(0); 357 } 358 359 static int __init x86_serial_nr_setup(char *s) 360 { 361 disable_x86_serial_nr = 0; 362 return 1; 363 } 364 __setup("serialnumber", x86_serial_nr_setup); 365 #else 366 static inline int flag_is_changeable_p(u32 flag) 367 { 368 return 1; 369 } 370 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 371 { 372 } 373 #endif 374 375 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 376 { 377 if (cpu_has(c, X86_FEATURE_SMEP)) 378 cr4_set_bits(X86_CR4_SMEP); 379 } 380 381 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 382 { 383 unsigned long eflags = native_save_fl(); 384 385 /* This should have been cleared long ago */ 386 BUG_ON(eflags & X86_EFLAGS_AC); 387 388 if (cpu_has(c, X86_FEATURE_SMAP)) 389 cr4_set_bits(X86_CR4_SMAP); 390 } 391 392 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 393 { 394 /* Check the boot processor, plus build option for UMIP. */ 395 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 396 goto out; 397 398 /* Check the current processor's cpuid bits. */ 399 if (!cpu_has(c, X86_FEATURE_UMIP)) 400 goto out; 401 402 cr4_set_bits(X86_CR4_UMIP); 403 404 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 405 406 return; 407 408 out: 409 /* 410 * Make sure UMIP is disabled in case it was enabled in a 411 * previous boot (e.g., via kexec). 412 */ 413 cr4_clear_bits(X86_CR4_UMIP); 414 } 415 416 /* These bits should not change their value after CPU init is finished. */ 417 static const unsigned long cr4_pinned_mask = 418 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 419 X86_CR4_FSGSBASE | X86_CR4_CET; 420 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 421 static unsigned long cr4_pinned_bits __ro_after_init; 422 423 void native_write_cr0(unsigned long val) 424 { 425 unsigned long bits_missing = 0; 426 427 set_register: 428 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 429 430 if (static_branch_likely(&cr_pinning)) { 431 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 432 bits_missing = X86_CR0_WP; 433 val |= bits_missing; 434 goto set_register; 435 } 436 /* Warn after we've set the missing bits. */ 437 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 438 } 439 } 440 EXPORT_SYMBOL(native_write_cr0); 441 442 void __no_profile native_write_cr4(unsigned long val) 443 { 444 unsigned long bits_changed = 0; 445 446 set_register: 447 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 448 449 if (static_branch_likely(&cr_pinning)) { 450 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 451 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 452 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 453 goto set_register; 454 } 455 /* Warn after we've corrected the changed bits. */ 456 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 457 bits_changed); 458 } 459 } 460 #if IS_MODULE(CONFIG_LKDTM) 461 EXPORT_SYMBOL_GPL(native_write_cr4); 462 #endif 463 464 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 465 { 466 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 467 468 lockdep_assert_irqs_disabled(); 469 470 newval = (cr4 & ~clear) | set; 471 if (newval != cr4) { 472 this_cpu_write(cpu_tlbstate.cr4, newval); 473 __write_cr4(newval); 474 } 475 } 476 EXPORT_SYMBOL(cr4_update_irqsoff); 477 478 /* Read the CR4 shadow. */ 479 unsigned long cr4_read_shadow(void) 480 { 481 return this_cpu_read(cpu_tlbstate.cr4); 482 } 483 EXPORT_SYMBOL_GPL(cr4_read_shadow); 484 485 void cr4_init(void) 486 { 487 unsigned long cr4 = __read_cr4(); 488 489 if (boot_cpu_has(X86_FEATURE_PCID)) 490 cr4 |= X86_CR4_PCIDE; 491 if (static_branch_likely(&cr_pinning)) 492 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 493 494 __write_cr4(cr4); 495 496 /* Initialize cr4 shadow for this CPU. */ 497 this_cpu_write(cpu_tlbstate.cr4, cr4); 498 } 499 500 /* 501 * Once CPU feature detection is finished (and boot params have been 502 * parsed), record any of the sensitive CR bits that are set, and 503 * enable CR pinning. 504 */ 505 static void __init setup_cr_pinning(void) 506 { 507 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 508 static_key_enable(&cr_pinning.key); 509 } 510 511 static __init int x86_nofsgsbase_setup(char *arg) 512 { 513 /* Require an exact match without trailing characters. */ 514 if (strlen(arg)) 515 return 0; 516 517 /* Do not emit a message if the feature is not present. */ 518 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 519 return 1; 520 521 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 522 pr_info("FSGSBASE disabled via kernel command line\n"); 523 return 1; 524 } 525 __setup("nofsgsbase", x86_nofsgsbase_setup); 526 527 /* 528 * Protection Keys are not available in 32-bit mode. 529 */ 530 static bool pku_disabled; 531 532 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 533 { 534 if (c == &boot_cpu_data) { 535 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 536 return; 537 /* 538 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 539 * bit to be set. Enforce it. 540 */ 541 setup_force_cpu_cap(X86_FEATURE_OSPKE); 542 543 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 544 return; 545 } 546 547 cr4_set_bits(X86_CR4_PKE); 548 /* Load the default PKRU value */ 549 pkru_write_default(); 550 } 551 552 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 553 static __init int setup_disable_pku(char *arg) 554 { 555 /* 556 * Do not clear the X86_FEATURE_PKU bit. All of the 557 * runtime checks are against OSPKE so clearing the 558 * bit does nothing. 559 * 560 * This way, we will see "pku" in cpuinfo, but not 561 * "ospke", which is exactly what we want. It shows 562 * that the CPU has PKU, but the OS has not enabled it. 563 * This happens to be exactly how a system would look 564 * if we disabled the config option. 565 */ 566 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 567 pku_disabled = true; 568 return 1; 569 } 570 __setup("nopku", setup_disable_pku); 571 #endif 572 573 #ifdef CONFIG_X86_KERNEL_IBT 574 575 __noendbr u64 ibt_save(bool disable) 576 { 577 u64 msr = 0; 578 579 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 580 rdmsrl(MSR_IA32_S_CET, msr); 581 if (disable) 582 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 583 } 584 585 return msr; 586 } 587 588 __noendbr void ibt_restore(u64 save) 589 { 590 u64 msr; 591 592 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 593 rdmsrl(MSR_IA32_S_CET, msr); 594 msr &= ~CET_ENDBR_EN; 595 msr |= (save & CET_ENDBR_EN); 596 wrmsrl(MSR_IA32_S_CET, msr); 597 } 598 } 599 600 #endif 601 602 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 603 { 604 u64 msr = CET_ENDBR_EN; 605 606 if (!HAS_KERNEL_IBT || 607 !cpu_feature_enabled(X86_FEATURE_IBT)) 608 return; 609 610 wrmsrl(MSR_IA32_S_CET, msr); 611 cr4_set_bits(X86_CR4_CET); 612 613 if (!ibt_selftest()) { 614 pr_err("IBT selftest: Failed!\n"); 615 wrmsrl(MSR_IA32_S_CET, 0); 616 setup_clear_cpu_cap(X86_FEATURE_IBT); 617 return; 618 } 619 } 620 621 __noendbr void cet_disable(void) 622 { 623 if (cpu_feature_enabled(X86_FEATURE_IBT)) 624 wrmsrl(MSR_IA32_S_CET, 0); 625 } 626 627 /* 628 * Some CPU features depend on higher CPUID levels, which may not always 629 * be available due to CPUID level capping or broken virtualization 630 * software. Add those features to this table to auto-disable them. 631 */ 632 struct cpuid_dependent_feature { 633 u32 feature; 634 u32 level; 635 }; 636 637 static const struct cpuid_dependent_feature 638 cpuid_dependent_features[] = { 639 { X86_FEATURE_MWAIT, 0x00000005 }, 640 { X86_FEATURE_DCA, 0x00000009 }, 641 { X86_FEATURE_XSAVE, 0x0000000d }, 642 { 0, 0 } 643 }; 644 645 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 646 { 647 const struct cpuid_dependent_feature *df; 648 649 for (df = cpuid_dependent_features; df->feature; df++) { 650 651 if (!cpu_has(c, df->feature)) 652 continue; 653 /* 654 * Note: cpuid_level is set to -1 if unavailable, but 655 * extended_extended_level is set to 0 if unavailable 656 * and the legitimate extended levels are all negative 657 * when signed; hence the weird messing around with 658 * signs here... 659 */ 660 if (!((s32)df->level < 0 ? 661 (u32)df->level > (u32)c->extended_cpuid_level : 662 (s32)df->level > (s32)c->cpuid_level)) 663 continue; 664 665 clear_cpu_cap(c, df->feature); 666 if (!warn) 667 continue; 668 669 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 670 x86_cap_flag(df->feature), df->level); 671 } 672 } 673 674 /* 675 * Naming convention should be: <Name> [(<Codename>)] 676 * This table only is used unless init_<vendor>() below doesn't set it; 677 * in particular, if CPUID levels 0x80000002..4 are supported, this 678 * isn't used 679 */ 680 681 /* Look up CPU names by table lookup. */ 682 static const char *table_lookup_model(struct cpuinfo_x86 *c) 683 { 684 #ifdef CONFIG_X86_32 685 const struct legacy_cpu_model_info *info; 686 687 if (c->x86_model >= 16) 688 return NULL; /* Range check */ 689 690 if (!this_cpu) 691 return NULL; 692 693 info = this_cpu->legacy_models; 694 695 while (info->family) { 696 if (info->family == c->x86) 697 return info->model_names[c->x86_model]; 698 info++; 699 } 700 #endif 701 return NULL; /* Not found */ 702 } 703 704 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 705 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 706 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 707 708 #ifdef CONFIG_X86_32 709 /* The 32-bit entry code needs to find cpu_entry_area. */ 710 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 711 #endif 712 713 /* Load the original GDT from the per-cpu structure */ 714 void load_direct_gdt(int cpu) 715 { 716 struct desc_ptr gdt_descr; 717 718 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 719 gdt_descr.size = GDT_SIZE - 1; 720 load_gdt(&gdt_descr); 721 } 722 EXPORT_SYMBOL_GPL(load_direct_gdt); 723 724 /* Load a fixmap remapping of the per-cpu GDT */ 725 void load_fixmap_gdt(int cpu) 726 { 727 struct desc_ptr gdt_descr; 728 729 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 730 gdt_descr.size = GDT_SIZE - 1; 731 load_gdt(&gdt_descr); 732 } 733 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 734 735 /** 736 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 737 * @cpu: The CPU number for which this is invoked 738 * 739 * Invoked during early boot to switch from early GDT and early per CPU to 740 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 741 * switch is implicit by loading the direct GDT. On 64bit this requires 742 * to update GSBASE. 743 */ 744 void __init switch_gdt_and_percpu_base(int cpu) 745 { 746 load_direct_gdt(cpu); 747 748 #ifdef CONFIG_X86_64 749 /* 750 * No need to load %gs. It is already correct. 751 * 752 * Writing %gs on 64bit would zero GSBASE which would make any per 753 * CPU operation up to the point of the wrmsrl() fault. 754 * 755 * Set GSBASE to the new offset. Until the wrmsrl() happens the 756 * early mapping is still valid. That means the GSBASE update will 757 * lose any prior per CPU data which was not copied over in 758 * setup_per_cpu_areas(). 759 * 760 * This works even with stackprotector enabled because the 761 * per CPU stack canary is 0 in both per CPU areas. 762 */ 763 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 764 #else 765 /* 766 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 767 * it is required to load FS again so that the 'hidden' part is 768 * updated from the new GDT. Up to this point the early per CPU 769 * translation is active. Any content of the early per CPU data 770 * which was not copied over in setup_per_cpu_areas() is lost. 771 */ 772 loadsegment(fs, __KERNEL_PERCPU); 773 #endif 774 } 775 776 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 777 778 static void get_model_name(struct cpuinfo_x86 *c) 779 { 780 unsigned int *v; 781 char *p, *q, *s; 782 783 if (c->extended_cpuid_level < 0x80000004) 784 return; 785 786 v = (unsigned int *)c->x86_model_id; 787 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 788 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 789 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 790 c->x86_model_id[48] = 0; 791 792 /* Trim whitespace */ 793 p = q = s = &c->x86_model_id[0]; 794 795 while (*p == ' ') 796 p++; 797 798 while (*p) { 799 /* Note the last non-whitespace index */ 800 if (!isspace(*p)) 801 s = q; 802 803 *q++ = *p++; 804 } 805 806 *(s + 1) = '\0'; 807 } 808 809 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 810 { 811 unsigned int eax, ebx, ecx, edx; 812 813 c->x86_max_cores = 1; 814 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 815 return; 816 817 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 818 if (eax & 0x1f) 819 c->x86_max_cores = (eax >> 26) + 1; 820 } 821 822 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 823 { 824 unsigned int n, dummy, ebx, ecx, edx, l2size; 825 826 n = c->extended_cpuid_level; 827 828 if (n >= 0x80000005) { 829 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 830 c->x86_cache_size = (ecx>>24) + (edx>>24); 831 #ifdef CONFIG_X86_64 832 /* On K8 L1 TLB is inclusive, so don't count it */ 833 c->x86_tlbsize = 0; 834 #endif 835 } 836 837 if (n < 0x80000006) /* Some chips just has a large L1. */ 838 return; 839 840 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 841 l2size = ecx >> 16; 842 843 #ifdef CONFIG_X86_64 844 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 845 #else 846 /* do processor-specific cache resizing */ 847 if (this_cpu->legacy_cache_size) 848 l2size = this_cpu->legacy_cache_size(c, l2size); 849 850 /* Allow user to override all this if necessary. */ 851 if (cachesize_override != -1) 852 l2size = cachesize_override; 853 854 if (l2size == 0) 855 return; /* Again, no L2 cache is possible */ 856 #endif 857 858 c->x86_cache_size = l2size; 859 } 860 861 u16 __read_mostly tlb_lli_4k[NR_INFO]; 862 u16 __read_mostly tlb_lli_2m[NR_INFO]; 863 u16 __read_mostly tlb_lli_4m[NR_INFO]; 864 u16 __read_mostly tlb_lld_4k[NR_INFO]; 865 u16 __read_mostly tlb_lld_2m[NR_INFO]; 866 u16 __read_mostly tlb_lld_4m[NR_INFO]; 867 u16 __read_mostly tlb_lld_1g[NR_INFO]; 868 869 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 870 { 871 if (this_cpu->c_detect_tlb) 872 this_cpu->c_detect_tlb(c); 873 874 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 875 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 876 tlb_lli_4m[ENTRIES]); 877 878 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 879 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 880 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 881 } 882 883 int detect_ht_early(struct cpuinfo_x86 *c) 884 { 885 #ifdef CONFIG_SMP 886 u32 eax, ebx, ecx, edx; 887 888 if (!cpu_has(c, X86_FEATURE_HT)) 889 return -1; 890 891 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 892 return -1; 893 894 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 895 return -1; 896 897 cpuid(1, &eax, &ebx, &ecx, &edx); 898 899 smp_num_siblings = (ebx & 0xff0000) >> 16; 900 if (smp_num_siblings == 1) 901 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 902 #endif 903 return 0; 904 } 905 906 void detect_ht(struct cpuinfo_x86 *c) 907 { 908 #ifdef CONFIG_SMP 909 int index_msb, core_bits; 910 911 if (detect_ht_early(c) < 0) 912 return; 913 914 index_msb = get_count_order(smp_num_siblings); 915 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 916 917 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 918 919 index_msb = get_count_order(smp_num_siblings); 920 921 core_bits = get_count_order(c->x86_max_cores); 922 923 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 924 ((1 << core_bits) - 1); 925 #endif 926 } 927 928 static void get_cpu_vendor(struct cpuinfo_x86 *c) 929 { 930 char *v = c->x86_vendor_id; 931 int i; 932 933 for (i = 0; i < X86_VENDOR_NUM; i++) { 934 if (!cpu_devs[i]) 935 break; 936 937 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 938 (cpu_devs[i]->c_ident[1] && 939 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 940 941 this_cpu = cpu_devs[i]; 942 c->x86_vendor = this_cpu->c_x86_vendor; 943 return; 944 } 945 } 946 947 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 948 "CPU: Your system may be unstable.\n", v); 949 950 c->x86_vendor = X86_VENDOR_UNKNOWN; 951 this_cpu = &default_cpu; 952 } 953 954 void cpu_detect(struct cpuinfo_x86 *c) 955 { 956 /* Get vendor name */ 957 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 958 (unsigned int *)&c->x86_vendor_id[0], 959 (unsigned int *)&c->x86_vendor_id[8], 960 (unsigned int *)&c->x86_vendor_id[4]); 961 962 c->x86 = 4; 963 /* Intel-defined flags: level 0x00000001 */ 964 if (c->cpuid_level >= 0x00000001) { 965 u32 junk, tfms, cap0, misc; 966 967 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 968 c->x86 = x86_family(tfms); 969 c->x86_model = x86_model(tfms); 970 c->x86_stepping = x86_stepping(tfms); 971 972 if (cap0 & (1<<19)) { 973 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 974 c->x86_cache_alignment = c->x86_clflush_size; 975 } 976 } 977 } 978 979 static void apply_forced_caps(struct cpuinfo_x86 *c) 980 { 981 int i; 982 983 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 984 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 985 c->x86_capability[i] |= cpu_caps_set[i]; 986 } 987 } 988 989 static void init_speculation_control(struct cpuinfo_x86 *c) 990 { 991 /* 992 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 993 * and they also have a different bit for STIBP support. Also, 994 * a hypervisor might have set the individual AMD bits even on 995 * Intel CPUs, for finer-grained selection of what's available. 996 */ 997 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 998 set_cpu_cap(c, X86_FEATURE_IBRS); 999 set_cpu_cap(c, X86_FEATURE_IBPB); 1000 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1001 } 1002 1003 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 1004 set_cpu_cap(c, X86_FEATURE_STIBP); 1005 1006 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 1007 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 1008 set_cpu_cap(c, X86_FEATURE_SSBD); 1009 1010 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 1011 set_cpu_cap(c, X86_FEATURE_IBRS); 1012 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1013 } 1014 1015 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 1016 set_cpu_cap(c, X86_FEATURE_IBPB); 1017 1018 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 1019 set_cpu_cap(c, X86_FEATURE_STIBP); 1020 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1021 } 1022 1023 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1024 set_cpu_cap(c, X86_FEATURE_SSBD); 1025 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1026 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1027 } 1028 } 1029 1030 void get_cpu_cap(struct cpuinfo_x86 *c) 1031 { 1032 u32 eax, ebx, ecx, edx; 1033 1034 /* Intel-defined flags: level 0x00000001 */ 1035 if (c->cpuid_level >= 0x00000001) { 1036 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1037 1038 c->x86_capability[CPUID_1_ECX] = ecx; 1039 c->x86_capability[CPUID_1_EDX] = edx; 1040 } 1041 1042 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1043 if (c->cpuid_level >= 0x00000006) 1044 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1045 1046 /* Additional Intel-defined flags: level 0x00000007 */ 1047 if (c->cpuid_level >= 0x00000007) { 1048 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1049 c->x86_capability[CPUID_7_0_EBX] = ebx; 1050 c->x86_capability[CPUID_7_ECX] = ecx; 1051 c->x86_capability[CPUID_7_EDX] = edx; 1052 1053 /* Check valid sub-leaf index before accessing it */ 1054 if (eax >= 1) { 1055 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1056 c->x86_capability[CPUID_7_1_EAX] = eax; 1057 } 1058 } 1059 1060 /* Extended state features: level 0x0000000d */ 1061 if (c->cpuid_level >= 0x0000000d) { 1062 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1063 1064 c->x86_capability[CPUID_D_1_EAX] = eax; 1065 } 1066 1067 /* AMD-defined flags: level 0x80000001 */ 1068 eax = cpuid_eax(0x80000000); 1069 c->extended_cpuid_level = eax; 1070 1071 if ((eax & 0xffff0000) == 0x80000000) { 1072 if (eax >= 0x80000001) { 1073 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1074 1075 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1076 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1077 } 1078 } 1079 1080 if (c->extended_cpuid_level >= 0x80000007) { 1081 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1082 1083 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1084 c->x86_power = edx; 1085 } 1086 1087 if (c->extended_cpuid_level >= 0x80000008) { 1088 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1089 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1090 } 1091 1092 if (c->extended_cpuid_level >= 0x8000000a) 1093 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1094 1095 if (c->extended_cpuid_level >= 0x8000001f) 1096 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1097 1098 if (c->extended_cpuid_level >= 0x80000021) 1099 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1100 1101 init_scattered_cpuid_features(c); 1102 init_speculation_control(c); 1103 1104 /* 1105 * Clear/Set all flags overridden by options, after probe. 1106 * This needs to happen each time we re-probe, which may happen 1107 * several times during CPU initialization. 1108 */ 1109 apply_forced_caps(c); 1110 } 1111 1112 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1113 { 1114 u32 eax, ebx, ecx, edx; 1115 1116 if (c->extended_cpuid_level >= 0x80000008) { 1117 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1118 1119 c->x86_virt_bits = (eax >> 8) & 0xff; 1120 c->x86_phys_bits = eax & 0xff; 1121 } 1122 #ifdef CONFIG_X86_32 1123 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 1124 c->x86_phys_bits = 36; 1125 #endif 1126 c->x86_cache_bits = c->x86_phys_bits; 1127 } 1128 1129 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1130 { 1131 #ifdef CONFIG_X86_32 1132 int i; 1133 1134 /* 1135 * First of all, decide if this is a 486 or higher 1136 * It's a 486 if we can modify the AC flag 1137 */ 1138 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1139 c->x86 = 4; 1140 else 1141 c->x86 = 3; 1142 1143 for (i = 0; i < X86_VENDOR_NUM; i++) 1144 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1145 c->x86_vendor_id[0] = 0; 1146 cpu_devs[i]->c_identify(c); 1147 if (c->x86_vendor_id[0]) { 1148 get_cpu_vendor(c); 1149 break; 1150 } 1151 } 1152 #endif 1153 } 1154 1155 #define NO_SPECULATION BIT(0) 1156 #define NO_MELTDOWN BIT(1) 1157 #define NO_SSB BIT(2) 1158 #define NO_L1TF BIT(3) 1159 #define NO_MDS BIT(4) 1160 #define MSBDS_ONLY BIT(5) 1161 #define NO_SWAPGS BIT(6) 1162 #define NO_ITLB_MULTIHIT BIT(7) 1163 #define NO_SPECTRE_V2 BIT(8) 1164 #define NO_MMIO BIT(9) 1165 #define NO_EIBRS_PBRSB BIT(10) 1166 1167 #define VULNWL(vendor, family, model, whitelist) \ 1168 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1169 1170 #define VULNWL_INTEL(model, whitelist) \ 1171 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1172 1173 #define VULNWL_AMD(family, whitelist) \ 1174 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1175 1176 #define VULNWL_HYGON(family, whitelist) \ 1177 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1178 1179 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1180 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1181 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1182 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1183 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1184 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1185 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1186 1187 /* Intel Family 6 */ 1188 VULNWL_INTEL(TIGERLAKE, NO_MMIO), 1189 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), 1190 VULNWL_INTEL(ALDERLAKE, NO_MMIO), 1191 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), 1192 1193 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1194 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1195 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1196 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1197 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1198 1199 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1200 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1201 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1202 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1203 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1204 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1205 1206 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1207 1208 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1209 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1210 1211 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1212 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1213 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1214 1215 /* 1216 * Technically, swapgs isn't serializing on AMD (despite it previously 1217 * being documented as such in the APM). But according to AMD, %gs is 1218 * updated non-speculatively, and the issuing of %gs-relative memory 1219 * operands will be blocked until the %gs update completes, which is 1220 * good enough for our purposes. 1221 */ 1222 1223 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), 1224 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1225 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1226 1227 /* AMD Family 0xf - 0x12 */ 1228 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1229 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1230 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1231 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1232 1233 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1234 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1235 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1236 1237 /* Zhaoxin Family 7 */ 1238 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1239 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1240 {} 1241 }; 1242 1243 #define VULNBL(vendor, family, model, blacklist) \ 1244 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1245 1246 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1247 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1248 INTEL_FAM6_##model, steppings, \ 1249 X86_FEATURE_ANY, issues) 1250 1251 #define VULNBL_AMD(family, blacklist) \ 1252 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1253 1254 #define VULNBL_HYGON(family, blacklist) \ 1255 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1256 1257 #define SRBDS BIT(0) 1258 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1259 #define MMIO BIT(1) 1260 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1261 #define MMIO_SBDS BIT(2) 1262 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1263 #define RETBLEED BIT(3) 1264 /* CPU is affected by SMT (cross-thread) return predictions */ 1265 #define SMT_RSB BIT(4) 1266 1267 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1268 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1269 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1270 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1271 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1272 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), 1273 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), 1274 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1275 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), 1276 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1277 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1278 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED), 1279 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1280 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1281 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1282 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), 1283 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1284 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO), 1285 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO), 1286 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1287 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), 1288 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1289 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1290 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED), 1291 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1292 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO), 1293 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1294 1295 VULNBL_AMD(0x15, RETBLEED), 1296 VULNBL_AMD(0x16, RETBLEED), 1297 VULNBL_AMD(0x17, RETBLEED | SMT_RSB), 1298 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB), 1299 {} 1300 }; 1301 1302 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1303 { 1304 const struct x86_cpu_id *m = x86_match_cpu(table); 1305 1306 return m && !!(m->driver_data & which); 1307 } 1308 1309 u64 x86_read_arch_cap_msr(void) 1310 { 1311 u64 ia32_cap = 0; 1312 1313 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1314 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1315 1316 return ia32_cap; 1317 } 1318 1319 static bool arch_cap_mmio_immune(u64 ia32_cap) 1320 { 1321 return (ia32_cap & ARCH_CAP_FBSDP_NO && 1322 ia32_cap & ARCH_CAP_PSDP_NO && 1323 ia32_cap & ARCH_CAP_SBDR_SSDP_NO); 1324 } 1325 1326 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1327 { 1328 u64 ia32_cap = x86_read_arch_cap_msr(); 1329 1330 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1331 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1332 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1333 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1334 1335 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1336 return; 1337 1338 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1339 1340 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1341 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1342 1343 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1344 !(ia32_cap & ARCH_CAP_SSB_NO) && 1345 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1346 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1347 1348 /* 1349 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1350 * flag and protect from vendor-specific bugs via the whitelist. 1351 */ 1352 if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { 1353 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1354 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1355 !(ia32_cap & ARCH_CAP_PBRSB_NO)) 1356 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1357 } 1358 1359 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1360 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1361 setup_force_cpu_bug(X86_BUG_MDS); 1362 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1363 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1364 } 1365 1366 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1367 setup_force_cpu_bug(X86_BUG_SWAPGS); 1368 1369 /* 1370 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1371 * - TSX is supported or 1372 * - TSX_CTRL is present 1373 * 1374 * TSX_CTRL check is needed for cases when TSX could be disabled before 1375 * the kernel boot e.g. kexec. 1376 * TSX_CTRL check alone is not sufficient for cases when the microcode 1377 * update is not present or running as guest that don't get TSX_CTRL. 1378 */ 1379 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1380 (cpu_has(c, X86_FEATURE_RTM) || 1381 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1382 setup_force_cpu_bug(X86_BUG_TAA); 1383 1384 /* 1385 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1386 * in the vulnerability blacklist. 1387 * 1388 * Some of the implications and mitigation of Shared Buffers Data 1389 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1390 * SRBDS. 1391 */ 1392 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1393 cpu_has(c, X86_FEATURE_RDSEED)) && 1394 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1395 setup_force_cpu_bug(X86_BUG_SRBDS); 1396 1397 /* 1398 * Processor MMIO Stale Data bug enumeration 1399 * 1400 * Affected CPU list is generally enough to enumerate the vulnerability, 1401 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1402 * not want the guest to enumerate the bug. 1403 * 1404 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1405 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1406 */ 1407 if (!arch_cap_mmio_immune(ia32_cap)) { 1408 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1409 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1410 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1411 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1412 } 1413 1414 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1415 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA)) 1416 setup_force_cpu_bug(X86_BUG_RETBLEED); 1417 } 1418 1419 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1420 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1421 1422 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1423 return; 1424 1425 /* Rogue Data Cache Load? No! */ 1426 if (ia32_cap & ARCH_CAP_RDCL_NO) 1427 return; 1428 1429 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1430 1431 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1432 return; 1433 1434 setup_force_cpu_bug(X86_BUG_L1TF); 1435 } 1436 1437 /* 1438 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1439 * unfortunately, that's not true in practice because of early VIA 1440 * chips and (more importantly) broken virtualizers that are not easy 1441 * to detect. In the latter case it doesn't even *fail* reliably, so 1442 * probing for it doesn't even work. Disable it completely on 32-bit 1443 * unless we can find a reliable way to detect all the broken cases. 1444 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1445 */ 1446 static void detect_nopl(void) 1447 { 1448 #ifdef CONFIG_X86_32 1449 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1450 #else 1451 setup_force_cpu_cap(X86_FEATURE_NOPL); 1452 #endif 1453 } 1454 1455 /* 1456 * We parse cpu parameters early because fpu__init_system() is executed 1457 * before parse_early_param(). 1458 */ 1459 static void __init cpu_parse_early_param(void) 1460 { 1461 char arg[128]; 1462 char *argptr = arg, *opt; 1463 int arglen, taint = 0; 1464 1465 #ifdef CONFIG_X86_32 1466 if (cmdline_find_option_bool(boot_command_line, "no387")) 1467 #ifdef CONFIG_MATH_EMULATION 1468 setup_clear_cpu_cap(X86_FEATURE_FPU); 1469 #else 1470 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1471 #endif 1472 1473 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1474 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1475 #endif 1476 1477 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1478 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1479 1480 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1481 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1482 1483 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1484 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1485 1486 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1487 if (arglen <= 0) 1488 return; 1489 1490 pr_info("Clearing CPUID bits:"); 1491 1492 while (argptr) { 1493 bool found __maybe_unused = false; 1494 unsigned int bit; 1495 1496 opt = strsep(&argptr, ","); 1497 1498 /* 1499 * Handle naked numbers first for feature flags which don't 1500 * have names. 1501 */ 1502 if (!kstrtouint(opt, 10, &bit)) { 1503 if (bit < NCAPINTS * 32) { 1504 1505 #ifdef CONFIG_X86_FEATURE_NAMES 1506 /* empty-string, i.e., ""-defined feature flags */ 1507 if (!x86_cap_flags[bit]) 1508 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1509 else 1510 #endif 1511 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1512 1513 setup_clear_cpu_cap(bit); 1514 taint++; 1515 } 1516 /* 1517 * The assumption is that there are no feature names with only 1518 * numbers in the name thus go to the next argument. 1519 */ 1520 continue; 1521 } 1522 1523 #ifdef CONFIG_X86_FEATURE_NAMES 1524 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1525 if (!x86_cap_flag(bit)) 1526 continue; 1527 1528 if (strcmp(x86_cap_flag(bit), opt)) 1529 continue; 1530 1531 pr_cont(" %s", opt); 1532 setup_clear_cpu_cap(bit); 1533 taint++; 1534 found = true; 1535 break; 1536 } 1537 1538 if (!found) 1539 pr_cont(" (unknown: %s)", opt); 1540 #endif 1541 } 1542 pr_cont("\n"); 1543 1544 if (taint) 1545 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1546 } 1547 1548 /* 1549 * Do minimum CPU detection early. 1550 * Fields really needed: vendor, cpuid_level, family, model, mask, 1551 * cache alignment. 1552 * The others are not touched to avoid unwanted side effects. 1553 * 1554 * WARNING: this function is only called on the boot CPU. Don't add code 1555 * here that is supposed to run on all CPUs. 1556 */ 1557 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1558 { 1559 #ifdef CONFIG_X86_64 1560 c->x86_clflush_size = 64; 1561 c->x86_phys_bits = 36; 1562 c->x86_virt_bits = 48; 1563 #else 1564 c->x86_clflush_size = 32; 1565 c->x86_phys_bits = 32; 1566 c->x86_virt_bits = 32; 1567 #endif 1568 c->x86_cache_alignment = c->x86_clflush_size; 1569 1570 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1571 c->extended_cpuid_level = 0; 1572 1573 if (!have_cpuid_p()) 1574 identify_cpu_without_cpuid(c); 1575 1576 /* cyrix could have cpuid enabled via c_identify()*/ 1577 if (have_cpuid_p()) { 1578 cpu_detect(c); 1579 get_cpu_vendor(c); 1580 get_cpu_cap(c); 1581 get_cpu_address_sizes(c); 1582 setup_force_cpu_cap(X86_FEATURE_CPUID); 1583 cpu_parse_early_param(); 1584 1585 if (this_cpu->c_early_init) 1586 this_cpu->c_early_init(c); 1587 1588 c->cpu_index = 0; 1589 filter_cpuid_features(c, false); 1590 1591 if (this_cpu->c_bsp_init) 1592 this_cpu->c_bsp_init(c); 1593 } else { 1594 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1595 } 1596 1597 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1598 1599 cpu_set_bug_bits(c); 1600 1601 sld_setup(c); 1602 1603 fpu__init_system(c); 1604 1605 init_sigframe_size(); 1606 1607 #ifdef CONFIG_X86_32 1608 /* 1609 * Regardless of whether PCID is enumerated, the SDM says 1610 * that it can't be enabled in 32-bit mode. 1611 */ 1612 setup_clear_cpu_cap(X86_FEATURE_PCID); 1613 #endif 1614 1615 /* 1616 * Later in the boot process pgtable_l5_enabled() relies on 1617 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1618 * enabled by this point we need to clear the feature bit to avoid 1619 * false-positives at the later stage. 1620 * 1621 * pgtable_l5_enabled() can be false here for several reasons: 1622 * - 5-level paging is disabled compile-time; 1623 * - it's 32-bit kernel; 1624 * - machine doesn't support 5-level paging; 1625 * - user specified 'no5lvl' in kernel command line. 1626 */ 1627 if (!pgtable_l5_enabled()) 1628 setup_clear_cpu_cap(X86_FEATURE_LA57); 1629 1630 detect_nopl(); 1631 } 1632 1633 void __init early_cpu_init(void) 1634 { 1635 const struct cpu_dev *const *cdev; 1636 int count = 0; 1637 1638 #ifdef CONFIG_PROCESSOR_SELECT 1639 pr_info("KERNEL supported cpus:\n"); 1640 #endif 1641 1642 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1643 const struct cpu_dev *cpudev = *cdev; 1644 1645 if (count >= X86_VENDOR_NUM) 1646 break; 1647 cpu_devs[count] = cpudev; 1648 count++; 1649 1650 #ifdef CONFIG_PROCESSOR_SELECT 1651 { 1652 unsigned int j; 1653 1654 for (j = 0; j < 2; j++) { 1655 if (!cpudev->c_ident[j]) 1656 continue; 1657 pr_info(" %s %s\n", cpudev->c_vendor, 1658 cpudev->c_ident[j]); 1659 } 1660 } 1661 #endif 1662 } 1663 early_identify_cpu(&boot_cpu_data); 1664 } 1665 1666 static bool detect_null_seg_behavior(void) 1667 { 1668 /* 1669 * Empirically, writing zero to a segment selector on AMD does 1670 * not clear the base, whereas writing zero to a segment 1671 * selector on Intel does clear the base. Intel's behavior 1672 * allows slightly faster context switches in the common case 1673 * where GS is unused by the prev and next threads. 1674 * 1675 * Since neither vendor documents this anywhere that I can see, 1676 * detect it directly instead of hard-coding the choice by 1677 * vendor. 1678 * 1679 * I've designated AMD's behavior as the "bug" because it's 1680 * counterintuitive and less friendly. 1681 */ 1682 1683 unsigned long old_base, tmp; 1684 rdmsrl(MSR_FS_BASE, old_base); 1685 wrmsrl(MSR_FS_BASE, 1); 1686 loadsegment(fs, 0); 1687 rdmsrl(MSR_FS_BASE, tmp); 1688 wrmsrl(MSR_FS_BASE, old_base); 1689 return tmp == 0; 1690 } 1691 1692 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1693 { 1694 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1695 if (!IS_ENABLED(CONFIG_X86_64)) 1696 return; 1697 1698 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1699 return; 1700 1701 /* 1702 * CPUID bit above wasn't set. If this kernel is still running 1703 * as a HV guest, then the HV has decided not to advertize 1704 * that CPUID bit for whatever reason. For example, one 1705 * member of the migration pool might be vulnerable. Which 1706 * means, the bug is present: set the BUG flag and return. 1707 */ 1708 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1709 set_cpu_bug(c, X86_BUG_NULL_SEG); 1710 return; 1711 } 1712 1713 /* 1714 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1715 * 0x18 is the respective family for Hygon. 1716 */ 1717 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1718 detect_null_seg_behavior()) 1719 return; 1720 1721 /* All the remaining ones are affected */ 1722 set_cpu_bug(c, X86_BUG_NULL_SEG); 1723 } 1724 1725 static void generic_identify(struct cpuinfo_x86 *c) 1726 { 1727 c->extended_cpuid_level = 0; 1728 1729 if (!have_cpuid_p()) 1730 identify_cpu_without_cpuid(c); 1731 1732 /* cyrix could have cpuid enabled via c_identify()*/ 1733 if (!have_cpuid_p()) 1734 return; 1735 1736 cpu_detect(c); 1737 1738 get_cpu_vendor(c); 1739 1740 get_cpu_cap(c); 1741 1742 get_cpu_address_sizes(c); 1743 1744 if (c->cpuid_level >= 0x00000001) { 1745 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1746 #ifdef CONFIG_X86_32 1747 # ifdef CONFIG_SMP 1748 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1749 # else 1750 c->apicid = c->initial_apicid; 1751 # endif 1752 #endif 1753 c->phys_proc_id = c->initial_apicid; 1754 } 1755 1756 get_model_name(c); /* Default name */ 1757 1758 /* 1759 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1760 * systems that run Linux at CPL > 0 may or may not have the 1761 * issue, but, even if they have the issue, there's absolutely 1762 * nothing we can do about it because we can't use the real IRET 1763 * instruction. 1764 * 1765 * NB: For the time being, only 32-bit kernels support 1766 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1767 * whether to apply espfix using paravirt hooks. If any 1768 * non-paravirt system ever shows up that does *not* have the 1769 * ESPFIX issue, we can change this. 1770 */ 1771 #ifdef CONFIG_X86_32 1772 set_cpu_bug(c, X86_BUG_ESPFIX); 1773 #endif 1774 } 1775 1776 /* 1777 * Validate that ACPI/mptables have the same information about the 1778 * effective APIC id and update the package map. 1779 */ 1780 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1781 { 1782 #ifdef CONFIG_SMP 1783 unsigned int apicid, cpu = smp_processor_id(); 1784 1785 apicid = apic->cpu_present_to_apicid(cpu); 1786 1787 if (apicid != c->apicid) { 1788 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1789 cpu, apicid, c->initial_apicid); 1790 } 1791 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1792 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1793 #else 1794 c->logical_proc_id = 0; 1795 #endif 1796 } 1797 1798 /* 1799 * This does the hard work of actually picking apart the CPU stuff... 1800 */ 1801 static void identify_cpu(struct cpuinfo_x86 *c) 1802 { 1803 int i; 1804 1805 c->loops_per_jiffy = loops_per_jiffy; 1806 c->x86_cache_size = 0; 1807 c->x86_vendor = X86_VENDOR_UNKNOWN; 1808 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1809 c->x86_vendor_id[0] = '\0'; /* Unset */ 1810 c->x86_model_id[0] = '\0'; /* Unset */ 1811 c->x86_max_cores = 1; 1812 c->x86_coreid_bits = 0; 1813 c->cu_id = 0xff; 1814 #ifdef CONFIG_X86_64 1815 c->x86_clflush_size = 64; 1816 c->x86_phys_bits = 36; 1817 c->x86_virt_bits = 48; 1818 #else 1819 c->cpuid_level = -1; /* CPUID not detected */ 1820 c->x86_clflush_size = 32; 1821 c->x86_phys_bits = 32; 1822 c->x86_virt_bits = 32; 1823 #endif 1824 c->x86_cache_alignment = c->x86_clflush_size; 1825 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1826 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1827 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1828 #endif 1829 1830 generic_identify(c); 1831 1832 if (this_cpu->c_identify) 1833 this_cpu->c_identify(c); 1834 1835 /* Clear/Set all flags overridden by options, after probe */ 1836 apply_forced_caps(c); 1837 1838 #ifdef CONFIG_X86_64 1839 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1840 #endif 1841 1842 /* 1843 * Vendor-specific initialization. In this section we 1844 * canonicalize the feature flags, meaning if there are 1845 * features a certain CPU supports which CPUID doesn't 1846 * tell us, CPUID claiming incorrect flags, or other bugs, 1847 * we handle them here. 1848 * 1849 * At the end of this section, c->x86_capability better 1850 * indicate the features this CPU genuinely supports! 1851 */ 1852 if (this_cpu->c_init) 1853 this_cpu->c_init(c); 1854 1855 /* Disable the PN if appropriate */ 1856 squash_the_stupid_serial_number(c); 1857 1858 /* Set up SMEP/SMAP/UMIP */ 1859 setup_smep(c); 1860 setup_smap(c); 1861 setup_umip(c); 1862 1863 /* Enable FSGSBASE instructions if available. */ 1864 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1865 cr4_set_bits(X86_CR4_FSGSBASE); 1866 elf_hwcap2 |= HWCAP2_FSGSBASE; 1867 } 1868 1869 /* 1870 * The vendor-specific functions might have changed features. 1871 * Now we do "generic changes." 1872 */ 1873 1874 /* Filter out anything that depends on CPUID levels we don't have */ 1875 filter_cpuid_features(c, true); 1876 1877 /* If the model name is still unset, do table lookup. */ 1878 if (!c->x86_model_id[0]) { 1879 const char *p; 1880 p = table_lookup_model(c); 1881 if (p) 1882 strcpy(c->x86_model_id, p); 1883 else 1884 /* Last resort... */ 1885 sprintf(c->x86_model_id, "%02x/%02x", 1886 c->x86, c->x86_model); 1887 } 1888 1889 #ifdef CONFIG_X86_64 1890 detect_ht(c); 1891 #endif 1892 1893 x86_init_rdrand(c); 1894 setup_pku(c); 1895 setup_cet(c); 1896 1897 /* 1898 * Clear/Set all flags overridden by options, need do it 1899 * before following smp all cpus cap AND. 1900 */ 1901 apply_forced_caps(c); 1902 1903 /* 1904 * On SMP, boot_cpu_data holds the common feature set between 1905 * all CPUs; so make sure that we indicate which features are 1906 * common between the CPUs. The first time this routine gets 1907 * executed, c == &boot_cpu_data. 1908 */ 1909 if (c != &boot_cpu_data) { 1910 /* AND the already accumulated flags with these */ 1911 for (i = 0; i < NCAPINTS; i++) 1912 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1913 1914 /* OR, i.e. replicate the bug flags */ 1915 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1916 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1917 } 1918 1919 ppin_init(c); 1920 1921 /* Init Machine Check Exception if available. */ 1922 mcheck_cpu_init(c); 1923 1924 select_idle_routine(c); 1925 1926 #ifdef CONFIG_NUMA 1927 numa_add_cpu(smp_processor_id()); 1928 #endif 1929 } 1930 1931 /* 1932 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1933 * on 32-bit kernels: 1934 */ 1935 #ifdef CONFIG_X86_32 1936 void enable_sep_cpu(void) 1937 { 1938 struct tss_struct *tss; 1939 int cpu; 1940 1941 if (!boot_cpu_has(X86_FEATURE_SEP)) 1942 return; 1943 1944 cpu = get_cpu(); 1945 tss = &per_cpu(cpu_tss_rw, cpu); 1946 1947 /* 1948 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1949 * see the big comment in struct x86_hw_tss's definition. 1950 */ 1951 1952 tss->x86_tss.ss1 = __KERNEL_CS; 1953 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1954 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1955 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1956 1957 put_cpu(); 1958 } 1959 #endif 1960 1961 void __init identify_boot_cpu(void) 1962 { 1963 identify_cpu(&boot_cpu_data); 1964 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1965 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1966 #ifdef CONFIG_X86_32 1967 enable_sep_cpu(); 1968 #endif 1969 cpu_detect_tlb(&boot_cpu_data); 1970 setup_cr_pinning(); 1971 1972 tsx_init(); 1973 lkgs_init(); 1974 } 1975 1976 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1977 { 1978 BUG_ON(c == &boot_cpu_data); 1979 identify_cpu(c); 1980 #ifdef CONFIG_X86_32 1981 enable_sep_cpu(); 1982 #endif 1983 validate_apic_and_package_id(c); 1984 x86_spec_ctrl_setup_ap(); 1985 update_srbds_msr(); 1986 1987 tsx_ap_init(); 1988 } 1989 1990 void print_cpu_info(struct cpuinfo_x86 *c) 1991 { 1992 const char *vendor = NULL; 1993 1994 if (c->x86_vendor < X86_VENDOR_NUM) { 1995 vendor = this_cpu->c_vendor; 1996 } else { 1997 if (c->cpuid_level >= 0) 1998 vendor = c->x86_vendor_id; 1999 } 2000 2001 if (vendor && !strstr(c->x86_model_id, vendor)) 2002 pr_cont("%s ", vendor); 2003 2004 if (c->x86_model_id[0]) 2005 pr_cont("%s", c->x86_model_id); 2006 else 2007 pr_cont("%d86", c->x86); 2008 2009 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2010 2011 if (c->x86_stepping || c->cpuid_level >= 0) 2012 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2013 else 2014 pr_cont(")\n"); 2015 } 2016 2017 /* 2018 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 2019 * function prevents it from becoming an environment variable for init. 2020 */ 2021 static __init int setup_clearcpuid(char *arg) 2022 { 2023 return 1; 2024 } 2025 __setup("clearcpuid=", setup_clearcpuid); 2026 2027 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = { 2028 .current_task = &init_task, 2029 .preempt_count = INIT_PREEMPT_COUNT, 2030 .top_of_stack = TOP_OF_INIT_STACK, 2031 }; 2032 EXPORT_PER_CPU_SYMBOL(pcpu_hot); 2033 2034 #ifdef CONFIG_X86_64 2035 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 2036 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 2037 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2038 2039 static void wrmsrl_cstar(unsigned long val) 2040 { 2041 /* 2042 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2043 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2044 * guest. Avoid the pointless write on all Intel CPUs. 2045 */ 2046 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2047 wrmsrl(MSR_CSTAR, val); 2048 } 2049 2050 /* May not be marked __init: used by software suspend */ 2051 void syscall_init(void) 2052 { 2053 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2054 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2055 2056 #ifdef CONFIG_IA32_EMULATION 2057 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2058 /* 2059 * This only works on Intel CPUs. 2060 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2061 * This does not cause SYSENTER to jump to the wrong location, because 2062 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2063 */ 2064 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2065 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2066 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2067 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2068 #else 2069 wrmsrl_cstar((unsigned long)ignore_sysret); 2070 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2071 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2072 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2073 #endif 2074 2075 /* 2076 * Flags to clear on syscall; clear as much as possible 2077 * to minimize user space-kernel interference. 2078 */ 2079 wrmsrl(MSR_SYSCALL_MASK, 2080 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2081 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2082 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2083 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2084 X86_EFLAGS_AC|X86_EFLAGS_ID); 2085 } 2086 2087 #else /* CONFIG_X86_64 */ 2088 2089 #ifdef CONFIG_STACKPROTECTOR 2090 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2091 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2092 #endif 2093 2094 #endif /* CONFIG_X86_64 */ 2095 2096 /* 2097 * Clear all 6 debug registers: 2098 */ 2099 static void clear_all_debug_regs(void) 2100 { 2101 int i; 2102 2103 for (i = 0; i < 8; i++) { 2104 /* Ignore db4, db5 */ 2105 if ((i == 4) || (i == 5)) 2106 continue; 2107 2108 set_debugreg(0, i); 2109 } 2110 } 2111 2112 #ifdef CONFIG_KGDB 2113 /* 2114 * Restore debug regs if using kgdbwait and you have a kernel debugger 2115 * connection established. 2116 */ 2117 static void dbg_restore_debug_regs(void) 2118 { 2119 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2120 arch_kgdb_ops.correct_hw_break(); 2121 } 2122 #else /* ! CONFIG_KGDB */ 2123 #define dbg_restore_debug_regs() 2124 #endif /* ! CONFIG_KGDB */ 2125 2126 static void wait_for_master_cpu(int cpu) 2127 { 2128 #ifdef CONFIG_SMP 2129 /* 2130 * wait for ACK from master CPU before continuing 2131 * with AP initialization 2132 */ 2133 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 2134 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 2135 cpu_relax(); 2136 #endif 2137 } 2138 2139 static inline void setup_getcpu(int cpu) 2140 { 2141 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2142 struct desc_struct d = { }; 2143 2144 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2145 wrmsr(MSR_TSC_AUX, cpudata, 0); 2146 2147 /* Store CPU and node number in limit. */ 2148 d.limit0 = cpudata; 2149 d.limit1 = cpudata >> 16; 2150 2151 d.type = 5; /* RO data, expand down, accessed */ 2152 d.dpl = 3; /* Visible to user code */ 2153 d.s = 1; /* Not a system segment */ 2154 d.p = 1; /* Present */ 2155 d.d = 1; /* 32-bit */ 2156 2157 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2158 } 2159 2160 #ifdef CONFIG_X86_64 2161 static inline void ucode_cpu_init(int cpu) 2162 { 2163 if (cpu) 2164 load_ucode_ap(); 2165 } 2166 2167 static inline void tss_setup_ist(struct tss_struct *tss) 2168 { 2169 /* Set up the per-CPU TSS IST stacks */ 2170 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2171 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2172 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2173 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2174 /* Only mapped when SEV-ES is active */ 2175 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2176 } 2177 2178 #else /* CONFIG_X86_64 */ 2179 2180 static inline void ucode_cpu_init(int cpu) 2181 { 2182 show_ucode_info_early(); 2183 } 2184 2185 static inline void tss_setup_ist(struct tss_struct *tss) { } 2186 2187 #endif /* !CONFIG_X86_64 */ 2188 2189 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2190 { 2191 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2192 2193 #ifdef CONFIG_X86_IOPL_IOPERM 2194 tss->io_bitmap.prev_max = 0; 2195 tss->io_bitmap.prev_sequence = 0; 2196 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2197 /* 2198 * Invalidate the extra array entry past the end of the all 2199 * permission bitmap as required by the hardware. 2200 */ 2201 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2202 #endif 2203 } 2204 2205 /* 2206 * Setup everything needed to handle exceptions from the IDT, including the IST 2207 * exceptions which use paranoid_entry(). 2208 */ 2209 void cpu_init_exception_handling(void) 2210 { 2211 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2212 int cpu = raw_smp_processor_id(); 2213 2214 /* paranoid_entry() gets the CPU number from the GDT */ 2215 setup_getcpu(cpu); 2216 2217 /* IST vectors need TSS to be set up. */ 2218 tss_setup_ist(tss); 2219 tss_setup_io_bitmap(tss); 2220 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2221 2222 load_TR_desc(); 2223 2224 /* GHCB needs to be setup to handle #VC. */ 2225 setup_ghcb(); 2226 2227 /* Finally load the IDT */ 2228 load_current_idt(); 2229 } 2230 2231 /* 2232 * cpu_init() initializes state that is per-CPU. Some data is already 2233 * initialized (naturally) in the bootstrap process, such as the GDT. We 2234 * reload it nevertheless, this function acts as a 'CPU state barrier', 2235 * nothing should get across. 2236 */ 2237 void cpu_init(void) 2238 { 2239 struct task_struct *cur = current; 2240 int cpu = raw_smp_processor_id(); 2241 2242 wait_for_master_cpu(cpu); 2243 2244 ucode_cpu_init(cpu); 2245 2246 #ifdef CONFIG_NUMA 2247 if (this_cpu_read(numa_node) == 0 && 2248 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2249 set_numa_node(early_cpu_to_node(cpu)); 2250 #endif 2251 pr_debug("Initializing CPU#%d\n", cpu); 2252 2253 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2254 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2255 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2256 2257 if (IS_ENABLED(CONFIG_X86_64)) { 2258 loadsegment(fs, 0); 2259 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2260 syscall_init(); 2261 2262 wrmsrl(MSR_FS_BASE, 0); 2263 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2264 barrier(); 2265 2266 x2apic_setup(); 2267 } 2268 2269 mmgrab(&init_mm); 2270 cur->active_mm = &init_mm; 2271 BUG_ON(cur->mm); 2272 initialize_tlbstate_and_flush(); 2273 enter_lazy_tlb(&init_mm, cur); 2274 2275 /* 2276 * sp0 points to the entry trampoline stack regardless of what task 2277 * is running. 2278 */ 2279 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2280 2281 load_mm_ldt(&init_mm); 2282 2283 clear_all_debug_regs(); 2284 dbg_restore_debug_regs(); 2285 2286 doublefault_init_cpu_tss(); 2287 2288 fpu__init_cpu(); 2289 2290 if (is_uv_system()) 2291 uv_cpu_init(); 2292 2293 load_fixmap_gdt(cpu); 2294 } 2295 2296 #ifdef CONFIG_SMP 2297 void cpu_init_secondary(void) 2298 { 2299 /* 2300 * Relies on the BP having set-up the IDT tables, which are loaded 2301 * on this CPU in cpu_init_exception_handling(). 2302 */ 2303 cpu_init_exception_handling(); 2304 cpu_init(); 2305 } 2306 #endif 2307 2308 #ifdef CONFIG_MICROCODE_LATE_LOADING 2309 /** 2310 * store_cpu_caps() - Store a snapshot of CPU capabilities 2311 * @curr_info: Pointer where to store it 2312 * 2313 * Returns: None 2314 */ 2315 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2316 { 2317 /* Reload CPUID max function as it might've changed. */ 2318 curr_info->cpuid_level = cpuid_eax(0); 2319 2320 /* Copy all capability leafs and pick up the synthetic ones. */ 2321 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2322 sizeof(curr_info->x86_capability)); 2323 2324 /* Get the hardware CPUID leafs */ 2325 get_cpu_cap(curr_info); 2326 } 2327 2328 /** 2329 * microcode_check() - Check if any CPU capabilities changed after an update. 2330 * @prev_info: CPU capabilities stored before an update. 2331 * 2332 * The microcode loader calls this upon late microcode load to recheck features, 2333 * only when microcode has been updated. Caller holds microcode_mutex and CPU 2334 * hotplug lock. 2335 * 2336 * Return: None 2337 */ 2338 void microcode_check(struct cpuinfo_x86 *prev_info) 2339 { 2340 struct cpuinfo_x86 curr_info; 2341 2342 perf_check_microcode(); 2343 2344 store_cpu_caps(&curr_info); 2345 2346 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2347 sizeof(prev_info->x86_capability))) 2348 return; 2349 2350 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2351 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2352 } 2353 #endif 2354 2355 /* 2356 * Invoked from core CPU hotplug code after hotplug operations 2357 */ 2358 void arch_smt_update(void) 2359 { 2360 /* Handle the speculative execution misfeatures */ 2361 cpu_bugs_smt_update(); 2362 /* Check whether IPI broadcasting can be enabled */ 2363 apic_smt_update(); 2364 } 2365