1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/init.h> 18 #include <linux/kprobes.h> 19 #include <linux/kgdb.h> 20 #include <linux/smp.h> 21 #include <linux/io.h> 22 #include <linux/syscore_ops.h> 23 24 #include <asm/stackprotector.h> 25 #include <asm/perf_event.h> 26 #include <asm/mmu_context.h> 27 #include <asm/doublefault.h> 28 #include <asm/archrandom.h> 29 #include <asm/hypervisor.h> 30 #include <asm/processor.h> 31 #include <asm/tlbflush.h> 32 #include <asm/debugreg.h> 33 #include <asm/sections.h> 34 #include <asm/vsyscall.h> 35 #include <linux/topology.h> 36 #include <linux/cpumask.h> 37 #include <asm/pgtable.h> 38 #include <linux/atomic.h> 39 #include <asm/proto.h> 40 #include <asm/setup.h> 41 #include <asm/apic.h> 42 #include <asm/desc.h> 43 #include <asm/fpu/internal.h> 44 #include <asm/mtrr.h> 45 #include <asm/hwcap2.h> 46 #include <linux/numa.h> 47 #include <asm/asm.h> 48 #include <asm/bugs.h> 49 #include <asm/cpu.h> 50 #include <asm/mce.h> 51 #include <asm/msr.h> 52 #include <asm/pat.h> 53 #include <asm/microcode.h> 54 #include <asm/microcode_intel.h> 55 #include <asm/intel-family.h> 56 #include <asm/cpu_device_id.h> 57 #include <asm/uv/uv.h> 58 59 #include "cpu.h" 60 61 u32 elf_hwcap2 __read_mostly; 62 63 /* all of these masks are initialized in setup_cpu_local_masks() */ 64 cpumask_var_t cpu_initialized_mask; 65 cpumask_var_t cpu_callout_mask; 66 cpumask_var_t cpu_callin_mask; 67 68 /* representing cpus for which sibling maps can be computed */ 69 cpumask_var_t cpu_sibling_setup_mask; 70 71 /* Number of siblings per CPU package */ 72 int smp_num_siblings = 1; 73 EXPORT_SYMBOL(smp_num_siblings); 74 75 /* Last level cache ID of each logical CPU */ 76 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 77 78 /* correctly size the local cpu masks */ 79 void __init setup_cpu_local_masks(void) 80 { 81 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 82 alloc_bootmem_cpumask_var(&cpu_callin_mask); 83 alloc_bootmem_cpumask_var(&cpu_callout_mask); 84 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 85 } 86 87 static void default_init(struct cpuinfo_x86 *c) 88 { 89 #ifdef CONFIG_X86_64 90 cpu_detect_cache_sizes(c); 91 #else 92 /* Not much we can do here... */ 93 /* Check if at least it has cpuid */ 94 if (c->cpuid_level == -1) { 95 /* No cpuid. It must be an ancient CPU */ 96 if (c->x86 == 4) 97 strcpy(c->x86_model_id, "486"); 98 else if (c->x86 == 3) 99 strcpy(c->x86_model_id, "386"); 100 } 101 #endif 102 } 103 104 static const struct cpu_dev default_cpu = { 105 .c_init = default_init, 106 .c_vendor = "Unknown", 107 .c_x86_vendor = X86_VENDOR_UNKNOWN, 108 }; 109 110 static const struct cpu_dev *this_cpu = &default_cpu; 111 112 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 113 #ifdef CONFIG_X86_64 114 /* 115 * We need valid kernel segments for data and code in long mode too 116 * IRET will check the segment types kkeil 2000/10/28 117 * Also sysret mandates a special GDT layout 118 * 119 * TLS descriptors are currently at a different place compared to i386. 120 * Hopefully nobody expects them at a fixed place (Wine?) 121 */ 122 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 123 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 124 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 125 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 126 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 128 #else 129 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 130 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 131 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 132 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 133 /* 134 * Segments used for calling PnP BIOS have byte granularity. 135 * They code segments and data segments have fixed 64k limits, 136 * the transfer segment sizes are set at run time. 137 */ 138 /* 32-bit code */ 139 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 140 /* 16-bit code */ 141 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 142 /* 16-bit data */ 143 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 144 /* 16-bit data */ 145 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 146 /* 16-bit data */ 147 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 148 /* 149 * The APM segments have byte granularity and their bases 150 * are set at run time. All have 64k limits. 151 */ 152 /* 32-bit code */ 153 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 154 /* 16-bit code */ 155 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 156 /* data */ 157 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 158 159 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 160 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 161 GDT_STACK_CANARY_INIT 162 #endif 163 } }; 164 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 165 166 static int __init x86_mpx_setup(char *s) 167 { 168 /* require an exact match without trailing characters */ 169 if (strlen(s)) 170 return 0; 171 172 /* do not emit a message if the feature is not present */ 173 if (!boot_cpu_has(X86_FEATURE_MPX)) 174 return 1; 175 176 setup_clear_cpu_cap(X86_FEATURE_MPX); 177 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 178 return 1; 179 } 180 __setup("nompx", x86_mpx_setup); 181 182 #ifdef CONFIG_X86_64 183 static int __init x86_nopcid_setup(char *s) 184 { 185 /* nopcid doesn't accept parameters */ 186 if (s) 187 return -EINVAL; 188 189 /* do not emit a message if the feature is not present */ 190 if (!boot_cpu_has(X86_FEATURE_PCID)) 191 return 0; 192 193 setup_clear_cpu_cap(X86_FEATURE_PCID); 194 pr_info("nopcid: PCID feature disabled\n"); 195 return 0; 196 } 197 early_param("nopcid", x86_nopcid_setup); 198 #endif 199 200 static int __init x86_noinvpcid_setup(char *s) 201 { 202 /* noinvpcid doesn't accept parameters */ 203 if (s) 204 return -EINVAL; 205 206 /* do not emit a message if the feature is not present */ 207 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 208 return 0; 209 210 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 211 pr_info("noinvpcid: INVPCID feature disabled\n"); 212 return 0; 213 } 214 early_param("noinvpcid", x86_noinvpcid_setup); 215 216 #ifdef CONFIG_X86_32 217 static int cachesize_override = -1; 218 static int disable_x86_serial_nr = 1; 219 220 static int __init cachesize_setup(char *str) 221 { 222 get_option(&str, &cachesize_override); 223 return 1; 224 } 225 __setup("cachesize=", cachesize_setup); 226 227 static int __init x86_sep_setup(char *s) 228 { 229 setup_clear_cpu_cap(X86_FEATURE_SEP); 230 return 1; 231 } 232 __setup("nosep", x86_sep_setup); 233 234 /* Standard macro to see if a specific flag is changeable */ 235 static inline int flag_is_changeable_p(u32 flag) 236 { 237 u32 f1, f2; 238 239 /* 240 * Cyrix and IDT cpus allow disabling of CPUID 241 * so the code below may return different results 242 * when it is executed before and after enabling 243 * the CPUID. Add "volatile" to not allow gcc to 244 * optimize the subsequent calls to this function. 245 */ 246 asm volatile ("pushfl \n\t" 247 "pushfl \n\t" 248 "popl %0 \n\t" 249 "movl %0, %1 \n\t" 250 "xorl %2, %0 \n\t" 251 "pushl %0 \n\t" 252 "popfl \n\t" 253 "pushfl \n\t" 254 "popl %0 \n\t" 255 "popfl \n\t" 256 257 : "=&r" (f1), "=&r" (f2) 258 : "ir" (flag)); 259 260 return ((f1^f2) & flag) != 0; 261 } 262 263 /* Probe for the CPUID instruction */ 264 int have_cpuid_p(void) 265 { 266 return flag_is_changeable_p(X86_EFLAGS_ID); 267 } 268 269 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 270 { 271 unsigned long lo, hi; 272 273 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 274 return; 275 276 /* Disable processor serial number: */ 277 278 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 279 lo |= 0x200000; 280 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 281 282 pr_notice("CPU serial number disabled.\n"); 283 clear_cpu_cap(c, X86_FEATURE_PN); 284 285 /* Disabling the serial number may affect the cpuid level */ 286 c->cpuid_level = cpuid_eax(0); 287 } 288 289 static int __init x86_serial_nr_setup(char *s) 290 { 291 disable_x86_serial_nr = 0; 292 return 1; 293 } 294 __setup("serialnumber", x86_serial_nr_setup); 295 #else 296 static inline int flag_is_changeable_p(u32 flag) 297 { 298 return 1; 299 } 300 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 301 { 302 } 303 #endif 304 305 static __init int setup_disable_smep(char *arg) 306 { 307 setup_clear_cpu_cap(X86_FEATURE_SMEP); 308 /* Check for things that depend on SMEP being enabled: */ 309 check_mpx_erratum(&boot_cpu_data); 310 return 1; 311 } 312 __setup("nosmep", setup_disable_smep); 313 314 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 315 { 316 if (cpu_has(c, X86_FEATURE_SMEP)) 317 cr4_set_bits(X86_CR4_SMEP); 318 } 319 320 static __init int setup_disable_smap(char *arg) 321 { 322 setup_clear_cpu_cap(X86_FEATURE_SMAP); 323 return 1; 324 } 325 __setup("nosmap", setup_disable_smap); 326 327 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 328 { 329 unsigned long eflags = native_save_fl(); 330 331 /* This should have been cleared long ago */ 332 BUG_ON(eflags & X86_EFLAGS_AC); 333 334 if (cpu_has(c, X86_FEATURE_SMAP)) { 335 #ifdef CONFIG_X86_SMAP 336 cr4_set_bits(X86_CR4_SMAP); 337 #else 338 cr4_clear_bits(X86_CR4_SMAP); 339 #endif 340 } 341 } 342 343 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 344 { 345 /* Check the boot processor, plus build option for UMIP. */ 346 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 347 goto out; 348 349 /* Check the current processor's cpuid bits. */ 350 if (!cpu_has(c, X86_FEATURE_UMIP)) 351 goto out; 352 353 cr4_set_bits(X86_CR4_UMIP); 354 355 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 356 357 return; 358 359 out: 360 /* 361 * Make sure UMIP is disabled in case it was enabled in a 362 * previous boot (e.g., via kexec). 363 */ 364 cr4_clear_bits(X86_CR4_UMIP); 365 } 366 367 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 368 static unsigned long cr4_pinned_bits __ro_after_init; 369 370 void native_write_cr0(unsigned long val) 371 { 372 unsigned long bits_missing = 0; 373 374 set_register: 375 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); 376 377 if (static_branch_likely(&cr_pinning)) { 378 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 379 bits_missing = X86_CR0_WP; 380 val |= bits_missing; 381 goto set_register; 382 } 383 /* Warn after we've set the missing bits. */ 384 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 385 } 386 } 387 EXPORT_SYMBOL(native_write_cr0); 388 389 void native_write_cr4(unsigned long val) 390 { 391 unsigned long bits_missing = 0; 392 393 set_register: 394 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); 395 396 if (static_branch_likely(&cr_pinning)) { 397 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { 398 bits_missing = ~val & cr4_pinned_bits; 399 val |= bits_missing; 400 goto set_register; 401 } 402 /* Warn after we've set the missing bits. */ 403 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n", 404 bits_missing); 405 } 406 } 407 EXPORT_SYMBOL(native_write_cr4); 408 409 void cr4_init(void) 410 { 411 unsigned long cr4 = __read_cr4(); 412 413 if (boot_cpu_has(X86_FEATURE_PCID)) 414 cr4 |= X86_CR4_PCIDE; 415 if (static_branch_likely(&cr_pinning)) 416 cr4 |= cr4_pinned_bits; 417 418 __write_cr4(cr4); 419 420 /* Initialize cr4 shadow for this CPU. */ 421 this_cpu_write(cpu_tlbstate.cr4, cr4); 422 } 423 424 /* 425 * Once CPU feature detection is finished (and boot params have been 426 * parsed), record any of the sensitive CR bits that are set, and 427 * enable CR pinning. 428 */ 429 static void __init setup_cr_pinning(void) 430 { 431 unsigned long mask; 432 433 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); 434 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; 435 static_key_enable(&cr_pinning.key); 436 } 437 438 /* 439 * Protection Keys are not available in 32-bit mode. 440 */ 441 static bool pku_disabled; 442 443 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 444 { 445 struct pkru_state *pk; 446 447 /* check the boot processor, plus compile options for PKU: */ 448 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 449 return; 450 /* checks the actual processor's cpuid bits: */ 451 if (!cpu_has(c, X86_FEATURE_PKU)) 452 return; 453 if (pku_disabled) 454 return; 455 456 cr4_set_bits(X86_CR4_PKE); 457 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 458 if (pk) 459 pk->pkru = init_pkru_value; 460 /* 461 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 462 * cpuid bit to be set. We need to ensure that we 463 * update that bit in this CPU's "cpu_info". 464 */ 465 get_cpu_cap(c); 466 } 467 468 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 469 static __init int setup_disable_pku(char *arg) 470 { 471 /* 472 * Do not clear the X86_FEATURE_PKU bit. All of the 473 * runtime checks are against OSPKE so clearing the 474 * bit does nothing. 475 * 476 * This way, we will see "pku" in cpuinfo, but not 477 * "ospke", which is exactly what we want. It shows 478 * that the CPU has PKU, but the OS has not enabled it. 479 * This happens to be exactly how a system would look 480 * if we disabled the config option. 481 */ 482 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 483 pku_disabled = true; 484 return 1; 485 } 486 __setup("nopku", setup_disable_pku); 487 #endif /* CONFIG_X86_64 */ 488 489 /* 490 * Some CPU features depend on higher CPUID levels, which may not always 491 * be available due to CPUID level capping or broken virtualization 492 * software. Add those features to this table to auto-disable them. 493 */ 494 struct cpuid_dependent_feature { 495 u32 feature; 496 u32 level; 497 }; 498 499 static const struct cpuid_dependent_feature 500 cpuid_dependent_features[] = { 501 { X86_FEATURE_MWAIT, 0x00000005 }, 502 { X86_FEATURE_DCA, 0x00000009 }, 503 { X86_FEATURE_XSAVE, 0x0000000d }, 504 { 0, 0 } 505 }; 506 507 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 508 { 509 const struct cpuid_dependent_feature *df; 510 511 for (df = cpuid_dependent_features; df->feature; df++) { 512 513 if (!cpu_has(c, df->feature)) 514 continue; 515 /* 516 * Note: cpuid_level is set to -1 if unavailable, but 517 * extended_extended_level is set to 0 if unavailable 518 * and the legitimate extended levels are all negative 519 * when signed; hence the weird messing around with 520 * signs here... 521 */ 522 if (!((s32)df->level < 0 ? 523 (u32)df->level > (u32)c->extended_cpuid_level : 524 (s32)df->level > (s32)c->cpuid_level)) 525 continue; 526 527 clear_cpu_cap(c, df->feature); 528 if (!warn) 529 continue; 530 531 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 532 x86_cap_flag(df->feature), df->level); 533 } 534 } 535 536 /* 537 * Naming convention should be: <Name> [(<Codename>)] 538 * This table only is used unless init_<vendor>() below doesn't set it; 539 * in particular, if CPUID levels 0x80000002..4 are supported, this 540 * isn't used 541 */ 542 543 /* Look up CPU names by table lookup. */ 544 static const char *table_lookup_model(struct cpuinfo_x86 *c) 545 { 546 #ifdef CONFIG_X86_32 547 const struct legacy_cpu_model_info *info; 548 549 if (c->x86_model >= 16) 550 return NULL; /* Range check */ 551 552 if (!this_cpu) 553 return NULL; 554 555 info = this_cpu->legacy_models; 556 557 while (info->family) { 558 if (info->family == c->x86) 559 return info->model_names[c->x86_model]; 560 info++; 561 } 562 #endif 563 return NULL; /* Not found */ 564 } 565 566 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 567 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 568 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 569 570 void load_percpu_segment(int cpu) 571 { 572 #ifdef CONFIG_X86_32 573 loadsegment(fs, __KERNEL_PERCPU); 574 #else 575 __loadsegment_simple(gs, 0); 576 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 577 #endif 578 load_stack_canary_segment(); 579 } 580 581 #ifdef CONFIG_X86_32 582 /* The 32-bit entry code needs to find cpu_entry_area. */ 583 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 584 #endif 585 586 /* Load the original GDT from the per-cpu structure */ 587 void load_direct_gdt(int cpu) 588 { 589 struct desc_ptr gdt_descr; 590 591 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 592 gdt_descr.size = GDT_SIZE - 1; 593 load_gdt(&gdt_descr); 594 } 595 EXPORT_SYMBOL_GPL(load_direct_gdt); 596 597 /* Load a fixmap remapping of the per-cpu GDT */ 598 void load_fixmap_gdt(int cpu) 599 { 600 struct desc_ptr gdt_descr; 601 602 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 603 gdt_descr.size = GDT_SIZE - 1; 604 load_gdt(&gdt_descr); 605 } 606 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 607 608 /* 609 * Current gdt points %fs at the "master" per-cpu area: after this, 610 * it's on the real one. 611 */ 612 void switch_to_new_gdt(int cpu) 613 { 614 /* Load the original GDT */ 615 load_direct_gdt(cpu); 616 /* Reload the per-cpu base */ 617 load_percpu_segment(cpu); 618 } 619 620 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 621 622 static void get_model_name(struct cpuinfo_x86 *c) 623 { 624 unsigned int *v; 625 char *p, *q, *s; 626 627 if (c->extended_cpuid_level < 0x80000004) 628 return; 629 630 v = (unsigned int *)c->x86_model_id; 631 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 632 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 633 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 634 c->x86_model_id[48] = 0; 635 636 /* Trim whitespace */ 637 p = q = s = &c->x86_model_id[0]; 638 639 while (*p == ' ') 640 p++; 641 642 while (*p) { 643 /* Note the last non-whitespace index */ 644 if (!isspace(*p)) 645 s = q; 646 647 *q++ = *p++; 648 } 649 650 *(s + 1) = '\0'; 651 } 652 653 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 654 { 655 unsigned int eax, ebx, ecx, edx; 656 657 c->x86_max_cores = 1; 658 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 659 return; 660 661 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 662 if (eax & 0x1f) 663 c->x86_max_cores = (eax >> 26) + 1; 664 } 665 666 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 667 { 668 unsigned int n, dummy, ebx, ecx, edx, l2size; 669 670 n = c->extended_cpuid_level; 671 672 if (n >= 0x80000005) { 673 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 674 c->x86_cache_size = (ecx>>24) + (edx>>24); 675 #ifdef CONFIG_X86_64 676 /* On K8 L1 TLB is inclusive, so don't count it */ 677 c->x86_tlbsize = 0; 678 #endif 679 } 680 681 if (n < 0x80000006) /* Some chips just has a large L1. */ 682 return; 683 684 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 685 l2size = ecx >> 16; 686 687 #ifdef CONFIG_X86_64 688 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 689 #else 690 /* do processor-specific cache resizing */ 691 if (this_cpu->legacy_cache_size) 692 l2size = this_cpu->legacy_cache_size(c, l2size); 693 694 /* Allow user to override all this if necessary. */ 695 if (cachesize_override != -1) 696 l2size = cachesize_override; 697 698 if (l2size == 0) 699 return; /* Again, no L2 cache is possible */ 700 #endif 701 702 c->x86_cache_size = l2size; 703 } 704 705 u16 __read_mostly tlb_lli_4k[NR_INFO]; 706 u16 __read_mostly tlb_lli_2m[NR_INFO]; 707 u16 __read_mostly tlb_lli_4m[NR_INFO]; 708 u16 __read_mostly tlb_lld_4k[NR_INFO]; 709 u16 __read_mostly tlb_lld_2m[NR_INFO]; 710 u16 __read_mostly tlb_lld_4m[NR_INFO]; 711 u16 __read_mostly tlb_lld_1g[NR_INFO]; 712 713 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 714 { 715 if (this_cpu->c_detect_tlb) 716 this_cpu->c_detect_tlb(c); 717 718 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 719 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 720 tlb_lli_4m[ENTRIES]); 721 722 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 723 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 724 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 725 } 726 727 int detect_ht_early(struct cpuinfo_x86 *c) 728 { 729 #ifdef CONFIG_SMP 730 u32 eax, ebx, ecx, edx; 731 732 if (!cpu_has(c, X86_FEATURE_HT)) 733 return -1; 734 735 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 736 return -1; 737 738 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 739 return -1; 740 741 cpuid(1, &eax, &ebx, &ecx, &edx); 742 743 smp_num_siblings = (ebx & 0xff0000) >> 16; 744 if (smp_num_siblings == 1) 745 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 746 #endif 747 return 0; 748 } 749 750 void detect_ht(struct cpuinfo_x86 *c) 751 { 752 #ifdef CONFIG_SMP 753 int index_msb, core_bits; 754 755 if (detect_ht_early(c) < 0) 756 return; 757 758 index_msb = get_count_order(smp_num_siblings); 759 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 760 761 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 762 763 index_msb = get_count_order(smp_num_siblings); 764 765 core_bits = get_count_order(c->x86_max_cores); 766 767 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 768 ((1 << core_bits) - 1); 769 #endif 770 } 771 772 static void get_cpu_vendor(struct cpuinfo_x86 *c) 773 { 774 char *v = c->x86_vendor_id; 775 int i; 776 777 for (i = 0; i < X86_VENDOR_NUM; i++) { 778 if (!cpu_devs[i]) 779 break; 780 781 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 782 (cpu_devs[i]->c_ident[1] && 783 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 784 785 this_cpu = cpu_devs[i]; 786 c->x86_vendor = this_cpu->c_x86_vendor; 787 return; 788 } 789 } 790 791 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 792 "CPU: Your system may be unstable.\n", v); 793 794 c->x86_vendor = X86_VENDOR_UNKNOWN; 795 this_cpu = &default_cpu; 796 } 797 798 void cpu_detect(struct cpuinfo_x86 *c) 799 { 800 /* Get vendor name */ 801 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 802 (unsigned int *)&c->x86_vendor_id[0], 803 (unsigned int *)&c->x86_vendor_id[8], 804 (unsigned int *)&c->x86_vendor_id[4]); 805 806 c->x86 = 4; 807 /* Intel-defined flags: level 0x00000001 */ 808 if (c->cpuid_level >= 0x00000001) { 809 u32 junk, tfms, cap0, misc; 810 811 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 812 c->x86 = x86_family(tfms); 813 c->x86_model = x86_model(tfms); 814 c->x86_stepping = x86_stepping(tfms); 815 816 if (cap0 & (1<<19)) { 817 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 818 c->x86_cache_alignment = c->x86_clflush_size; 819 } 820 } 821 } 822 823 static void apply_forced_caps(struct cpuinfo_x86 *c) 824 { 825 int i; 826 827 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 828 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 829 c->x86_capability[i] |= cpu_caps_set[i]; 830 } 831 } 832 833 static void init_speculation_control(struct cpuinfo_x86 *c) 834 { 835 /* 836 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 837 * and they also have a different bit for STIBP support. Also, 838 * a hypervisor might have set the individual AMD bits even on 839 * Intel CPUs, for finer-grained selection of what's available. 840 */ 841 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 842 set_cpu_cap(c, X86_FEATURE_IBRS); 843 set_cpu_cap(c, X86_FEATURE_IBPB); 844 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 845 } 846 847 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 848 set_cpu_cap(c, X86_FEATURE_STIBP); 849 850 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 851 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 852 set_cpu_cap(c, X86_FEATURE_SSBD); 853 854 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 855 set_cpu_cap(c, X86_FEATURE_IBRS); 856 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 857 } 858 859 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 860 set_cpu_cap(c, X86_FEATURE_IBPB); 861 862 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 863 set_cpu_cap(c, X86_FEATURE_STIBP); 864 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 865 } 866 867 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 868 set_cpu_cap(c, X86_FEATURE_SSBD); 869 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 870 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 871 } 872 } 873 874 static void init_cqm(struct cpuinfo_x86 *c) 875 { 876 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 877 c->x86_cache_max_rmid = -1; 878 c->x86_cache_occ_scale = -1; 879 return; 880 } 881 882 /* will be overridden if occupancy monitoring exists */ 883 c->x86_cache_max_rmid = cpuid_ebx(0xf); 884 885 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 886 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 887 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 888 u32 eax, ebx, ecx, edx; 889 890 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 891 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 892 893 c->x86_cache_max_rmid = ecx; 894 c->x86_cache_occ_scale = ebx; 895 } 896 } 897 898 void get_cpu_cap(struct cpuinfo_x86 *c) 899 { 900 u32 eax, ebx, ecx, edx; 901 902 /* Intel-defined flags: level 0x00000001 */ 903 if (c->cpuid_level >= 0x00000001) { 904 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 905 906 c->x86_capability[CPUID_1_ECX] = ecx; 907 c->x86_capability[CPUID_1_EDX] = edx; 908 } 909 910 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 911 if (c->cpuid_level >= 0x00000006) 912 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 913 914 /* Additional Intel-defined flags: level 0x00000007 */ 915 if (c->cpuid_level >= 0x00000007) { 916 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 917 c->x86_capability[CPUID_7_0_EBX] = ebx; 918 c->x86_capability[CPUID_7_ECX] = ecx; 919 c->x86_capability[CPUID_7_EDX] = edx; 920 921 /* Check valid sub-leaf index before accessing it */ 922 if (eax >= 1) { 923 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 924 c->x86_capability[CPUID_7_1_EAX] = eax; 925 } 926 } 927 928 /* Extended state features: level 0x0000000d */ 929 if (c->cpuid_level >= 0x0000000d) { 930 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 931 932 c->x86_capability[CPUID_D_1_EAX] = eax; 933 } 934 935 /* AMD-defined flags: level 0x80000001 */ 936 eax = cpuid_eax(0x80000000); 937 c->extended_cpuid_level = eax; 938 939 if ((eax & 0xffff0000) == 0x80000000) { 940 if (eax >= 0x80000001) { 941 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 942 943 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 944 c->x86_capability[CPUID_8000_0001_EDX] = edx; 945 } 946 } 947 948 if (c->extended_cpuid_level >= 0x80000007) { 949 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 950 951 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 952 c->x86_power = edx; 953 } 954 955 if (c->extended_cpuid_level >= 0x80000008) { 956 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 957 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 958 } 959 960 if (c->extended_cpuid_level >= 0x8000000a) 961 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 962 963 init_scattered_cpuid_features(c); 964 init_speculation_control(c); 965 init_cqm(c); 966 967 /* 968 * Clear/Set all flags overridden by options, after probe. 969 * This needs to happen each time we re-probe, which may happen 970 * several times during CPU initialization. 971 */ 972 apply_forced_caps(c); 973 } 974 975 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 976 { 977 u32 eax, ebx, ecx, edx; 978 979 if (c->extended_cpuid_level >= 0x80000008) { 980 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 981 982 c->x86_virt_bits = (eax >> 8) & 0xff; 983 c->x86_phys_bits = eax & 0xff; 984 } 985 #ifdef CONFIG_X86_32 986 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 987 c->x86_phys_bits = 36; 988 #endif 989 c->x86_cache_bits = c->x86_phys_bits; 990 } 991 992 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 993 { 994 #ifdef CONFIG_X86_32 995 int i; 996 997 /* 998 * First of all, decide if this is a 486 or higher 999 * It's a 486 if we can modify the AC flag 1000 */ 1001 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1002 c->x86 = 4; 1003 else 1004 c->x86 = 3; 1005 1006 for (i = 0; i < X86_VENDOR_NUM; i++) 1007 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1008 c->x86_vendor_id[0] = 0; 1009 cpu_devs[i]->c_identify(c); 1010 if (c->x86_vendor_id[0]) { 1011 get_cpu_vendor(c); 1012 break; 1013 } 1014 } 1015 #endif 1016 } 1017 1018 #define NO_SPECULATION BIT(0) 1019 #define NO_MELTDOWN BIT(1) 1020 #define NO_SSB BIT(2) 1021 #define NO_L1TF BIT(3) 1022 #define NO_MDS BIT(4) 1023 #define MSBDS_ONLY BIT(5) 1024 #define NO_SWAPGS BIT(6) 1025 #define NO_ITLB_MULTIHIT BIT(7) 1026 1027 #define VULNWL(_vendor, _family, _model, _whitelist) \ 1028 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } 1029 1030 #define VULNWL_INTEL(model, whitelist) \ 1031 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1032 1033 #define VULNWL_AMD(family, whitelist) \ 1034 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1035 1036 #define VULNWL_HYGON(family, whitelist) \ 1037 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1038 1039 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1040 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1041 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1042 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1043 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1044 1045 /* Intel Family 6 */ 1046 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1047 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1048 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1049 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1050 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1051 1052 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1053 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1054 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1055 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1056 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1057 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1058 1059 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1060 1061 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1062 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1063 1064 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1065 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1066 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1067 1068 /* 1069 * Technically, swapgs isn't serializing on AMD (despite it previously 1070 * being documented as such in the APM). But according to AMD, %gs is 1071 * updated non-speculatively, and the issuing of %gs-relative memory 1072 * operands will be blocked until the %gs update completes, which is 1073 * good enough for our purposes. 1074 */ 1075 1076 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1077 1078 /* AMD Family 0xf - 0x12 */ 1079 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1080 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1081 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1082 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1083 1084 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1085 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1086 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1087 {} 1088 }; 1089 1090 static bool __init cpu_matches(unsigned long which) 1091 { 1092 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 1093 1094 return m && !!(m->driver_data & which); 1095 } 1096 1097 u64 x86_read_arch_cap_msr(void) 1098 { 1099 u64 ia32_cap = 0; 1100 1101 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1102 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1103 1104 return ia32_cap; 1105 } 1106 1107 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1108 { 1109 u64 ia32_cap = x86_read_arch_cap_msr(); 1110 1111 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1112 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1113 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1114 1115 if (cpu_matches(NO_SPECULATION)) 1116 return; 1117 1118 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1119 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1120 1121 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 1122 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1123 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1124 1125 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1126 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1127 1128 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1129 setup_force_cpu_bug(X86_BUG_MDS); 1130 if (cpu_matches(MSBDS_ONLY)) 1131 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1132 } 1133 1134 if (!cpu_matches(NO_SWAPGS)) 1135 setup_force_cpu_bug(X86_BUG_SWAPGS); 1136 1137 /* 1138 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1139 * - TSX is supported or 1140 * - TSX_CTRL is present 1141 * 1142 * TSX_CTRL check is needed for cases when TSX could be disabled before 1143 * the kernel boot e.g. kexec. 1144 * TSX_CTRL check alone is not sufficient for cases when the microcode 1145 * update is not present or running as guest that don't get TSX_CTRL. 1146 */ 1147 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1148 (cpu_has(c, X86_FEATURE_RTM) || 1149 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1150 setup_force_cpu_bug(X86_BUG_TAA); 1151 1152 if (cpu_matches(NO_MELTDOWN)) 1153 return; 1154 1155 /* Rogue Data Cache Load? No! */ 1156 if (ia32_cap & ARCH_CAP_RDCL_NO) 1157 return; 1158 1159 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1160 1161 if (cpu_matches(NO_L1TF)) 1162 return; 1163 1164 setup_force_cpu_bug(X86_BUG_L1TF); 1165 } 1166 1167 /* 1168 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1169 * unfortunately, that's not true in practice because of early VIA 1170 * chips and (more importantly) broken virtualizers that are not easy 1171 * to detect. In the latter case it doesn't even *fail* reliably, so 1172 * probing for it doesn't even work. Disable it completely on 32-bit 1173 * unless we can find a reliable way to detect all the broken cases. 1174 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1175 */ 1176 static void detect_nopl(void) 1177 { 1178 #ifdef CONFIG_X86_32 1179 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1180 #else 1181 setup_force_cpu_cap(X86_FEATURE_NOPL); 1182 #endif 1183 } 1184 1185 /* 1186 * Do minimum CPU detection early. 1187 * Fields really needed: vendor, cpuid_level, family, model, mask, 1188 * cache alignment. 1189 * The others are not touched to avoid unwanted side effects. 1190 * 1191 * WARNING: this function is only called on the boot CPU. Don't add code 1192 * here that is supposed to run on all CPUs. 1193 */ 1194 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1195 { 1196 #ifdef CONFIG_X86_64 1197 c->x86_clflush_size = 64; 1198 c->x86_phys_bits = 36; 1199 c->x86_virt_bits = 48; 1200 #else 1201 c->x86_clflush_size = 32; 1202 c->x86_phys_bits = 32; 1203 c->x86_virt_bits = 32; 1204 #endif 1205 c->x86_cache_alignment = c->x86_clflush_size; 1206 1207 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1208 c->extended_cpuid_level = 0; 1209 1210 if (!have_cpuid_p()) 1211 identify_cpu_without_cpuid(c); 1212 1213 /* cyrix could have cpuid enabled via c_identify()*/ 1214 if (have_cpuid_p()) { 1215 cpu_detect(c); 1216 get_cpu_vendor(c); 1217 get_cpu_cap(c); 1218 get_cpu_address_sizes(c); 1219 setup_force_cpu_cap(X86_FEATURE_CPUID); 1220 1221 if (this_cpu->c_early_init) 1222 this_cpu->c_early_init(c); 1223 1224 c->cpu_index = 0; 1225 filter_cpuid_features(c, false); 1226 1227 if (this_cpu->c_bsp_init) 1228 this_cpu->c_bsp_init(c); 1229 } else { 1230 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1231 } 1232 1233 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1234 1235 cpu_set_bug_bits(c); 1236 1237 fpu__init_system(c); 1238 1239 #ifdef CONFIG_X86_32 1240 /* 1241 * Regardless of whether PCID is enumerated, the SDM says 1242 * that it can't be enabled in 32-bit mode. 1243 */ 1244 setup_clear_cpu_cap(X86_FEATURE_PCID); 1245 #endif 1246 1247 /* 1248 * Later in the boot process pgtable_l5_enabled() relies on 1249 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1250 * enabled by this point we need to clear the feature bit to avoid 1251 * false-positives at the later stage. 1252 * 1253 * pgtable_l5_enabled() can be false here for several reasons: 1254 * - 5-level paging is disabled compile-time; 1255 * - it's 32-bit kernel; 1256 * - machine doesn't support 5-level paging; 1257 * - user specified 'no5lvl' in kernel command line. 1258 */ 1259 if (!pgtable_l5_enabled()) 1260 setup_clear_cpu_cap(X86_FEATURE_LA57); 1261 1262 detect_nopl(); 1263 } 1264 1265 void __init early_cpu_init(void) 1266 { 1267 const struct cpu_dev *const *cdev; 1268 int count = 0; 1269 1270 #ifdef CONFIG_PROCESSOR_SELECT 1271 pr_info("KERNEL supported cpus:\n"); 1272 #endif 1273 1274 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1275 const struct cpu_dev *cpudev = *cdev; 1276 1277 if (count >= X86_VENDOR_NUM) 1278 break; 1279 cpu_devs[count] = cpudev; 1280 count++; 1281 1282 #ifdef CONFIG_PROCESSOR_SELECT 1283 { 1284 unsigned int j; 1285 1286 for (j = 0; j < 2; j++) { 1287 if (!cpudev->c_ident[j]) 1288 continue; 1289 pr_info(" %s %s\n", cpudev->c_vendor, 1290 cpudev->c_ident[j]); 1291 } 1292 } 1293 #endif 1294 } 1295 early_identify_cpu(&boot_cpu_data); 1296 } 1297 1298 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1299 { 1300 #ifdef CONFIG_X86_64 1301 /* 1302 * Empirically, writing zero to a segment selector on AMD does 1303 * not clear the base, whereas writing zero to a segment 1304 * selector on Intel does clear the base. Intel's behavior 1305 * allows slightly faster context switches in the common case 1306 * where GS is unused by the prev and next threads. 1307 * 1308 * Since neither vendor documents this anywhere that I can see, 1309 * detect it directly instead of hardcoding the choice by 1310 * vendor. 1311 * 1312 * I've designated AMD's behavior as the "bug" because it's 1313 * counterintuitive and less friendly. 1314 */ 1315 1316 unsigned long old_base, tmp; 1317 rdmsrl(MSR_FS_BASE, old_base); 1318 wrmsrl(MSR_FS_BASE, 1); 1319 loadsegment(fs, 0); 1320 rdmsrl(MSR_FS_BASE, tmp); 1321 if (tmp != 0) 1322 set_cpu_bug(c, X86_BUG_NULL_SEG); 1323 wrmsrl(MSR_FS_BASE, old_base); 1324 #endif 1325 } 1326 1327 static void generic_identify(struct cpuinfo_x86 *c) 1328 { 1329 c->extended_cpuid_level = 0; 1330 1331 if (!have_cpuid_p()) 1332 identify_cpu_without_cpuid(c); 1333 1334 /* cyrix could have cpuid enabled via c_identify()*/ 1335 if (!have_cpuid_p()) 1336 return; 1337 1338 cpu_detect(c); 1339 1340 get_cpu_vendor(c); 1341 1342 get_cpu_cap(c); 1343 1344 get_cpu_address_sizes(c); 1345 1346 if (c->cpuid_level >= 0x00000001) { 1347 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1348 #ifdef CONFIG_X86_32 1349 # ifdef CONFIG_SMP 1350 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1351 # else 1352 c->apicid = c->initial_apicid; 1353 # endif 1354 #endif 1355 c->phys_proc_id = c->initial_apicid; 1356 } 1357 1358 get_model_name(c); /* Default name */ 1359 1360 detect_null_seg_behavior(c); 1361 1362 /* 1363 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1364 * systems that run Linux at CPL > 0 may or may not have the 1365 * issue, but, even if they have the issue, there's absolutely 1366 * nothing we can do about it because we can't use the real IRET 1367 * instruction. 1368 * 1369 * NB: For the time being, only 32-bit kernels support 1370 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1371 * whether to apply espfix using paravirt hooks. If any 1372 * non-paravirt system ever shows up that does *not* have the 1373 * ESPFIX issue, we can change this. 1374 */ 1375 #ifdef CONFIG_X86_32 1376 # ifdef CONFIG_PARAVIRT_XXL 1377 do { 1378 extern void native_iret(void); 1379 if (pv_ops.cpu.iret == native_iret) 1380 set_cpu_bug(c, X86_BUG_ESPFIX); 1381 } while (0); 1382 # else 1383 set_cpu_bug(c, X86_BUG_ESPFIX); 1384 # endif 1385 #endif 1386 } 1387 1388 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1389 { 1390 /* 1391 * The heavy lifting of max_rmid and cache_occ_scale are handled 1392 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1393 * in case CQM bits really aren't there in this CPU. 1394 */ 1395 if (c != &boot_cpu_data) { 1396 boot_cpu_data.x86_cache_max_rmid = 1397 min(boot_cpu_data.x86_cache_max_rmid, 1398 c->x86_cache_max_rmid); 1399 } 1400 } 1401 1402 /* 1403 * Validate that ACPI/mptables have the same information about the 1404 * effective APIC id and update the package map. 1405 */ 1406 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1407 { 1408 #ifdef CONFIG_SMP 1409 unsigned int apicid, cpu = smp_processor_id(); 1410 1411 apicid = apic->cpu_present_to_apicid(cpu); 1412 1413 if (apicid != c->apicid) { 1414 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1415 cpu, apicid, c->initial_apicid); 1416 } 1417 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1418 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1419 #else 1420 c->logical_proc_id = 0; 1421 #endif 1422 } 1423 1424 /* 1425 * This does the hard work of actually picking apart the CPU stuff... 1426 */ 1427 static void identify_cpu(struct cpuinfo_x86 *c) 1428 { 1429 int i; 1430 1431 c->loops_per_jiffy = loops_per_jiffy; 1432 c->x86_cache_size = 0; 1433 c->x86_vendor = X86_VENDOR_UNKNOWN; 1434 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1435 c->x86_vendor_id[0] = '\0'; /* Unset */ 1436 c->x86_model_id[0] = '\0'; /* Unset */ 1437 c->x86_max_cores = 1; 1438 c->x86_coreid_bits = 0; 1439 c->cu_id = 0xff; 1440 #ifdef CONFIG_X86_64 1441 c->x86_clflush_size = 64; 1442 c->x86_phys_bits = 36; 1443 c->x86_virt_bits = 48; 1444 #else 1445 c->cpuid_level = -1; /* CPUID not detected */ 1446 c->x86_clflush_size = 32; 1447 c->x86_phys_bits = 32; 1448 c->x86_virt_bits = 32; 1449 #endif 1450 c->x86_cache_alignment = c->x86_clflush_size; 1451 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1452 1453 generic_identify(c); 1454 1455 if (this_cpu->c_identify) 1456 this_cpu->c_identify(c); 1457 1458 /* Clear/Set all flags overridden by options, after probe */ 1459 apply_forced_caps(c); 1460 1461 #ifdef CONFIG_X86_64 1462 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1463 #endif 1464 1465 /* 1466 * Vendor-specific initialization. In this section we 1467 * canonicalize the feature flags, meaning if there are 1468 * features a certain CPU supports which CPUID doesn't 1469 * tell us, CPUID claiming incorrect flags, or other bugs, 1470 * we handle them here. 1471 * 1472 * At the end of this section, c->x86_capability better 1473 * indicate the features this CPU genuinely supports! 1474 */ 1475 if (this_cpu->c_init) 1476 this_cpu->c_init(c); 1477 1478 /* Disable the PN if appropriate */ 1479 squash_the_stupid_serial_number(c); 1480 1481 /* Set up SMEP/SMAP/UMIP */ 1482 setup_smep(c); 1483 setup_smap(c); 1484 setup_umip(c); 1485 1486 /* 1487 * The vendor-specific functions might have changed features. 1488 * Now we do "generic changes." 1489 */ 1490 1491 /* Filter out anything that depends on CPUID levels we don't have */ 1492 filter_cpuid_features(c, true); 1493 1494 /* If the model name is still unset, do table lookup. */ 1495 if (!c->x86_model_id[0]) { 1496 const char *p; 1497 p = table_lookup_model(c); 1498 if (p) 1499 strcpy(c->x86_model_id, p); 1500 else 1501 /* Last resort... */ 1502 sprintf(c->x86_model_id, "%02x/%02x", 1503 c->x86, c->x86_model); 1504 } 1505 1506 #ifdef CONFIG_X86_64 1507 detect_ht(c); 1508 #endif 1509 1510 x86_init_rdrand(c); 1511 x86_init_cache_qos(c); 1512 setup_pku(c); 1513 1514 /* 1515 * Clear/Set all flags overridden by options, need do it 1516 * before following smp all cpus cap AND. 1517 */ 1518 apply_forced_caps(c); 1519 1520 /* 1521 * On SMP, boot_cpu_data holds the common feature set between 1522 * all CPUs; so make sure that we indicate which features are 1523 * common between the CPUs. The first time this routine gets 1524 * executed, c == &boot_cpu_data. 1525 */ 1526 if (c != &boot_cpu_data) { 1527 /* AND the already accumulated flags with these */ 1528 for (i = 0; i < NCAPINTS; i++) 1529 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1530 1531 /* OR, i.e. replicate the bug flags */ 1532 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1533 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1534 } 1535 1536 /* Init Machine Check Exception if available. */ 1537 mcheck_cpu_init(c); 1538 1539 select_idle_routine(c); 1540 1541 #ifdef CONFIG_NUMA 1542 numa_add_cpu(smp_processor_id()); 1543 #endif 1544 } 1545 1546 /* 1547 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1548 * on 32-bit kernels: 1549 */ 1550 #ifdef CONFIG_X86_32 1551 void enable_sep_cpu(void) 1552 { 1553 struct tss_struct *tss; 1554 int cpu; 1555 1556 if (!boot_cpu_has(X86_FEATURE_SEP)) 1557 return; 1558 1559 cpu = get_cpu(); 1560 tss = &per_cpu(cpu_tss_rw, cpu); 1561 1562 /* 1563 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1564 * see the big comment in struct x86_hw_tss's definition. 1565 */ 1566 1567 tss->x86_tss.ss1 = __KERNEL_CS; 1568 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1569 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1570 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1571 1572 put_cpu(); 1573 } 1574 #endif 1575 1576 void __init identify_boot_cpu(void) 1577 { 1578 identify_cpu(&boot_cpu_data); 1579 #ifdef CONFIG_X86_32 1580 sysenter_setup(); 1581 enable_sep_cpu(); 1582 #endif 1583 cpu_detect_tlb(&boot_cpu_data); 1584 setup_cr_pinning(); 1585 1586 tsx_init(); 1587 } 1588 1589 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1590 { 1591 BUG_ON(c == &boot_cpu_data); 1592 identify_cpu(c); 1593 #ifdef CONFIG_X86_32 1594 enable_sep_cpu(); 1595 #endif 1596 mtrr_ap_init(); 1597 validate_apic_and_package_id(c); 1598 x86_spec_ctrl_setup_ap(); 1599 } 1600 1601 static __init int setup_noclflush(char *arg) 1602 { 1603 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1604 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1605 return 1; 1606 } 1607 __setup("noclflush", setup_noclflush); 1608 1609 void print_cpu_info(struct cpuinfo_x86 *c) 1610 { 1611 const char *vendor = NULL; 1612 1613 if (c->x86_vendor < X86_VENDOR_NUM) { 1614 vendor = this_cpu->c_vendor; 1615 } else { 1616 if (c->cpuid_level >= 0) 1617 vendor = c->x86_vendor_id; 1618 } 1619 1620 if (vendor && !strstr(c->x86_model_id, vendor)) 1621 pr_cont("%s ", vendor); 1622 1623 if (c->x86_model_id[0]) 1624 pr_cont("%s", c->x86_model_id); 1625 else 1626 pr_cont("%d86", c->x86); 1627 1628 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1629 1630 if (c->x86_stepping || c->cpuid_level >= 0) 1631 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1632 else 1633 pr_cont(")\n"); 1634 } 1635 1636 /* 1637 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1638 * But we need to keep a dummy __setup around otherwise it would 1639 * show up as an environment variable for init. 1640 */ 1641 static __init int setup_clearcpuid(char *arg) 1642 { 1643 return 1; 1644 } 1645 __setup("clearcpuid=", setup_clearcpuid); 1646 1647 #ifdef CONFIG_X86_64 1648 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1649 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1650 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1651 1652 /* 1653 * The following percpu variables are hot. Align current_task to 1654 * cacheline size such that they fall in the same cacheline. 1655 */ 1656 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1657 &init_task; 1658 EXPORT_PER_CPU_SYMBOL(current_task); 1659 1660 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1661 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1662 1663 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1664 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1665 1666 /* May not be marked __init: used by software suspend */ 1667 void syscall_init(void) 1668 { 1669 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1670 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1671 1672 #ifdef CONFIG_IA32_EMULATION 1673 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1674 /* 1675 * This only works on Intel CPUs. 1676 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1677 * This does not cause SYSENTER to jump to the wrong location, because 1678 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1679 */ 1680 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1681 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1682 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1683 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1684 #else 1685 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1686 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1687 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1688 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1689 #endif 1690 1691 /* Flags to clear on syscall */ 1692 wrmsrl(MSR_SYSCALL_MASK, 1693 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1694 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1695 } 1696 1697 DEFINE_PER_CPU(int, debug_stack_usage); 1698 DEFINE_PER_CPU(u32, debug_idt_ctr); 1699 1700 void debug_stack_set_zero(void) 1701 { 1702 this_cpu_inc(debug_idt_ctr); 1703 load_current_idt(); 1704 } 1705 NOKPROBE_SYMBOL(debug_stack_set_zero); 1706 1707 void debug_stack_reset(void) 1708 { 1709 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1710 return; 1711 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1712 load_current_idt(); 1713 } 1714 NOKPROBE_SYMBOL(debug_stack_reset); 1715 1716 #else /* CONFIG_X86_64 */ 1717 1718 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1719 EXPORT_PER_CPU_SYMBOL(current_task); 1720 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1721 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1722 1723 /* 1724 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1725 * the top of the kernel stack. Use an extra percpu variable to track the 1726 * top of the kernel stack directly. 1727 */ 1728 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1729 (unsigned long)&init_thread_union + THREAD_SIZE; 1730 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1731 1732 #ifdef CONFIG_STACKPROTECTOR 1733 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1734 #endif 1735 1736 #endif /* CONFIG_X86_64 */ 1737 1738 /* 1739 * Clear all 6 debug registers: 1740 */ 1741 static void clear_all_debug_regs(void) 1742 { 1743 int i; 1744 1745 for (i = 0; i < 8; i++) { 1746 /* Ignore db4, db5 */ 1747 if ((i == 4) || (i == 5)) 1748 continue; 1749 1750 set_debugreg(0, i); 1751 } 1752 } 1753 1754 #ifdef CONFIG_KGDB 1755 /* 1756 * Restore debug regs if using kgdbwait and you have a kernel debugger 1757 * connection established. 1758 */ 1759 static void dbg_restore_debug_regs(void) 1760 { 1761 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1762 arch_kgdb_ops.correct_hw_break(); 1763 } 1764 #else /* ! CONFIG_KGDB */ 1765 #define dbg_restore_debug_regs() 1766 #endif /* ! CONFIG_KGDB */ 1767 1768 static void wait_for_master_cpu(int cpu) 1769 { 1770 #ifdef CONFIG_SMP 1771 /* 1772 * wait for ACK from master CPU before continuing 1773 * with AP initialization 1774 */ 1775 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1776 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1777 cpu_relax(); 1778 #endif 1779 } 1780 1781 #ifdef CONFIG_X86_64 1782 static inline void setup_getcpu(int cpu) 1783 { 1784 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1785 struct desc_struct d = { }; 1786 1787 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1788 write_rdtscp_aux(cpudata); 1789 1790 /* Store CPU and node number in limit. */ 1791 d.limit0 = cpudata; 1792 d.limit1 = cpudata >> 16; 1793 1794 d.type = 5; /* RO data, expand down, accessed */ 1795 d.dpl = 3; /* Visible to user code */ 1796 d.s = 1; /* Not a system segment */ 1797 d.p = 1; /* Present */ 1798 d.d = 1; /* 32-bit */ 1799 1800 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1801 } 1802 1803 static inline void ucode_cpu_init(int cpu) 1804 { 1805 if (cpu) 1806 load_ucode_ap(); 1807 } 1808 1809 static inline void tss_setup_ist(struct tss_struct *tss) 1810 { 1811 /* Set up the per-CPU TSS IST stacks */ 1812 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1813 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1814 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1815 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1816 } 1817 1818 #else /* CONFIG_X86_64 */ 1819 1820 static inline void setup_getcpu(int cpu) { } 1821 1822 static inline void ucode_cpu_init(int cpu) 1823 { 1824 show_ucode_info_early(); 1825 } 1826 1827 static inline void tss_setup_ist(struct tss_struct *tss) { } 1828 1829 #endif /* !CONFIG_X86_64 */ 1830 1831 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 1832 { 1833 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 1834 1835 #ifdef CONFIG_X86_IOPL_IOPERM 1836 tss->io_bitmap.prev_max = 0; 1837 tss->io_bitmap.prev_sequence = 0; 1838 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 1839 /* 1840 * Invalidate the extra array entry past the end of the all 1841 * permission bitmap as required by the hardware. 1842 */ 1843 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 1844 #endif 1845 } 1846 1847 /* 1848 * cpu_init() initializes state that is per-CPU. Some data is already 1849 * initialized (naturally) in the bootstrap process, such as the GDT 1850 * and IDT. We reload them nevertheless, this function acts as a 1851 * 'CPU state barrier', nothing should get across. 1852 */ 1853 void cpu_init(void) 1854 { 1855 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1856 struct task_struct *cur = current; 1857 int cpu = raw_smp_processor_id(); 1858 1859 wait_for_master_cpu(cpu); 1860 1861 ucode_cpu_init(cpu); 1862 1863 #ifdef CONFIG_NUMA 1864 if (this_cpu_read(numa_node) == 0 && 1865 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1866 set_numa_node(early_cpu_to_node(cpu)); 1867 #endif 1868 setup_getcpu(cpu); 1869 1870 pr_debug("Initializing CPU#%d\n", cpu); 1871 1872 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 1873 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 1874 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1875 1876 /* 1877 * Initialize the per-CPU GDT with the boot GDT, 1878 * and set up the GDT descriptor: 1879 */ 1880 switch_to_new_gdt(cpu); 1881 load_current_idt(); 1882 1883 if (IS_ENABLED(CONFIG_X86_64)) { 1884 loadsegment(fs, 0); 1885 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1886 syscall_init(); 1887 1888 wrmsrl(MSR_FS_BASE, 0); 1889 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1890 barrier(); 1891 1892 x2apic_setup(); 1893 } 1894 1895 mmgrab(&init_mm); 1896 cur->active_mm = &init_mm; 1897 BUG_ON(cur->mm); 1898 initialize_tlbstate_and_flush(); 1899 enter_lazy_tlb(&init_mm, cur); 1900 1901 /* Initialize the TSS. */ 1902 tss_setup_ist(tss); 1903 tss_setup_io_bitmap(tss); 1904 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1905 1906 load_TR_desc(); 1907 /* 1908 * sp0 points to the entry trampoline stack regardless of what task 1909 * is running. 1910 */ 1911 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1912 1913 load_mm_ldt(&init_mm); 1914 1915 clear_all_debug_regs(); 1916 dbg_restore_debug_regs(); 1917 1918 doublefault_init_cpu_tss(); 1919 1920 fpu__init_cpu(); 1921 1922 if (is_uv_system()) 1923 uv_cpu_init(); 1924 1925 load_fixmap_gdt(cpu); 1926 } 1927 1928 /* 1929 * The microcode loader calls this upon late microcode load to recheck features, 1930 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1931 * hotplug lock. 1932 */ 1933 void microcode_check(void) 1934 { 1935 struct cpuinfo_x86 info; 1936 1937 perf_check_microcode(); 1938 1939 /* Reload CPUID max function as it might've changed. */ 1940 info.cpuid_level = cpuid_eax(0); 1941 1942 /* 1943 * Copy all capability leafs to pick up the synthetic ones so that 1944 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1945 * get overwritten in get_cpu_cap(). 1946 */ 1947 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1948 1949 get_cpu_cap(&info); 1950 1951 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1952 return; 1953 1954 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1955 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1956 } 1957 1958 /* 1959 * Invoked from core CPU hotplug code after hotplug operations 1960 */ 1961 void arch_smt_update(void) 1962 { 1963 /* Handle the speculative execution misfeatures */ 1964 cpu_bugs_smt_update(); 1965 /* Check whether IPI broadcasting can be enabled */ 1966 apic_smt_update(); 1967 } 1968