1 #include <linux/init.h> 2 #include <linux/string.h> 3 #include <linux/delay.h> 4 #include <linux/smp.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/bootmem.h> 8 #include <asm/semaphore.h> 9 #include <asm/processor.h> 10 #include <asm/i387.h> 11 #include <asm/msr.h> 12 #include <asm/io.h> 13 #include <asm/mmu_context.h> 14 #include <asm/mtrr.h> 15 #include <asm/mce.h> 16 #ifdef CONFIG_X86_LOCAL_APIC 17 #include <asm/mpspec.h> 18 #include <asm/apic.h> 19 #include <mach_apic.h> 20 #endif 21 22 #include "cpu.h" 23 24 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { 25 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 26 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 27 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 28 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 29 /* 30 * Segments used for calling PnP BIOS have byte granularity. 31 * They code segments and data segments have fixed 64k limits, 32 * the transfer segment sizes are set at run time. 33 */ 34 /* 32-bit code */ 35 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 36 /* 16-bit code */ 37 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 38 /* 16-bit data */ 39 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 40 /* 16-bit data */ 41 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 42 /* 16-bit data */ 43 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 44 /* 45 * The APM segments have byte granularity and their bases 46 * are set at run time. All have 64k limits. 47 */ 48 /* 32-bit code */ 49 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 50 /* 16-bit code */ 51 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 52 /* data */ 53 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 54 55 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, 56 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, 57 } }; 58 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 59 60 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; 61 62 static int cachesize_override __cpuinitdata = -1; 63 static int disable_x86_serial_nr __cpuinitdata = 1; 64 65 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; 66 67 static void __cpuinit default_init(struct cpuinfo_x86 * c) 68 { 69 /* Not much we can do here... */ 70 /* Check if at least it has cpuid */ 71 if (c->cpuid_level == -1) { 72 /* No cpuid. It must be an ancient CPU */ 73 if (c->x86 == 4) 74 strcpy(c->x86_model_id, "486"); 75 else if (c->x86 == 3) 76 strcpy(c->x86_model_id, "386"); 77 } 78 } 79 80 static struct cpu_dev __cpuinitdata default_cpu = { 81 .c_init = default_init, 82 .c_vendor = "Unknown", 83 }; 84 static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu; 85 86 static int __init cachesize_setup(char *str) 87 { 88 get_option (&str, &cachesize_override); 89 return 1; 90 } 91 __setup("cachesize=", cachesize_setup); 92 93 int __cpuinit get_model_name(struct cpuinfo_x86 *c) 94 { 95 unsigned int *v; 96 char *p, *q; 97 98 if (cpuid_eax(0x80000000) < 0x80000004) 99 return 0; 100 101 v = (unsigned int *) c->x86_model_id; 102 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 103 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 104 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 105 c->x86_model_id[48] = 0; 106 107 /* Intel chips right-justify this string for some dumb reason; 108 undo that brain damage */ 109 p = q = &c->x86_model_id[0]; 110 while ( *p == ' ' ) 111 p++; 112 if ( p != q ) { 113 while ( *p ) 114 *q++ = *p++; 115 while ( q <= &c->x86_model_id[48] ) 116 *q++ = '\0'; /* Zero-pad the rest */ 117 } 118 119 return 1; 120 } 121 122 123 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 124 { 125 unsigned int n, dummy, ecx, edx, l2size; 126 127 n = cpuid_eax(0x80000000); 128 129 if (n >= 0x80000005) { 130 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); 131 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 132 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 133 c->x86_cache_size=(ecx>>24)+(edx>>24); 134 } 135 136 if (n < 0x80000006) /* Some chips just has a large L1. */ 137 return; 138 139 ecx = cpuid_ecx(0x80000006); 140 l2size = ecx >> 16; 141 142 /* do processor-specific cache resizing */ 143 if (this_cpu->c_size_cache) 144 l2size = this_cpu->c_size_cache(c,l2size); 145 146 /* Allow user to override all this if necessary. */ 147 if (cachesize_override != -1) 148 l2size = cachesize_override; 149 150 if ( l2size == 0 ) 151 return; /* Again, no L2 cache is possible */ 152 153 c->x86_cache_size = l2size; 154 155 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 156 l2size, ecx & 0xFF); 157 } 158 159 /* Naming convention should be: <Name> [(<Codename>)] */ 160 /* This table only is used unless init_<vendor>() below doesn't set it; */ 161 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */ 162 163 /* Look up CPU names by table lookup. */ 164 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) 165 { 166 struct cpu_model_info *info; 167 168 if ( c->x86_model >= 16 ) 169 return NULL; /* Range check */ 170 171 if (!this_cpu) 172 return NULL; 173 174 info = this_cpu->c_models; 175 176 while (info && info->family) { 177 if (info->family == c->x86) 178 return info->model_names[c->x86_model]; 179 info++; 180 } 181 return NULL; /* Not found */ 182 } 183 184 185 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) 186 { 187 char *v = c->x86_vendor_id; 188 int i; 189 static int printed; 190 191 for (i = 0; i < X86_VENDOR_NUM; i++) { 192 if (cpu_devs[i]) { 193 if (!strcmp(v,cpu_devs[i]->c_ident[0]) || 194 (cpu_devs[i]->c_ident[1] && 195 !strcmp(v,cpu_devs[i]->c_ident[1]))) { 196 c->x86_vendor = i; 197 if (!early) 198 this_cpu = cpu_devs[i]; 199 return; 200 } 201 } 202 } 203 if (!printed) { 204 printed++; 205 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); 206 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 207 } 208 c->x86_vendor = X86_VENDOR_UNKNOWN; 209 this_cpu = &default_cpu; 210 } 211 212 213 static int __init x86_fxsr_setup(char * s) 214 { 215 setup_clear_cpu_cap(X86_FEATURE_FXSR); 216 setup_clear_cpu_cap(X86_FEATURE_XMM); 217 return 1; 218 } 219 __setup("nofxsr", x86_fxsr_setup); 220 221 222 static int __init x86_sep_setup(char * s) 223 { 224 setup_clear_cpu_cap(X86_FEATURE_SEP); 225 return 1; 226 } 227 __setup("nosep", x86_sep_setup); 228 229 230 /* Standard macro to see if a specific flag is changeable */ 231 static inline int flag_is_changeable_p(u32 flag) 232 { 233 u32 f1, f2; 234 235 asm("pushfl\n\t" 236 "pushfl\n\t" 237 "popl %0\n\t" 238 "movl %0,%1\n\t" 239 "xorl %2,%0\n\t" 240 "pushl %0\n\t" 241 "popfl\n\t" 242 "pushfl\n\t" 243 "popl %0\n\t" 244 "popfl\n\t" 245 : "=&r" (f1), "=&r" (f2) 246 : "ir" (flag)); 247 248 return ((f1^f2) & flag) != 0; 249 } 250 251 252 /* Probe for the CPUID instruction */ 253 static int __cpuinit have_cpuid_p(void) 254 { 255 return flag_is_changeable_p(X86_EFLAGS_ID); 256 } 257 258 void __init cpu_detect(struct cpuinfo_x86 *c) 259 { 260 /* Get vendor name */ 261 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 262 (unsigned int *)&c->x86_vendor_id[0], 263 (unsigned int *)&c->x86_vendor_id[8], 264 (unsigned int *)&c->x86_vendor_id[4]); 265 266 c->x86 = 4; 267 if (c->cpuid_level >= 0x00000001) { 268 u32 junk, tfms, cap0, misc; 269 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 270 c->x86 = (tfms >> 8) & 15; 271 c->x86_model = (tfms >> 4) & 15; 272 if (c->x86 == 0xf) 273 c->x86 += (tfms >> 20) & 0xff; 274 if (c->x86 >= 0x6) 275 c->x86_model += ((tfms >> 16) & 0xF) << 4; 276 c->x86_mask = tfms & 15; 277 if (cap0 & (1<<19)) { 278 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; 279 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 280 } 281 } 282 } 283 static void __cpuinit early_get_cap(struct cpuinfo_x86 *c) 284 { 285 u32 tfms, xlvl; 286 unsigned int ebx; 287 288 memset(&c->x86_capability, 0, sizeof c->x86_capability); 289 if (have_cpuid_p()) { 290 /* Intel-defined flags: level 0x00000001 */ 291 if (c->cpuid_level >= 0x00000001) { 292 u32 capability, excap; 293 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 294 c->x86_capability[0] = capability; 295 c->x86_capability[4] = excap; 296 } 297 298 /* AMD-defined flags: level 0x80000001 */ 299 xlvl = cpuid_eax(0x80000000); 300 if ((xlvl & 0xffff0000) == 0x80000000) { 301 if (xlvl >= 0x80000001) { 302 c->x86_capability[1] = cpuid_edx(0x80000001); 303 c->x86_capability[6] = cpuid_ecx(0x80000001); 304 } 305 } 306 307 } 308 309 } 310 311 /* Do minimum CPU detection early. 312 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. 313 The others are not touched to avoid unwanted side effects. 314 315 WARNING: this function is only called on the BP. Don't add code here 316 that is supposed to run on all CPUs. */ 317 static void __init early_cpu_detect(void) 318 { 319 struct cpuinfo_x86 *c = &boot_cpu_data; 320 321 c->x86_cache_alignment = 32; 322 c->x86_clflush_size = 32; 323 324 if (!have_cpuid_p()) 325 return; 326 327 cpu_detect(c); 328 329 get_cpu_vendor(c, 1); 330 331 switch (c->x86_vendor) { 332 case X86_VENDOR_AMD: 333 early_init_amd(c); 334 break; 335 case X86_VENDOR_INTEL: 336 early_init_intel(c); 337 break; 338 } 339 340 early_get_cap(c); 341 } 342 343 static void __cpuinit generic_identify(struct cpuinfo_x86 * c) 344 { 345 u32 tfms, xlvl; 346 unsigned int ebx; 347 348 if (have_cpuid_p()) { 349 /* Get vendor name */ 350 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 351 (unsigned int *)&c->x86_vendor_id[0], 352 (unsigned int *)&c->x86_vendor_id[8], 353 (unsigned int *)&c->x86_vendor_id[4]); 354 355 get_cpu_vendor(c, 0); 356 /* Initialize the standard set of capabilities */ 357 /* Note that the vendor-specific code below might override */ 358 359 /* Intel-defined flags: level 0x00000001 */ 360 if ( c->cpuid_level >= 0x00000001 ) { 361 u32 capability, excap; 362 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 363 c->x86_capability[0] = capability; 364 c->x86_capability[4] = excap; 365 c->x86 = (tfms >> 8) & 15; 366 c->x86_model = (tfms >> 4) & 15; 367 if (c->x86 == 0xf) 368 c->x86 += (tfms >> 20) & 0xff; 369 if (c->x86 >= 0x6) 370 c->x86_model += ((tfms >> 16) & 0xF) << 4; 371 c->x86_mask = tfms & 15; 372 #ifdef CONFIG_X86_HT 373 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); 374 #else 375 c->apicid = (ebx >> 24) & 0xFF; 376 #endif 377 if (c->x86_capability[0] & (1<<19)) 378 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; 379 } else { 380 /* Have CPUID level 0 only - unheard of */ 381 c->x86 = 4; 382 } 383 384 /* AMD-defined flags: level 0x80000001 */ 385 xlvl = cpuid_eax(0x80000000); 386 if ( (xlvl & 0xffff0000) == 0x80000000 ) { 387 if ( xlvl >= 0x80000001 ) { 388 c->x86_capability[1] = cpuid_edx(0x80000001); 389 c->x86_capability[6] = cpuid_ecx(0x80000001); 390 } 391 if ( xlvl >= 0x80000004 ) 392 get_model_name(c); /* Default name */ 393 } 394 395 init_scattered_cpuid_features(c); 396 } 397 398 #ifdef CONFIG_X86_HT 399 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; 400 #endif 401 } 402 403 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 404 { 405 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) { 406 /* Disable processor serial number */ 407 unsigned long lo,hi; 408 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi); 409 lo |= 0x200000; 410 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi); 411 printk(KERN_NOTICE "CPU serial number disabled.\n"); 412 clear_bit(X86_FEATURE_PN, c->x86_capability); 413 414 /* Disabling the serial number may affect the cpuid level */ 415 c->cpuid_level = cpuid_eax(0); 416 } 417 } 418 419 static int __init x86_serial_nr_setup(char *s) 420 { 421 disable_x86_serial_nr = 0; 422 return 1; 423 } 424 __setup("serialnumber", x86_serial_nr_setup); 425 426 427 428 /* 429 * This does the hard work of actually picking apart the CPU stuff... 430 */ 431 void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 432 { 433 int i; 434 435 c->loops_per_jiffy = loops_per_jiffy; 436 c->x86_cache_size = -1; 437 c->x86_vendor = X86_VENDOR_UNKNOWN; 438 c->cpuid_level = -1; /* CPUID not detected */ 439 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 440 c->x86_vendor_id[0] = '\0'; /* Unset */ 441 c->x86_model_id[0] = '\0'; /* Unset */ 442 c->x86_max_cores = 1; 443 c->x86_clflush_size = 32; 444 memset(&c->x86_capability, 0, sizeof c->x86_capability); 445 446 if (!have_cpuid_p()) { 447 /* First of all, decide if this is a 486 or higher */ 448 /* It's a 486 if we can modify the AC flag */ 449 if ( flag_is_changeable_p(X86_EFLAGS_AC) ) 450 c->x86 = 4; 451 else 452 c->x86 = 3; 453 } 454 455 generic_identify(c); 456 457 if (this_cpu->c_identify) 458 this_cpu->c_identify(c); 459 460 /* 461 * Vendor-specific initialization. In this section we 462 * canonicalize the feature flags, meaning if there are 463 * features a certain CPU supports which CPUID doesn't 464 * tell us, CPUID claiming incorrect flags, or other bugs, 465 * we handle them here. 466 * 467 * At the end of this section, c->x86_capability better 468 * indicate the features this CPU genuinely supports! 469 */ 470 if (this_cpu->c_init) 471 this_cpu->c_init(c); 472 473 /* Disable the PN if appropriate */ 474 squash_the_stupid_serial_number(c); 475 476 /* 477 * The vendor-specific functions might have changed features. Now 478 * we do "generic changes." 479 */ 480 481 /* If the model name is still unset, do table lookup. */ 482 if ( !c->x86_model_id[0] ) { 483 char *p; 484 p = table_lookup_model(c); 485 if ( p ) 486 strcpy(c->x86_model_id, p); 487 else 488 /* Last resort... */ 489 sprintf(c->x86_model_id, "%02x/%02x", 490 c->x86, c->x86_model); 491 } 492 493 /* 494 * On SMP, boot_cpu_data holds the common feature set between 495 * all CPUs; so make sure that we indicate which features are 496 * common between the CPUs. The first time this routine gets 497 * executed, c == &boot_cpu_data. 498 */ 499 if ( c != &boot_cpu_data ) { 500 /* AND the already accumulated flags with these */ 501 for ( i = 0 ; i < NCAPINTS ; i++ ) 502 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 503 } 504 505 /* Clear all flags overriden by options */ 506 for (i = 0; i < NCAPINTS; i++) 507 c->x86_capability[i] ^= cleared_cpu_caps[i]; 508 509 /* Init Machine Check Exception if available. */ 510 mcheck_init(c); 511 512 select_idle_routine(c); 513 } 514 515 void __init identify_boot_cpu(void) 516 { 517 identify_cpu(&boot_cpu_data); 518 sysenter_setup(); 519 enable_sep_cpu(); 520 } 521 522 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 523 { 524 BUG_ON(c == &boot_cpu_data); 525 identify_cpu(c); 526 enable_sep_cpu(); 527 mtrr_ap_init(); 528 } 529 530 #ifdef CONFIG_X86_HT 531 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 532 { 533 u32 eax, ebx, ecx, edx; 534 int index_msb, core_bits; 535 536 cpuid(1, &eax, &ebx, &ecx, &edx); 537 538 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) 539 return; 540 541 smp_num_siblings = (ebx & 0xff0000) >> 16; 542 543 if (smp_num_siblings == 1) { 544 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 545 } else if (smp_num_siblings > 1 ) { 546 547 if (smp_num_siblings > NR_CPUS) { 548 printk(KERN_WARNING "CPU: Unsupported number of the " 549 "siblings %d", smp_num_siblings); 550 smp_num_siblings = 1; 551 return; 552 } 553 554 index_msb = get_count_order(smp_num_siblings); 555 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); 556 557 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 558 c->phys_proc_id); 559 560 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 561 562 index_msb = get_count_order(smp_num_siblings) ; 563 564 core_bits = get_count_order(c->x86_max_cores); 565 566 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) & 567 ((1 << core_bits) - 1); 568 569 if (c->x86_max_cores > 1) 570 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 571 c->cpu_core_id); 572 } 573 } 574 #endif 575 576 static __init int setup_noclflush(char *arg) 577 { 578 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 579 return 1; 580 } 581 __setup("noclflush", setup_noclflush); 582 583 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 584 { 585 char *vendor = NULL; 586 587 if (c->x86_vendor < X86_VENDOR_NUM) 588 vendor = this_cpu->c_vendor; 589 else if (c->cpuid_level >= 0) 590 vendor = c->x86_vendor_id; 591 592 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) 593 printk("%s ", vendor); 594 595 if (!c->x86_model_id[0]) 596 printk("%d86", c->x86); 597 else 598 printk("%s", c->x86_model_id); 599 600 if (c->x86_mask || c->cpuid_level >= 0) 601 printk(" stepping %02x\n", c->x86_mask); 602 else 603 printk("\n"); 604 } 605 606 static __init int setup_disablecpuid(char *arg) 607 { 608 int bit; 609 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 610 setup_clear_cpu_cap(bit); 611 else 612 return 0; 613 return 1; 614 } 615 __setup("clearcpuid=", setup_disablecpuid); 616 617 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; 618 619 /* This is hacky. :) 620 * We're emulating future behavior. 621 * In the future, the cpu-specific init functions will be called implicitly 622 * via the magic of initcalls. 623 * They will insert themselves into the cpu_devs structure. 624 * Then, when cpu_init() is called, we can just iterate over that array. 625 */ 626 627 extern int intel_cpu_init(void); 628 extern int cyrix_init_cpu(void); 629 extern int nsc_init_cpu(void); 630 extern int amd_init_cpu(void); 631 extern int centaur_init_cpu(void); 632 extern int transmeta_init_cpu(void); 633 extern int nexgen_init_cpu(void); 634 extern int umc_init_cpu(void); 635 636 void __init early_cpu_init(void) 637 { 638 intel_cpu_init(); 639 cyrix_init_cpu(); 640 nsc_init_cpu(); 641 amd_init_cpu(); 642 centaur_init_cpu(); 643 transmeta_init_cpu(); 644 nexgen_init_cpu(); 645 umc_init_cpu(); 646 early_cpu_detect(); 647 } 648 649 /* Make sure %fs is initialized properly in idle threads */ 650 struct pt_regs * __devinit idle_regs(struct pt_regs *regs) 651 { 652 memset(regs, 0, sizeof(struct pt_regs)); 653 regs->fs = __KERNEL_PERCPU; 654 return regs; 655 } 656 657 /* Current gdt points %fs at the "master" per-cpu area: after this, 658 * it's on the real one. */ 659 void switch_to_new_gdt(void) 660 { 661 struct desc_ptr gdt_descr; 662 663 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); 664 gdt_descr.size = GDT_SIZE - 1; 665 load_gdt(&gdt_descr); 666 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); 667 } 668 669 /* 670 * cpu_init() initializes state that is per-CPU. Some data is already 671 * initialized (naturally) in the bootstrap process, such as the GDT 672 * and IDT. We reload them nevertheless, this function acts as a 673 * 'CPU state barrier', nothing should get across. 674 */ 675 void __cpuinit cpu_init(void) 676 { 677 int cpu = smp_processor_id(); 678 struct task_struct *curr = current; 679 struct tss_struct * t = &per_cpu(init_tss, cpu); 680 struct thread_struct *thread = &curr->thread; 681 682 if (cpu_test_and_set(cpu, cpu_initialized)) { 683 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 684 for (;;) local_irq_enable(); 685 } 686 687 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 688 689 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 690 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 691 692 load_idt(&idt_descr); 693 switch_to_new_gdt(); 694 695 /* 696 * Set up and load the per-CPU TSS and LDT 697 */ 698 atomic_inc(&init_mm.mm_count); 699 curr->active_mm = &init_mm; 700 if (curr->mm) 701 BUG(); 702 enter_lazy_tlb(&init_mm, curr); 703 704 load_sp0(t, thread); 705 set_tss_desc(cpu,t); 706 load_TR_desc(); 707 load_LDT(&init_mm.context); 708 709 #ifdef CONFIG_DOUBLEFAULT 710 /* Set up doublefault TSS pointer in the GDT */ 711 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 712 #endif 713 714 /* Clear %gs. */ 715 asm volatile ("mov %0, %%gs" : : "r" (0)); 716 717 /* Clear all 6 debug registers: */ 718 set_debugreg(0, 0); 719 set_debugreg(0, 1); 720 set_debugreg(0, 2); 721 set_debugreg(0, 3); 722 set_debugreg(0, 6); 723 set_debugreg(0, 7); 724 725 /* 726 * Force FPU initialization: 727 */ 728 current_thread_info()->status = 0; 729 clear_used_math(); 730 mxcsr_feature_mask_init(); 731 } 732 733 #ifdef CONFIG_HOTPLUG_CPU 734 void __cpuinit cpu_uninit(void) 735 { 736 int cpu = raw_smp_processor_id(); 737 cpu_clear(cpu, cpu_initialized); 738 739 /* lazy TLB state */ 740 per_cpu(cpu_tlbstate, cpu).state = 0; 741 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; 742 } 743 #endif 744