1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 26 #include <asm/stackprotector.h> 27 #include <asm/perf_event.h> 28 #include <asm/mmu_context.h> 29 #include <asm/doublefault.h> 30 #include <asm/archrandom.h> 31 #include <asm/hypervisor.h> 32 #include <asm/processor.h> 33 #include <asm/tlbflush.h> 34 #include <asm/debugreg.h> 35 #include <asm/sections.h> 36 #include <asm/vsyscall.h> 37 #include <linux/topology.h> 38 #include <linux/cpumask.h> 39 #include <linux/atomic.h> 40 #include <asm/proto.h> 41 #include <asm/setup.h> 42 #include <asm/apic.h> 43 #include <asm/desc.h> 44 #include <asm/fpu/internal.h> 45 #include <asm/mtrr.h> 46 #include <asm/hwcap2.h> 47 #include <linux/numa.h> 48 #include <asm/asm.h> 49 #include <asm/bugs.h> 50 #include <asm/cpu.h> 51 #include <asm/mce.h> 52 #include <asm/msr.h> 53 #include <asm/memtype.h> 54 #include <asm/microcode.h> 55 #include <asm/microcode_intel.h> 56 #include <asm/intel-family.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/uv/uv.h> 59 60 #include "cpu.h" 61 62 u32 elf_hwcap2 __read_mostly; 63 64 /* all of these masks are initialized in setup_cpu_local_masks() */ 65 cpumask_var_t cpu_initialized_mask; 66 cpumask_var_t cpu_callout_mask; 67 cpumask_var_t cpu_callin_mask; 68 69 /* representing cpus for which sibling maps can be computed */ 70 cpumask_var_t cpu_sibling_setup_mask; 71 72 /* Number of siblings per CPU package */ 73 int smp_num_siblings = 1; 74 EXPORT_SYMBOL(smp_num_siblings); 75 76 /* Last level cache ID of each logical CPU */ 77 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 78 79 /* correctly size the local cpu masks */ 80 void __init setup_cpu_local_masks(void) 81 { 82 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 83 alloc_bootmem_cpumask_var(&cpu_callin_mask); 84 alloc_bootmem_cpumask_var(&cpu_callout_mask); 85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 86 } 87 88 static void default_init(struct cpuinfo_x86 *c) 89 { 90 #ifdef CONFIG_X86_64 91 cpu_detect_cache_sizes(c); 92 #else 93 /* Not much we can do here... */ 94 /* Check if at least it has cpuid */ 95 if (c->cpuid_level == -1) { 96 /* No cpuid. It must be an ancient CPU */ 97 if (c->x86 == 4) 98 strcpy(c->x86_model_id, "486"); 99 else if (c->x86 == 3) 100 strcpy(c->x86_model_id, "386"); 101 } 102 #endif 103 } 104 105 static const struct cpu_dev default_cpu = { 106 .c_init = default_init, 107 .c_vendor = "Unknown", 108 .c_x86_vendor = X86_VENDOR_UNKNOWN, 109 }; 110 111 static const struct cpu_dev *this_cpu = &default_cpu; 112 113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 114 #ifdef CONFIG_X86_64 115 /* 116 * We need valid kernel segments for data and code in long mode too 117 * IRET will check the segment types kkeil 2000/10/28 118 * Also sysret mandates a special GDT layout 119 * 120 * TLS descriptors are currently at a different place compared to i386. 121 * Hopefully nobody expects them at a fixed place (Wine?) 122 */ 123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 129 #else 130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 134 /* 135 * Segments used for calling PnP BIOS have byte granularity. 136 * They code segments and data segments have fixed 64k limits, 137 * the transfer segment sizes are set at run time. 138 */ 139 /* 32-bit code */ 140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 141 /* 16-bit code */ 142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 143 /* 16-bit data */ 144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 145 /* 16-bit data */ 146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 147 /* 16-bit data */ 148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 149 /* 150 * The APM segments have byte granularity and their bases 151 * are set at run time. All have 64k limits. 152 */ 153 /* 32-bit code */ 154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 155 /* 16-bit code */ 156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 157 /* data */ 158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 159 160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 162 GDT_STACK_CANARY_INIT 163 #endif 164 } }; 165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 166 167 #ifdef CONFIG_X86_64 168 static int __init x86_nopcid_setup(char *s) 169 { 170 /* nopcid doesn't accept parameters */ 171 if (s) 172 return -EINVAL; 173 174 /* do not emit a message if the feature is not present */ 175 if (!boot_cpu_has(X86_FEATURE_PCID)) 176 return 0; 177 178 setup_clear_cpu_cap(X86_FEATURE_PCID); 179 pr_info("nopcid: PCID feature disabled\n"); 180 return 0; 181 } 182 early_param("nopcid", x86_nopcid_setup); 183 #endif 184 185 static int __init x86_noinvpcid_setup(char *s) 186 { 187 /* noinvpcid doesn't accept parameters */ 188 if (s) 189 return -EINVAL; 190 191 /* do not emit a message if the feature is not present */ 192 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 193 return 0; 194 195 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 196 pr_info("noinvpcid: INVPCID feature disabled\n"); 197 return 0; 198 } 199 early_param("noinvpcid", x86_noinvpcid_setup); 200 201 #ifdef CONFIG_X86_32 202 static int cachesize_override = -1; 203 static int disable_x86_serial_nr = 1; 204 205 static int __init cachesize_setup(char *str) 206 { 207 get_option(&str, &cachesize_override); 208 return 1; 209 } 210 __setup("cachesize=", cachesize_setup); 211 212 static int __init x86_sep_setup(char *s) 213 { 214 setup_clear_cpu_cap(X86_FEATURE_SEP); 215 return 1; 216 } 217 __setup("nosep", x86_sep_setup); 218 219 /* Standard macro to see if a specific flag is changeable */ 220 static inline int flag_is_changeable_p(u32 flag) 221 { 222 u32 f1, f2; 223 224 /* 225 * Cyrix and IDT cpus allow disabling of CPUID 226 * so the code below may return different results 227 * when it is executed before and after enabling 228 * the CPUID. Add "volatile" to not allow gcc to 229 * optimize the subsequent calls to this function. 230 */ 231 asm volatile ("pushfl \n\t" 232 "pushfl \n\t" 233 "popl %0 \n\t" 234 "movl %0, %1 \n\t" 235 "xorl %2, %0 \n\t" 236 "pushl %0 \n\t" 237 "popfl \n\t" 238 "pushfl \n\t" 239 "popl %0 \n\t" 240 "popfl \n\t" 241 242 : "=&r" (f1), "=&r" (f2) 243 : "ir" (flag)); 244 245 return ((f1^f2) & flag) != 0; 246 } 247 248 /* Probe for the CPUID instruction */ 249 int have_cpuid_p(void) 250 { 251 return flag_is_changeable_p(X86_EFLAGS_ID); 252 } 253 254 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 255 { 256 unsigned long lo, hi; 257 258 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 259 return; 260 261 /* Disable processor serial number: */ 262 263 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 264 lo |= 0x200000; 265 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 266 267 pr_notice("CPU serial number disabled.\n"); 268 clear_cpu_cap(c, X86_FEATURE_PN); 269 270 /* Disabling the serial number may affect the cpuid level */ 271 c->cpuid_level = cpuid_eax(0); 272 } 273 274 static int __init x86_serial_nr_setup(char *s) 275 { 276 disable_x86_serial_nr = 0; 277 return 1; 278 } 279 __setup("serialnumber", x86_serial_nr_setup); 280 #else 281 static inline int flag_is_changeable_p(u32 flag) 282 { 283 return 1; 284 } 285 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 286 { 287 } 288 #endif 289 290 static __init int setup_disable_smep(char *arg) 291 { 292 setup_clear_cpu_cap(X86_FEATURE_SMEP); 293 return 1; 294 } 295 __setup("nosmep", setup_disable_smep); 296 297 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 298 { 299 if (cpu_has(c, X86_FEATURE_SMEP)) 300 cr4_set_bits(X86_CR4_SMEP); 301 } 302 303 static __init int setup_disable_smap(char *arg) 304 { 305 setup_clear_cpu_cap(X86_FEATURE_SMAP); 306 return 1; 307 } 308 __setup("nosmap", setup_disable_smap); 309 310 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 311 { 312 unsigned long eflags = native_save_fl(); 313 314 /* This should have been cleared long ago */ 315 BUG_ON(eflags & X86_EFLAGS_AC); 316 317 if (cpu_has(c, X86_FEATURE_SMAP)) { 318 #ifdef CONFIG_X86_SMAP 319 cr4_set_bits(X86_CR4_SMAP); 320 #else 321 cr4_clear_bits(X86_CR4_SMAP); 322 #endif 323 } 324 } 325 326 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 327 { 328 /* Check the boot processor, plus build option for UMIP. */ 329 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 330 goto out; 331 332 /* Check the current processor's cpuid bits. */ 333 if (!cpu_has(c, X86_FEATURE_UMIP)) 334 goto out; 335 336 cr4_set_bits(X86_CR4_UMIP); 337 338 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 339 340 return; 341 342 out: 343 /* 344 * Make sure UMIP is disabled in case it was enabled in a 345 * previous boot (e.g., via kexec). 346 */ 347 cr4_clear_bits(X86_CR4_UMIP); 348 } 349 350 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 351 static unsigned long cr4_pinned_bits __ro_after_init; 352 353 void native_write_cr0(unsigned long val) 354 { 355 unsigned long bits_missing = 0; 356 357 set_register: 358 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); 359 360 if (static_branch_likely(&cr_pinning)) { 361 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 362 bits_missing = X86_CR0_WP; 363 val |= bits_missing; 364 goto set_register; 365 } 366 /* Warn after we've set the missing bits. */ 367 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 368 } 369 } 370 EXPORT_SYMBOL(native_write_cr0); 371 372 void native_write_cr4(unsigned long val) 373 { 374 unsigned long bits_missing = 0; 375 376 set_register: 377 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); 378 379 if (static_branch_likely(&cr_pinning)) { 380 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { 381 bits_missing = ~val & cr4_pinned_bits; 382 val |= bits_missing; 383 goto set_register; 384 } 385 /* Warn after we've set the missing bits. */ 386 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n", 387 bits_missing); 388 } 389 } 390 #if IS_MODULE(CONFIG_LKDTM) 391 EXPORT_SYMBOL_GPL(native_write_cr4); 392 #endif 393 394 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 395 { 396 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 397 398 lockdep_assert_irqs_disabled(); 399 400 newval = (cr4 & ~clear) | set; 401 if (newval != cr4) { 402 this_cpu_write(cpu_tlbstate.cr4, newval); 403 __write_cr4(newval); 404 } 405 } 406 EXPORT_SYMBOL(cr4_update_irqsoff); 407 408 /* Read the CR4 shadow. */ 409 unsigned long cr4_read_shadow(void) 410 { 411 return this_cpu_read(cpu_tlbstate.cr4); 412 } 413 EXPORT_SYMBOL_GPL(cr4_read_shadow); 414 415 void cr4_init(void) 416 { 417 unsigned long cr4 = __read_cr4(); 418 419 if (boot_cpu_has(X86_FEATURE_PCID)) 420 cr4 |= X86_CR4_PCIDE; 421 if (static_branch_likely(&cr_pinning)) 422 cr4 |= cr4_pinned_bits; 423 424 __write_cr4(cr4); 425 426 /* Initialize cr4 shadow for this CPU. */ 427 this_cpu_write(cpu_tlbstate.cr4, cr4); 428 } 429 430 /* 431 * Once CPU feature detection is finished (and boot params have been 432 * parsed), record any of the sensitive CR bits that are set, and 433 * enable CR pinning. 434 */ 435 static void __init setup_cr_pinning(void) 436 { 437 unsigned long mask; 438 439 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); 440 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; 441 static_key_enable(&cr_pinning.key); 442 } 443 444 /* 445 * Protection Keys are not available in 32-bit mode. 446 */ 447 static bool pku_disabled; 448 449 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 450 { 451 struct pkru_state *pk; 452 453 /* check the boot processor, plus compile options for PKU: */ 454 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 455 return; 456 /* checks the actual processor's cpuid bits: */ 457 if (!cpu_has(c, X86_FEATURE_PKU)) 458 return; 459 if (pku_disabled) 460 return; 461 462 cr4_set_bits(X86_CR4_PKE); 463 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 464 if (pk) 465 pk->pkru = init_pkru_value; 466 /* 467 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 468 * cpuid bit to be set. We need to ensure that we 469 * update that bit in this CPU's "cpu_info". 470 */ 471 set_cpu_cap(c, X86_FEATURE_OSPKE); 472 } 473 474 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 475 static __init int setup_disable_pku(char *arg) 476 { 477 /* 478 * Do not clear the X86_FEATURE_PKU bit. All of the 479 * runtime checks are against OSPKE so clearing the 480 * bit does nothing. 481 * 482 * This way, we will see "pku" in cpuinfo, but not 483 * "ospke", which is exactly what we want. It shows 484 * that the CPU has PKU, but the OS has not enabled it. 485 * This happens to be exactly how a system would look 486 * if we disabled the config option. 487 */ 488 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 489 pku_disabled = true; 490 return 1; 491 } 492 __setup("nopku", setup_disable_pku); 493 #endif /* CONFIG_X86_64 */ 494 495 /* 496 * Some CPU features depend on higher CPUID levels, which may not always 497 * be available due to CPUID level capping or broken virtualization 498 * software. Add those features to this table to auto-disable them. 499 */ 500 struct cpuid_dependent_feature { 501 u32 feature; 502 u32 level; 503 }; 504 505 static const struct cpuid_dependent_feature 506 cpuid_dependent_features[] = { 507 { X86_FEATURE_MWAIT, 0x00000005 }, 508 { X86_FEATURE_DCA, 0x00000009 }, 509 { X86_FEATURE_XSAVE, 0x0000000d }, 510 { 0, 0 } 511 }; 512 513 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 514 { 515 const struct cpuid_dependent_feature *df; 516 517 for (df = cpuid_dependent_features; df->feature; df++) { 518 519 if (!cpu_has(c, df->feature)) 520 continue; 521 /* 522 * Note: cpuid_level is set to -1 if unavailable, but 523 * extended_extended_level is set to 0 if unavailable 524 * and the legitimate extended levels are all negative 525 * when signed; hence the weird messing around with 526 * signs here... 527 */ 528 if (!((s32)df->level < 0 ? 529 (u32)df->level > (u32)c->extended_cpuid_level : 530 (s32)df->level > (s32)c->cpuid_level)) 531 continue; 532 533 clear_cpu_cap(c, df->feature); 534 if (!warn) 535 continue; 536 537 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 538 x86_cap_flag(df->feature), df->level); 539 } 540 } 541 542 /* 543 * Naming convention should be: <Name> [(<Codename>)] 544 * This table only is used unless init_<vendor>() below doesn't set it; 545 * in particular, if CPUID levels 0x80000002..4 are supported, this 546 * isn't used 547 */ 548 549 /* Look up CPU names by table lookup. */ 550 static const char *table_lookup_model(struct cpuinfo_x86 *c) 551 { 552 #ifdef CONFIG_X86_32 553 const struct legacy_cpu_model_info *info; 554 555 if (c->x86_model >= 16) 556 return NULL; /* Range check */ 557 558 if (!this_cpu) 559 return NULL; 560 561 info = this_cpu->legacy_models; 562 563 while (info->family) { 564 if (info->family == c->x86) 565 return info->model_names[c->x86_model]; 566 info++; 567 } 568 #endif 569 return NULL; /* Not found */ 570 } 571 572 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 573 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 574 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 575 576 void load_percpu_segment(int cpu) 577 { 578 #ifdef CONFIG_X86_32 579 loadsegment(fs, __KERNEL_PERCPU); 580 #else 581 __loadsegment_simple(gs, 0); 582 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 583 #endif 584 load_stack_canary_segment(); 585 } 586 587 #ifdef CONFIG_X86_32 588 /* The 32-bit entry code needs to find cpu_entry_area. */ 589 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 590 #endif 591 592 /* Load the original GDT from the per-cpu structure */ 593 void load_direct_gdt(int cpu) 594 { 595 struct desc_ptr gdt_descr; 596 597 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 598 gdt_descr.size = GDT_SIZE - 1; 599 load_gdt(&gdt_descr); 600 } 601 EXPORT_SYMBOL_GPL(load_direct_gdt); 602 603 /* Load a fixmap remapping of the per-cpu GDT */ 604 void load_fixmap_gdt(int cpu) 605 { 606 struct desc_ptr gdt_descr; 607 608 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 609 gdt_descr.size = GDT_SIZE - 1; 610 load_gdt(&gdt_descr); 611 } 612 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 613 614 /* 615 * Current gdt points %fs at the "master" per-cpu area: after this, 616 * it's on the real one. 617 */ 618 void switch_to_new_gdt(int cpu) 619 { 620 /* Load the original GDT */ 621 load_direct_gdt(cpu); 622 /* Reload the per-cpu base */ 623 load_percpu_segment(cpu); 624 } 625 626 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 627 628 static void get_model_name(struct cpuinfo_x86 *c) 629 { 630 unsigned int *v; 631 char *p, *q, *s; 632 633 if (c->extended_cpuid_level < 0x80000004) 634 return; 635 636 v = (unsigned int *)c->x86_model_id; 637 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 638 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 639 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 640 c->x86_model_id[48] = 0; 641 642 /* Trim whitespace */ 643 p = q = s = &c->x86_model_id[0]; 644 645 while (*p == ' ') 646 p++; 647 648 while (*p) { 649 /* Note the last non-whitespace index */ 650 if (!isspace(*p)) 651 s = q; 652 653 *q++ = *p++; 654 } 655 656 *(s + 1) = '\0'; 657 } 658 659 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 660 { 661 unsigned int eax, ebx, ecx, edx; 662 663 c->x86_max_cores = 1; 664 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 665 return; 666 667 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 668 if (eax & 0x1f) 669 c->x86_max_cores = (eax >> 26) + 1; 670 } 671 672 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 673 { 674 unsigned int n, dummy, ebx, ecx, edx, l2size; 675 676 n = c->extended_cpuid_level; 677 678 if (n >= 0x80000005) { 679 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 680 c->x86_cache_size = (ecx>>24) + (edx>>24); 681 #ifdef CONFIG_X86_64 682 /* On K8 L1 TLB is inclusive, so don't count it */ 683 c->x86_tlbsize = 0; 684 #endif 685 } 686 687 if (n < 0x80000006) /* Some chips just has a large L1. */ 688 return; 689 690 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 691 l2size = ecx >> 16; 692 693 #ifdef CONFIG_X86_64 694 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 695 #else 696 /* do processor-specific cache resizing */ 697 if (this_cpu->legacy_cache_size) 698 l2size = this_cpu->legacy_cache_size(c, l2size); 699 700 /* Allow user to override all this if necessary. */ 701 if (cachesize_override != -1) 702 l2size = cachesize_override; 703 704 if (l2size == 0) 705 return; /* Again, no L2 cache is possible */ 706 #endif 707 708 c->x86_cache_size = l2size; 709 } 710 711 u16 __read_mostly tlb_lli_4k[NR_INFO]; 712 u16 __read_mostly tlb_lli_2m[NR_INFO]; 713 u16 __read_mostly tlb_lli_4m[NR_INFO]; 714 u16 __read_mostly tlb_lld_4k[NR_INFO]; 715 u16 __read_mostly tlb_lld_2m[NR_INFO]; 716 u16 __read_mostly tlb_lld_4m[NR_INFO]; 717 u16 __read_mostly tlb_lld_1g[NR_INFO]; 718 719 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 720 { 721 if (this_cpu->c_detect_tlb) 722 this_cpu->c_detect_tlb(c); 723 724 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 725 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 726 tlb_lli_4m[ENTRIES]); 727 728 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 729 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 730 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 731 } 732 733 int detect_ht_early(struct cpuinfo_x86 *c) 734 { 735 #ifdef CONFIG_SMP 736 u32 eax, ebx, ecx, edx; 737 738 if (!cpu_has(c, X86_FEATURE_HT)) 739 return -1; 740 741 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 742 return -1; 743 744 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 745 return -1; 746 747 cpuid(1, &eax, &ebx, &ecx, &edx); 748 749 smp_num_siblings = (ebx & 0xff0000) >> 16; 750 if (smp_num_siblings == 1) 751 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 752 #endif 753 return 0; 754 } 755 756 void detect_ht(struct cpuinfo_x86 *c) 757 { 758 #ifdef CONFIG_SMP 759 int index_msb, core_bits; 760 761 if (detect_ht_early(c) < 0) 762 return; 763 764 index_msb = get_count_order(smp_num_siblings); 765 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 766 767 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 768 769 index_msb = get_count_order(smp_num_siblings); 770 771 core_bits = get_count_order(c->x86_max_cores); 772 773 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 774 ((1 << core_bits) - 1); 775 #endif 776 } 777 778 static void get_cpu_vendor(struct cpuinfo_x86 *c) 779 { 780 char *v = c->x86_vendor_id; 781 int i; 782 783 for (i = 0; i < X86_VENDOR_NUM; i++) { 784 if (!cpu_devs[i]) 785 break; 786 787 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 788 (cpu_devs[i]->c_ident[1] && 789 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 790 791 this_cpu = cpu_devs[i]; 792 c->x86_vendor = this_cpu->c_x86_vendor; 793 return; 794 } 795 } 796 797 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 798 "CPU: Your system may be unstable.\n", v); 799 800 c->x86_vendor = X86_VENDOR_UNKNOWN; 801 this_cpu = &default_cpu; 802 } 803 804 void cpu_detect(struct cpuinfo_x86 *c) 805 { 806 /* Get vendor name */ 807 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 808 (unsigned int *)&c->x86_vendor_id[0], 809 (unsigned int *)&c->x86_vendor_id[8], 810 (unsigned int *)&c->x86_vendor_id[4]); 811 812 c->x86 = 4; 813 /* Intel-defined flags: level 0x00000001 */ 814 if (c->cpuid_level >= 0x00000001) { 815 u32 junk, tfms, cap0, misc; 816 817 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 818 c->x86 = x86_family(tfms); 819 c->x86_model = x86_model(tfms); 820 c->x86_stepping = x86_stepping(tfms); 821 822 if (cap0 & (1<<19)) { 823 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 824 c->x86_cache_alignment = c->x86_clflush_size; 825 } 826 } 827 } 828 829 static void apply_forced_caps(struct cpuinfo_x86 *c) 830 { 831 int i; 832 833 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 834 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 835 c->x86_capability[i] |= cpu_caps_set[i]; 836 } 837 } 838 839 static void init_speculation_control(struct cpuinfo_x86 *c) 840 { 841 /* 842 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 843 * and they also have a different bit for STIBP support. Also, 844 * a hypervisor might have set the individual AMD bits even on 845 * Intel CPUs, for finer-grained selection of what's available. 846 */ 847 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 848 set_cpu_cap(c, X86_FEATURE_IBRS); 849 set_cpu_cap(c, X86_FEATURE_IBPB); 850 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 851 } 852 853 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 854 set_cpu_cap(c, X86_FEATURE_STIBP); 855 856 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 857 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 858 set_cpu_cap(c, X86_FEATURE_SSBD); 859 860 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 861 set_cpu_cap(c, X86_FEATURE_IBRS); 862 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 863 } 864 865 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 866 set_cpu_cap(c, X86_FEATURE_IBPB); 867 868 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 869 set_cpu_cap(c, X86_FEATURE_STIBP); 870 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 871 } 872 873 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 874 set_cpu_cap(c, X86_FEATURE_SSBD); 875 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 876 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 877 } 878 } 879 880 void get_cpu_cap(struct cpuinfo_x86 *c) 881 { 882 u32 eax, ebx, ecx, edx; 883 884 /* Intel-defined flags: level 0x00000001 */ 885 if (c->cpuid_level >= 0x00000001) { 886 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 887 888 c->x86_capability[CPUID_1_ECX] = ecx; 889 c->x86_capability[CPUID_1_EDX] = edx; 890 } 891 892 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 893 if (c->cpuid_level >= 0x00000006) 894 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 895 896 /* Additional Intel-defined flags: level 0x00000007 */ 897 if (c->cpuid_level >= 0x00000007) { 898 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 899 c->x86_capability[CPUID_7_0_EBX] = ebx; 900 c->x86_capability[CPUID_7_ECX] = ecx; 901 c->x86_capability[CPUID_7_EDX] = edx; 902 903 /* Check valid sub-leaf index before accessing it */ 904 if (eax >= 1) { 905 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 906 c->x86_capability[CPUID_7_1_EAX] = eax; 907 } 908 } 909 910 /* Extended state features: level 0x0000000d */ 911 if (c->cpuid_level >= 0x0000000d) { 912 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 913 914 c->x86_capability[CPUID_D_1_EAX] = eax; 915 } 916 917 /* AMD-defined flags: level 0x80000001 */ 918 eax = cpuid_eax(0x80000000); 919 c->extended_cpuid_level = eax; 920 921 if ((eax & 0xffff0000) == 0x80000000) { 922 if (eax >= 0x80000001) { 923 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 924 925 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 926 c->x86_capability[CPUID_8000_0001_EDX] = edx; 927 } 928 } 929 930 if (c->extended_cpuid_level >= 0x80000007) { 931 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 932 933 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 934 c->x86_power = edx; 935 } 936 937 if (c->extended_cpuid_level >= 0x80000008) { 938 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 939 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 940 } 941 942 if (c->extended_cpuid_level >= 0x8000000a) 943 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 944 945 init_scattered_cpuid_features(c); 946 init_speculation_control(c); 947 948 /* 949 * Clear/Set all flags overridden by options, after probe. 950 * This needs to happen each time we re-probe, which may happen 951 * several times during CPU initialization. 952 */ 953 apply_forced_caps(c); 954 } 955 956 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 957 { 958 u32 eax, ebx, ecx, edx; 959 960 if (c->extended_cpuid_level >= 0x80000008) { 961 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 962 963 c->x86_virt_bits = (eax >> 8) & 0xff; 964 c->x86_phys_bits = eax & 0xff; 965 } 966 #ifdef CONFIG_X86_32 967 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 968 c->x86_phys_bits = 36; 969 #endif 970 c->x86_cache_bits = c->x86_phys_bits; 971 } 972 973 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 974 { 975 #ifdef CONFIG_X86_32 976 int i; 977 978 /* 979 * First of all, decide if this is a 486 or higher 980 * It's a 486 if we can modify the AC flag 981 */ 982 if (flag_is_changeable_p(X86_EFLAGS_AC)) 983 c->x86 = 4; 984 else 985 c->x86 = 3; 986 987 for (i = 0; i < X86_VENDOR_NUM; i++) 988 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 989 c->x86_vendor_id[0] = 0; 990 cpu_devs[i]->c_identify(c); 991 if (c->x86_vendor_id[0]) { 992 get_cpu_vendor(c); 993 break; 994 } 995 } 996 #endif 997 } 998 999 #define NO_SPECULATION BIT(0) 1000 #define NO_MELTDOWN BIT(1) 1001 #define NO_SSB BIT(2) 1002 #define NO_L1TF BIT(3) 1003 #define NO_MDS BIT(4) 1004 #define MSBDS_ONLY BIT(5) 1005 #define NO_SWAPGS BIT(6) 1006 #define NO_ITLB_MULTIHIT BIT(7) 1007 #define NO_SPECTRE_V2 BIT(8) 1008 1009 #define VULNWL(vendor, family, model, whitelist) \ 1010 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1011 1012 #define VULNWL_INTEL(model, whitelist) \ 1013 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1014 1015 #define VULNWL_AMD(family, whitelist) \ 1016 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1017 1018 #define VULNWL_HYGON(family, whitelist) \ 1019 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1020 1021 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1022 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1023 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1024 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1025 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1026 1027 /* Intel Family 6 */ 1028 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1029 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1030 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1031 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1032 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1033 1034 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1035 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1036 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1037 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1038 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1039 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1040 1041 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1042 1043 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1044 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1045 1046 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1047 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1048 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1049 1050 /* 1051 * Technically, swapgs isn't serializing on AMD (despite it previously 1052 * being documented as such in the APM). But according to AMD, %gs is 1053 * updated non-speculatively, and the issuing of %gs-relative memory 1054 * operands will be blocked until the %gs update completes, which is 1055 * good enough for our purposes. 1056 */ 1057 1058 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1059 1060 /* AMD Family 0xf - 0x12 */ 1061 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1062 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1063 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1064 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1065 1066 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1067 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1068 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1069 1070 /* Zhaoxin Family 7 */ 1071 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1072 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1073 {} 1074 }; 1075 1076 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1077 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1078 INTEL_FAM6_##model, steppings, \ 1079 X86_FEATURE_ANY, issues) 1080 1081 #define SRBDS BIT(0) 1082 1083 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1084 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1085 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1086 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1087 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1088 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1089 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1090 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS), 1091 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS), 1092 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS), 1093 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS), 1094 {} 1095 }; 1096 1097 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1098 { 1099 const struct x86_cpu_id *m = x86_match_cpu(table); 1100 1101 return m && !!(m->driver_data & which); 1102 } 1103 1104 u64 x86_read_arch_cap_msr(void) 1105 { 1106 u64 ia32_cap = 0; 1107 1108 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1109 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1110 1111 return ia32_cap; 1112 } 1113 1114 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1115 { 1116 u64 ia32_cap = x86_read_arch_cap_msr(); 1117 1118 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1119 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1120 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1121 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1122 1123 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1124 return; 1125 1126 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1127 1128 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1129 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1130 1131 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1132 !(ia32_cap & ARCH_CAP_SSB_NO) && 1133 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1134 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1135 1136 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1137 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1138 1139 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1140 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1141 setup_force_cpu_bug(X86_BUG_MDS); 1142 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1143 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1144 } 1145 1146 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1147 setup_force_cpu_bug(X86_BUG_SWAPGS); 1148 1149 /* 1150 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1151 * - TSX is supported or 1152 * - TSX_CTRL is present 1153 * 1154 * TSX_CTRL check is needed for cases when TSX could be disabled before 1155 * the kernel boot e.g. kexec. 1156 * TSX_CTRL check alone is not sufficient for cases when the microcode 1157 * update is not present or running as guest that don't get TSX_CTRL. 1158 */ 1159 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1160 (cpu_has(c, X86_FEATURE_RTM) || 1161 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1162 setup_force_cpu_bug(X86_BUG_TAA); 1163 1164 /* 1165 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1166 * in the vulnerability blacklist. 1167 */ 1168 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1169 cpu_has(c, X86_FEATURE_RDSEED)) && 1170 cpu_matches(cpu_vuln_blacklist, SRBDS)) 1171 setup_force_cpu_bug(X86_BUG_SRBDS); 1172 1173 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1174 return; 1175 1176 /* Rogue Data Cache Load? No! */ 1177 if (ia32_cap & ARCH_CAP_RDCL_NO) 1178 return; 1179 1180 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1181 1182 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1183 return; 1184 1185 setup_force_cpu_bug(X86_BUG_L1TF); 1186 } 1187 1188 /* 1189 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1190 * unfortunately, that's not true in practice because of early VIA 1191 * chips and (more importantly) broken virtualizers that are not easy 1192 * to detect. In the latter case it doesn't even *fail* reliably, so 1193 * probing for it doesn't even work. Disable it completely on 32-bit 1194 * unless we can find a reliable way to detect all the broken cases. 1195 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1196 */ 1197 static void detect_nopl(void) 1198 { 1199 #ifdef CONFIG_X86_32 1200 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1201 #else 1202 setup_force_cpu_cap(X86_FEATURE_NOPL); 1203 #endif 1204 } 1205 1206 /* 1207 * Do minimum CPU detection early. 1208 * Fields really needed: vendor, cpuid_level, family, model, mask, 1209 * cache alignment. 1210 * The others are not touched to avoid unwanted side effects. 1211 * 1212 * WARNING: this function is only called on the boot CPU. Don't add code 1213 * here that is supposed to run on all CPUs. 1214 */ 1215 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1216 { 1217 #ifdef CONFIG_X86_64 1218 c->x86_clflush_size = 64; 1219 c->x86_phys_bits = 36; 1220 c->x86_virt_bits = 48; 1221 #else 1222 c->x86_clflush_size = 32; 1223 c->x86_phys_bits = 32; 1224 c->x86_virt_bits = 32; 1225 #endif 1226 c->x86_cache_alignment = c->x86_clflush_size; 1227 1228 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1229 c->extended_cpuid_level = 0; 1230 1231 if (!have_cpuid_p()) 1232 identify_cpu_without_cpuid(c); 1233 1234 /* cyrix could have cpuid enabled via c_identify()*/ 1235 if (have_cpuid_p()) { 1236 cpu_detect(c); 1237 get_cpu_vendor(c); 1238 get_cpu_cap(c); 1239 get_cpu_address_sizes(c); 1240 setup_force_cpu_cap(X86_FEATURE_CPUID); 1241 1242 if (this_cpu->c_early_init) 1243 this_cpu->c_early_init(c); 1244 1245 c->cpu_index = 0; 1246 filter_cpuid_features(c, false); 1247 1248 if (this_cpu->c_bsp_init) 1249 this_cpu->c_bsp_init(c); 1250 } else { 1251 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1252 } 1253 1254 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1255 1256 cpu_set_bug_bits(c); 1257 1258 cpu_set_core_cap_bits(c); 1259 1260 fpu__init_system(c); 1261 1262 #ifdef CONFIG_X86_32 1263 /* 1264 * Regardless of whether PCID is enumerated, the SDM says 1265 * that it can't be enabled in 32-bit mode. 1266 */ 1267 setup_clear_cpu_cap(X86_FEATURE_PCID); 1268 #endif 1269 1270 /* 1271 * Later in the boot process pgtable_l5_enabled() relies on 1272 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1273 * enabled by this point we need to clear the feature bit to avoid 1274 * false-positives at the later stage. 1275 * 1276 * pgtable_l5_enabled() can be false here for several reasons: 1277 * - 5-level paging is disabled compile-time; 1278 * - it's 32-bit kernel; 1279 * - machine doesn't support 5-level paging; 1280 * - user specified 'no5lvl' in kernel command line. 1281 */ 1282 if (!pgtable_l5_enabled()) 1283 setup_clear_cpu_cap(X86_FEATURE_LA57); 1284 1285 detect_nopl(); 1286 } 1287 1288 void __init early_cpu_init(void) 1289 { 1290 const struct cpu_dev *const *cdev; 1291 int count = 0; 1292 1293 #ifdef CONFIG_PROCESSOR_SELECT 1294 pr_info("KERNEL supported cpus:\n"); 1295 #endif 1296 1297 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1298 const struct cpu_dev *cpudev = *cdev; 1299 1300 if (count >= X86_VENDOR_NUM) 1301 break; 1302 cpu_devs[count] = cpudev; 1303 count++; 1304 1305 #ifdef CONFIG_PROCESSOR_SELECT 1306 { 1307 unsigned int j; 1308 1309 for (j = 0; j < 2; j++) { 1310 if (!cpudev->c_ident[j]) 1311 continue; 1312 pr_info(" %s %s\n", cpudev->c_vendor, 1313 cpudev->c_ident[j]); 1314 } 1315 } 1316 #endif 1317 } 1318 early_identify_cpu(&boot_cpu_data); 1319 } 1320 1321 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1322 { 1323 #ifdef CONFIG_X86_64 1324 /* 1325 * Empirically, writing zero to a segment selector on AMD does 1326 * not clear the base, whereas writing zero to a segment 1327 * selector on Intel does clear the base. Intel's behavior 1328 * allows slightly faster context switches in the common case 1329 * where GS is unused by the prev and next threads. 1330 * 1331 * Since neither vendor documents this anywhere that I can see, 1332 * detect it directly instead of hardcoding the choice by 1333 * vendor. 1334 * 1335 * I've designated AMD's behavior as the "bug" because it's 1336 * counterintuitive and less friendly. 1337 */ 1338 1339 unsigned long old_base, tmp; 1340 rdmsrl(MSR_FS_BASE, old_base); 1341 wrmsrl(MSR_FS_BASE, 1); 1342 loadsegment(fs, 0); 1343 rdmsrl(MSR_FS_BASE, tmp); 1344 if (tmp != 0) 1345 set_cpu_bug(c, X86_BUG_NULL_SEG); 1346 wrmsrl(MSR_FS_BASE, old_base); 1347 #endif 1348 } 1349 1350 static void generic_identify(struct cpuinfo_x86 *c) 1351 { 1352 c->extended_cpuid_level = 0; 1353 1354 if (!have_cpuid_p()) 1355 identify_cpu_without_cpuid(c); 1356 1357 /* cyrix could have cpuid enabled via c_identify()*/ 1358 if (!have_cpuid_p()) 1359 return; 1360 1361 cpu_detect(c); 1362 1363 get_cpu_vendor(c); 1364 1365 get_cpu_cap(c); 1366 1367 get_cpu_address_sizes(c); 1368 1369 if (c->cpuid_level >= 0x00000001) { 1370 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1371 #ifdef CONFIG_X86_32 1372 # ifdef CONFIG_SMP 1373 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1374 # else 1375 c->apicid = c->initial_apicid; 1376 # endif 1377 #endif 1378 c->phys_proc_id = c->initial_apicid; 1379 } 1380 1381 get_model_name(c); /* Default name */ 1382 1383 detect_null_seg_behavior(c); 1384 1385 /* 1386 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1387 * systems that run Linux at CPL > 0 may or may not have the 1388 * issue, but, even if they have the issue, there's absolutely 1389 * nothing we can do about it because we can't use the real IRET 1390 * instruction. 1391 * 1392 * NB: For the time being, only 32-bit kernels support 1393 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1394 * whether to apply espfix using paravirt hooks. If any 1395 * non-paravirt system ever shows up that does *not* have the 1396 * ESPFIX issue, we can change this. 1397 */ 1398 #ifdef CONFIG_X86_32 1399 # ifdef CONFIG_PARAVIRT_XXL 1400 do { 1401 extern void native_iret(void); 1402 if (pv_ops.cpu.iret == native_iret) 1403 set_cpu_bug(c, X86_BUG_ESPFIX); 1404 } while (0); 1405 # else 1406 set_cpu_bug(c, X86_BUG_ESPFIX); 1407 # endif 1408 #endif 1409 } 1410 1411 /* 1412 * Validate that ACPI/mptables have the same information about the 1413 * effective APIC id and update the package map. 1414 */ 1415 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1416 { 1417 #ifdef CONFIG_SMP 1418 unsigned int apicid, cpu = smp_processor_id(); 1419 1420 apicid = apic->cpu_present_to_apicid(cpu); 1421 1422 if (apicid != c->apicid) { 1423 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1424 cpu, apicid, c->initial_apicid); 1425 } 1426 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1427 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1428 #else 1429 c->logical_proc_id = 0; 1430 #endif 1431 } 1432 1433 /* 1434 * This does the hard work of actually picking apart the CPU stuff... 1435 */ 1436 static void identify_cpu(struct cpuinfo_x86 *c) 1437 { 1438 int i; 1439 1440 c->loops_per_jiffy = loops_per_jiffy; 1441 c->x86_cache_size = 0; 1442 c->x86_vendor = X86_VENDOR_UNKNOWN; 1443 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1444 c->x86_vendor_id[0] = '\0'; /* Unset */ 1445 c->x86_model_id[0] = '\0'; /* Unset */ 1446 c->x86_max_cores = 1; 1447 c->x86_coreid_bits = 0; 1448 c->cu_id = 0xff; 1449 #ifdef CONFIG_X86_64 1450 c->x86_clflush_size = 64; 1451 c->x86_phys_bits = 36; 1452 c->x86_virt_bits = 48; 1453 #else 1454 c->cpuid_level = -1; /* CPUID not detected */ 1455 c->x86_clflush_size = 32; 1456 c->x86_phys_bits = 32; 1457 c->x86_virt_bits = 32; 1458 #endif 1459 c->x86_cache_alignment = c->x86_clflush_size; 1460 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1461 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1462 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1463 #endif 1464 1465 generic_identify(c); 1466 1467 if (this_cpu->c_identify) 1468 this_cpu->c_identify(c); 1469 1470 /* Clear/Set all flags overridden by options, after probe */ 1471 apply_forced_caps(c); 1472 1473 #ifdef CONFIG_X86_64 1474 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1475 #endif 1476 1477 /* 1478 * Vendor-specific initialization. In this section we 1479 * canonicalize the feature flags, meaning if there are 1480 * features a certain CPU supports which CPUID doesn't 1481 * tell us, CPUID claiming incorrect flags, or other bugs, 1482 * we handle them here. 1483 * 1484 * At the end of this section, c->x86_capability better 1485 * indicate the features this CPU genuinely supports! 1486 */ 1487 if (this_cpu->c_init) 1488 this_cpu->c_init(c); 1489 1490 /* Disable the PN if appropriate */ 1491 squash_the_stupid_serial_number(c); 1492 1493 /* Set up SMEP/SMAP/UMIP */ 1494 setup_smep(c); 1495 setup_smap(c); 1496 setup_umip(c); 1497 1498 /* 1499 * The vendor-specific functions might have changed features. 1500 * Now we do "generic changes." 1501 */ 1502 1503 /* Filter out anything that depends on CPUID levels we don't have */ 1504 filter_cpuid_features(c, true); 1505 1506 /* If the model name is still unset, do table lookup. */ 1507 if (!c->x86_model_id[0]) { 1508 const char *p; 1509 p = table_lookup_model(c); 1510 if (p) 1511 strcpy(c->x86_model_id, p); 1512 else 1513 /* Last resort... */ 1514 sprintf(c->x86_model_id, "%02x/%02x", 1515 c->x86, c->x86_model); 1516 } 1517 1518 #ifdef CONFIG_X86_64 1519 detect_ht(c); 1520 #endif 1521 1522 x86_init_rdrand(c); 1523 setup_pku(c); 1524 1525 /* 1526 * Clear/Set all flags overridden by options, need do it 1527 * before following smp all cpus cap AND. 1528 */ 1529 apply_forced_caps(c); 1530 1531 /* 1532 * On SMP, boot_cpu_data holds the common feature set between 1533 * all CPUs; so make sure that we indicate which features are 1534 * common between the CPUs. The first time this routine gets 1535 * executed, c == &boot_cpu_data. 1536 */ 1537 if (c != &boot_cpu_data) { 1538 /* AND the already accumulated flags with these */ 1539 for (i = 0; i < NCAPINTS; i++) 1540 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1541 1542 /* OR, i.e. replicate the bug flags */ 1543 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1544 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1545 } 1546 1547 /* Init Machine Check Exception if available. */ 1548 mcheck_cpu_init(c); 1549 1550 select_idle_routine(c); 1551 1552 #ifdef CONFIG_NUMA 1553 numa_add_cpu(smp_processor_id()); 1554 #endif 1555 } 1556 1557 /* 1558 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1559 * on 32-bit kernels: 1560 */ 1561 #ifdef CONFIG_X86_32 1562 void enable_sep_cpu(void) 1563 { 1564 struct tss_struct *tss; 1565 int cpu; 1566 1567 if (!boot_cpu_has(X86_FEATURE_SEP)) 1568 return; 1569 1570 cpu = get_cpu(); 1571 tss = &per_cpu(cpu_tss_rw, cpu); 1572 1573 /* 1574 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1575 * see the big comment in struct x86_hw_tss's definition. 1576 */ 1577 1578 tss->x86_tss.ss1 = __KERNEL_CS; 1579 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1580 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1581 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1582 1583 put_cpu(); 1584 } 1585 #endif 1586 1587 void __init identify_boot_cpu(void) 1588 { 1589 identify_cpu(&boot_cpu_data); 1590 #ifdef CONFIG_X86_32 1591 sysenter_setup(); 1592 enable_sep_cpu(); 1593 #endif 1594 cpu_detect_tlb(&boot_cpu_data); 1595 setup_cr_pinning(); 1596 1597 tsx_init(); 1598 } 1599 1600 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1601 { 1602 BUG_ON(c == &boot_cpu_data); 1603 identify_cpu(c); 1604 #ifdef CONFIG_X86_32 1605 enable_sep_cpu(); 1606 #endif 1607 mtrr_ap_init(); 1608 validate_apic_and_package_id(c); 1609 x86_spec_ctrl_setup_ap(); 1610 update_srbds_msr(); 1611 } 1612 1613 static __init int setup_noclflush(char *arg) 1614 { 1615 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1616 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1617 return 1; 1618 } 1619 __setup("noclflush", setup_noclflush); 1620 1621 void print_cpu_info(struct cpuinfo_x86 *c) 1622 { 1623 const char *vendor = NULL; 1624 1625 if (c->x86_vendor < X86_VENDOR_NUM) { 1626 vendor = this_cpu->c_vendor; 1627 } else { 1628 if (c->cpuid_level >= 0) 1629 vendor = c->x86_vendor_id; 1630 } 1631 1632 if (vendor && !strstr(c->x86_model_id, vendor)) 1633 pr_cont("%s ", vendor); 1634 1635 if (c->x86_model_id[0]) 1636 pr_cont("%s", c->x86_model_id); 1637 else 1638 pr_cont("%d86", c->x86); 1639 1640 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1641 1642 if (c->x86_stepping || c->cpuid_level >= 0) 1643 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1644 else 1645 pr_cont(")\n"); 1646 } 1647 1648 /* 1649 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1650 * But we need to keep a dummy __setup around otherwise it would 1651 * show up as an environment variable for init. 1652 */ 1653 static __init int setup_clearcpuid(char *arg) 1654 { 1655 return 1; 1656 } 1657 __setup("clearcpuid=", setup_clearcpuid); 1658 1659 #ifdef CONFIG_X86_64 1660 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1661 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1662 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1663 1664 /* 1665 * The following percpu variables are hot. Align current_task to 1666 * cacheline size such that they fall in the same cacheline. 1667 */ 1668 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1669 &init_task; 1670 EXPORT_PER_CPU_SYMBOL(current_task); 1671 1672 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1673 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1674 1675 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1676 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1677 1678 /* May not be marked __init: used by software suspend */ 1679 void syscall_init(void) 1680 { 1681 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1682 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1683 1684 #ifdef CONFIG_IA32_EMULATION 1685 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1686 /* 1687 * This only works on Intel CPUs. 1688 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1689 * This does not cause SYSENTER to jump to the wrong location, because 1690 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1691 */ 1692 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1693 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1694 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1695 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1696 #else 1697 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1698 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1699 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1700 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1701 #endif 1702 1703 /* Flags to clear on syscall */ 1704 wrmsrl(MSR_SYSCALL_MASK, 1705 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1706 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1707 } 1708 1709 #else /* CONFIG_X86_64 */ 1710 1711 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1712 EXPORT_PER_CPU_SYMBOL(current_task); 1713 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1714 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1715 1716 /* 1717 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1718 * the top of the kernel stack. Use an extra percpu variable to track the 1719 * top of the kernel stack directly. 1720 */ 1721 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1722 (unsigned long)&init_thread_union + THREAD_SIZE; 1723 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1724 1725 #ifdef CONFIG_STACKPROTECTOR 1726 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1727 #endif 1728 1729 #endif /* CONFIG_X86_64 */ 1730 1731 /* 1732 * Clear all 6 debug registers: 1733 */ 1734 static void clear_all_debug_regs(void) 1735 { 1736 int i; 1737 1738 for (i = 0; i < 8; i++) { 1739 /* Ignore db4, db5 */ 1740 if ((i == 4) || (i == 5)) 1741 continue; 1742 1743 set_debugreg(0, i); 1744 } 1745 } 1746 1747 #ifdef CONFIG_KGDB 1748 /* 1749 * Restore debug regs if using kgdbwait and you have a kernel debugger 1750 * connection established. 1751 */ 1752 static void dbg_restore_debug_regs(void) 1753 { 1754 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1755 arch_kgdb_ops.correct_hw_break(); 1756 } 1757 #else /* ! CONFIG_KGDB */ 1758 #define dbg_restore_debug_regs() 1759 #endif /* ! CONFIG_KGDB */ 1760 1761 static void wait_for_master_cpu(int cpu) 1762 { 1763 #ifdef CONFIG_SMP 1764 /* 1765 * wait for ACK from master CPU before continuing 1766 * with AP initialization 1767 */ 1768 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1769 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1770 cpu_relax(); 1771 #endif 1772 } 1773 1774 #ifdef CONFIG_X86_64 1775 static inline void setup_getcpu(int cpu) 1776 { 1777 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1778 struct desc_struct d = { }; 1779 1780 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1781 write_rdtscp_aux(cpudata); 1782 1783 /* Store CPU and node number in limit. */ 1784 d.limit0 = cpudata; 1785 d.limit1 = cpudata >> 16; 1786 1787 d.type = 5; /* RO data, expand down, accessed */ 1788 d.dpl = 3; /* Visible to user code */ 1789 d.s = 1; /* Not a system segment */ 1790 d.p = 1; /* Present */ 1791 d.d = 1; /* 32-bit */ 1792 1793 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1794 } 1795 1796 static inline void ucode_cpu_init(int cpu) 1797 { 1798 if (cpu) 1799 load_ucode_ap(); 1800 } 1801 1802 static inline void tss_setup_ist(struct tss_struct *tss) 1803 { 1804 /* Set up the per-CPU TSS IST stacks */ 1805 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1806 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1807 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1808 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1809 } 1810 1811 #else /* CONFIG_X86_64 */ 1812 1813 static inline void setup_getcpu(int cpu) { } 1814 1815 static inline void ucode_cpu_init(int cpu) 1816 { 1817 show_ucode_info_early(); 1818 } 1819 1820 static inline void tss_setup_ist(struct tss_struct *tss) { } 1821 1822 #endif /* !CONFIG_X86_64 */ 1823 1824 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 1825 { 1826 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 1827 1828 #ifdef CONFIG_X86_IOPL_IOPERM 1829 tss->io_bitmap.prev_max = 0; 1830 tss->io_bitmap.prev_sequence = 0; 1831 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 1832 /* 1833 * Invalidate the extra array entry past the end of the all 1834 * permission bitmap as required by the hardware. 1835 */ 1836 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 1837 #endif 1838 } 1839 1840 /* 1841 * cpu_init() initializes state that is per-CPU. Some data is already 1842 * initialized (naturally) in the bootstrap process, such as the GDT 1843 * and IDT. We reload them nevertheless, this function acts as a 1844 * 'CPU state barrier', nothing should get across. 1845 */ 1846 void cpu_init(void) 1847 { 1848 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1849 struct task_struct *cur = current; 1850 int cpu = raw_smp_processor_id(); 1851 1852 wait_for_master_cpu(cpu); 1853 1854 ucode_cpu_init(cpu); 1855 1856 #ifdef CONFIG_NUMA 1857 if (this_cpu_read(numa_node) == 0 && 1858 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1859 set_numa_node(early_cpu_to_node(cpu)); 1860 #endif 1861 setup_getcpu(cpu); 1862 1863 pr_debug("Initializing CPU#%d\n", cpu); 1864 1865 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 1866 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 1867 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1868 1869 /* 1870 * Initialize the per-CPU GDT with the boot GDT, 1871 * and set up the GDT descriptor: 1872 */ 1873 switch_to_new_gdt(cpu); 1874 load_current_idt(); 1875 1876 if (IS_ENABLED(CONFIG_X86_64)) { 1877 loadsegment(fs, 0); 1878 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1879 syscall_init(); 1880 1881 wrmsrl(MSR_FS_BASE, 0); 1882 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1883 barrier(); 1884 1885 x2apic_setup(); 1886 } 1887 1888 mmgrab(&init_mm); 1889 cur->active_mm = &init_mm; 1890 BUG_ON(cur->mm); 1891 initialize_tlbstate_and_flush(); 1892 enter_lazy_tlb(&init_mm, cur); 1893 1894 /* Initialize the TSS. */ 1895 tss_setup_ist(tss); 1896 tss_setup_io_bitmap(tss); 1897 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1898 1899 load_TR_desc(); 1900 /* 1901 * sp0 points to the entry trampoline stack regardless of what task 1902 * is running. 1903 */ 1904 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1905 1906 load_mm_ldt(&init_mm); 1907 1908 clear_all_debug_regs(); 1909 dbg_restore_debug_regs(); 1910 1911 doublefault_init_cpu_tss(); 1912 1913 fpu__init_cpu(); 1914 1915 if (is_uv_system()) 1916 uv_cpu_init(); 1917 1918 load_fixmap_gdt(cpu); 1919 } 1920 1921 /* 1922 * The microcode loader calls this upon late microcode load to recheck features, 1923 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1924 * hotplug lock. 1925 */ 1926 void microcode_check(void) 1927 { 1928 struct cpuinfo_x86 info; 1929 1930 perf_check_microcode(); 1931 1932 /* Reload CPUID max function as it might've changed. */ 1933 info.cpuid_level = cpuid_eax(0); 1934 1935 /* 1936 * Copy all capability leafs to pick up the synthetic ones so that 1937 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1938 * get overwritten in get_cpu_cap(). 1939 */ 1940 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1941 1942 get_cpu_cap(&info); 1943 1944 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1945 return; 1946 1947 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1948 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1949 } 1950 1951 /* 1952 * Invoked from core CPU hotplug code after hotplug operations 1953 */ 1954 void arch_smt_update(void) 1955 { 1956 /* Handle the speculative execution misfeatures */ 1957 cpu_bugs_smt_update(); 1958 /* Check whether IPI broadcasting can be enabled */ 1959 apic_smt_update(); 1960 } 1961