1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_event.h> 17 #include <asm/mmu_context.h> 18 #include <asm/archrandom.h> 19 #include <asm/hypervisor.h> 20 #include <asm/processor.h> 21 #include <asm/debugreg.h> 22 #include <asm/sections.h> 23 #include <linux/topology.h> 24 #include <linux/cpumask.h> 25 #include <asm/pgtable.h> 26 #include <linux/atomic.h> 27 #include <asm/proto.h> 28 #include <asm/setup.h> 29 #include <asm/apic.h> 30 #include <asm/desc.h> 31 #include <asm/i387.h> 32 #include <asm/fpu-internal.h> 33 #include <asm/mtrr.h> 34 #include <linux/numa.h> 35 #include <asm/asm.h> 36 #include <asm/cpu.h> 37 #include <asm/mce.h> 38 #include <asm/msr.h> 39 #include <asm/pat.h> 40 #include <asm/microcode.h> 41 #include <asm/microcode_intel.h> 42 43 #ifdef CONFIG_X86_LOCAL_APIC 44 #include <asm/uv/uv.h> 45 #endif 46 47 #include "cpu.h" 48 49 /* all of these masks are initialized in setup_cpu_local_masks() */ 50 cpumask_var_t cpu_initialized_mask; 51 cpumask_var_t cpu_callout_mask; 52 cpumask_var_t cpu_callin_mask; 53 54 /* representing cpus for which sibling maps can be computed */ 55 cpumask_var_t cpu_sibling_setup_mask; 56 57 /* correctly size the local cpu masks */ 58 void __init setup_cpu_local_masks(void) 59 { 60 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 61 alloc_bootmem_cpumask_var(&cpu_callin_mask); 62 alloc_bootmem_cpumask_var(&cpu_callout_mask); 63 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 64 } 65 66 static void default_init(struct cpuinfo_x86 *c) 67 { 68 #ifdef CONFIG_X86_64 69 cpu_detect_cache_sizes(c); 70 #else 71 /* Not much we can do here... */ 72 /* Check if at least it has cpuid */ 73 if (c->cpuid_level == -1) { 74 /* No cpuid. It must be an ancient CPU */ 75 if (c->x86 == 4) 76 strcpy(c->x86_model_id, "486"); 77 else if (c->x86 == 3) 78 strcpy(c->x86_model_id, "386"); 79 } 80 #endif 81 } 82 83 static const struct cpu_dev default_cpu = { 84 .c_init = default_init, 85 .c_vendor = "Unknown", 86 .c_x86_vendor = X86_VENDOR_UNKNOWN, 87 }; 88 89 static const struct cpu_dev *this_cpu = &default_cpu; 90 91 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 92 #ifdef CONFIG_X86_64 93 /* 94 * We need valid kernel segments for data and code in long mode too 95 * IRET will check the segment types kkeil 2000/10/28 96 * Also sysret mandates a special GDT layout 97 * 98 * TLS descriptors are currently at a different place compared to i386. 99 * Hopefully nobody expects them at a fixed place (Wine?) 100 */ 101 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 102 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 103 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 104 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 105 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 107 #else 108 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 109 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 111 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 112 /* 113 * Segments used for calling PnP BIOS have byte granularity. 114 * They code segments and data segments have fixed 64k limits, 115 * the transfer segment sizes are set at run time. 116 */ 117 /* 32-bit code */ 118 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 119 /* 16-bit code */ 120 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 121 /* 16-bit data */ 122 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 123 /* 16-bit data */ 124 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 125 /* 16-bit data */ 126 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 127 /* 128 * The APM segments have byte granularity and their bases 129 * are set at run time. All have 64k limits. 130 */ 131 /* 32-bit code */ 132 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 133 /* 16-bit code */ 134 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 135 /* data */ 136 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 137 138 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 139 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 140 GDT_STACK_CANARY_INIT 141 #endif 142 } }; 143 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 144 145 static int __init x86_xsave_setup(char *s) 146 { 147 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 148 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 149 setup_clear_cpu_cap(X86_FEATURE_AVX); 150 setup_clear_cpu_cap(X86_FEATURE_AVX2); 151 return 1; 152 } 153 __setup("noxsave", x86_xsave_setup); 154 155 static int __init x86_xsaveopt_setup(char *s) 156 { 157 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 158 return 1; 159 } 160 __setup("noxsaveopt", x86_xsaveopt_setup); 161 162 #ifdef CONFIG_X86_32 163 static int cachesize_override = -1; 164 static int disable_x86_serial_nr = 1; 165 166 static int __init cachesize_setup(char *str) 167 { 168 get_option(&str, &cachesize_override); 169 return 1; 170 } 171 __setup("cachesize=", cachesize_setup); 172 173 static int __init x86_fxsr_setup(char *s) 174 { 175 setup_clear_cpu_cap(X86_FEATURE_FXSR); 176 setup_clear_cpu_cap(X86_FEATURE_XMM); 177 return 1; 178 } 179 __setup("nofxsr", x86_fxsr_setup); 180 181 static int __init x86_sep_setup(char *s) 182 { 183 setup_clear_cpu_cap(X86_FEATURE_SEP); 184 return 1; 185 } 186 __setup("nosep", x86_sep_setup); 187 188 /* Standard macro to see if a specific flag is changeable */ 189 static inline int flag_is_changeable_p(u32 flag) 190 { 191 u32 f1, f2; 192 193 /* 194 * Cyrix and IDT cpus allow disabling of CPUID 195 * so the code below may return different results 196 * when it is executed before and after enabling 197 * the CPUID. Add "volatile" to not allow gcc to 198 * optimize the subsequent calls to this function. 199 */ 200 asm volatile ("pushfl \n\t" 201 "pushfl \n\t" 202 "popl %0 \n\t" 203 "movl %0, %1 \n\t" 204 "xorl %2, %0 \n\t" 205 "pushl %0 \n\t" 206 "popfl \n\t" 207 "pushfl \n\t" 208 "popl %0 \n\t" 209 "popfl \n\t" 210 211 : "=&r" (f1), "=&r" (f2) 212 : "ir" (flag)); 213 214 return ((f1^f2) & flag) != 0; 215 } 216 217 /* Probe for the CPUID instruction */ 218 int have_cpuid_p(void) 219 { 220 return flag_is_changeable_p(X86_EFLAGS_ID); 221 } 222 223 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 224 { 225 unsigned long lo, hi; 226 227 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 228 return; 229 230 /* Disable processor serial number: */ 231 232 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 233 lo |= 0x200000; 234 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 235 236 printk(KERN_NOTICE "CPU serial number disabled.\n"); 237 clear_cpu_cap(c, X86_FEATURE_PN); 238 239 /* Disabling the serial number may affect the cpuid level */ 240 c->cpuid_level = cpuid_eax(0); 241 } 242 243 static int __init x86_serial_nr_setup(char *s) 244 { 245 disable_x86_serial_nr = 0; 246 return 1; 247 } 248 __setup("serialnumber", x86_serial_nr_setup); 249 #else 250 static inline int flag_is_changeable_p(u32 flag) 251 { 252 return 1; 253 } 254 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 255 { 256 } 257 #endif 258 259 static __init int setup_disable_smep(char *arg) 260 { 261 setup_clear_cpu_cap(X86_FEATURE_SMEP); 262 return 1; 263 } 264 __setup("nosmep", setup_disable_smep); 265 266 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 267 { 268 if (cpu_has(c, X86_FEATURE_SMEP)) 269 set_in_cr4(X86_CR4_SMEP); 270 } 271 272 static __init int setup_disable_smap(char *arg) 273 { 274 setup_clear_cpu_cap(X86_FEATURE_SMAP); 275 return 1; 276 } 277 __setup("nosmap", setup_disable_smap); 278 279 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 280 { 281 unsigned long eflags; 282 283 /* This should have been cleared long ago */ 284 raw_local_save_flags(eflags); 285 BUG_ON(eflags & X86_EFLAGS_AC); 286 287 if (cpu_has(c, X86_FEATURE_SMAP)) 288 set_in_cr4(X86_CR4_SMAP); 289 } 290 291 /* 292 * Some CPU features depend on higher CPUID levels, which may not always 293 * be available due to CPUID level capping or broken virtualization 294 * software. Add those features to this table to auto-disable them. 295 */ 296 struct cpuid_dependent_feature { 297 u32 feature; 298 u32 level; 299 }; 300 301 static const struct cpuid_dependent_feature 302 cpuid_dependent_features[] = { 303 { X86_FEATURE_MWAIT, 0x00000005 }, 304 { X86_FEATURE_DCA, 0x00000009 }, 305 { X86_FEATURE_XSAVE, 0x0000000d }, 306 { 0, 0 } 307 }; 308 309 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 310 { 311 const struct cpuid_dependent_feature *df; 312 313 for (df = cpuid_dependent_features; df->feature; df++) { 314 315 if (!cpu_has(c, df->feature)) 316 continue; 317 /* 318 * Note: cpuid_level is set to -1 if unavailable, but 319 * extended_extended_level is set to 0 if unavailable 320 * and the legitimate extended levels are all negative 321 * when signed; hence the weird messing around with 322 * signs here... 323 */ 324 if (!((s32)df->level < 0 ? 325 (u32)df->level > (u32)c->extended_cpuid_level : 326 (s32)df->level > (s32)c->cpuid_level)) 327 continue; 328 329 clear_cpu_cap(c, df->feature); 330 if (!warn) 331 continue; 332 333 printk(KERN_WARNING 334 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 335 x86_cap_flags[df->feature], df->level); 336 } 337 } 338 339 /* 340 * Naming convention should be: <Name> [(<Codename>)] 341 * This table only is used unless init_<vendor>() below doesn't set it; 342 * in particular, if CPUID levels 0x80000002..4 are supported, this 343 * isn't used 344 */ 345 346 /* Look up CPU names by table lookup. */ 347 static const char *table_lookup_model(struct cpuinfo_x86 *c) 348 { 349 #ifdef CONFIG_X86_32 350 const struct legacy_cpu_model_info *info; 351 352 if (c->x86_model >= 16) 353 return NULL; /* Range check */ 354 355 if (!this_cpu) 356 return NULL; 357 358 info = this_cpu->legacy_models; 359 360 while (info->family) { 361 if (info->family == c->x86) 362 return info->model_names[c->x86_model]; 363 info++; 364 } 365 #endif 366 return NULL; /* Not found */ 367 } 368 369 __u32 cpu_caps_cleared[NCAPINTS]; 370 __u32 cpu_caps_set[NCAPINTS]; 371 372 void load_percpu_segment(int cpu) 373 { 374 #ifdef CONFIG_X86_32 375 loadsegment(fs, __KERNEL_PERCPU); 376 #else 377 loadsegment(gs, 0); 378 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 379 #endif 380 load_stack_canary_segment(); 381 } 382 383 /* 384 * Current gdt points %fs at the "master" per-cpu area: after this, 385 * it's on the real one. 386 */ 387 void switch_to_new_gdt(int cpu) 388 { 389 struct desc_ptr gdt_descr; 390 391 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 392 gdt_descr.size = GDT_SIZE - 1; 393 load_gdt(&gdt_descr); 394 /* Reload the per-cpu base */ 395 396 load_percpu_segment(cpu); 397 } 398 399 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 400 401 static void get_model_name(struct cpuinfo_x86 *c) 402 { 403 unsigned int *v; 404 char *p, *q; 405 406 if (c->extended_cpuid_level < 0x80000004) 407 return; 408 409 v = (unsigned int *)c->x86_model_id; 410 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 411 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 412 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 413 c->x86_model_id[48] = 0; 414 415 /* 416 * Intel chips right-justify this string for some dumb reason; 417 * undo that brain damage: 418 */ 419 p = q = &c->x86_model_id[0]; 420 while (*p == ' ') 421 p++; 422 if (p != q) { 423 while (*p) 424 *q++ = *p++; 425 while (q <= &c->x86_model_id[48]) 426 *q++ = '\0'; /* Zero-pad the rest */ 427 } 428 } 429 430 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 431 { 432 unsigned int n, dummy, ebx, ecx, edx, l2size; 433 434 n = c->extended_cpuid_level; 435 436 if (n >= 0x80000005) { 437 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 438 c->x86_cache_size = (ecx>>24) + (edx>>24); 439 #ifdef CONFIG_X86_64 440 /* On K8 L1 TLB is inclusive, so don't count it */ 441 c->x86_tlbsize = 0; 442 #endif 443 } 444 445 if (n < 0x80000006) /* Some chips just has a large L1. */ 446 return; 447 448 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 449 l2size = ecx >> 16; 450 451 #ifdef CONFIG_X86_64 452 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 453 #else 454 /* do processor-specific cache resizing */ 455 if (this_cpu->legacy_cache_size) 456 l2size = this_cpu->legacy_cache_size(c, l2size); 457 458 /* Allow user to override all this if necessary. */ 459 if (cachesize_override != -1) 460 l2size = cachesize_override; 461 462 if (l2size == 0) 463 return; /* Again, no L2 cache is possible */ 464 #endif 465 466 c->x86_cache_size = l2size; 467 } 468 469 u16 __read_mostly tlb_lli_4k[NR_INFO]; 470 u16 __read_mostly tlb_lli_2m[NR_INFO]; 471 u16 __read_mostly tlb_lli_4m[NR_INFO]; 472 u16 __read_mostly tlb_lld_4k[NR_INFO]; 473 u16 __read_mostly tlb_lld_2m[NR_INFO]; 474 u16 __read_mostly tlb_lld_4m[NR_INFO]; 475 476 /* 477 * tlb_flushall_shift shows the balance point in replacing cr3 write 478 * with multiple 'invlpg'. It will do this replacement when 479 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. 480 * If tlb_flushall_shift is -1, means the replacement will be disabled. 481 */ 482 s8 __read_mostly tlb_flushall_shift = -1; 483 484 void cpu_detect_tlb(struct cpuinfo_x86 *c) 485 { 486 if (this_cpu->c_detect_tlb) 487 this_cpu->c_detect_tlb(c); 488 489 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 490 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 491 "tlb_flushall_shift: %d\n", 492 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 493 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], 494 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], 495 tlb_flushall_shift); 496 } 497 498 void detect_ht(struct cpuinfo_x86 *c) 499 { 500 #ifdef CONFIG_X86_HT 501 u32 eax, ebx, ecx, edx; 502 int index_msb, core_bits; 503 static bool printed; 504 505 if (!cpu_has(c, X86_FEATURE_HT)) 506 return; 507 508 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 509 goto out; 510 511 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 512 return; 513 514 cpuid(1, &eax, &ebx, &ecx, &edx); 515 516 smp_num_siblings = (ebx & 0xff0000) >> 16; 517 518 if (smp_num_siblings == 1) { 519 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 520 goto out; 521 } 522 523 if (smp_num_siblings <= 1) 524 goto out; 525 526 index_msb = get_count_order(smp_num_siblings); 527 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 528 529 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 530 531 index_msb = get_count_order(smp_num_siblings); 532 533 core_bits = get_count_order(c->x86_max_cores); 534 535 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 536 ((1 << core_bits) - 1); 537 538 out: 539 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 540 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 541 c->phys_proc_id); 542 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 543 c->cpu_core_id); 544 printed = 1; 545 } 546 #endif 547 } 548 549 static void get_cpu_vendor(struct cpuinfo_x86 *c) 550 { 551 char *v = c->x86_vendor_id; 552 int i; 553 554 for (i = 0; i < X86_VENDOR_NUM; i++) { 555 if (!cpu_devs[i]) 556 break; 557 558 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 559 (cpu_devs[i]->c_ident[1] && 560 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 561 562 this_cpu = cpu_devs[i]; 563 c->x86_vendor = this_cpu->c_x86_vendor; 564 return; 565 } 566 } 567 568 printk_once(KERN_ERR 569 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 570 "CPU: Your system may be unstable.\n", v); 571 572 c->x86_vendor = X86_VENDOR_UNKNOWN; 573 this_cpu = &default_cpu; 574 } 575 576 void cpu_detect(struct cpuinfo_x86 *c) 577 { 578 /* Get vendor name */ 579 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 580 (unsigned int *)&c->x86_vendor_id[0], 581 (unsigned int *)&c->x86_vendor_id[8], 582 (unsigned int *)&c->x86_vendor_id[4]); 583 584 c->x86 = 4; 585 /* Intel-defined flags: level 0x00000001 */ 586 if (c->cpuid_level >= 0x00000001) { 587 u32 junk, tfms, cap0, misc; 588 589 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 590 c->x86 = (tfms >> 8) & 0xf; 591 c->x86_model = (tfms >> 4) & 0xf; 592 c->x86_mask = tfms & 0xf; 593 594 if (c->x86 == 0xf) 595 c->x86 += (tfms >> 20) & 0xff; 596 if (c->x86 >= 0x6) 597 c->x86_model += ((tfms >> 16) & 0xf) << 4; 598 599 if (cap0 & (1<<19)) { 600 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 601 c->x86_cache_alignment = c->x86_clflush_size; 602 } 603 } 604 } 605 606 void get_cpu_cap(struct cpuinfo_x86 *c) 607 { 608 u32 tfms, xlvl; 609 u32 ebx; 610 611 /* Intel-defined flags: level 0x00000001 */ 612 if (c->cpuid_level >= 0x00000001) { 613 u32 capability, excap; 614 615 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 616 c->x86_capability[0] = capability; 617 c->x86_capability[4] = excap; 618 } 619 620 /* Additional Intel-defined flags: level 0x00000007 */ 621 if (c->cpuid_level >= 0x00000007) { 622 u32 eax, ebx, ecx, edx; 623 624 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 625 626 c->x86_capability[9] = ebx; 627 } 628 629 /* AMD-defined flags: level 0x80000001 */ 630 xlvl = cpuid_eax(0x80000000); 631 c->extended_cpuid_level = xlvl; 632 633 if ((xlvl & 0xffff0000) == 0x80000000) { 634 if (xlvl >= 0x80000001) { 635 c->x86_capability[1] = cpuid_edx(0x80000001); 636 c->x86_capability[6] = cpuid_ecx(0x80000001); 637 } 638 } 639 640 if (c->extended_cpuid_level >= 0x80000008) { 641 u32 eax = cpuid_eax(0x80000008); 642 643 c->x86_virt_bits = (eax >> 8) & 0xff; 644 c->x86_phys_bits = eax & 0xff; 645 } 646 #ifdef CONFIG_X86_32 647 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 648 c->x86_phys_bits = 36; 649 #endif 650 651 if (c->extended_cpuid_level >= 0x80000007) 652 c->x86_power = cpuid_edx(0x80000007); 653 654 init_scattered_cpuid_features(c); 655 } 656 657 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 658 { 659 #ifdef CONFIG_X86_32 660 int i; 661 662 /* 663 * First of all, decide if this is a 486 or higher 664 * It's a 486 if we can modify the AC flag 665 */ 666 if (flag_is_changeable_p(X86_EFLAGS_AC)) 667 c->x86 = 4; 668 else 669 c->x86 = 3; 670 671 for (i = 0; i < X86_VENDOR_NUM; i++) 672 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 673 c->x86_vendor_id[0] = 0; 674 cpu_devs[i]->c_identify(c); 675 if (c->x86_vendor_id[0]) { 676 get_cpu_vendor(c); 677 break; 678 } 679 } 680 #endif 681 } 682 683 /* 684 * Do minimum CPU detection early. 685 * Fields really needed: vendor, cpuid_level, family, model, mask, 686 * cache alignment. 687 * The others are not touched to avoid unwanted side effects. 688 * 689 * WARNING: this function is only called on the BP. Don't add code here 690 * that is supposed to run on all CPUs. 691 */ 692 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 693 { 694 #ifdef CONFIG_X86_64 695 c->x86_clflush_size = 64; 696 c->x86_phys_bits = 36; 697 c->x86_virt_bits = 48; 698 #else 699 c->x86_clflush_size = 32; 700 c->x86_phys_bits = 32; 701 c->x86_virt_bits = 32; 702 #endif 703 c->x86_cache_alignment = c->x86_clflush_size; 704 705 memset(&c->x86_capability, 0, sizeof c->x86_capability); 706 c->extended_cpuid_level = 0; 707 708 if (!have_cpuid_p()) 709 identify_cpu_without_cpuid(c); 710 711 /* cyrix could have cpuid enabled via c_identify()*/ 712 if (!have_cpuid_p()) 713 return; 714 715 cpu_detect(c); 716 get_cpu_vendor(c); 717 get_cpu_cap(c); 718 fpu_detect(c); 719 720 if (this_cpu->c_early_init) 721 this_cpu->c_early_init(c); 722 723 c->cpu_index = 0; 724 filter_cpuid_features(c, false); 725 726 if (this_cpu->c_bsp_init) 727 this_cpu->c_bsp_init(c); 728 729 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 730 } 731 732 void __init early_cpu_init(void) 733 { 734 const struct cpu_dev *const *cdev; 735 int count = 0; 736 737 #ifdef CONFIG_PROCESSOR_SELECT 738 printk(KERN_INFO "KERNEL supported cpus:\n"); 739 #endif 740 741 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 742 const struct cpu_dev *cpudev = *cdev; 743 744 if (count >= X86_VENDOR_NUM) 745 break; 746 cpu_devs[count] = cpudev; 747 count++; 748 749 #ifdef CONFIG_PROCESSOR_SELECT 750 { 751 unsigned int j; 752 753 for (j = 0; j < 2; j++) { 754 if (!cpudev->c_ident[j]) 755 continue; 756 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 757 cpudev->c_ident[j]); 758 } 759 } 760 #endif 761 } 762 early_identify_cpu(&boot_cpu_data); 763 } 764 765 /* 766 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 767 * unfortunately, that's not true in practice because of early VIA 768 * chips and (more importantly) broken virtualizers that are not easy 769 * to detect. In the latter case it doesn't even *fail* reliably, so 770 * probing for it doesn't even work. Disable it completely on 32-bit 771 * unless we can find a reliable way to detect all the broken cases. 772 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 773 */ 774 static void detect_nopl(struct cpuinfo_x86 *c) 775 { 776 #ifdef CONFIG_X86_32 777 clear_cpu_cap(c, X86_FEATURE_NOPL); 778 #else 779 set_cpu_cap(c, X86_FEATURE_NOPL); 780 #endif 781 } 782 783 static void generic_identify(struct cpuinfo_x86 *c) 784 { 785 c->extended_cpuid_level = 0; 786 787 if (!have_cpuid_p()) 788 identify_cpu_without_cpuid(c); 789 790 /* cyrix could have cpuid enabled via c_identify()*/ 791 if (!have_cpuid_p()) 792 return; 793 794 cpu_detect(c); 795 796 get_cpu_vendor(c); 797 798 get_cpu_cap(c); 799 800 if (c->cpuid_level >= 0x00000001) { 801 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 802 #ifdef CONFIG_X86_32 803 # ifdef CONFIG_X86_HT 804 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 805 # else 806 c->apicid = c->initial_apicid; 807 # endif 808 #endif 809 c->phys_proc_id = c->initial_apicid; 810 } 811 812 get_model_name(c); /* Default name */ 813 814 detect_nopl(c); 815 } 816 817 /* 818 * This does the hard work of actually picking apart the CPU stuff... 819 */ 820 static void identify_cpu(struct cpuinfo_x86 *c) 821 { 822 int i; 823 824 c->loops_per_jiffy = loops_per_jiffy; 825 c->x86_cache_size = -1; 826 c->x86_vendor = X86_VENDOR_UNKNOWN; 827 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 828 c->x86_vendor_id[0] = '\0'; /* Unset */ 829 c->x86_model_id[0] = '\0'; /* Unset */ 830 c->x86_max_cores = 1; 831 c->x86_coreid_bits = 0; 832 #ifdef CONFIG_X86_64 833 c->x86_clflush_size = 64; 834 c->x86_phys_bits = 36; 835 c->x86_virt_bits = 48; 836 #else 837 c->cpuid_level = -1; /* CPUID not detected */ 838 c->x86_clflush_size = 32; 839 c->x86_phys_bits = 32; 840 c->x86_virt_bits = 32; 841 #endif 842 c->x86_cache_alignment = c->x86_clflush_size; 843 memset(&c->x86_capability, 0, sizeof c->x86_capability); 844 845 generic_identify(c); 846 847 if (this_cpu->c_identify) 848 this_cpu->c_identify(c); 849 850 /* Clear/Set all flags overriden by options, after probe */ 851 for (i = 0; i < NCAPINTS; i++) { 852 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 853 c->x86_capability[i] |= cpu_caps_set[i]; 854 } 855 856 #ifdef CONFIG_X86_64 857 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 858 #endif 859 860 /* 861 * Vendor-specific initialization. In this section we 862 * canonicalize the feature flags, meaning if there are 863 * features a certain CPU supports which CPUID doesn't 864 * tell us, CPUID claiming incorrect flags, or other bugs, 865 * we handle them here. 866 * 867 * At the end of this section, c->x86_capability better 868 * indicate the features this CPU genuinely supports! 869 */ 870 if (this_cpu->c_init) 871 this_cpu->c_init(c); 872 873 /* Disable the PN if appropriate */ 874 squash_the_stupid_serial_number(c); 875 876 /* Set up SMEP/SMAP */ 877 setup_smep(c); 878 setup_smap(c); 879 880 /* 881 * The vendor-specific functions might have changed features. 882 * Now we do "generic changes." 883 */ 884 885 /* Filter out anything that depends on CPUID levels we don't have */ 886 filter_cpuid_features(c, true); 887 888 /* If the model name is still unset, do table lookup. */ 889 if (!c->x86_model_id[0]) { 890 const char *p; 891 p = table_lookup_model(c); 892 if (p) 893 strcpy(c->x86_model_id, p); 894 else 895 /* Last resort... */ 896 sprintf(c->x86_model_id, "%02x/%02x", 897 c->x86, c->x86_model); 898 } 899 900 #ifdef CONFIG_X86_64 901 detect_ht(c); 902 #endif 903 904 init_hypervisor(c); 905 x86_init_rdrand(c); 906 907 /* 908 * Clear/Set all flags overriden by options, need do it 909 * before following smp all cpus cap AND. 910 */ 911 for (i = 0; i < NCAPINTS; i++) { 912 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 913 c->x86_capability[i] |= cpu_caps_set[i]; 914 } 915 916 /* 917 * On SMP, boot_cpu_data holds the common feature set between 918 * all CPUs; so make sure that we indicate which features are 919 * common between the CPUs. The first time this routine gets 920 * executed, c == &boot_cpu_data. 921 */ 922 if (c != &boot_cpu_data) { 923 /* AND the already accumulated flags with these */ 924 for (i = 0; i < NCAPINTS; i++) 925 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 926 927 /* OR, i.e. replicate the bug flags */ 928 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 929 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 930 } 931 932 /* Init Machine Check Exception if available. */ 933 mcheck_cpu_init(c); 934 935 select_idle_routine(c); 936 937 #ifdef CONFIG_NUMA 938 numa_add_cpu(smp_processor_id()); 939 #endif 940 } 941 942 #ifdef CONFIG_X86_64 943 static void vgetcpu_set_mode(void) 944 { 945 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 946 vgetcpu_mode = VGETCPU_RDTSCP; 947 else 948 vgetcpu_mode = VGETCPU_LSL; 949 } 950 #endif 951 952 void __init identify_boot_cpu(void) 953 { 954 identify_cpu(&boot_cpu_data); 955 init_amd_e400_c1e_mask(); 956 #ifdef CONFIG_X86_32 957 sysenter_setup(); 958 enable_sep_cpu(); 959 #else 960 vgetcpu_set_mode(); 961 #endif 962 cpu_detect_tlb(&boot_cpu_data); 963 } 964 965 void identify_secondary_cpu(struct cpuinfo_x86 *c) 966 { 967 BUG_ON(c == &boot_cpu_data); 968 identify_cpu(c); 969 #ifdef CONFIG_X86_32 970 enable_sep_cpu(); 971 #endif 972 mtrr_ap_init(); 973 } 974 975 struct msr_range { 976 unsigned min; 977 unsigned max; 978 }; 979 980 static const struct msr_range msr_range_array[] = { 981 { 0x00000000, 0x00000418}, 982 { 0xc0000000, 0xc000040b}, 983 { 0xc0010000, 0xc0010142}, 984 { 0xc0011000, 0xc001103b}, 985 }; 986 987 static void __print_cpu_msr(void) 988 { 989 unsigned index_min, index_max; 990 unsigned index; 991 u64 val; 992 int i; 993 994 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 995 index_min = msr_range_array[i].min; 996 index_max = msr_range_array[i].max; 997 998 for (index = index_min; index < index_max; index++) { 999 if (rdmsrl_safe(index, &val)) 1000 continue; 1001 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 1002 } 1003 } 1004 } 1005 1006 static int show_msr; 1007 1008 static __init int setup_show_msr(char *arg) 1009 { 1010 int num; 1011 1012 get_option(&arg, &num); 1013 1014 if (num > 0) 1015 show_msr = num; 1016 return 1; 1017 } 1018 __setup("show_msr=", setup_show_msr); 1019 1020 static __init int setup_noclflush(char *arg) 1021 { 1022 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 1023 return 1; 1024 } 1025 __setup("noclflush", setup_noclflush); 1026 1027 void print_cpu_info(struct cpuinfo_x86 *c) 1028 { 1029 const char *vendor = NULL; 1030 1031 if (c->x86_vendor < X86_VENDOR_NUM) { 1032 vendor = this_cpu->c_vendor; 1033 } else { 1034 if (c->cpuid_level >= 0) 1035 vendor = c->x86_vendor_id; 1036 } 1037 1038 if (vendor && !strstr(c->x86_model_id, vendor)) 1039 printk(KERN_CONT "%s ", vendor); 1040 1041 if (c->x86_model_id[0]) 1042 printk(KERN_CONT "%s", strim(c->x86_model_id)); 1043 else 1044 printk(KERN_CONT "%d86", c->x86); 1045 1046 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); 1047 1048 if (c->x86_mask || c->cpuid_level >= 0) 1049 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); 1050 else 1051 printk(KERN_CONT ")\n"); 1052 1053 print_cpu_msr(c); 1054 } 1055 1056 void print_cpu_msr(struct cpuinfo_x86 *c) 1057 { 1058 if (c->cpu_index < show_msr) 1059 __print_cpu_msr(); 1060 } 1061 1062 static __init int setup_disablecpuid(char *arg) 1063 { 1064 int bit; 1065 1066 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1067 setup_clear_cpu_cap(bit); 1068 else 1069 return 0; 1070 1071 return 1; 1072 } 1073 __setup("clearcpuid=", setup_disablecpuid); 1074 1075 #ifdef CONFIG_X86_64 1076 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1077 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1078 (unsigned long) debug_idt_table }; 1079 1080 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1081 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1082 1083 /* 1084 * The following four percpu variables are hot. Align current_task to 1085 * cacheline size such that all four fall in the same cacheline. 1086 */ 1087 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1088 &init_task; 1089 EXPORT_PER_CPU_SYMBOL(current_task); 1090 1091 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1092 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1093 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1094 1095 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1096 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1097 1098 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1099 1100 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1101 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1102 1103 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1104 1105 /* 1106 * Special IST stacks which the CPU switches to when it calls 1107 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1108 * limit), all of them are 4K, except the debug stack which 1109 * is 8K. 1110 */ 1111 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1112 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1113 [DEBUG_STACK - 1] = DEBUG_STKSZ 1114 }; 1115 1116 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1117 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1118 1119 /* May not be marked __init: used by software suspend */ 1120 void syscall_init(void) 1121 { 1122 /* 1123 * LSTAR and STAR live in a bit strange symbiosis. 1124 * They both write to the same internal register. STAR allows to 1125 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1126 */ 1127 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1128 wrmsrl(MSR_LSTAR, system_call); 1129 wrmsrl(MSR_CSTAR, ignore_sysret); 1130 1131 #ifdef CONFIG_IA32_EMULATION 1132 syscall32_cpu_init(); 1133 #endif 1134 1135 /* Flags to clear on syscall */ 1136 wrmsrl(MSR_SYSCALL_MASK, 1137 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1138 X86_EFLAGS_IOPL|X86_EFLAGS_AC); 1139 } 1140 1141 /* 1142 * Copies of the original ist values from the tss are only accessed during 1143 * debugging, no special alignment required. 1144 */ 1145 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1146 1147 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1148 DEFINE_PER_CPU(int, debug_stack_usage); 1149 1150 int is_debug_stack(unsigned long addr) 1151 { 1152 return __get_cpu_var(debug_stack_usage) || 1153 (addr <= __get_cpu_var(debug_stack_addr) && 1154 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); 1155 } 1156 1157 DEFINE_PER_CPU(u32, debug_idt_ctr); 1158 1159 void debug_stack_set_zero(void) 1160 { 1161 this_cpu_inc(debug_idt_ctr); 1162 load_current_idt(); 1163 } 1164 1165 void debug_stack_reset(void) 1166 { 1167 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1168 return; 1169 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1170 load_current_idt(); 1171 } 1172 1173 #else /* CONFIG_X86_64 */ 1174 1175 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1176 EXPORT_PER_CPU_SYMBOL(current_task); 1177 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1178 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1179 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1180 1181 #ifdef CONFIG_CC_STACKPROTECTOR 1182 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1183 #endif 1184 1185 #endif /* CONFIG_X86_64 */ 1186 1187 /* 1188 * Clear all 6 debug registers: 1189 */ 1190 static void clear_all_debug_regs(void) 1191 { 1192 int i; 1193 1194 for (i = 0; i < 8; i++) { 1195 /* Ignore db4, db5 */ 1196 if ((i == 4) || (i == 5)) 1197 continue; 1198 1199 set_debugreg(0, i); 1200 } 1201 } 1202 1203 #ifdef CONFIG_KGDB 1204 /* 1205 * Restore debug regs if using kgdbwait and you have a kernel debugger 1206 * connection established. 1207 */ 1208 static void dbg_restore_debug_regs(void) 1209 { 1210 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1211 arch_kgdb_ops.correct_hw_break(); 1212 } 1213 #else /* ! CONFIG_KGDB */ 1214 #define dbg_restore_debug_regs() 1215 #endif /* ! CONFIG_KGDB */ 1216 1217 /* 1218 * cpu_init() initializes state that is per-CPU. Some data is already 1219 * initialized (naturally) in the bootstrap process, such as the GDT 1220 * and IDT. We reload them nevertheless, this function acts as a 1221 * 'CPU state barrier', nothing should get across. 1222 * A lot of state is already set up in PDA init for 64 bit 1223 */ 1224 #ifdef CONFIG_X86_64 1225 1226 void cpu_init(void) 1227 { 1228 struct orig_ist *oist; 1229 struct task_struct *me; 1230 struct tss_struct *t; 1231 unsigned long v; 1232 int cpu; 1233 int i; 1234 1235 /* 1236 * Load microcode on this cpu if a valid microcode is available. 1237 * This is early microcode loading procedure. 1238 */ 1239 load_ucode_ap(); 1240 1241 cpu = stack_smp_processor_id(); 1242 t = &per_cpu(init_tss, cpu); 1243 oist = &per_cpu(orig_ist, cpu); 1244 1245 #ifdef CONFIG_NUMA 1246 if (this_cpu_read(numa_node) == 0 && 1247 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1248 set_numa_node(early_cpu_to_node(cpu)); 1249 #endif 1250 1251 me = current; 1252 1253 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1254 panic("CPU#%d already initialized!\n", cpu); 1255 1256 pr_debug("Initializing CPU#%d\n", cpu); 1257 1258 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1259 1260 /* 1261 * Initialize the per-CPU GDT with the boot GDT, 1262 * and set up the GDT descriptor: 1263 */ 1264 1265 switch_to_new_gdt(cpu); 1266 loadsegment(fs, 0); 1267 1268 load_current_idt(); 1269 1270 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1271 syscall_init(); 1272 1273 wrmsrl(MSR_FS_BASE, 0); 1274 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1275 barrier(); 1276 1277 x86_configure_nx(); 1278 enable_x2apic(); 1279 1280 /* 1281 * set up and load the per-CPU TSS 1282 */ 1283 if (!oist->ist[0]) { 1284 char *estacks = per_cpu(exception_stacks, cpu); 1285 1286 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1287 estacks += exception_stack_sizes[v]; 1288 oist->ist[v] = t->x86_tss.ist[v] = 1289 (unsigned long)estacks; 1290 if (v == DEBUG_STACK-1) 1291 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1292 } 1293 } 1294 1295 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1296 1297 /* 1298 * <= is required because the CPU will access up to 1299 * 8 bits beyond the end of the IO permission bitmap. 1300 */ 1301 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1302 t->io_bitmap[i] = ~0UL; 1303 1304 atomic_inc(&init_mm.mm_count); 1305 me->active_mm = &init_mm; 1306 BUG_ON(me->mm); 1307 enter_lazy_tlb(&init_mm, me); 1308 1309 load_sp0(t, ¤t->thread); 1310 set_tss_desc(cpu, t); 1311 load_TR_desc(); 1312 load_LDT(&init_mm.context); 1313 1314 clear_all_debug_regs(); 1315 dbg_restore_debug_regs(); 1316 1317 fpu_init(); 1318 1319 if (is_uv_system()) 1320 uv_cpu_init(); 1321 } 1322 1323 #else 1324 1325 void cpu_init(void) 1326 { 1327 int cpu = smp_processor_id(); 1328 struct task_struct *curr = current; 1329 struct tss_struct *t = &per_cpu(init_tss, cpu); 1330 struct thread_struct *thread = &curr->thread; 1331 1332 show_ucode_info_early(); 1333 1334 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1335 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1336 for (;;) 1337 local_irq_enable(); 1338 } 1339 1340 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1341 1342 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1343 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1344 1345 load_current_idt(); 1346 switch_to_new_gdt(cpu); 1347 1348 /* 1349 * Set up and load the per-CPU TSS and LDT 1350 */ 1351 atomic_inc(&init_mm.mm_count); 1352 curr->active_mm = &init_mm; 1353 BUG_ON(curr->mm); 1354 enter_lazy_tlb(&init_mm, curr); 1355 1356 load_sp0(t, thread); 1357 set_tss_desc(cpu, t); 1358 load_TR_desc(); 1359 load_LDT(&init_mm.context); 1360 1361 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1362 1363 #ifdef CONFIG_DOUBLEFAULT 1364 /* Set up doublefault TSS pointer in the GDT */ 1365 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1366 #endif 1367 1368 clear_all_debug_regs(); 1369 dbg_restore_debug_regs(); 1370 1371 fpu_init(); 1372 } 1373 #endif 1374 1375 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 1376 void warn_pre_alternatives(void) 1377 { 1378 WARN(1, "You're using static_cpu_has before alternatives have run!\n"); 1379 } 1380 EXPORT_SYMBOL_GPL(warn_pre_alternatives); 1381 #endif 1382 1383 inline bool __static_cpu_has_safe(u16 bit) 1384 { 1385 return boot_cpu_has(bit); 1386 } 1387 EXPORT_SYMBOL_GPL(__static_cpu_has_safe); 1388