1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 26 #include <asm/cmdline.h> 27 #include <asm/stackprotector.h> 28 #include <asm/perf_event.h> 29 #include <asm/mmu_context.h> 30 #include <asm/doublefault.h> 31 #include <asm/archrandom.h> 32 #include <asm/hypervisor.h> 33 #include <asm/processor.h> 34 #include <asm/tlbflush.h> 35 #include <asm/debugreg.h> 36 #include <asm/sections.h> 37 #include <asm/vsyscall.h> 38 #include <linux/topology.h> 39 #include <linux/cpumask.h> 40 #include <linux/atomic.h> 41 #include <asm/proto.h> 42 #include <asm/setup.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/fpu/api.h> 46 #include <asm/mtrr.h> 47 #include <asm/hwcap2.h> 48 #include <linux/numa.h> 49 #include <asm/numa.h> 50 #include <asm/asm.h> 51 #include <asm/bugs.h> 52 #include <asm/cpu.h> 53 #include <asm/mce.h> 54 #include <asm/msr.h> 55 #include <asm/memtype.h> 56 #include <asm/microcode.h> 57 #include <asm/microcode_intel.h> 58 #include <asm/intel-family.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/uv/uv.h> 61 #include <asm/sigframe.h> 62 #include <asm/traps.h> 63 64 #include "cpu.h" 65 66 u32 elf_hwcap2 __read_mostly; 67 68 /* all of these masks are initialized in setup_cpu_local_masks() */ 69 cpumask_var_t cpu_initialized_mask; 70 cpumask_var_t cpu_callout_mask; 71 cpumask_var_t cpu_callin_mask; 72 73 /* representing cpus for which sibling maps can be computed */ 74 cpumask_var_t cpu_sibling_setup_mask; 75 76 /* Number of siblings per CPU package */ 77 int smp_num_siblings = 1; 78 EXPORT_SYMBOL(smp_num_siblings); 79 80 /* Last level cache ID of each logical CPU */ 81 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 82 83 u16 get_llc_id(unsigned int cpu) 84 { 85 return per_cpu(cpu_llc_id, cpu); 86 } 87 EXPORT_SYMBOL_GPL(get_llc_id); 88 89 /* L2 cache ID of each logical CPU */ 90 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 91 92 static struct ppin_info { 93 int feature; 94 int msr_ppin_ctl; 95 int msr_ppin; 96 } ppin_info[] = { 97 [X86_VENDOR_INTEL] = { 98 .feature = X86_FEATURE_INTEL_PPIN, 99 .msr_ppin_ctl = MSR_PPIN_CTL, 100 .msr_ppin = MSR_PPIN 101 }, 102 [X86_VENDOR_AMD] = { 103 .feature = X86_FEATURE_AMD_PPIN, 104 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 105 .msr_ppin = MSR_AMD_PPIN 106 }, 107 }; 108 109 static const struct x86_cpu_id ppin_cpuids[] = { 110 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 111 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 112 113 /* Legacy models without CPUID enumeration */ 114 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 115 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 116 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 117 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 124 125 {} 126 }; 127 128 static void ppin_init(struct cpuinfo_x86 *c) 129 { 130 const struct x86_cpu_id *id; 131 unsigned long long val; 132 struct ppin_info *info; 133 134 id = x86_match_cpu(ppin_cpuids); 135 if (!id) 136 return; 137 138 /* 139 * Testing the presence of the MSR is not enough. Need to check 140 * that the PPIN_CTL allows reading of the PPIN. 141 */ 142 info = (struct ppin_info *)id->driver_data; 143 144 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 145 goto clear_ppin; 146 147 if ((val & 3UL) == 1UL) { 148 /* PPIN locked in disabled mode */ 149 goto clear_ppin; 150 } 151 152 /* If PPIN is disabled, try to enable */ 153 if (!(val & 2UL)) { 154 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 155 rdmsrl_safe(info->msr_ppin_ctl, &val); 156 } 157 158 /* Is the enable bit set? */ 159 if (val & 2UL) { 160 c->ppin = __rdmsr(info->msr_ppin); 161 set_cpu_cap(c, info->feature); 162 return; 163 } 164 165 clear_ppin: 166 clear_cpu_cap(c, info->feature); 167 } 168 169 /* correctly size the local cpu masks */ 170 void __init setup_cpu_local_masks(void) 171 { 172 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 173 alloc_bootmem_cpumask_var(&cpu_callin_mask); 174 alloc_bootmem_cpumask_var(&cpu_callout_mask); 175 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 176 } 177 178 static void default_init(struct cpuinfo_x86 *c) 179 { 180 #ifdef CONFIG_X86_64 181 cpu_detect_cache_sizes(c); 182 #else 183 /* Not much we can do here... */ 184 /* Check if at least it has cpuid */ 185 if (c->cpuid_level == -1) { 186 /* No cpuid. It must be an ancient CPU */ 187 if (c->x86 == 4) 188 strcpy(c->x86_model_id, "486"); 189 else if (c->x86 == 3) 190 strcpy(c->x86_model_id, "386"); 191 } 192 #endif 193 } 194 195 static const struct cpu_dev default_cpu = { 196 .c_init = default_init, 197 .c_vendor = "Unknown", 198 .c_x86_vendor = X86_VENDOR_UNKNOWN, 199 }; 200 201 static const struct cpu_dev *this_cpu = &default_cpu; 202 203 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 204 #ifdef CONFIG_X86_64 205 /* 206 * We need valid kernel segments for data and code in long mode too 207 * IRET will check the segment types kkeil 2000/10/28 208 * Also sysret mandates a special GDT layout 209 * 210 * TLS descriptors are currently at a different place compared to i386. 211 * Hopefully nobody expects them at a fixed place (Wine?) 212 */ 213 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 214 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 215 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 216 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 217 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 218 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 219 #else 220 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 221 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 222 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 223 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 224 /* 225 * Segments used for calling PnP BIOS have byte granularity. 226 * They code segments and data segments have fixed 64k limits, 227 * the transfer segment sizes are set at run time. 228 */ 229 /* 32-bit code */ 230 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 231 /* 16-bit code */ 232 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 233 /* 16-bit data */ 234 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 235 /* 16-bit data */ 236 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 237 /* 16-bit data */ 238 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 239 /* 240 * The APM segments have byte granularity and their bases 241 * are set at run time. All have 64k limits. 242 */ 243 /* 32-bit code */ 244 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 245 /* 16-bit code */ 246 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 247 /* data */ 248 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 249 250 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 251 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 252 #endif 253 } }; 254 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 255 256 #ifdef CONFIG_X86_64 257 static int __init x86_nopcid_setup(char *s) 258 { 259 /* nopcid doesn't accept parameters */ 260 if (s) 261 return -EINVAL; 262 263 /* do not emit a message if the feature is not present */ 264 if (!boot_cpu_has(X86_FEATURE_PCID)) 265 return 0; 266 267 setup_clear_cpu_cap(X86_FEATURE_PCID); 268 pr_info("nopcid: PCID feature disabled\n"); 269 return 0; 270 } 271 early_param("nopcid", x86_nopcid_setup); 272 #endif 273 274 static int __init x86_noinvpcid_setup(char *s) 275 { 276 /* noinvpcid doesn't accept parameters */ 277 if (s) 278 return -EINVAL; 279 280 /* do not emit a message if the feature is not present */ 281 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 282 return 0; 283 284 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 285 pr_info("noinvpcid: INVPCID feature disabled\n"); 286 return 0; 287 } 288 early_param("noinvpcid", x86_noinvpcid_setup); 289 290 #ifdef CONFIG_X86_32 291 static int cachesize_override = -1; 292 static int disable_x86_serial_nr = 1; 293 294 static int __init cachesize_setup(char *str) 295 { 296 get_option(&str, &cachesize_override); 297 return 1; 298 } 299 __setup("cachesize=", cachesize_setup); 300 301 static int __init x86_sep_setup(char *s) 302 { 303 setup_clear_cpu_cap(X86_FEATURE_SEP); 304 return 1; 305 } 306 __setup("nosep", x86_sep_setup); 307 308 /* Standard macro to see if a specific flag is changeable */ 309 static inline int flag_is_changeable_p(u32 flag) 310 { 311 u32 f1, f2; 312 313 /* 314 * Cyrix and IDT cpus allow disabling of CPUID 315 * so the code below may return different results 316 * when it is executed before and after enabling 317 * the CPUID. Add "volatile" to not allow gcc to 318 * optimize the subsequent calls to this function. 319 */ 320 asm volatile ("pushfl \n\t" 321 "pushfl \n\t" 322 "popl %0 \n\t" 323 "movl %0, %1 \n\t" 324 "xorl %2, %0 \n\t" 325 "pushl %0 \n\t" 326 "popfl \n\t" 327 "pushfl \n\t" 328 "popl %0 \n\t" 329 "popfl \n\t" 330 331 : "=&r" (f1), "=&r" (f2) 332 : "ir" (flag)); 333 334 return ((f1^f2) & flag) != 0; 335 } 336 337 /* Probe for the CPUID instruction */ 338 int have_cpuid_p(void) 339 { 340 return flag_is_changeable_p(X86_EFLAGS_ID); 341 } 342 343 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 344 { 345 unsigned long lo, hi; 346 347 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 348 return; 349 350 /* Disable processor serial number: */ 351 352 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 353 lo |= 0x200000; 354 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 355 356 pr_notice("CPU serial number disabled.\n"); 357 clear_cpu_cap(c, X86_FEATURE_PN); 358 359 /* Disabling the serial number may affect the cpuid level */ 360 c->cpuid_level = cpuid_eax(0); 361 } 362 363 static int __init x86_serial_nr_setup(char *s) 364 { 365 disable_x86_serial_nr = 0; 366 return 1; 367 } 368 __setup("serialnumber", x86_serial_nr_setup); 369 #else 370 static inline int flag_is_changeable_p(u32 flag) 371 { 372 return 1; 373 } 374 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 375 { 376 } 377 #endif 378 379 static __init int setup_disable_smep(char *arg) 380 { 381 setup_clear_cpu_cap(X86_FEATURE_SMEP); 382 return 1; 383 } 384 __setup("nosmep", setup_disable_smep); 385 386 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 387 { 388 if (cpu_has(c, X86_FEATURE_SMEP)) 389 cr4_set_bits(X86_CR4_SMEP); 390 } 391 392 static __init int setup_disable_smap(char *arg) 393 { 394 setup_clear_cpu_cap(X86_FEATURE_SMAP); 395 return 1; 396 } 397 __setup("nosmap", setup_disable_smap); 398 399 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 400 { 401 unsigned long eflags = native_save_fl(); 402 403 /* This should have been cleared long ago */ 404 BUG_ON(eflags & X86_EFLAGS_AC); 405 406 if (cpu_has(c, X86_FEATURE_SMAP)) { 407 #ifdef CONFIG_X86_SMAP 408 cr4_set_bits(X86_CR4_SMAP); 409 #else 410 clear_cpu_cap(c, X86_FEATURE_SMAP); 411 cr4_clear_bits(X86_CR4_SMAP); 412 #endif 413 } 414 } 415 416 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 417 { 418 /* Check the boot processor, plus build option for UMIP. */ 419 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 420 goto out; 421 422 /* Check the current processor's cpuid bits. */ 423 if (!cpu_has(c, X86_FEATURE_UMIP)) 424 goto out; 425 426 cr4_set_bits(X86_CR4_UMIP); 427 428 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 429 430 return; 431 432 out: 433 /* 434 * Make sure UMIP is disabled in case it was enabled in a 435 * previous boot (e.g., via kexec). 436 */ 437 cr4_clear_bits(X86_CR4_UMIP); 438 } 439 440 /* These bits should not change their value after CPU init is finished. */ 441 static const unsigned long cr4_pinned_mask = 442 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 443 X86_CR4_FSGSBASE | X86_CR4_CET; 444 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 445 static unsigned long cr4_pinned_bits __ro_after_init; 446 447 void native_write_cr0(unsigned long val) 448 { 449 unsigned long bits_missing = 0; 450 451 set_register: 452 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 453 454 if (static_branch_likely(&cr_pinning)) { 455 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 456 bits_missing = X86_CR0_WP; 457 val |= bits_missing; 458 goto set_register; 459 } 460 /* Warn after we've set the missing bits. */ 461 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 462 } 463 } 464 EXPORT_SYMBOL(native_write_cr0); 465 466 void __no_profile native_write_cr4(unsigned long val) 467 { 468 unsigned long bits_changed = 0; 469 470 set_register: 471 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 472 473 if (static_branch_likely(&cr_pinning)) { 474 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 475 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 476 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 477 goto set_register; 478 } 479 /* Warn after we've corrected the changed bits. */ 480 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 481 bits_changed); 482 } 483 } 484 #if IS_MODULE(CONFIG_LKDTM) 485 EXPORT_SYMBOL_GPL(native_write_cr4); 486 #endif 487 488 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 489 { 490 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 491 492 lockdep_assert_irqs_disabled(); 493 494 newval = (cr4 & ~clear) | set; 495 if (newval != cr4) { 496 this_cpu_write(cpu_tlbstate.cr4, newval); 497 __write_cr4(newval); 498 } 499 } 500 EXPORT_SYMBOL(cr4_update_irqsoff); 501 502 /* Read the CR4 shadow. */ 503 unsigned long cr4_read_shadow(void) 504 { 505 return this_cpu_read(cpu_tlbstate.cr4); 506 } 507 EXPORT_SYMBOL_GPL(cr4_read_shadow); 508 509 void cr4_init(void) 510 { 511 unsigned long cr4 = __read_cr4(); 512 513 if (boot_cpu_has(X86_FEATURE_PCID)) 514 cr4 |= X86_CR4_PCIDE; 515 if (static_branch_likely(&cr_pinning)) 516 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 517 518 __write_cr4(cr4); 519 520 /* Initialize cr4 shadow for this CPU. */ 521 this_cpu_write(cpu_tlbstate.cr4, cr4); 522 } 523 524 /* 525 * Once CPU feature detection is finished (and boot params have been 526 * parsed), record any of the sensitive CR bits that are set, and 527 * enable CR pinning. 528 */ 529 static void __init setup_cr_pinning(void) 530 { 531 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 532 static_key_enable(&cr_pinning.key); 533 } 534 535 static __init int x86_nofsgsbase_setup(char *arg) 536 { 537 /* Require an exact match without trailing characters. */ 538 if (strlen(arg)) 539 return 0; 540 541 /* Do not emit a message if the feature is not present. */ 542 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 543 return 1; 544 545 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 546 pr_info("FSGSBASE disabled via kernel command line\n"); 547 return 1; 548 } 549 __setup("nofsgsbase", x86_nofsgsbase_setup); 550 551 /* 552 * Protection Keys are not available in 32-bit mode. 553 */ 554 static bool pku_disabled; 555 556 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 557 { 558 if (c == &boot_cpu_data) { 559 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 560 return; 561 /* 562 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 563 * bit to be set. Enforce it. 564 */ 565 setup_force_cpu_cap(X86_FEATURE_OSPKE); 566 567 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 568 return; 569 } 570 571 cr4_set_bits(X86_CR4_PKE); 572 /* Load the default PKRU value */ 573 pkru_write_default(); 574 } 575 576 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 577 static __init int setup_disable_pku(char *arg) 578 { 579 /* 580 * Do not clear the X86_FEATURE_PKU bit. All of the 581 * runtime checks are against OSPKE so clearing the 582 * bit does nothing. 583 * 584 * This way, we will see "pku" in cpuinfo, but not 585 * "ospke", which is exactly what we want. It shows 586 * that the CPU has PKU, but the OS has not enabled it. 587 * This happens to be exactly how a system would look 588 * if we disabled the config option. 589 */ 590 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 591 pku_disabled = true; 592 return 1; 593 } 594 __setup("nopku", setup_disable_pku); 595 #endif /* CONFIG_X86_64 */ 596 597 #ifdef CONFIG_X86_KERNEL_IBT 598 599 __noendbr u64 ibt_save(void) 600 { 601 u64 msr = 0; 602 603 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 604 rdmsrl(MSR_IA32_S_CET, msr); 605 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 606 } 607 608 return msr; 609 } 610 611 __noendbr void ibt_restore(u64 save) 612 { 613 u64 msr; 614 615 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 616 rdmsrl(MSR_IA32_S_CET, msr); 617 msr &= ~CET_ENDBR_EN; 618 msr |= (save & CET_ENDBR_EN); 619 wrmsrl(MSR_IA32_S_CET, msr); 620 } 621 } 622 623 #endif 624 625 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 626 { 627 u64 msr = CET_ENDBR_EN; 628 629 if (!HAS_KERNEL_IBT || 630 !cpu_feature_enabled(X86_FEATURE_IBT)) 631 return; 632 633 wrmsrl(MSR_IA32_S_CET, msr); 634 cr4_set_bits(X86_CR4_CET); 635 636 if (!ibt_selftest()) { 637 pr_err("IBT selftest: Failed!\n"); 638 setup_clear_cpu_cap(X86_FEATURE_IBT); 639 return; 640 } 641 } 642 643 __noendbr void cet_disable(void) 644 { 645 if (cpu_feature_enabled(X86_FEATURE_IBT)) 646 wrmsrl(MSR_IA32_S_CET, 0); 647 } 648 649 /* 650 * Some CPU features depend on higher CPUID levels, which may not always 651 * be available due to CPUID level capping or broken virtualization 652 * software. Add those features to this table to auto-disable them. 653 */ 654 struct cpuid_dependent_feature { 655 u32 feature; 656 u32 level; 657 }; 658 659 static const struct cpuid_dependent_feature 660 cpuid_dependent_features[] = { 661 { X86_FEATURE_MWAIT, 0x00000005 }, 662 { X86_FEATURE_DCA, 0x00000009 }, 663 { X86_FEATURE_XSAVE, 0x0000000d }, 664 { 0, 0 } 665 }; 666 667 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 668 { 669 const struct cpuid_dependent_feature *df; 670 671 for (df = cpuid_dependent_features; df->feature; df++) { 672 673 if (!cpu_has(c, df->feature)) 674 continue; 675 /* 676 * Note: cpuid_level is set to -1 if unavailable, but 677 * extended_extended_level is set to 0 if unavailable 678 * and the legitimate extended levels are all negative 679 * when signed; hence the weird messing around with 680 * signs here... 681 */ 682 if (!((s32)df->level < 0 ? 683 (u32)df->level > (u32)c->extended_cpuid_level : 684 (s32)df->level > (s32)c->cpuid_level)) 685 continue; 686 687 clear_cpu_cap(c, df->feature); 688 if (!warn) 689 continue; 690 691 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 692 x86_cap_flag(df->feature), df->level); 693 } 694 } 695 696 /* 697 * Naming convention should be: <Name> [(<Codename>)] 698 * This table only is used unless init_<vendor>() below doesn't set it; 699 * in particular, if CPUID levels 0x80000002..4 are supported, this 700 * isn't used 701 */ 702 703 /* Look up CPU names by table lookup. */ 704 static const char *table_lookup_model(struct cpuinfo_x86 *c) 705 { 706 #ifdef CONFIG_X86_32 707 const struct legacy_cpu_model_info *info; 708 709 if (c->x86_model >= 16) 710 return NULL; /* Range check */ 711 712 if (!this_cpu) 713 return NULL; 714 715 info = this_cpu->legacy_models; 716 717 while (info->family) { 718 if (info->family == c->x86) 719 return info->model_names[c->x86_model]; 720 info++; 721 } 722 #endif 723 return NULL; /* Not found */ 724 } 725 726 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 727 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 728 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 729 730 void load_percpu_segment(int cpu) 731 { 732 #ifdef CONFIG_X86_32 733 loadsegment(fs, __KERNEL_PERCPU); 734 #else 735 __loadsegment_simple(gs, 0); 736 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 737 #endif 738 } 739 740 #ifdef CONFIG_X86_32 741 /* The 32-bit entry code needs to find cpu_entry_area. */ 742 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 743 #endif 744 745 /* Load the original GDT from the per-cpu structure */ 746 void load_direct_gdt(int cpu) 747 { 748 struct desc_ptr gdt_descr; 749 750 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 751 gdt_descr.size = GDT_SIZE - 1; 752 load_gdt(&gdt_descr); 753 } 754 EXPORT_SYMBOL_GPL(load_direct_gdt); 755 756 /* Load a fixmap remapping of the per-cpu GDT */ 757 void load_fixmap_gdt(int cpu) 758 { 759 struct desc_ptr gdt_descr; 760 761 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 762 gdt_descr.size = GDT_SIZE - 1; 763 load_gdt(&gdt_descr); 764 } 765 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 766 767 /* 768 * Current gdt points %fs at the "master" per-cpu area: after this, 769 * it's on the real one. 770 */ 771 void switch_to_new_gdt(int cpu) 772 { 773 /* Load the original GDT */ 774 load_direct_gdt(cpu); 775 /* Reload the per-cpu base */ 776 load_percpu_segment(cpu); 777 } 778 779 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 780 781 static void get_model_name(struct cpuinfo_x86 *c) 782 { 783 unsigned int *v; 784 char *p, *q, *s; 785 786 if (c->extended_cpuid_level < 0x80000004) 787 return; 788 789 v = (unsigned int *)c->x86_model_id; 790 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 791 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 792 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 793 c->x86_model_id[48] = 0; 794 795 /* Trim whitespace */ 796 p = q = s = &c->x86_model_id[0]; 797 798 while (*p == ' ') 799 p++; 800 801 while (*p) { 802 /* Note the last non-whitespace index */ 803 if (!isspace(*p)) 804 s = q; 805 806 *q++ = *p++; 807 } 808 809 *(s + 1) = '\0'; 810 } 811 812 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 813 { 814 unsigned int eax, ebx, ecx, edx; 815 816 c->x86_max_cores = 1; 817 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 818 return; 819 820 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 821 if (eax & 0x1f) 822 c->x86_max_cores = (eax >> 26) + 1; 823 } 824 825 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 826 { 827 unsigned int n, dummy, ebx, ecx, edx, l2size; 828 829 n = c->extended_cpuid_level; 830 831 if (n >= 0x80000005) { 832 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 833 c->x86_cache_size = (ecx>>24) + (edx>>24); 834 #ifdef CONFIG_X86_64 835 /* On K8 L1 TLB is inclusive, so don't count it */ 836 c->x86_tlbsize = 0; 837 #endif 838 } 839 840 if (n < 0x80000006) /* Some chips just has a large L1. */ 841 return; 842 843 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 844 l2size = ecx >> 16; 845 846 #ifdef CONFIG_X86_64 847 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 848 #else 849 /* do processor-specific cache resizing */ 850 if (this_cpu->legacy_cache_size) 851 l2size = this_cpu->legacy_cache_size(c, l2size); 852 853 /* Allow user to override all this if necessary. */ 854 if (cachesize_override != -1) 855 l2size = cachesize_override; 856 857 if (l2size == 0) 858 return; /* Again, no L2 cache is possible */ 859 #endif 860 861 c->x86_cache_size = l2size; 862 } 863 864 u16 __read_mostly tlb_lli_4k[NR_INFO]; 865 u16 __read_mostly tlb_lli_2m[NR_INFO]; 866 u16 __read_mostly tlb_lli_4m[NR_INFO]; 867 u16 __read_mostly tlb_lld_4k[NR_INFO]; 868 u16 __read_mostly tlb_lld_2m[NR_INFO]; 869 u16 __read_mostly tlb_lld_4m[NR_INFO]; 870 u16 __read_mostly tlb_lld_1g[NR_INFO]; 871 872 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 873 { 874 if (this_cpu->c_detect_tlb) 875 this_cpu->c_detect_tlb(c); 876 877 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 878 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 879 tlb_lli_4m[ENTRIES]); 880 881 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 882 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 883 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 884 } 885 886 int detect_ht_early(struct cpuinfo_x86 *c) 887 { 888 #ifdef CONFIG_SMP 889 u32 eax, ebx, ecx, edx; 890 891 if (!cpu_has(c, X86_FEATURE_HT)) 892 return -1; 893 894 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 895 return -1; 896 897 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 898 return -1; 899 900 cpuid(1, &eax, &ebx, &ecx, &edx); 901 902 smp_num_siblings = (ebx & 0xff0000) >> 16; 903 if (smp_num_siblings == 1) 904 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 905 #endif 906 return 0; 907 } 908 909 void detect_ht(struct cpuinfo_x86 *c) 910 { 911 #ifdef CONFIG_SMP 912 int index_msb, core_bits; 913 914 if (detect_ht_early(c) < 0) 915 return; 916 917 index_msb = get_count_order(smp_num_siblings); 918 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 919 920 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 921 922 index_msb = get_count_order(smp_num_siblings); 923 924 core_bits = get_count_order(c->x86_max_cores); 925 926 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 927 ((1 << core_bits) - 1); 928 #endif 929 } 930 931 static void get_cpu_vendor(struct cpuinfo_x86 *c) 932 { 933 char *v = c->x86_vendor_id; 934 int i; 935 936 for (i = 0; i < X86_VENDOR_NUM; i++) { 937 if (!cpu_devs[i]) 938 break; 939 940 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 941 (cpu_devs[i]->c_ident[1] && 942 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 943 944 this_cpu = cpu_devs[i]; 945 c->x86_vendor = this_cpu->c_x86_vendor; 946 return; 947 } 948 } 949 950 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 951 "CPU: Your system may be unstable.\n", v); 952 953 c->x86_vendor = X86_VENDOR_UNKNOWN; 954 this_cpu = &default_cpu; 955 } 956 957 void cpu_detect(struct cpuinfo_x86 *c) 958 { 959 /* Get vendor name */ 960 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 961 (unsigned int *)&c->x86_vendor_id[0], 962 (unsigned int *)&c->x86_vendor_id[8], 963 (unsigned int *)&c->x86_vendor_id[4]); 964 965 c->x86 = 4; 966 /* Intel-defined flags: level 0x00000001 */ 967 if (c->cpuid_level >= 0x00000001) { 968 u32 junk, tfms, cap0, misc; 969 970 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 971 c->x86 = x86_family(tfms); 972 c->x86_model = x86_model(tfms); 973 c->x86_stepping = x86_stepping(tfms); 974 975 if (cap0 & (1<<19)) { 976 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 977 c->x86_cache_alignment = c->x86_clflush_size; 978 } 979 } 980 } 981 982 static void apply_forced_caps(struct cpuinfo_x86 *c) 983 { 984 int i; 985 986 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 987 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 988 c->x86_capability[i] |= cpu_caps_set[i]; 989 } 990 } 991 992 static void init_speculation_control(struct cpuinfo_x86 *c) 993 { 994 /* 995 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 996 * and they also have a different bit for STIBP support. Also, 997 * a hypervisor might have set the individual AMD bits even on 998 * Intel CPUs, for finer-grained selection of what's available. 999 */ 1000 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 1001 set_cpu_cap(c, X86_FEATURE_IBRS); 1002 set_cpu_cap(c, X86_FEATURE_IBPB); 1003 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1004 } 1005 1006 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 1007 set_cpu_cap(c, X86_FEATURE_STIBP); 1008 1009 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 1010 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 1011 set_cpu_cap(c, X86_FEATURE_SSBD); 1012 1013 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 1014 set_cpu_cap(c, X86_FEATURE_IBRS); 1015 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1016 } 1017 1018 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 1019 set_cpu_cap(c, X86_FEATURE_IBPB); 1020 1021 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 1022 set_cpu_cap(c, X86_FEATURE_STIBP); 1023 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1024 } 1025 1026 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1027 set_cpu_cap(c, X86_FEATURE_SSBD); 1028 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1029 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1030 } 1031 } 1032 1033 void get_cpu_cap(struct cpuinfo_x86 *c) 1034 { 1035 u32 eax, ebx, ecx, edx; 1036 1037 /* Intel-defined flags: level 0x00000001 */ 1038 if (c->cpuid_level >= 0x00000001) { 1039 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1040 1041 c->x86_capability[CPUID_1_ECX] = ecx; 1042 c->x86_capability[CPUID_1_EDX] = edx; 1043 } 1044 1045 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1046 if (c->cpuid_level >= 0x00000006) 1047 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1048 1049 /* Additional Intel-defined flags: level 0x00000007 */ 1050 if (c->cpuid_level >= 0x00000007) { 1051 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1052 c->x86_capability[CPUID_7_0_EBX] = ebx; 1053 c->x86_capability[CPUID_7_ECX] = ecx; 1054 c->x86_capability[CPUID_7_EDX] = edx; 1055 1056 /* Check valid sub-leaf index before accessing it */ 1057 if (eax >= 1) { 1058 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1059 c->x86_capability[CPUID_7_1_EAX] = eax; 1060 } 1061 } 1062 1063 /* Extended state features: level 0x0000000d */ 1064 if (c->cpuid_level >= 0x0000000d) { 1065 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1066 1067 c->x86_capability[CPUID_D_1_EAX] = eax; 1068 } 1069 1070 /* AMD-defined flags: level 0x80000001 */ 1071 eax = cpuid_eax(0x80000000); 1072 c->extended_cpuid_level = eax; 1073 1074 if ((eax & 0xffff0000) == 0x80000000) { 1075 if (eax >= 0x80000001) { 1076 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1077 1078 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1079 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1080 } 1081 } 1082 1083 if (c->extended_cpuid_level >= 0x80000007) { 1084 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1085 1086 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1087 c->x86_power = edx; 1088 } 1089 1090 if (c->extended_cpuid_level >= 0x80000008) { 1091 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1092 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1093 } 1094 1095 if (c->extended_cpuid_level >= 0x8000000a) 1096 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1097 1098 if (c->extended_cpuid_level >= 0x8000001f) 1099 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1100 1101 init_scattered_cpuid_features(c); 1102 init_speculation_control(c); 1103 1104 /* 1105 * Clear/Set all flags overridden by options, after probe. 1106 * This needs to happen each time we re-probe, which may happen 1107 * several times during CPU initialization. 1108 */ 1109 apply_forced_caps(c); 1110 } 1111 1112 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1113 { 1114 u32 eax, ebx, ecx, edx; 1115 1116 if (c->extended_cpuid_level >= 0x80000008) { 1117 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1118 1119 c->x86_virt_bits = (eax >> 8) & 0xff; 1120 c->x86_phys_bits = eax & 0xff; 1121 } 1122 #ifdef CONFIG_X86_32 1123 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 1124 c->x86_phys_bits = 36; 1125 #endif 1126 c->x86_cache_bits = c->x86_phys_bits; 1127 } 1128 1129 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1130 { 1131 #ifdef CONFIG_X86_32 1132 int i; 1133 1134 /* 1135 * First of all, decide if this is a 486 or higher 1136 * It's a 486 if we can modify the AC flag 1137 */ 1138 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1139 c->x86 = 4; 1140 else 1141 c->x86 = 3; 1142 1143 for (i = 0; i < X86_VENDOR_NUM; i++) 1144 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1145 c->x86_vendor_id[0] = 0; 1146 cpu_devs[i]->c_identify(c); 1147 if (c->x86_vendor_id[0]) { 1148 get_cpu_vendor(c); 1149 break; 1150 } 1151 } 1152 #endif 1153 } 1154 1155 #define NO_SPECULATION BIT(0) 1156 #define NO_MELTDOWN BIT(1) 1157 #define NO_SSB BIT(2) 1158 #define NO_L1TF BIT(3) 1159 #define NO_MDS BIT(4) 1160 #define MSBDS_ONLY BIT(5) 1161 #define NO_SWAPGS BIT(6) 1162 #define NO_ITLB_MULTIHIT BIT(7) 1163 #define NO_SPECTRE_V2 BIT(8) 1164 1165 #define VULNWL(vendor, family, model, whitelist) \ 1166 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1167 1168 #define VULNWL_INTEL(model, whitelist) \ 1169 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1170 1171 #define VULNWL_AMD(family, whitelist) \ 1172 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1173 1174 #define VULNWL_HYGON(family, whitelist) \ 1175 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1176 1177 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1178 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1179 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1180 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1181 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1182 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1183 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1184 1185 /* Intel Family 6 */ 1186 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1187 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1188 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1189 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1190 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1191 1192 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1193 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1194 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1195 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1196 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1197 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1198 1199 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1200 1201 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1202 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1203 1204 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1205 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1206 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1207 1208 /* 1209 * Technically, swapgs isn't serializing on AMD (despite it previously 1210 * being documented as such in the APM). But according to AMD, %gs is 1211 * updated non-speculatively, and the issuing of %gs-relative memory 1212 * operands will be blocked until the %gs update completes, which is 1213 * good enough for our purposes. 1214 */ 1215 1216 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1217 1218 /* AMD Family 0xf - 0x12 */ 1219 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1220 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1221 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1222 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1223 1224 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1225 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1226 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1227 1228 /* Zhaoxin Family 7 */ 1229 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1230 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1231 {} 1232 }; 1233 1234 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1235 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1236 INTEL_FAM6_##model, steppings, \ 1237 X86_FEATURE_ANY, issues) 1238 1239 #define SRBDS BIT(0) 1240 1241 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1242 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1243 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1244 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1245 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1246 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1247 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1248 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS), 1249 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS), 1250 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS), 1251 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS), 1252 {} 1253 }; 1254 1255 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1256 { 1257 const struct x86_cpu_id *m = x86_match_cpu(table); 1258 1259 return m && !!(m->driver_data & which); 1260 } 1261 1262 u64 x86_read_arch_cap_msr(void) 1263 { 1264 u64 ia32_cap = 0; 1265 1266 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1267 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1268 1269 return ia32_cap; 1270 } 1271 1272 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1273 { 1274 u64 ia32_cap = x86_read_arch_cap_msr(); 1275 1276 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1277 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1278 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1279 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1280 1281 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1282 return; 1283 1284 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1285 1286 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1287 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1288 1289 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1290 !(ia32_cap & ARCH_CAP_SSB_NO) && 1291 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1292 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1293 1294 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1295 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1296 1297 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1298 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1299 setup_force_cpu_bug(X86_BUG_MDS); 1300 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1301 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1302 } 1303 1304 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1305 setup_force_cpu_bug(X86_BUG_SWAPGS); 1306 1307 /* 1308 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1309 * - TSX is supported or 1310 * - TSX_CTRL is present 1311 * 1312 * TSX_CTRL check is needed for cases when TSX could be disabled before 1313 * the kernel boot e.g. kexec. 1314 * TSX_CTRL check alone is not sufficient for cases when the microcode 1315 * update is not present or running as guest that don't get TSX_CTRL. 1316 */ 1317 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1318 (cpu_has(c, X86_FEATURE_RTM) || 1319 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1320 setup_force_cpu_bug(X86_BUG_TAA); 1321 1322 /* 1323 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1324 * in the vulnerability blacklist. 1325 */ 1326 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1327 cpu_has(c, X86_FEATURE_RDSEED)) && 1328 cpu_matches(cpu_vuln_blacklist, SRBDS)) 1329 setup_force_cpu_bug(X86_BUG_SRBDS); 1330 1331 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1332 return; 1333 1334 /* Rogue Data Cache Load? No! */ 1335 if (ia32_cap & ARCH_CAP_RDCL_NO) 1336 return; 1337 1338 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1339 1340 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1341 return; 1342 1343 setup_force_cpu_bug(X86_BUG_L1TF); 1344 } 1345 1346 /* 1347 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1348 * unfortunately, that's not true in practice because of early VIA 1349 * chips and (more importantly) broken virtualizers that are not easy 1350 * to detect. In the latter case it doesn't even *fail* reliably, so 1351 * probing for it doesn't even work. Disable it completely on 32-bit 1352 * unless we can find a reliable way to detect all the broken cases. 1353 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1354 */ 1355 static void detect_nopl(void) 1356 { 1357 #ifdef CONFIG_X86_32 1358 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1359 #else 1360 setup_force_cpu_cap(X86_FEATURE_NOPL); 1361 #endif 1362 } 1363 1364 /* 1365 * We parse cpu parameters early because fpu__init_system() is executed 1366 * before parse_early_param(). 1367 */ 1368 static void __init cpu_parse_early_param(void) 1369 { 1370 char arg[128]; 1371 char *argptr = arg; 1372 int arglen, res, bit; 1373 1374 #ifdef CONFIG_X86_32 1375 if (cmdline_find_option_bool(boot_command_line, "no387")) 1376 #ifdef CONFIG_MATH_EMULATION 1377 setup_clear_cpu_cap(X86_FEATURE_FPU); 1378 #else 1379 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1380 #endif 1381 1382 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1383 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1384 #endif 1385 1386 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1387 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1388 1389 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1390 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1391 1392 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1393 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1394 1395 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1396 if (arglen <= 0) 1397 return; 1398 1399 pr_info("Clearing CPUID bits:"); 1400 do { 1401 res = get_option(&argptr, &bit); 1402 if (res == 0 || res == 3) 1403 break; 1404 1405 /* If the argument was too long, the last bit may be cut off */ 1406 if (res == 1 && arglen >= sizeof(arg)) 1407 break; 1408 1409 if (bit >= 0 && bit < NCAPINTS * 32) { 1410 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1411 setup_clear_cpu_cap(bit); 1412 } 1413 } while (res == 2); 1414 pr_cont("\n"); 1415 } 1416 1417 /* 1418 * Do minimum CPU detection early. 1419 * Fields really needed: vendor, cpuid_level, family, model, mask, 1420 * cache alignment. 1421 * The others are not touched to avoid unwanted side effects. 1422 * 1423 * WARNING: this function is only called on the boot CPU. Don't add code 1424 * here that is supposed to run on all CPUs. 1425 */ 1426 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1427 { 1428 #ifdef CONFIG_X86_64 1429 c->x86_clflush_size = 64; 1430 c->x86_phys_bits = 36; 1431 c->x86_virt_bits = 48; 1432 #else 1433 c->x86_clflush_size = 32; 1434 c->x86_phys_bits = 32; 1435 c->x86_virt_bits = 32; 1436 #endif 1437 c->x86_cache_alignment = c->x86_clflush_size; 1438 1439 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1440 c->extended_cpuid_level = 0; 1441 1442 if (!have_cpuid_p()) 1443 identify_cpu_without_cpuid(c); 1444 1445 /* cyrix could have cpuid enabled via c_identify()*/ 1446 if (have_cpuid_p()) { 1447 cpu_detect(c); 1448 get_cpu_vendor(c); 1449 get_cpu_cap(c); 1450 get_cpu_address_sizes(c); 1451 setup_force_cpu_cap(X86_FEATURE_CPUID); 1452 cpu_parse_early_param(); 1453 1454 if (this_cpu->c_early_init) 1455 this_cpu->c_early_init(c); 1456 1457 c->cpu_index = 0; 1458 filter_cpuid_features(c, false); 1459 1460 if (this_cpu->c_bsp_init) 1461 this_cpu->c_bsp_init(c); 1462 } else { 1463 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1464 } 1465 1466 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1467 1468 cpu_set_bug_bits(c); 1469 1470 sld_setup(c); 1471 1472 fpu__init_system(c); 1473 1474 init_sigframe_size(); 1475 1476 #ifdef CONFIG_X86_32 1477 /* 1478 * Regardless of whether PCID is enumerated, the SDM says 1479 * that it can't be enabled in 32-bit mode. 1480 */ 1481 setup_clear_cpu_cap(X86_FEATURE_PCID); 1482 #endif 1483 1484 /* 1485 * Later in the boot process pgtable_l5_enabled() relies on 1486 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1487 * enabled by this point we need to clear the feature bit to avoid 1488 * false-positives at the later stage. 1489 * 1490 * pgtable_l5_enabled() can be false here for several reasons: 1491 * - 5-level paging is disabled compile-time; 1492 * - it's 32-bit kernel; 1493 * - machine doesn't support 5-level paging; 1494 * - user specified 'no5lvl' in kernel command line. 1495 */ 1496 if (!pgtable_l5_enabled()) 1497 setup_clear_cpu_cap(X86_FEATURE_LA57); 1498 1499 detect_nopl(); 1500 } 1501 1502 void __init early_cpu_init(void) 1503 { 1504 const struct cpu_dev *const *cdev; 1505 int count = 0; 1506 1507 #ifdef CONFIG_PROCESSOR_SELECT 1508 pr_info("KERNEL supported cpus:\n"); 1509 #endif 1510 1511 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1512 const struct cpu_dev *cpudev = *cdev; 1513 1514 if (count >= X86_VENDOR_NUM) 1515 break; 1516 cpu_devs[count] = cpudev; 1517 count++; 1518 1519 #ifdef CONFIG_PROCESSOR_SELECT 1520 { 1521 unsigned int j; 1522 1523 for (j = 0; j < 2; j++) { 1524 if (!cpudev->c_ident[j]) 1525 continue; 1526 pr_info(" %s %s\n", cpudev->c_vendor, 1527 cpudev->c_ident[j]); 1528 } 1529 } 1530 #endif 1531 } 1532 early_identify_cpu(&boot_cpu_data); 1533 } 1534 1535 static bool detect_null_seg_behavior(void) 1536 { 1537 /* 1538 * Empirically, writing zero to a segment selector on AMD does 1539 * not clear the base, whereas writing zero to a segment 1540 * selector on Intel does clear the base. Intel's behavior 1541 * allows slightly faster context switches in the common case 1542 * where GS is unused by the prev and next threads. 1543 * 1544 * Since neither vendor documents this anywhere that I can see, 1545 * detect it directly instead of hard-coding the choice by 1546 * vendor. 1547 * 1548 * I've designated AMD's behavior as the "bug" because it's 1549 * counterintuitive and less friendly. 1550 */ 1551 1552 unsigned long old_base, tmp; 1553 rdmsrl(MSR_FS_BASE, old_base); 1554 wrmsrl(MSR_FS_BASE, 1); 1555 loadsegment(fs, 0); 1556 rdmsrl(MSR_FS_BASE, tmp); 1557 wrmsrl(MSR_FS_BASE, old_base); 1558 return tmp == 0; 1559 } 1560 1561 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1562 { 1563 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1564 if (!IS_ENABLED(CONFIG_X86_64)) 1565 return; 1566 1567 /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ 1568 if (c->extended_cpuid_level >= 0x80000021 && 1569 cpuid_eax(0x80000021) & BIT(6)) 1570 return; 1571 1572 /* 1573 * CPUID bit above wasn't set. If this kernel is still running 1574 * as a HV guest, then the HV has decided not to advertize 1575 * that CPUID bit for whatever reason. For example, one 1576 * member of the migration pool might be vulnerable. Which 1577 * means, the bug is present: set the BUG flag and return. 1578 */ 1579 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1580 set_cpu_bug(c, X86_BUG_NULL_SEG); 1581 return; 1582 } 1583 1584 /* 1585 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1586 * 0x18 is the respective family for Hygon. 1587 */ 1588 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1589 detect_null_seg_behavior()) 1590 return; 1591 1592 /* All the remaining ones are affected */ 1593 set_cpu_bug(c, X86_BUG_NULL_SEG); 1594 } 1595 1596 static void generic_identify(struct cpuinfo_x86 *c) 1597 { 1598 c->extended_cpuid_level = 0; 1599 1600 if (!have_cpuid_p()) 1601 identify_cpu_without_cpuid(c); 1602 1603 /* cyrix could have cpuid enabled via c_identify()*/ 1604 if (!have_cpuid_p()) 1605 return; 1606 1607 cpu_detect(c); 1608 1609 get_cpu_vendor(c); 1610 1611 get_cpu_cap(c); 1612 1613 get_cpu_address_sizes(c); 1614 1615 if (c->cpuid_level >= 0x00000001) { 1616 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1617 #ifdef CONFIG_X86_32 1618 # ifdef CONFIG_SMP 1619 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1620 # else 1621 c->apicid = c->initial_apicid; 1622 # endif 1623 #endif 1624 c->phys_proc_id = c->initial_apicid; 1625 } 1626 1627 get_model_name(c); /* Default name */ 1628 1629 /* 1630 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1631 * systems that run Linux at CPL > 0 may or may not have the 1632 * issue, but, even if they have the issue, there's absolutely 1633 * nothing we can do about it because we can't use the real IRET 1634 * instruction. 1635 * 1636 * NB: For the time being, only 32-bit kernels support 1637 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1638 * whether to apply espfix using paravirt hooks. If any 1639 * non-paravirt system ever shows up that does *not* have the 1640 * ESPFIX issue, we can change this. 1641 */ 1642 #ifdef CONFIG_X86_32 1643 set_cpu_bug(c, X86_BUG_ESPFIX); 1644 #endif 1645 } 1646 1647 /* 1648 * Validate that ACPI/mptables have the same information about the 1649 * effective APIC id and update the package map. 1650 */ 1651 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1652 { 1653 #ifdef CONFIG_SMP 1654 unsigned int apicid, cpu = smp_processor_id(); 1655 1656 apicid = apic->cpu_present_to_apicid(cpu); 1657 1658 if (apicid != c->apicid) { 1659 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1660 cpu, apicid, c->initial_apicid); 1661 } 1662 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1663 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1664 #else 1665 c->logical_proc_id = 0; 1666 #endif 1667 } 1668 1669 /* 1670 * This does the hard work of actually picking apart the CPU stuff... 1671 */ 1672 static void identify_cpu(struct cpuinfo_x86 *c) 1673 { 1674 int i; 1675 1676 c->loops_per_jiffy = loops_per_jiffy; 1677 c->x86_cache_size = 0; 1678 c->x86_vendor = X86_VENDOR_UNKNOWN; 1679 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1680 c->x86_vendor_id[0] = '\0'; /* Unset */ 1681 c->x86_model_id[0] = '\0'; /* Unset */ 1682 c->x86_max_cores = 1; 1683 c->x86_coreid_bits = 0; 1684 c->cu_id = 0xff; 1685 #ifdef CONFIG_X86_64 1686 c->x86_clflush_size = 64; 1687 c->x86_phys_bits = 36; 1688 c->x86_virt_bits = 48; 1689 #else 1690 c->cpuid_level = -1; /* CPUID not detected */ 1691 c->x86_clflush_size = 32; 1692 c->x86_phys_bits = 32; 1693 c->x86_virt_bits = 32; 1694 #endif 1695 c->x86_cache_alignment = c->x86_clflush_size; 1696 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1697 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1698 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1699 #endif 1700 1701 generic_identify(c); 1702 1703 if (this_cpu->c_identify) 1704 this_cpu->c_identify(c); 1705 1706 /* Clear/Set all flags overridden by options, after probe */ 1707 apply_forced_caps(c); 1708 1709 #ifdef CONFIG_X86_64 1710 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1711 #endif 1712 1713 /* 1714 * Vendor-specific initialization. In this section we 1715 * canonicalize the feature flags, meaning if there are 1716 * features a certain CPU supports which CPUID doesn't 1717 * tell us, CPUID claiming incorrect flags, or other bugs, 1718 * we handle them here. 1719 * 1720 * At the end of this section, c->x86_capability better 1721 * indicate the features this CPU genuinely supports! 1722 */ 1723 if (this_cpu->c_init) 1724 this_cpu->c_init(c); 1725 1726 /* Disable the PN if appropriate */ 1727 squash_the_stupid_serial_number(c); 1728 1729 /* Set up SMEP/SMAP/UMIP */ 1730 setup_smep(c); 1731 setup_smap(c); 1732 setup_umip(c); 1733 1734 /* Enable FSGSBASE instructions if available. */ 1735 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1736 cr4_set_bits(X86_CR4_FSGSBASE); 1737 elf_hwcap2 |= HWCAP2_FSGSBASE; 1738 } 1739 1740 /* 1741 * The vendor-specific functions might have changed features. 1742 * Now we do "generic changes." 1743 */ 1744 1745 /* Filter out anything that depends on CPUID levels we don't have */ 1746 filter_cpuid_features(c, true); 1747 1748 /* If the model name is still unset, do table lookup. */ 1749 if (!c->x86_model_id[0]) { 1750 const char *p; 1751 p = table_lookup_model(c); 1752 if (p) 1753 strcpy(c->x86_model_id, p); 1754 else 1755 /* Last resort... */ 1756 sprintf(c->x86_model_id, "%02x/%02x", 1757 c->x86, c->x86_model); 1758 } 1759 1760 #ifdef CONFIG_X86_64 1761 detect_ht(c); 1762 #endif 1763 1764 x86_init_rdrand(c); 1765 setup_pku(c); 1766 setup_cet(c); 1767 1768 /* 1769 * Clear/Set all flags overridden by options, need do it 1770 * before following smp all cpus cap AND. 1771 */ 1772 apply_forced_caps(c); 1773 1774 /* 1775 * On SMP, boot_cpu_data holds the common feature set between 1776 * all CPUs; so make sure that we indicate which features are 1777 * common between the CPUs. The first time this routine gets 1778 * executed, c == &boot_cpu_data. 1779 */ 1780 if (c != &boot_cpu_data) { 1781 /* AND the already accumulated flags with these */ 1782 for (i = 0; i < NCAPINTS; i++) 1783 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1784 1785 /* OR, i.e. replicate the bug flags */ 1786 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1787 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1788 } 1789 1790 ppin_init(c); 1791 1792 /* Init Machine Check Exception if available. */ 1793 mcheck_cpu_init(c); 1794 1795 select_idle_routine(c); 1796 1797 #ifdef CONFIG_NUMA 1798 numa_add_cpu(smp_processor_id()); 1799 #endif 1800 } 1801 1802 /* 1803 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1804 * on 32-bit kernels: 1805 */ 1806 #ifdef CONFIG_X86_32 1807 void enable_sep_cpu(void) 1808 { 1809 struct tss_struct *tss; 1810 int cpu; 1811 1812 if (!boot_cpu_has(X86_FEATURE_SEP)) 1813 return; 1814 1815 cpu = get_cpu(); 1816 tss = &per_cpu(cpu_tss_rw, cpu); 1817 1818 /* 1819 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1820 * see the big comment in struct x86_hw_tss's definition. 1821 */ 1822 1823 tss->x86_tss.ss1 = __KERNEL_CS; 1824 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1825 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1826 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1827 1828 put_cpu(); 1829 } 1830 #endif 1831 1832 void __init identify_boot_cpu(void) 1833 { 1834 identify_cpu(&boot_cpu_data); 1835 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1836 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1837 #ifdef CONFIG_X86_32 1838 sysenter_setup(); 1839 enable_sep_cpu(); 1840 #endif 1841 cpu_detect_tlb(&boot_cpu_data); 1842 setup_cr_pinning(); 1843 1844 tsx_init(); 1845 } 1846 1847 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1848 { 1849 BUG_ON(c == &boot_cpu_data); 1850 identify_cpu(c); 1851 #ifdef CONFIG_X86_32 1852 enable_sep_cpu(); 1853 #endif 1854 mtrr_ap_init(); 1855 validate_apic_and_package_id(c); 1856 x86_spec_ctrl_setup_ap(); 1857 update_srbds_msr(); 1858 } 1859 1860 static __init int setup_noclflush(char *arg) 1861 { 1862 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1863 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1864 return 1; 1865 } 1866 __setup("noclflush", setup_noclflush); 1867 1868 void print_cpu_info(struct cpuinfo_x86 *c) 1869 { 1870 const char *vendor = NULL; 1871 1872 if (c->x86_vendor < X86_VENDOR_NUM) { 1873 vendor = this_cpu->c_vendor; 1874 } else { 1875 if (c->cpuid_level >= 0) 1876 vendor = c->x86_vendor_id; 1877 } 1878 1879 if (vendor && !strstr(c->x86_model_id, vendor)) 1880 pr_cont("%s ", vendor); 1881 1882 if (c->x86_model_id[0]) 1883 pr_cont("%s", c->x86_model_id); 1884 else 1885 pr_cont("%d86", c->x86); 1886 1887 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1888 1889 if (c->x86_stepping || c->cpuid_level >= 0) 1890 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1891 else 1892 pr_cont(")\n"); 1893 } 1894 1895 /* 1896 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 1897 * function prevents it from becoming an environment variable for init. 1898 */ 1899 static __init int setup_clearcpuid(char *arg) 1900 { 1901 return 1; 1902 } 1903 __setup("clearcpuid=", setup_clearcpuid); 1904 1905 #ifdef CONFIG_X86_64 1906 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1907 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1908 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1909 1910 /* 1911 * The following percpu variables are hot. Align current_task to 1912 * cacheline size such that they fall in the same cacheline. 1913 */ 1914 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1915 &init_task; 1916 EXPORT_PER_CPU_SYMBOL(current_task); 1917 1918 DEFINE_PER_CPU(void *, hardirq_stack_ptr); 1919 DEFINE_PER_CPU(bool, hardirq_stack_inuse); 1920 1921 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1922 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1923 1924 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 1925 1926 static void wrmsrl_cstar(unsigned long val) 1927 { 1928 /* 1929 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 1930 * is so far ignored by the CPU, but raises a #VE trap in a TDX 1931 * guest. Avoid the pointless write on all Intel CPUs. 1932 */ 1933 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 1934 wrmsrl(MSR_CSTAR, val); 1935 } 1936 1937 /* May not be marked __init: used by software suspend */ 1938 void syscall_init(void) 1939 { 1940 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1941 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1942 1943 #ifdef CONFIG_IA32_EMULATION 1944 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 1945 /* 1946 * This only works on Intel CPUs. 1947 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1948 * This does not cause SYSENTER to jump to the wrong location, because 1949 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1950 */ 1951 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1952 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1953 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1954 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1955 #else 1956 wrmsrl_cstar((unsigned long)ignore_sysret); 1957 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1958 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1959 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1960 #endif 1961 1962 /* 1963 * Flags to clear on syscall; clear as much as possible 1964 * to minimize user space-kernel interference. 1965 */ 1966 wrmsrl(MSR_SYSCALL_MASK, 1967 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 1968 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 1969 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 1970 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 1971 X86_EFLAGS_AC|X86_EFLAGS_ID); 1972 } 1973 1974 #else /* CONFIG_X86_64 */ 1975 1976 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1977 EXPORT_PER_CPU_SYMBOL(current_task); 1978 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1979 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1980 1981 /* 1982 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1983 * the top of the kernel stack. Use an extra percpu variable to track the 1984 * top of the kernel stack directly. 1985 */ 1986 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1987 (unsigned long)&init_thread_union + THREAD_SIZE; 1988 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1989 1990 #ifdef CONFIG_STACKPROTECTOR 1991 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 1992 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 1993 #endif 1994 1995 #endif /* CONFIG_X86_64 */ 1996 1997 /* 1998 * Clear all 6 debug registers: 1999 */ 2000 static void clear_all_debug_regs(void) 2001 { 2002 int i; 2003 2004 for (i = 0; i < 8; i++) { 2005 /* Ignore db4, db5 */ 2006 if ((i == 4) || (i == 5)) 2007 continue; 2008 2009 set_debugreg(0, i); 2010 } 2011 } 2012 2013 #ifdef CONFIG_KGDB 2014 /* 2015 * Restore debug regs if using kgdbwait and you have a kernel debugger 2016 * connection established. 2017 */ 2018 static void dbg_restore_debug_regs(void) 2019 { 2020 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2021 arch_kgdb_ops.correct_hw_break(); 2022 } 2023 #else /* ! CONFIG_KGDB */ 2024 #define dbg_restore_debug_regs() 2025 #endif /* ! CONFIG_KGDB */ 2026 2027 static void wait_for_master_cpu(int cpu) 2028 { 2029 #ifdef CONFIG_SMP 2030 /* 2031 * wait for ACK from master CPU before continuing 2032 * with AP initialization 2033 */ 2034 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 2035 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 2036 cpu_relax(); 2037 #endif 2038 } 2039 2040 #ifdef CONFIG_X86_64 2041 static inline void setup_getcpu(int cpu) 2042 { 2043 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2044 struct desc_struct d = { }; 2045 2046 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2047 wrmsr(MSR_TSC_AUX, cpudata, 0); 2048 2049 /* Store CPU and node number in limit. */ 2050 d.limit0 = cpudata; 2051 d.limit1 = cpudata >> 16; 2052 2053 d.type = 5; /* RO data, expand down, accessed */ 2054 d.dpl = 3; /* Visible to user code */ 2055 d.s = 1; /* Not a system segment */ 2056 d.p = 1; /* Present */ 2057 d.d = 1; /* 32-bit */ 2058 2059 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2060 } 2061 2062 static inline void ucode_cpu_init(int cpu) 2063 { 2064 if (cpu) 2065 load_ucode_ap(); 2066 } 2067 2068 static inline void tss_setup_ist(struct tss_struct *tss) 2069 { 2070 /* Set up the per-CPU TSS IST stacks */ 2071 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2072 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2073 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2074 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2075 /* Only mapped when SEV-ES is active */ 2076 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2077 } 2078 2079 #else /* CONFIG_X86_64 */ 2080 2081 static inline void setup_getcpu(int cpu) { } 2082 2083 static inline void ucode_cpu_init(int cpu) 2084 { 2085 show_ucode_info_early(); 2086 } 2087 2088 static inline void tss_setup_ist(struct tss_struct *tss) { } 2089 2090 #endif /* !CONFIG_X86_64 */ 2091 2092 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2093 { 2094 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2095 2096 #ifdef CONFIG_X86_IOPL_IOPERM 2097 tss->io_bitmap.prev_max = 0; 2098 tss->io_bitmap.prev_sequence = 0; 2099 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2100 /* 2101 * Invalidate the extra array entry past the end of the all 2102 * permission bitmap as required by the hardware. 2103 */ 2104 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2105 #endif 2106 } 2107 2108 /* 2109 * Setup everything needed to handle exceptions from the IDT, including the IST 2110 * exceptions which use paranoid_entry(). 2111 */ 2112 void cpu_init_exception_handling(void) 2113 { 2114 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2115 int cpu = raw_smp_processor_id(); 2116 2117 /* paranoid_entry() gets the CPU number from the GDT */ 2118 setup_getcpu(cpu); 2119 2120 /* IST vectors need TSS to be set up. */ 2121 tss_setup_ist(tss); 2122 tss_setup_io_bitmap(tss); 2123 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2124 2125 load_TR_desc(); 2126 2127 /* Finally load the IDT */ 2128 load_current_idt(); 2129 } 2130 2131 /* 2132 * cpu_init() initializes state that is per-CPU. Some data is already 2133 * initialized (naturally) in the bootstrap process, such as the GDT. We 2134 * reload it nevertheless, this function acts as a 'CPU state barrier', 2135 * nothing should get across. 2136 */ 2137 void cpu_init(void) 2138 { 2139 struct task_struct *cur = current; 2140 int cpu = raw_smp_processor_id(); 2141 2142 wait_for_master_cpu(cpu); 2143 2144 ucode_cpu_init(cpu); 2145 2146 #ifdef CONFIG_NUMA 2147 if (this_cpu_read(numa_node) == 0 && 2148 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2149 set_numa_node(early_cpu_to_node(cpu)); 2150 #endif 2151 pr_debug("Initializing CPU#%d\n", cpu); 2152 2153 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2154 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2155 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2156 2157 /* 2158 * Initialize the per-CPU GDT with the boot GDT, 2159 * and set up the GDT descriptor: 2160 */ 2161 switch_to_new_gdt(cpu); 2162 2163 if (IS_ENABLED(CONFIG_X86_64)) { 2164 loadsegment(fs, 0); 2165 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2166 syscall_init(); 2167 2168 wrmsrl(MSR_FS_BASE, 0); 2169 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2170 barrier(); 2171 2172 x2apic_setup(); 2173 } 2174 2175 mmgrab(&init_mm); 2176 cur->active_mm = &init_mm; 2177 BUG_ON(cur->mm); 2178 initialize_tlbstate_and_flush(); 2179 enter_lazy_tlb(&init_mm, cur); 2180 2181 /* 2182 * sp0 points to the entry trampoline stack regardless of what task 2183 * is running. 2184 */ 2185 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2186 2187 load_mm_ldt(&init_mm); 2188 2189 clear_all_debug_regs(); 2190 dbg_restore_debug_regs(); 2191 2192 doublefault_init_cpu_tss(); 2193 2194 fpu__init_cpu(); 2195 2196 if (is_uv_system()) 2197 uv_cpu_init(); 2198 2199 load_fixmap_gdt(cpu); 2200 } 2201 2202 #ifdef CONFIG_SMP 2203 void cpu_init_secondary(void) 2204 { 2205 /* 2206 * Relies on the BP having set-up the IDT tables, which are loaded 2207 * on this CPU in cpu_init_exception_handling(). 2208 */ 2209 cpu_init_exception_handling(); 2210 cpu_init(); 2211 } 2212 #endif 2213 2214 /* 2215 * The microcode loader calls this upon late microcode load to recheck features, 2216 * only when microcode has been updated. Caller holds microcode_mutex and CPU 2217 * hotplug lock. 2218 */ 2219 void microcode_check(void) 2220 { 2221 struct cpuinfo_x86 info; 2222 2223 perf_check_microcode(); 2224 2225 /* Reload CPUID max function as it might've changed. */ 2226 info.cpuid_level = cpuid_eax(0); 2227 2228 /* 2229 * Copy all capability leafs to pick up the synthetic ones so that 2230 * memcmp() below doesn't fail on that. The ones coming from CPUID will 2231 * get overwritten in get_cpu_cap(). 2232 */ 2233 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 2234 2235 get_cpu_cap(&info); 2236 2237 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 2238 return; 2239 2240 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2241 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2242 } 2243 2244 /* 2245 * Invoked from core CPU hotplug code after hotplug operations 2246 */ 2247 void arch_smt_update(void) 2248 { 2249 /* Handle the speculative execution misfeatures */ 2250 cpu_bugs_smt_update(); 2251 /* Check whether IPI broadcasting can be enabled */ 2252 apic_smt_update(); 2253 } 2254