1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 #include <asm/intel-family.h> 51 #include <asm/cpu_device_id.h> 52 53 #ifdef CONFIG_X86_LOCAL_APIC 54 #include <asm/uv/uv.h> 55 #endif 56 57 #include "cpu.h" 58 59 u32 elf_hwcap2 __read_mostly; 60 61 /* all of these masks are initialized in setup_cpu_local_masks() */ 62 cpumask_var_t cpu_initialized_mask; 63 cpumask_var_t cpu_callout_mask; 64 cpumask_var_t cpu_callin_mask; 65 66 /* representing cpus for which sibling maps can be computed */ 67 cpumask_var_t cpu_sibling_setup_mask; 68 69 /* correctly size the local cpu masks */ 70 void __init setup_cpu_local_masks(void) 71 { 72 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 73 alloc_bootmem_cpumask_var(&cpu_callin_mask); 74 alloc_bootmem_cpumask_var(&cpu_callout_mask); 75 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 76 } 77 78 static void default_init(struct cpuinfo_x86 *c) 79 { 80 #ifdef CONFIG_X86_64 81 cpu_detect_cache_sizes(c); 82 #else 83 /* Not much we can do here... */ 84 /* Check if at least it has cpuid */ 85 if (c->cpuid_level == -1) { 86 /* No cpuid. It must be an ancient CPU */ 87 if (c->x86 == 4) 88 strcpy(c->x86_model_id, "486"); 89 else if (c->x86 == 3) 90 strcpy(c->x86_model_id, "386"); 91 } 92 #endif 93 } 94 95 static const struct cpu_dev default_cpu = { 96 .c_init = default_init, 97 .c_vendor = "Unknown", 98 .c_x86_vendor = X86_VENDOR_UNKNOWN, 99 }; 100 101 static const struct cpu_dev *this_cpu = &default_cpu; 102 103 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 104 #ifdef CONFIG_X86_64 105 /* 106 * We need valid kernel segments for data and code in long mode too 107 * IRET will check the segment types kkeil 2000/10/28 108 * Also sysret mandates a special GDT layout 109 * 110 * TLS descriptors are currently at a different place compared to i386. 111 * Hopefully nobody expects them at a fixed place (Wine?) 112 */ 113 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 114 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 115 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 117 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 118 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 119 #else 120 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 121 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 122 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 123 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 124 /* 125 * Segments used for calling PnP BIOS have byte granularity. 126 * They code segments and data segments have fixed 64k limits, 127 * the transfer segment sizes are set at run time. 128 */ 129 /* 32-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 131 /* 16-bit code */ 132 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 16-bit data */ 138 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 139 /* 140 * The APM segments have byte granularity and their bases 141 * are set at run time. All have 64k limits. 142 */ 143 /* 32-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 145 /* 16-bit code */ 146 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 147 /* data */ 148 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 149 150 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 151 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 152 GDT_STACK_CANARY_INIT 153 #endif 154 } }; 155 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 156 157 static int __init x86_mpx_setup(char *s) 158 { 159 /* require an exact match without trailing characters */ 160 if (strlen(s)) 161 return 0; 162 163 /* do not emit a message if the feature is not present */ 164 if (!boot_cpu_has(X86_FEATURE_MPX)) 165 return 1; 166 167 setup_clear_cpu_cap(X86_FEATURE_MPX); 168 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 169 return 1; 170 } 171 __setup("nompx", x86_mpx_setup); 172 173 #ifdef CONFIG_X86_64 174 static int __init x86_nopcid_setup(char *s) 175 { 176 /* nopcid doesn't accept parameters */ 177 if (s) 178 return -EINVAL; 179 180 /* do not emit a message if the feature is not present */ 181 if (!boot_cpu_has(X86_FEATURE_PCID)) 182 return 0; 183 184 setup_clear_cpu_cap(X86_FEATURE_PCID); 185 pr_info("nopcid: PCID feature disabled\n"); 186 return 0; 187 } 188 early_param("nopcid", x86_nopcid_setup); 189 #endif 190 191 static int __init x86_noinvpcid_setup(char *s) 192 { 193 /* noinvpcid doesn't accept parameters */ 194 if (s) 195 return -EINVAL; 196 197 /* do not emit a message if the feature is not present */ 198 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 199 return 0; 200 201 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 202 pr_info("noinvpcid: INVPCID feature disabled\n"); 203 return 0; 204 } 205 early_param("noinvpcid", x86_noinvpcid_setup); 206 207 #ifdef CONFIG_X86_32 208 static int cachesize_override = -1; 209 static int disable_x86_serial_nr = 1; 210 211 static int __init cachesize_setup(char *str) 212 { 213 get_option(&str, &cachesize_override); 214 return 1; 215 } 216 __setup("cachesize=", cachesize_setup); 217 218 static int __init x86_sep_setup(char *s) 219 { 220 setup_clear_cpu_cap(X86_FEATURE_SEP); 221 return 1; 222 } 223 __setup("nosep", x86_sep_setup); 224 225 /* Standard macro to see if a specific flag is changeable */ 226 static inline int flag_is_changeable_p(u32 flag) 227 { 228 u32 f1, f2; 229 230 /* 231 * Cyrix and IDT cpus allow disabling of CPUID 232 * so the code below may return different results 233 * when it is executed before and after enabling 234 * the CPUID. Add "volatile" to not allow gcc to 235 * optimize the subsequent calls to this function. 236 */ 237 asm volatile ("pushfl \n\t" 238 "pushfl \n\t" 239 "popl %0 \n\t" 240 "movl %0, %1 \n\t" 241 "xorl %2, %0 \n\t" 242 "pushl %0 \n\t" 243 "popfl \n\t" 244 "pushfl \n\t" 245 "popl %0 \n\t" 246 "popfl \n\t" 247 248 : "=&r" (f1), "=&r" (f2) 249 : "ir" (flag)); 250 251 return ((f1^f2) & flag) != 0; 252 } 253 254 /* Probe for the CPUID instruction */ 255 int have_cpuid_p(void) 256 { 257 return flag_is_changeable_p(X86_EFLAGS_ID); 258 } 259 260 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 261 { 262 unsigned long lo, hi; 263 264 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 265 return; 266 267 /* Disable processor serial number: */ 268 269 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 270 lo |= 0x200000; 271 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 272 273 pr_notice("CPU serial number disabled.\n"); 274 clear_cpu_cap(c, X86_FEATURE_PN); 275 276 /* Disabling the serial number may affect the cpuid level */ 277 c->cpuid_level = cpuid_eax(0); 278 } 279 280 static int __init x86_serial_nr_setup(char *s) 281 { 282 disable_x86_serial_nr = 0; 283 return 1; 284 } 285 __setup("serialnumber", x86_serial_nr_setup); 286 #else 287 static inline int flag_is_changeable_p(u32 flag) 288 { 289 return 1; 290 } 291 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 292 { 293 } 294 #endif 295 296 static __init int setup_disable_smep(char *arg) 297 { 298 setup_clear_cpu_cap(X86_FEATURE_SMEP); 299 /* Check for things that depend on SMEP being enabled: */ 300 check_mpx_erratum(&boot_cpu_data); 301 return 1; 302 } 303 __setup("nosmep", setup_disable_smep); 304 305 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 306 { 307 if (cpu_has(c, X86_FEATURE_SMEP)) 308 cr4_set_bits(X86_CR4_SMEP); 309 } 310 311 static __init int setup_disable_smap(char *arg) 312 { 313 setup_clear_cpu_cap(X86_FEATURE_SMAP); 314 return 1; 315 } 316 __setup("nosmap", setup_disable_smap); 317 318 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 319 { 320 unsigned long eflags = native_save_fl(); 321 322 /* This should have been cleared long ago */ 323 BUG_ON(eflags & X86_EFLAGS_AC); 324 325 if (cpu_has(c, X86_FEATURE_SMAP)) { 326 #ifdef CONFIG_X86_SMAP 327 cr4_set_bits(X86_CR4_SMAP); 328 #else 329 cr4_clear_bits(X86_CR4_SMAP); 330 #endif 331 } 332 } 333 334 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 335 { 336 /* Check the boot processor, plus build option for UMIP. */ 337 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 338 goto out; 339 340 /* Check the current processor's cpuid bits. */ 341 if (!cpu_has(c, X86_FEATURE_UMIP)) 342 goto out; 343 344 cr4_set_bits(X86_CR4_UMIP); 345 346 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); 347 348 return; 349 350 out: 351 /* 352 * Make sure UMIP is disabled in case it was enabled in a 353 * previous boot (e.g., via kexec). 354 */ 355 cr4_clear_bits(X86_CR4_UMIP); 356 } 357 358 /* 359 * Protection Keys are not available in 32-bit mode. 360 */ 361 static bool pku_disabled; 362 363 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 364 { 365 /* check the boot processor, plus compile options for PKU: */ 366 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 367 return; 368 /* checks the actual processor's cpuid bits: */ 369 if (!cpu_has(c, X86_FEATURE_PKU)) 370 return; 371 if (pku_disabled) 372 return; 373 374 cr4_set_bits(X86_CR4_PKE); 375 /* 376 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 377 * cpuid bit to be set. We need to ensure that we 378 * update that bit in this CPU's "cpu_info". 379 */ 380 get_cpu_cap(c); 381 } 382 383 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 384 static __init int setup_disable_pku(char *arg) 385 { 386 /* 387 * Do not clear the X86_FEATURE_PKU bit. All of the 388 * runtime checks are against OSPKE so clearing the 389 * bit does nothing. 390 * 391 * This way, we will see "pku" in cpuinfo, but not 392 * "ospke", which is exactly what we want. It shows 393 * that the CPU has PKU, but the OS has not enabled it. 394 * This happens to be exactly how a system would look 395 * if we disabled the config option. 396 */ 397 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 398 pku_disabled = true; 399 return 1; 400 } 401 __setup("nopku", setup_disable_pku); 402 #endif /* CONFIG_X86_64 */ 403 404 /* 405 * Some CPU features depend on higher CPUID levels, which may not always 406 * be available due to CPUID level capping or broken virtualization 407 * software. Add those features to this table to auto-disable them. 408 */ 409 struct cpuid_dependent_feature { 410 u32 feature; 411 u32 level; 412 }; 413 414 static const struct cpuid_dependent_feature 415 cpuid_dependent_features[] = { 416 { X86_FEATURE_MWAIT, 0x00000005 }, 417 { X86_FEATURE_DCA, 0x00000009 }, 418 { X86_FEATURE_XSAVE, 0x0000000d }, 419 { 0, 0 } 420 }; 421 422 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 423 { 424 const struct cpuid_dependent_feature *df; 425 426 for (df = cpuid_dependent_features; df->feature; df++) { 427 428 if (!cpu_has(c, df->feature)) 429 continue; 430 /* 431 * Note: cpuid_level is set to -1 if unavailable, but 432 * extended_extended_level is set to 0 if unavailable 433 * and the legitimate extended levels are all negative 434 * when signed; hence the weird messing around with 435 * signs here... 436 */ 437 if (!((s32)df->level < 0 ? 438 (u32)df->level > (u32)c->extended_cpuid_level : 439 (s32)df->level > (s32)c->cpuid_level)) 440 continue; 441 442 clear_cpu_cap(c, df->feature); 443 if (!warn) 444 continue; 445 446 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 447 x86_cap_flag(df->feature), df->level); 448 } 449 } 450 451 /* 452 * Naming convention should be: <Name> [(<Codename>)] 453 * This table only is used unless init_<vendor>() below doesn't set it; 454 * in particular, if CPUID levels 0x80000002..4 are supported, this 455 * isn't used 456 */ 457 458 /* Look up CPU names by table lookup. */ 459 static const char *table_lookup_model(struct cpuinfo_x86 *c) 460 { 461 #ifdef CONFIG_X86_32 462 const struct legacy_cpu_model_info *info; 463 464 if (c->x86_model >= 16) 465 return NULL; /* Range check */ 466 467 if (!this_cpu) 468 return NULL; 469 470 info = this_cpu->legacy_models; 471 472 while (info->family) { 473 if (info->family == c->x86) 474 return info->model_names[c->x86_model]; 475 info++; 476 } 477 #endif 478 return NULL; /* Not found */ 479 } 480 481 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 482 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 483 484 void load_percpu_segment(int cpu) 485 { 486 #ifdef CONFIG_X86_32 487 loadsegment(fs, __KERNEL_PERCPU); 488 #else 489 __loadsegment_simple(gs, 0); 490 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 491 #endif 492 load_stack_canary_segment(); 493 } 494 495 #ifdef CONFIG_X86_32 496 /* The 32-bit entry code needs to find cpu_entry_area. */ 497 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 498 #endif 499 500 #ifdef CONFIG_X86_64 501 /* 502 * Special IST stacks which the CPU switches to when it calls 503 * an IST-marked descriptor entry. Up to 7 stacks (hardware 504 * limit), all of them are 4K, except the debug stack which 505 * is 8K. 506 */ 507 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 508 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 509 [DEBUG_STACK - 1] = DEBUG_STKSZ 510 }; 511 #endif 512 513 /* Load the original GDT from the per-cpu structure */ 514 void load_direct_gdt(int cpu) 515 { 516 struct desc_ptr gdt_descr; 517 518 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 519 gdt_descr.size = GDT_SIZE - 1; 520 load_gdt(&gdt_descr); 521 } 522 EXPORT_SYMBOL_GPL(load_direct_gdt); 523 524 /* Load a fixmap remapping of the per-cpu GDT */ 525 void load_fixmap_gdt(int cpu) 526 { 527 struct desc_ptr gdt_descr; 528 529 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 530 gdt_descr.size = GDT_SIZE - 1; 531 load_gdt(&gdt_descr); 532 } 533 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 534 535 /* 536 * Current gdt points %fs at the "master" per-cpu area: after this, 537 * it's on the real one. 538 */ 539 void switch_to_new_gdt(int cpu) 540 { 541 /* Load the original GDT */ 542 load_direct_gdt(cpu); 543 /* Reload the per-cpu base */ 544 load_percpu_segment(cpu); 545 } 546 547 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 548 549 static void get_model_name(struct cpuinfo_x86 *c) 550 { 551 unsigned int *v; 552 char *p, *q, *s; 553 554 if (c->extended_cpuid_level < 0x80000004) 555 return; 556 557 v = (unsigned int *)c->x86_model_id; 558 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 559 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 560 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 561 c->x86_model_id[48] = 0; 562 563 /* Trim whitespace */ 564 p = q = s = &c->x86_model_id[0]; 565 566 while (*p == ' ') 567 p++; 568 569 while (*p) { 570 /* Note the last non-whitespace index */ 571 if (!isspace(*p)) 572 s = q; 573 574 *q++ = *p++; 575 } 576 577 *(s + 1) = '\0'; 578 } 579 580 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 581 { 582 unsigned int n, dummy, ebx, ecx, edx, l2size; 583 584 n = c->extended_cpuid_level; 585 586 if (n >= 0x80000005) { 587 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 588 c->x86_cache_size = (ecx>>24) + (edx>>24); 589 #ifdef CONFIG_X86_64 590 /* On K8 L1 TLB is inclusive, so don't count it */ 591 c->x86_tlbsize = 0; 592 #endif 593 } 594 595 if (n < 0x80000006) /* Some chips just has a large L1. */ 596 return; 597 598 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 599 l2size = ecx >> 16; 600 601 #ifdef CONFIG_X86_64 602 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 603 #else 604 /* do processor-specific cache resizing */ 605 if (this_cpu->legacy_cache_size) 606 l2size = this_cpu->legacy_cache_size(c, l2size); 607 608 /* Allow user to override all this if necessary. */ 609 if (cachesize_override != -1) 610 l2size = cachesize_override; 611 612 if (l2size == 0) 613 return; /* Again, no L2 cache is possible */ 614 #endif 615 616 c->x86_cache_size = l2size; 617 } 618 619 u16 __read_mostly tlb_lli_4k[NR_INFO]; 620 u16 __read_mostly tlb_lli_2m[NR_INFO]; 621 u16 __read_mostly tlb_lli_4m[NR_INFO]; 622 u16 __read_mostly tlb_lld_4k[NR_INFO]; 623 u16 __read_mostly tlb_lld_2m[NR_INFO]; 624 u16 __read_mostly tlb_lld_4m[NR_INFO]; 625 u16 __read_mostly tlb_lld_1g[NR_INFO]; 626 627 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 628 { 629 if (this_cpu->c_detect_tlb) 630 this_cpu->c_detect_tlb(c); 631 632 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 633 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 634 tlb_lli_4m[ENTRIES]); 635 636 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 637 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 638 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 639 } 640 641 void detect_ht(struct cpuinfo_x86 *c) 642 { 643 #ifdef CONFIG_SMP 644 u32 eax, ebx, ecx, edx; 645 int index_msb, core_bits; 646 static bool printed; 647 648 if (!cpu_has(c, X86_FEATURE_HT)) 649 return; 650 651 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 652 goto out; 653 654 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 655 return; 656 657 cpuid(1, &eax, &ebx, &ecx, &edx); 658 659 smp_num_siblings = (ebx & 0xff0000) >> 16; 660 661 if (smp_num_siblings == 1) { 662 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 663 goto out; 664 } 665 666 if (smp_num_siblings <= 1) 667 goto out; 668 669 index_msb = get_count_order(smp_num_siblings); 670 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 671 672 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 673 674 index_msb = get_count_order(smp_num_siblings); 675 676 core_bits = get_count_order(c->x86_max_cores); 677 678 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 679 ((1 << core_bits) - 1); 680 681 out: 682 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 683 pr_info("CPU: Physical Processor ID: %d\n", 684 c->phys_proc_id); 685 pr_info("CPU: Processor Core ID: %d\n", 686 c->cpu_core_id); 687 printed = 1; 688 } 689 #endif 690 } 691 692 static void get_cpu_vendor(struct cpuinfo_x86 *c) 693 { 694 char *v = c->x86_vendor_id; 695 int i; 696 697 for (i = 0; i < X86_VENDOR_NUM; i++) { 698 if (!cpu_devs[i]) 699 break; 700 701 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 702 (cpu_devs[i]->c_ident[1] && 703 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 704 705 this_cpu = cpu_devs[i]; 706 c->x86_vendor = this_cpu->c_x86_vendor; 707 return; 708 } 709 } 710 711 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 712 "CPU: Your system may be unstable.\n", v); 713 714 c->x86_vendor = X86_VENDOR_UNKNOWN; 715 this_cpu = &default_cpu; 716 } 717 718 void cpu_detect(struct cpuinfo_x86 *c) 719 { 720 /* Get vendor name */ 721 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 722 (unsigned int *)&c->x86_vendor_id[0], 723 (unsigned int *)&c->x86_vendor_id[8], 724 (unsigned int *)&c->x86_vendor_id[4]); 725 726 c->x86 = 4; 727 /* Intel-defined flags: level 0x00000001 */ 728 if (c->cpuid_level >= 0x00000001) { 729 u32 junk, tfms, cap0, misc; 730 731 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 732 c->x86 = x86_family(tfms); 733 c->x86_model = x86_model(tfms); 734 c->x86_stepping = x86_stepping(tfms); 735 736 if (cap0 & (1<<19)) { 737 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 738 c->x86_cache_alignment = c->x86_clflush_size; 739 } 740 } 741 } 742 743 static void apply_forced_caps(struct cpuinfo_x86 *c) 744 { 745 int i; 746 747 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 748 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 749 c->x86_capability[i] |= cpu_caps_set[i]; 750 } 751 } 752 753 static void init_speculation_control(struct cpuinfo_x86 *c) 754 { 755 /* 756 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 757 * and they also have a different bit for STIBP support. Also, 758 * a hypervisor might have set the individual AMD bits even on 759 * Intel CPUs, for finer-grained selection of what's available. 760 * 761 * We use the AMD bits in 0x8000_0008 EBX as the generic hardware 762 * features, which are visible in /proc/cpuinfo and used by the 763 * kernel. So set those accordingly from the Intel bits. 764 */ 765 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 766 set_cpu_cap(c, X86_FEATURE_IBRS); 767 set_cpu_cap(c, X86_FEATURE_IBPB); 768 } 769 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 770 set_cpu_cap(c, X86_FEATURE_STIBP); 771 } 772 773 void get_cpu_cap(struct cpuinfo_x86 *c) 774 { 775 u32 eax, ebx, ecx, edx; 776 777 /* Intel-defined flags: level 0x00000001 */ 778 if (c->cpuid_level >= 0x00000001) { 779 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 780 781 c->x86_capability[CPUID_1_ECX] = ecx; 782 c->x86_capability[CPUID_1_EDX] = edx; 783 } 784 785 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 786 if (c->cpuid_level >= 0x00000006) 787 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 788 789 /* Additional Intel-defined flags: level 0x00000007 */ 790 if (c->cpuid_level >= 0x00000007) { 791 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 792 c->x86_capability[CPUID_7_0_EBX] = ebx; 793 c->x86_capability[CPUID_7_ECX] = ecx; 794 c->x86_capability[CPUID_7_EDX] = edx; 795 } 796 797 /* Extended state features: level 0x0000000d */ 798 if (c->cpuid_level >= 0x0000000d) { 799 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 800 801 c->x86_capability[CPUID_D_1_EAX] = eax; 802 } 803 804 /* Additional Intel-defined flags: level 0x0000000F */ 805 if (c->cpuid_level >= 0x0000000F) { 806 807 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 808 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 809 c->x86_capability[CPUID_F_0_EDX] = edx; 810 811 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 812 /* will be overridden if occupancy monitoring exists */ 813 c->x86_cache_max_rmid = ebx; 814 815 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 816 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 817 c->x86_capability[CPUID_F_1_EDX] = edx; 818 819 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 820 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 821 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 822 c->x86_cache_max_rmid = ecx; 823 c->x86_cache_occ_scale = ebx; 824 } 825 } else { 826 c->x86_cache_max_rmid = -1; 827 c->x86_cache_occ_scale = -1; 828 } 829 } 830 831 /* AMD-defined flags: level 0x80000001 */ 832 eax = cpuid_eax(0x80000000); 833 c->extended_cpuid_level = eax; 834 835 if ((eax & 0xffff0000) == 0x80000000) { 836 if (eax >= 0x80000001) { 837 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 838 839 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 840 c->x86_capability[CPUID_8000_0001_EDX] = edx; 841 } 842 } 843 844 if (c->extended_cpuid_level >= 0x80000007) { 845 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 846 847 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 848 c->x86_power = edx; 849 } 850 851 if (c->extended_cpuid_level >= 0x8000000a) 852 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 853 854 init_scattered_cpuid_features(c); 855 init_speculation_control(c); 856 857 /* 858 * Clear/Set all flags overridden by options, after probe. 859 * This needs to happen each time we re-probe, which may happen 860 * several times during CPU initialization. 861 */ 862 apply_forced_caps(c); 863 } 864 865 static void get_cpu_address_sizes(struct cpuinfo_x86 *c) 866 { 867 u32 eax, ebx, ecx, edx; 868 869 if (c->extended_cpuid_level >= 0x80000008) { 870 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 871 872 c->x86_virt_bits = (eax >> 8) & 0xff; 873 c->x86_phys_bits = eax & 0xff; 874 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 875 } 876 #ifdef CONFIG_X86_32 877 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 878 c->x86_phys_bits = 36; 879 #endif 880 } 881 882 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 883 { 884 #ifdef CONFIG_X86_32 885 int i; 886 887 /* 888 * First of all, decide if this is a 486 or higher 889 * It's a 486 if we can modify the AC flag 890 */ 891 if (flag_is_changeable_p(X86_EFLAGS_AC)) 892 c->x86 = 4; 893 else 894 c->x86 = 3; 895 896 for (i = 0; i < X86_VENDOR_NUM; i++) 897 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 898 c->x86_vendor_id[0] = 0; 899 cpu_devs[i]->c_identify(c); 900 if (c->x86_vendor_id[0]) { 901 get_cpu_vendor(c); 902 break; 903 } 904 } 905 #endif 906 } 907 908 static const __initconst struct x86_cpu_id cpu_no_speculation[] = { 909 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, 910 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, 911 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, 912 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, 913 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, 914 { X86_VENDOR_CENTAUR, 5 }, 915 { X86_VENDOR_INTEL, 5 }, 916 { X86_VENDOR_NSC, 5 }, 917 { X86_VENDOR_ANY, 4 }, 918 {} 919 }; 920 921 static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { 922 { X86_VENDOR_AMD }, 923 {} 924 }; 925 926 static bool __init cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c) 927 { 928 u64 ia32_cap = 0; 929 930 if (x86_match_cpu(cpu_no_meltdown)) 931 return false; 932 933 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) 934 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 935 936 /* Rogue Data Cache Load? No! */ 937 if (ia32_cap & ARCH_CAP_RDCL_NO) 938 return false; 939 940 return true; 941 } 942 943 /* 944 * Do minimum CPU detection early. 945 * Fields really needed: vendor, cpuid_level, family, model, mask, 946 * cache alignment. 947 * The others are not touched to avoid unwanted side effects. 948 * 949 * WARNING: this function is only called on the boot CPU. Don't add code 950 * here that is supposed to run on all CPUs. 951 */ 952 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 953 { 954 #ifdef CONFIG_X86_64 955 c->x86_clflush_size = 64; 956 c->x86_phys_bits = 36; 957 c->x86_virt_bits = 48; 958 #else 959 c->x86_clflush_size = 32; 960 c->x86_phys_bits = 32; 961 c->x86_virt_bits = 32; 962 #endif 963 c->x86_cache_alignment = c->x86_clflush_size; 964 965 memset(&c->x86_capability, 0, sizeof c->x86_capability); 966 c->extended_cpuid_level = 0; 967 968 /* cyrix could have cpuid enabled via c_identify()*/ 969 if (have_cpuid_p()) { 970 cpu_detect(c); 971 get_cpu_vendor(c); 972 get_cpu_cap(c); 973 get_cpu_address_sizes(c); 974 setup_force_cpu_cap(X86_FEATURE_CPUID); 975 976 if (this_cpu->c_early_init) 977 this_cpu->c_early_init(c); 978 979 c->cpu_index = 0; 980 filter_cpuid_features(c, false); 981 982 if (this_cpu->c_bsp_init) 983 this_cpu->c_bsp_init(c); 984 } else { 985 identify_cpu_without_cpuid(c); 986 setup_clear_cpu_cap(X86_FEATURE_CPUID); 987 } 988 989 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 990 991 if (!x86_match_cpu(cpu_no_speculation)) { 992 if (cpu_vulnerable_to_meltdown(c)) 993 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 994 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 995 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 996 } 997 998 fpu__init_system(c); 999 1000 #ifdef CONFIG_X86_32 1001 /* 1002 * Regardless of whether PCID is enumerated, the SDM says 1003 * that it can't be enabled in 32-bit mode. 1004 */ 1005 setup_clear_cpu_cap(X86_FEATURE_PCID); 1006 #endif 1007 } 1008 1009 void __init early_cpu_init(void) 1010 { 1011 const struct cpu_dev *const *cdev; 1012 int count = 0; 1013 1014 #ifdef CONFIG_PROCESSOR_SELECT 1015 pr_info("KERNEL supported cpus:\n"); 1016 #endif 1017 1018 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1019 const struct cpu_dev *cpudev = *cdev; 1020 1021 if (count >= X86_VENDOR_NUM) 1022 break; 1023 cpu_devs[count] = cpudev; 1024 count++; 1025 1026 #ifdef CONFIG_PROCESSOR_SELECT 1027 { 1028 unsigned int j; 1029 1030 for (j = 0; j < 2; j++) { 1031 if (!cpudev->c_ident[j]) 1032 continue; 1033 pr_info(" %s %s\n", cpudev->c_vendor, 1034 cpudev->c_ident[j]); 1035 } 1036 } 1037 #endif 1038 } 1039 early_identify_cpu(&boot_cpu_data); 1040 } 1041 1042 /* 1043 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1044 * unfortunately, that's not true in practice because of early VIA 1045 * chips and (more importantly) broken virtualizers that are not easy 1046 * to detect. In the latter case it doesn't even *fail* reliably, so 1047 * probing for it doesn't even work. Disable it completely on 32-bit 1048 * unless we can find a reliable way to detect all the broken cases. 1049 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1050 */ 1051 static void detect_nopl(struct cpuinfo_x86 *c) 1052 { 1053 #ifdef CONFIG_X86_32 1054 clear_cpu_cap(c, X86_FEATURE_NOPL); 1055 #else 1056 set_cpu_cap(c, X86_FEATURE_NOPL); 1057 #endif 1058 } 1059 1060 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1061 { 1062 #ifdef CONFIG_X86_64 1063 /* 1064 * Empirically, writing zero to a segment selector on AMD does 1065 * not clear the base, whereas writing zero to a segment 1066 * selector on Intel does clear the base. Intel's behavior 1067 * allows slightly faster context switches in the common case 1068 * where GS is unused by the prev and next threads. 1069 * 1070 * Since neither vendor documents this anywhere that I can see, 1071 * detect it directly instead of hardcoding the choice by 1072 * vendor. 1073 * 1074 * I've designated AMD's behavior as the "bug" because it's 1075 * counterintuitive and less friendly. 1076 */ 1077 1078 unsigned long old_base, tmp; 1079 rdmsrl(MSR_FS_BASE, old_base); 1080 wrmsrl(MSR_FS_BASE, 1); 1081 loadsegment(fs, 0); 1082 rdmsrl(MSR_FS_BASE, tmp); 1083 if (tmp != 0) 1084 set_cpu_bug(c, X86_BUG_NULL_SEG); 1085 wrmsrl(MSR_FS_BASE, old_base); 1086 #endif 1087 } 1088 1089 static void generic_identify(struct cpuinfo_x86 *c) 1090 { 1091 c->extended_cpuid_level = 0; 1092 1093 if (!have_cpuid_p()) 1094 identify_cpu_without_cpuid(c); 1095 1096 /* cyrix could have cpuid enabled via c_identify()*/ 1097 if (!have_cpuid_p()) 1098 return; 1099 1100 cpu_detect(c); 1101 1102 get_cpu_vendor(c); 1103 1104 get_cpu_cap(c); 1105 1106 get_cpu_address_sizes(c); 1107 1108 if (c->cpuid_level >= 0x00000001) { 1109 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1110 #ifdef CONFIG_X86_32 1111 # ifdef CONFIG_SMP 1112 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1113 # else 1114 c->apicid = c->initial_apicid; 1115 # endif 1116 #endif 1117 c->phys_proc_id = c->initial_apicid; 1118 } 1119 1120 get_model_name(c); /* Default name */ 1121 1122 detect_nopl(c); 1123 1124 detect_null_seg_behavior(c); 1125 1126 /* 1127 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1128 * systems that run Linux at CPL > 0 may or may not have the 1129 * issue, but, even if they have the issue, there's absolutely 1130 * nothing we can do about it because we can't use the real IRET 1131 * instruction. 1132 * 1133 * NB: For the time being, only 32-bit kernels support 1134 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1135 * whether to apply espfix using paravirt hooks. If any 1136 * non-paravirt system ever shows up that does *not* have the 1137 * ESPFIX issue, we can change this. 1138 */ 1139 #ifdef CONFIG_X86_32 1140 # ifdef CONFIG_PARAVIRT 1141 do { 1142 extern void native_iret(void); 1143 if (pv_cpu_ops.iret == native_iret) 1144 set_cpu_bug(c, X86_BUG_ESPFIX); 1145 } while (0); 1146 # else 1147 set_cpu_bug(c, X86_BUG_ESPFIX); 1148 # endif 1149 #endif 1150 } 1151 1152 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1153 { 1154 /* 1155 * The heavy lifting of max_rmid and cache_occ_scale are handled 1156 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1157 * in case CQM bits really aren't there in this CPU. 1158 */ 1159 if (c != &boot_cpu_data) { 1160 boot_cpu_data.x86_cache_max_rmid = 1161 min(boot_cpu_data.x86_cache_max_rmid, 1162 c->x86_cache_max_rmid); 1163 } 1164 } 1165 1166 /* 1167 * Validate that ACPI/mptables have the same information about the 1168 * effective APIC id and update the package map. 1169 */ 1170 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1171 { 1172 #ifdef CONFIG_SMP 1173 unsigned int apicid, cpu = smp_processor_id(); 1174 1175 apicid = apic->cpu_present_to_apicid(cpu); 1176 1177 if (apicid != c->apicid) { 1178 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1179 cpu, apicid, c->initial_apicid); 1180 } 1181 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1182 #else 1183 c->logical_proc_id = 0; 1184 #endif 1185 } 1186 1187 /* 1188 * This does the hard work of actually picking apart the CPU stuff... 1189 */ 1190 static void identify_cpu(struct cpuinfo_x86 *c) 1191 { 1192 int i; 1193 1194 c->loops_per_jiffy = loops_per_jiffy; 1195 c->x86_cache_size = 0; 1196 c->x86_vendor = X86_VENDOR_UNKNOWN; 1197 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1198 c->x86_vendor_id[0] = '\0'; /* Unset */ 1199 c->x86_model_id[0] = '\0'; /* Unset */ 1200 c->x86_max_cores = 1; 1201 c->x86_coreid_bits = 0; 1202 c->cu_id = 0xff; 1203 #ifdef CONFIG_X86_64 1204 c->x86_clflush_size = 64; 1205 c->x86_phys_bits = 36; 1206 c->x86_virt_bits = 48; 1207 #else 1208 c->cpuid_level = -1; /* CPUID not detected */ 1209 c->x86_clflush_size = 32; 1210 c->x86_phys_bits = 32; 1211 c->x86_virt_bits = 32; 1212 #endif 1213 c->x86_cache_alignment = c->x86_clflush_size; 1214 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1215 1216 generic_identify(c); 1217 1218 if (this_cpu->c_identify) 1219 this_cpu->c_identify(c); 1220 1221 /* Clear/Set all flags overridden by options, after probe */ 1222 apply_forced_caps(c); 1223 1224 #ifdef CONFIG_X86_64 1225 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1226 #endif 1227 1228 /* 1229 * Vendor-specific initialization. In this section we 1230 * canonicalize the feature flags, meaning if there are 1231 * features a certain CPU supports which CPUID doesn't 1232 * tell us, CPUID claiming incorrect flags, or other bugs, 1233 * we handle them here. 1234 * 1235 * At the end of this section, c->x86_capability better 1236 * indicate the features this CPU genuinely supports! 1237 */ 1238 if (this_cpu->c_init) 1239 this_cpu->c_init(c); 1240 1241 /* Disable the PN if appropriate */ 1242 squash_the_stupid_serial_number(c); 1243 1244 /* Set up SMEP/SMAP/UMIP */ 1245 setup_smep(c); 1246 setup_smap(c); 1247 setup_umip(c); 1248 1249 /* 1250 * The vendor-specific functions might have changed features. 1251 * Now we do "generic changes." 1252 */ 1253 1254 /* Filter out anything that depends on CPUID levels we don't have */ 1255 filter_cpuid_features(c, true); 1256 1257 /* If the model name is still unset, do table lookup. */ 1258 if (!c->x86_model_id[0]) { 1259 const char *p; 1260 p = table_lookup_model(c); 1261 if (p) 1262 strcpy(c->x86_model_id, p); 1263 else 1264 /* Last resort... */ 1265 sprintf(c->x86_model_id, "%02x/%02x", 1266 c->x86, c->x86_model); 1267 } 1268 1269 #ifdef CONFIG_X86_64 1270 detect_ht(c); 1271 #endif 1272 1273 x86_init_rdrand(c); 1274 x86_init_cache_qos(c); 1275 setup_pku(c); 1276 1277 /* 1278 * Clear/Set all flags overridden by options, need do it 1279 * before following smp all cpus cap AND. 1280 */ 1281 apply_forced_caps(c); 1282 1283 /* 1284 * On SMP, boot_cpu_data holds the common feature set between 1285 * all CPUs; so make sure that we indicate which features are 1286 * common between the CPUs. The first time this routine gets 1287 * executed, c == &boot_cpu_data. 1288 */ 1289 if (c != &boot_cpu_data) { 1290 /* AND the already accumulated flags with these */ 1291 for (i = 0; i < NCAPINTS; i++) 1292 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1293 1294 /* OR, i.e. replicate the bug flags */ 1295 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1296 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1297 } 1298 1299 /* Init Machine Check Exception if available. */ 1300 mcheck_cpu_init(c); 1301 1302 select_idle_routine(c); 1303 1304 #ifdef CONFIG_NUMA 1305 numa_add_cpu(smp_processor_id()); 1306 #endif 1307 } 1308 1309 /* 1310 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1311 * on 32-bit kernels: 1312 */ 1313 #ifdef CONFIG_X86_32 1314 void enable_sep_cpu(void) 1315 { 1316 struct tss_struct *tss; 1317 int cpu; 1318 1319 if (!boot_cpu_has(X86_FEATURE_SEP)) 1320 return; 1321 1322 cpu = get_cpu(); 1323 tss = &per_cpu(cpu_tss_rw, cpu); 1324 1325 /* 1326 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1327 * see the big comment in struct x86_hw_tss's definition. 1328 */ 1329 1330 tss->x86_tss.ss1 = __KERNEL_CS; 1331 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1332 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1333 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1334 1335 put_cpu(); 1336 } 1337 #endif 1338 1339 void __init identify_boot_cpu(void) 1340 { 1341 identify_cpu(&boot_cpu_data); 1342 #ifdef CONFIG_X86_32 1343 sysenter_setup(); 1344 enable_sep_cpu(); 1345 #endif 1346 cpu_detect_tlb(&boot_cpu_data); 1347 } 1348 1349 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1350 { 1351 BUG_ON(c == &boot_cpu_data); 1352 identify_cpu(c); 1353 #ifdef CONFIG_X86_32 1354 enable_sep_cpu(); 1355 #endif 1356 mtrr_ap_init(); 1357 validate_apic_and_package_id(c); 1358 } 1359 1360 static __init int setup_noclflush(char *arg) 1361 { 1362 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1363 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1364 return 1; 1365 } 1366 __setup("noclflush", setup_noclflush); 1367 1368 void print_cpu_info(struct cpuinfo_x86 *c) 1369 { 1370 const char *vendor = NULL; 1371 1372 if (c->x86_vendor < X86_VENDOR_NUM) { 1373 vendor = this_cpu->c_vendor; 1374 } else { 1375 if (c->cpuid_level >= 0) 1376 vendor = c->x86_vendor_id; 1377 } 1378 1379 if (vendor && !strstr(c->x86_model_id, vendor)) 1380 pr_cont("%s ", vendor); 1381 1382 if (c->x86_model_id[0]) 1383 pr_cont("%s", c->x86_model_id); 1384 else 1385 pr_cont("%d86", c->x86); 1386 1387 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1388 1389 if (c->x86_stepping || c->cpuid_level >= 0) 1390 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1391 else 1392 pr_cont(")\n"); 1393 } 1394 1395 /* 1396 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1397 * But we need to keep a dummy __setup around otherwise it would 1398 * show up as an environment variable for init. 1399 */ 1400 static __init int setup_clearcpuid(char *arg) 1401 { 1402 return 1; 1403 } 1404 __setup("clearcpuid=", setup_clearcpuid); 1405 1406 #ifdef CONFIG_X86_64 1407 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1408 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1409 EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union); 1410 1411 /* 1412 * The following percpu variables are hot. Align current_task to 1413 * cacheline size such that they fall in the same cacheline. 1414 */ 1415 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1416 &init_task; 1417 EXPORT_PER_CPU_SYMBOL(current_task); 1418 1419 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1420 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1421 1422 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1423 1424 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1425 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1426 1427 /* May not be marked __init: used by software suspend */ 1428 void syscall_init(void) 1429 { 1430 extern char _entry_trampoline[]; 1431 extern char entry_SYSCALL_64_trampoline[]; 1432 1433 int cpu = smp_processor_id(); 1434 unsigned long SYSCALL64_entry_trampoline = 1435 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + 1436 (entry_SYSCALL_64_trampoline - _entry_trampoline); 1437 1438 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1439 if (static_cpu_has(X86_FEATURE_PTI)) 1440 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); 1441 else 1442 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1443 1444 #ifdef CONFIG_IA32_EMULATION 1445 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1446 /* 1447 * This only works on Intel CPUs. 1448 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1449 * This does not cause SYSENTER to jump to the wrong location, because 1450 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1451 */ 1452 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1453 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 1454 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1455 #else 1456 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1457 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1458 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1459 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1460 #endif 1461 1462 /* Flags to clear on syscall */ 1463 wrmsrl(MSR_SYSCALL_MASK, 1464 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1465 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1466 } 1467 1468 /* 1469 * Copies of the original ist values from the tss are only accessed during 1470 * debugging, no special alignment required. 1471 */ 1472 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1473 1474 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1475 DEFINE_PER_CPU(int, debug_stack_usage); 1476 1477 int is_debug_stack(unsigned long addr) 1478 { 1479 return __this_cpu_read(debug_stack_usage) || 1480 (addr <= __this_cpu_read(debug_stack_addr) && 1481 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1482 } 1483 NOKPROBE_SYMBOL(is_debug_stack); 1484 1485 DEFINE_PER_CPU(u32, debug_idt_ctr); 1486 1487 void debug_stack_set_zero(void) 1488 { 1489 this_cpu_inc(debug_idt_ctr); 1490 load_current_idt(); 1491 } 1492 NOKPROBE_SYMBOL(debug_stack_set_zero); 1493 1494 void debug_stack_reset(void) 1495 { 1496 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1497 return; 1498 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1499 load_current_idt(); 1500 } 1501 NOKPROBE_SYMBOL(debug_stack_reset); 1502 1503 #else /* CONFIG_X86_64 */ 1504 1505 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1506 EXPORT_PER_CPU_SYMBOL(current_task); 1507 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1508 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1509 1510 /* 1511 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1512 * the top of the kernel stack. Use an extra percpu variable to track the 1513 * top of the kernel stack directly. 1514 */ 1515 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1516 (unsigned long)&init_thread_union + THREAD_SIZE; 1517 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1518 1519 #ifdef CONFIG_CC_STACKPROTECTOR 1520 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1521 #endif 1522 1523 #endif /* CONFIG_X86_64 */ 1524 1525 /* 1526 * Clear all 6 debug registers: 1527 */ 1528 static void clear_all_debug_regs(void) 1529 { 1530 int i; 1531 1532 for (i = 0; i < 8; i++) { 1533 /* Ignore db4, db5 */ 1534 if ((i == 4) || (i == 5)) 1535 continue; 1536 1537 set_debugreg(0, i); 1538 } 1539 } 1540 1541 #ifdef CONFIG_KGDB 1542 /* 1543 * Restore debug regs if using kgdbwait and you have a kernel debugger 1544 * connection established. 1545 */ 1546 static void dbg_restore_debug_regs(void) 1547 { 1548 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1549 arch_kgdb_ops.correct_hw_break(); 1550 } 1551 #else /* ! CONFIG_KGDB */ 1552 #define dbg_restore_debug_regs() 1553 #endif /* ! CONFIG_KGDB */ 1554 1555 static void wait_for_master_cpu(int cpu) 1556 { 1557 #ifdef CONFIG_SMP 1558 /* 1559 * wait for ACK from master CPU before continuing 1560 * with AP initialization 1561 */ 1562 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1563 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1564 cpu_relax(); 1565 #endif 1566 } 1567 1568 /* 1569 * cpu_init() initializes state that is per-CPU. Some data is already 1570 * initialized (naturally) in the bootstrap process, such as the GDT 1571 * and IDT. We reload them nevertheless, this function acts as a 1572 * 'CPU state barrier', nothing should get across. 1573 * A lot of state is already set up in PDA init for 64 bit 1574 */ 1575 #ifdef CONFIG_X86_64 1576 1577 void cpu_init(void) 1578 { 1579 struct orig_ist *oist; 1580 struct task_struct *me; 1581 struct tss_struct *t; 1582 unsigned long v; 1583 int cpu = raw_smp_processor_id(); 1584 int i; 1585 1586 wait_for_master_cpu(cpu); 1587 1588 /* 1589 * Initialize the CR4 shadow before doing anything that could 1590 * try to read it. 1591 */ 1592 cr4_init_shadow(); 1593 1594 if (cpu) 1595 load_ucode_ap(); 1596 1597 t = &per_cpu(cpu_tss_rw, cpu); 1598 oist = &per_cpu(orig_ist, cpu); 1599 1600 #ifdef CONFIG_NUMA 1601 if (this_cpu_read(numa_node) == 0 && 1602 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1603 set_numa_node(early_cpu_to_node(cpu)); 1604 #endif 1605 1606 me = current; 1607 1608 pr_debug("Initializing CPU#%d\n", cpu); 1609 1610 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1611 1612 /* 1613 * Initialize the per-CPU GDT with the boot GDT, 1614 * and set up the GDT descriptor: 1615 */ 1616 1617 switch_to_new_gdt(cpu); 1618 loadsegment(fs, 0); 1619 1620 load_current_idt(); 1621 1622 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1623 syscall_init(); 1624 1625 wrmsrl(MSR_FS_BASE, 0); 1626 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1627 barrier(); 1628 1629 x86_configure_nx(); 1630 x2apic_setup(); 1631 1632 /* 1633 * set up and load the per-CPU TSS 1634 */ 1635 if (!oist->ist[0]) { 1636 char *estacks = get_cpu_entry_area(cpu)->exception_stacks; 1637 1638 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1639 estacks += exception_stack_sizes[v]; 1640 oist->ist[v] = t->x86_tss.ist[v] = 1641 (unsigned long)estacks; 1642 if (v == DEBUG_STACK-1) 1643 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1644 } 1645 } 1646 1647 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1648 1649 /* 1650 * <= is required because the CPU will access up to 1651 * 8 bits beyond the end of the IO permission bitmap. 1652 */ 1653 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1654 t->io_bitmap[i] = ~0UL; 1655 1656 mmgrab(&init_mm); 1657 me->active_mm = &init_mm; 1658 BUG_ON(me->mm); 1659 initialize_tlbstate_and_flush(); 1660 enter_lazy_tlb(&init_mm, me); 1661 1662 /* 1663 * Initialize the TSS. sp0 points to the entry trampoline stack 1664 * regardless of what task is running. 1665 */ 1666 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1667 load_TR_desc(); 1668 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1669 1670 load_mm_ldt(&init_mm); 1671 1672 clear_all_debug_regs(); 1673 dbg_restore_debug_regs(); 1674 1675 fpu__init_cpu(); 1676 1677 if (is_uv_system()) 1678 uv_cpu_init(); 1679 1680 load_fixmap_gdt(cpu); 1681 } 1682 1683 #else 1684 1685 void cpu_init(void) 1686 { 1687 int cpu = smp_processor_id(); 1688 struct task_struct *curr = current; 1689 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1690 1691 wait_for_master_cpu(cpu); 1692 1693 /* 1694 * Initialize the CR4 shadow before doing anything that could 1695 * try to read it. 1696 */ 1697 cr4_init_shadow(); 1698 1699 show_ucode_info_early(); 1700 1701 pr_info("Initializing CPU#%d\n", cpu); 1702 1703 if (cpu_feature_enabled(X86_FEATURE_VME) || 1704 boot_cpu_has(X86_FEATURE_TSC) || 1705 boot_cpu_has(X86_FEATURE_DE)) 1706 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1707 1708 load_current_idt(); 1709 switch_to_new_gdt(cpu); 1710 1711 /* 1712 * Set up and load the per-CPU TSS and LDT 1713 */ 1714 mmgrab(&init_mm); 1715 curr->active_mm = &init_mm; 1716 BUG_ON(curr->mm); 1717 initialize_tlbstate_and_flush(); 1718 enter_lazy_tlb(&init_mm, curr); 1719 1720 /* 1721 * Initialize the TSS. Don't bother initializing sp0, as the initial 1722 * task never enters user mode. 1723 */ 1724 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1725 load_TR_desc(); 1726 1727 load_mm_ldt(&init_mm); 1728 1729 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1730 1731 #ifdef CONFIG_DOUBLEFAULT 1732 /* Set up doublefault TSS pointer in the GDT */ 1733 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1734 #endif 1735 1736 clear_all_debug_regs(); 1737 dbg_restore_debug_regs(); 1738 1739 fpu__init_cpu(); 1740 1741 load_fixmap_gdt(cpu); 1742 } 1743 #endif 1744 1745 static void bsp_resume(void) 1746 { 1747 if (this_cpu->c_bsp_resume) 1748 this_cpu->c_bsp_resume(&boot_cpu_data); 1749 } 1750 1751 static struct syscore_ops cpu_syscore_ops = { 1752 .resume = bsp_resume, 1753 }; 1754 1755 static int __init init_cpu_syscore(void) 1756 { 1757 register_syscore_ops(&cpu_syscore_ops); 1758 return 0; 1759 } 1760 core_initcall(init_cpu_syscore); 1761 1762 /* 1763 * The microcode loader calls this upon late microcode load to recheck features, 1764 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1765 * hotplug lock. 1766 */ 1767 void microcode_check(void) 1768 { 1769 struct cpuinfo_x86 info; 1770 1771 perf_check_microcode(); 1772 1773 /* Reload CPUID max function as it might've changed. */ 1774 info.cpuid_level = cpuid_eax(0); 1775 1776 /* 1777 * Copy all capability leafs to pick up the synthetic ones so that 1778 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1779 * get overwritten in get_cpu_cap(). 1780 */ 1781 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1782 1783 get_cpu_cap(&info); 1784 1785 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1786 return; 1787 1788 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1789 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1790 } 1791