1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kprobes.h> 12 #include <linux/kgdb.h> 13 #include <linux/smp.h> 14 #include <linux/io.h> 15 16 #include <asm/stackprotector.h> 17 #include <asm/perf_event.h> 18 #include <asm/mmu_context.h> 19 #include <asm/archrandom.h> 20 #include <asm/hypervisor.h> 21 #include <asm/processor.h> 22 #include <asm/debugreg.h> 23 #include <asm/sections.h> 24 #include <asm/vsyscall.h> 25 #include <linux/topology.h> 26 #include <linux/cpumask.h> 27 #include <asm/pgtable.h> 28 #include <linux/atomic.h> 29 #include <asm/proto.h> 30 #include <asm/setup.h> 31 #include <asm/apic.h> 32 #include <asm/desc.h> 33 #include <asm/i387.h> 34 #include <asm/fpu-internal.h> 35 #include <asm/mtrr.h> 36 #include <linux/numa.h> 37 #include <asm/asm.h> 38 #include <asm/cpu.h> 39 #include <asm/mce.h> 40 #include <asm/msr.h> 41 #include <asm/pat.h> 42 #include <asm/microcode.h> 43 #include <asm/microcode_intel.h> 44 45 #ifdef CONFIG_X86_LOCAL_APIC 46 #include <asm/uv/uv.h> 47 #endif 48 49 #include "cpu.h" 50 51 /* all of these masks are initialized in setup_cpu_local_masks() */ 52 cpumask_var_t cpu_initialized_mask; 53 cpumask_var_t cpu_callout_mask; 54 cpumask_var_t cpu_callin_mask; 55 56 /* representing cpus for which sibling maps can be computed */ 57 cpumask_var_t cpu_sibling_setup_mask; 58 59 /* correctly size the local cpu masks */ 60 void __init setup_cpu_local_masks(void) 61 { 62 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 63 alloc_bootmem_cpumask_var(&cpu_callin_mask); 64 alloc_bootmem_cpumask_var(&cpu_callout_mask); 65 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 66 } 67 68 static void default_init(struct cpuinfo_x86 *c) 69 { 70 #ifdef CONFIG_X86_64 71 cpu_detect_cache_sizes(c); 72 #else 73 /* Not much we can do here... */ 74 /* Check if at least it has cpuid */ 75 if (c->cpuid_level == -1) { 76 /* No cpuid. It must be an ancient CPU */ 77 if (c->x86 == 4) 78 strcpy(c->x86_model_id, "486"); 79 else if (c->x86 == 3) 80 strcpy(c->x86_model_id, "386"); 81 } 82 #endif 83 } 84 85 static const struct cpu_dev default_cpu = { 86 .c_init = default_init, 87 .c_vendor = "Unknown", 88 .c_x86_vendor = X86_VENDOR_UNKNOWN, 89 }; 90 91 static const struct cpu_dev *this_cpu = &default_cpu; 92 93 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 94 #ifdef CONFIG_X86_64 95 /* 96 * We need valid kernel segments for data and code in long mode too 97 * IRET will check the segment types kkeil 2000/10/28 98 * Also sysret mandates a special GDT layout 99 * 100 * TLS descriptors are currently at a different place compared to i386. 101 * Hopefully nobody expects them at a fixed place (Wine?) 102 */ 103 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 104 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 105 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 106 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 107 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 109 #else 110 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 111 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 112 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 113 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 114 /* 115 * Segments used for calling PnP BIOS have byte granularity. 116 * They code segments and data segments have fixed 64k limits, 117 * the transfer segment sizes are set at run time. 118 */ 119 /* 32-bit code */ 120 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 121 /* 16-bit code */ 122 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 123 /* 16-bit data */ 124 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 125 /* 16-bit data */ 126 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 127 /* 16-bit data */ 128 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 129 /* 130 * The APM segments have byte granularity and their bases 131 * are set at run time. All have 64k limits. 132 */ 133 /* 32-bit code */ 134 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 135 /* 16-bit code */ 136 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 137 /* data */ 138 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 139 140 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 141 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 142 GDT_STACK_CANARY_INIT 143 #endif 144 } }; 145 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 146 147 static int __init x86_xsave_setup(char *s) 148 { 149 if (strlen(s)) 150 return 0; 151 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 152 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 153 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 154 setup_clear_cpu_cap(X86_FEATURE_AVX); 155 setup_clear_cpu_cap(X86_FEATURE_AVX2); 156 return 1; 157 } 158 __setup("noxsave", x86_xsave_setup); 159 160 static int __init x86_xsaveopt_setup(char *s) 161 { 162 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 163 return 1; 164 } 165 __setup("noxsaveopt", x86_xsaveopt_setup); 166 167 static int __init x86_xsaves_setup(char *s) 168 { 169 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 170 return 1; 171 } 172 __setup("noxsaves", x86_xsaves_setup); 173 174 #ifdef CONFIG_X86_32 175 static int cachesize_override = -1; 176 static int disable_x86_serial_nr = 1; 177 178 static int __init cachesize_setup(char *str) 179 { 180 get_option(&str, &cachesize_override); 181 return 1; 182 } 183 __setup("cachesize=", cachesize_setup); 184 185 static int __init x86_fxsr_setup(char *s) 186 { 187 setup_clear_cpu_cap(X86_FEATURE_FXSR); 188 setup_clear_cpu_cap(X86_FEATURE_XMM); 189 return 1; 190 } 191 __setup("nofxsr", x86_fxsr_setup); 192 193 static int __init x86_sep_setup(char *s) 194 { 195 setup_clear_cpu_cap(X86_FEATURE_SEP); 196 return 1; 197 } 198 __setup("nosep", x86_sep_setup); 199 200 /* Standard macro to see if a specific flag is changeable */ 201 static inline int flag_is_changeable_p(u32 flag) 202 { 203 u32 f1, f2; 204 205 /* 206 * Cyrix and IDT cpus allow disabling of CPUID 207 * so the code below may return different results 208 * when it is executed before and after enabling 209 * the CPUID. Add "volatile" to not allow gcc to 210 * optimize the subsequent calls to this function. 211 */ 212 asm volatile ("pushfl \n\t" 213 "pushfl \n\t" 214 "popl %0 \n\t" 215 "movl %0, %1 \n\t" 216 "xorl %2, %0 \n\t" 217 "pushl %0 \n\t" 218 "popfl \n\t" 219 "pushfl \n\t" 220 "popl %0 \n\t" 221 "popfl \n\t" 222 223 : "=&r" (f1), "=&r" (f2) 224 : "ir" (flag)); 225 226 return ((f1^f2) & flag) != 0; 227 } 228 229 /* Probe for the CPUID instruction */ 230 int have_cpuid_p(void) 231 { 232 return flag_is_changeable_p(X86_EFLAGS_ID); 233 } 234 235 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 236 { 237 unsigned long lo, hi; 238 239 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 240 return; 241 242 /* Disable processor serial number: */ 243 244 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 245 lo |= 0x200000; 246 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 247 248 printk(KERN_NOTICE "CPU serial number disabled.\n"); 249 clear_cpu_cap(c, X86_FEATURE_PN); 250 251 /* Disabling the serial number may affect the cpuid level */ 252 c->cpuid_level = cpuid_eax(0); 253 } 254 255 static int __init x86_serial_nr_setup(char *s) 256 { 257 disable_x86_serial_nr = 0; 258 return 1; 259 } 260 __setup("serialnumber", x86_serial_nr_setup); 261 #else 262 static inline int flag_is_changeable_p(u32 flag) 263 { 264 return 1; 265 } 266 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 267 { 268 } 269 #endif 270 271 static __init int setup_disable_smep(char *arg) 272 { 273 setup_clear_cpu_cap(X86_FEATURE_SMEP); 274 return 1; 275 } 276 __setup("nosmep", setup_disable_smep); 277 278 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 279 { 280 if (cpu_has(c, X86_FEATURE_SMEP)) 281 set_in_cr4(X86_CR4_SMEP); 282 } 283 284 static __init int setup_disable_smap(char *arg) 285 { 286 setup_clear_cpu_cap(X86_FEATURE_SMAP); 287 return 1; 288 } 289 __setup("nosmap", setup_disable_smap); 290 291 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 292 { 293 unsigned long eflags; 294 295 /* This should have been cleared long ago */ 296 raw_local_save_flags(eflags); 297 BUG_ON(eflags & X86_EFLAGS_AC); 298 299 if (cpu_has(c, X86_FEATURE_SMAP)) { 300 #ifdef CONFIG_X86_SMAP 301 set_in_cr4(X86_CR4_SMAP); 302 #else 303 clear_in_cr4(X86_CR4_SMAP); 304 #endif 305 } 306 } 307 308 /* 309 * Some CPU features depend on higher CPUID levels, which may not always 310 * be available due to CPUID level capping or broken virtualization 311 * software. Add those features to this table to auto-disable them. 312 */ 313 struct cpuid_dependent_feature { 314 u32 feature; 315 u32 level; 316 }; 317 318 static const struct cpuid_dependent_feature 319 cpuid_dependent_features[] = { 320 { X86_FEATURE_MWAIT, 0x00000005 }, 321 { X86_FEATURE_DCA, 0x00000009 }, 322 { X86_FEATURE_XSAVE, 0x0000000d }, 323 { 0, 0 } 324 }; 325 326 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 327 { 328 const struct cpuid_dependent_feature *df; 329 330 for (df = cpuid_dependent_features; df->feature; df++) { 331 332 if (!cpu_has(c, df->feature)) 333 continue; 334 /* 335 * Note: cpuid_level is set to -1 if unavailable, but 336 * extended_extended_level is set to 0 if unavailable 337 * and the legitimate extended levels are all negative 338 * when signed; hence the weird messing around with 339 * signs here... 340 */ 341 if (!((s32)df->level < 0 ? 342 (u32)df->level > (u32)c->extended_cpuid_level : 343 (s32)df->level > (s32)c->cpuid_level)) 344 continue; 345 346 clear_cpu_cap(c, df->feature); 347 if (!warn) 348 continue; 349 350 printk(KERN_WARNING 351 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 352 x86_cap_flag(df->feature), df->level); 353 } 354 } 355 356 /* 357 * Naming convention should be: <Name> [(<Codename>)] 358 * This table only is used unless init_<vendor>() below doesn't set it; 359 * in particular, if CPUID levels 0x80000002..4 are supported, this 360 * isn't used 361 */ 362 363 /* Look up CPU names by table lookup. */ 364 static const char *table_lookup_model(struct cpuinfo_x86 *c) 365 { 366 #ifdef CONFIG_X86_32 367 const struct legacy_cpu_model_info *info; 368 369 if (c->x86_model >= 16) 370 return NULL; /* Range check */ 371 372 if (!this_cpu) 373 return NULL; 374 375 info = this_cpu->legacy_models; 376 377 while (info->family) { 378 if (info->family == c->x86) 379 return info->model_names[c->x86_model]; 380 info++; 381 } 382 #endif 383 return NULL; /* Not found */ 384 } 385 386 __u32 cpu_caps_cleared[NCAPINTS]; 387 __u32 cpu_caps_set[NCAPINTS]; 388 389 void load_percpu_segment(int cpu) 390 { 391 #ifdef CONFIG_X86_32 392 loadsegment(fs, __KERNEL_PERCPU); 393 #else 394 loadsegment(gs, 0); 395 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 396 #endif 397 load_stack_canary_segment(); 398 } 399 400 /* 401 * Current gdt points %fs at the "master" per-cpu area: after this, 402 * it's on the real one. 403 */ 404 void switch_to_new_gdt(int cpu) 405 { 406 struct desc_ptr gdt_descr; 407 408 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 409 gdt_descr.size = GDT_SIZE - 1; 410 load_gdt(&gdt_descr); 411 /* Reload the per-cpu base */ 412 413 load_percpu_segment(cpu); 414 } 415 416 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 417 418 static void get_model_name(struct cpuinfo_x86 *c) 419 { 420 unsigned int *v; 421 char *p, *q; 422 423 if (c->extended_cpuid_level < 0x80000004) 424 return; 425 426 v = (unsigned int *)c->x86_model_id; 427 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 428 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 429 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 430 c->x86_model_id[48] = 0; 431 432 /* 433 * Intel chips right-justify this string for some dumb reason; 434 * undo that brain damage: 435 */ 436 p = q = &c->x86_model_id[0]; 437 while (*p == ' ') 438 p++; 439 if (p != q) { 440 while (*p) 441 *q++ = *p++; 442 while (q <= &c->x86_model_id[48]) 443 *q++ = '\0'; /* Zero-pad the rest */ 444 } 445 } 446 447 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 448 { 449 unsigned int n, dummy, ebx, ecx, edx, l2size; 450 451 n = c->extended_cpuid_level; 452 453 if (n >= 0x80000005) { 454 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 455 c->x86_cache_size = (ecx>>24) + (edx>>24); 456 #ifdef CONFIG_X86_64 457 /* On K8 L1 TLB is inclusive, so don't count it */ 458 c->x86_tlbsize = 0; 459 #endif 460 } 461 462 if (n < 0x80000006) /* Some chips just has a large L1. */ 463 return; 464 465 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 466 l2size = ecx >> 16; 467 468 #ifdef CONFIG_X86_64 469 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 470 #else 471 /* do processor-specific cache resizing */ 472 if (this_cpu->legacy_cache_size) 473 l2size = this_cpu->legacy_cache_size(c, l2size); 474 475 /* Allow user to override all this if necessary. */ 476 if (cachesize_override != -1) 477 l2size = cachesize_override; 478 479 if (l2size == 0) 480 return; /* Again, no L2 cache is possible */ 481 #endif 482 483 c->x86_cache_size = l2size; 484 } 485 486 u16 __read_mostly tlb_lli_4k[NR_INFO]; 487 u16 __read_mostly tlb_lli_2m[NR_INFO]; 488 u16 __read_mostly tlb_lli_4m[NR_INFO]; 489 u16 __read_mostly tlb_lld_4k[NR_INFO]; 490 u16 __read_mostly tlb_lld_2m[NR_INFO]; 491 u16 __read_mostly tlb_lld_4m[NR_INFO]; 492 u16 __read_mostly tlb_lld_1g[NR_INFO]; 493 494 void cpu_detect_tlb(struct cpuinfo_x86 *c) 495 { 496 if (this_cpu->c_detect_tlb) 497 this_cpu->c_detect_tlb(c); 498 499 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" 500 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 501 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 502 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], 503 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], 504 tlb_lld_1g[ENTRIES]); 505 } 506 507 void detect_ht(struct cpuinfo_x86 *c) 508 { 509 #ifdef CONFIG_X86_HT 510 u32 eax, ebx, ecx, edx; 511 int index_msb, core_bits; 512 static bool printed; 513 514 if (!cpu_has(c, X86_FEATURE_HT)) 515 return; 516 517 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 518 goto out; 519 520 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 521 return; 522 523 cpuid(1, &eax, &ebx, &ecx, &edx); 524 525 smp_num_siblings = (ebx & 0xff0000) >> 16; 526 527 if (smp_num_siblings == 1) { 528 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 529 goto out; 530 } 531 532 if (smp_num_siblings <= 1) 533 goto out; 534 535 index_msb = get_count_order(smp_num_siblings); 536 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 537 538 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 539 540 index_msb = get_count_order(smp_num_siblings); 541 542 core_bits = get_count_order(c->x86_max_cores); 543 544 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 545 ((1 << core_bits) - 1); 546 547 out: 548 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 549 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 550 c->phys_proc_id); 551 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 552 c->cpu_core_id); 553 printed = 1; 554 } 555 #endif 556 } 557 558 static void get_cpu_vendor(struct cpuinfo_x86 *c) 559 { 560 char *v = c->x86_vendor_id; 561 int i; 562 563 for (i = 0; i < X86_VENDOR_NUM; i++) { 564 if (!cpu_devs[i]) 565 break; 566 567 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 568 (cpu_devs[i]->c_ident[1] && 569 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 570 571 this_cpu = cpu_devs[i]; 572 c->x86_vendor = this_cpu->c_x86_vendor; 573 return; 574 } 575 } 576 577 printk_once(KERN_ERR 578 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 579 "CPU: Your system may be unstable.\n", v); 580 581 c->x86_vendor = X86_VENDOR_UNKNOWN; 582 this_cpu = &default_cpu; 583 } 584 585 void cpu_detect(struct cpuinfo_x86 *c) 586 { 587 /* Get vendor name */ 588 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 589 (unsigned int *)&c->x86_vendor_id[0], 590 (unsigned int *)&c->x86_vendor_id[8], 591 (unsigned int *)&c->x86_vendor_id[4]); 592 593 c->x86 = 4; 594 /* Intel-defined flags: level 0x00000001 */ 595 if (c->cpuid_level >= 0x00000001) { 596 u32 junk, tfms, cap0, misc; 597 598 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 599 c->x86 = (tfms >> 8) & 0xf; 600 c->x86_model = (tfms >> 4) & 0xf; 601 c->x86_mask = tfms & 0xf; 602 603 if (c->x86 == 0xf) 604 c->x86 += (tfms >> 20) & 0xff; 605 if (c->x86 >= 0x6) 606 c->x86_model += ((tfms >> 16) & 0xf) << 4; 607 608 if (cap0 & (1<<19)) { 609 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 610 c->x86_cache_alignment = c->x86_clflush_size; 611 } 612 } 613 } 614 615 void get_cpu_cap(struct cpuinfo_x86 *c) 616 { 617 u32 tfms, xlvl; 618 u32 ebx; 619 620 /* Intel-defined flags: level 0x00000001 */ 621 if (c->cpuid_level >= 0x00000001) { 622 u32 capability, excap; 623 624 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 625 c->x86_capability[0] = capability; 626 c->x86_capability[4] = excap; 627 } 628 629 /* Additional Intel-defined flags: level 0x00000007 */ 630 if (c->cpuid_level >= 0x00000007) { 631 u32 eax, ebx, ecx, edx; 632 633 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 634 635 c->x86_capability[9] = ebx; 636 } 637 638 /* Extended state features: level 0x0000000d */ 639 if (c->cpuid_level >= 0x0000000d) { 640 u32 eax, ebx, ecx, edx; 641 642 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 643 644 c->x86_capability[10] = eax; 645 } 646 647 /* AMD-defined flags: level 0x80000001 */ 648 xlvl = cpuid_eax(0x80000000); 649 c->extended_cpuid_level = xlvl; 650 651 if ((xlvl & 0xffff0000) == 0x80000000) { 652 if (xlvl >= 0x80000001) { 653 c->x86_capability[1] = cpuid_edx(0x80000001); 654 c->x86_capability[6] = cpuid_ecx(0x80000001); 655 } 656 } 657 658 if (c->extended_cpuid_level >= 0x80000008) { 659 u32 eax = cpuid_eax(0x80000008); 660 661 c->x86_virt_bits = (eax >> 8) & 0xff; 662 c->x86_phys_bits = eax & 0xff; 663 } 664 #ifdef CONFIG_X86_32 665 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 666 c->x86_phys_bits = 36; 667 #endif 668 669 if (c->extended_cpuid_level >= 0x80000007) 670 c->x86_power = cpuid_edx(0x80000007); 671 672 init_scattered_cpuid_features(c); 673 } 674 675 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 676 { 677 #ifdef CONFIG_X86_32 678 int i; 679 680 /* 681 * First of all, decide if this is a 486 or higher 682 * It's a 486 if we can modify the AC flag 683 */ 684 if (flag_is_changeable_p(X86_EFLAGS_AC)) 685 c->x86 = 4; 686 else 687 c->x86 = 3; 688 689 for (i = 0; i < X86_VENDOR_NUM; i++) 690 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 691 c->x86_vendor_id[0] = 0; 692 cpu_devs[i]->c_identify(c); 693 if (c->x86_vendor_id[0]) { 694 get_cpu_vendor(c); 695 break; 696 } 697 } 698 #endif 699 } 700 701 /* 702 * Do minimum CPU detection early. 703 * Fields really needed: vendor, cpuid_level, family, model, mask, 704 * cache alignment. 705 * The others are not touched to avoid unwanted side effects. 706 * 707 * WARNING: this function is only called on the BP. Don't add code here 708 * that is supposed to run on all CPUs. 709 */ 710 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 711 { 712 #ifdef CONFIG_X86_64 713 c->x86_clflush_size = 64; 714 c->x86_phys_bits = 36; 715 c->x86_virt_bits = 48; 716 #else 717 c->x86_clflush_size = 32; 718 c->x86_phys_bits = 32; 719 c->x86_virt_bits = 32; 720 #endif 721 c->x86_cache_alignment = c->x86_clflush_size; 722 723 memset(&c->x86_capability, 0, sizeof c->x86_capability); 724 c->extended_cpuid_level = 0; 725 726 if (!have_cpuid_p()) 727 identify_cpu_without_cpuid(c); 728 729 /* cyrix could have cpuid enabled via c_identify()*/ 730 if (!have_cpuid_p()) 731 return; 732 733 cpu_detect(c); 734 get_cpu_vendor(c); 735 get_cpu_cap(c); 736 fpu_detect(c); 737 738 if (this_cpu->c_early_init) 739 this_cpu->c_early_init(c); 740 741 c->cpu_index = 0; 742 filter_cpuid_features(c, false); 743 744 if (this_cpu->c_bsp_init) 745 this_cpu->c_bsp_init(c); 746 747 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 748 } 749 750 void __init early_cpu_init(void) 751 { 752 const struct cpu_dev *const *cdev; 753 int count = 0; 754 755 #ifdef CONFIG_PROCESSOR_SELECT 756 printk(KERN_INFO "KERNEL supported cpus:\n"); 757 #endif 758 759 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 760 const struct cpu_dev *cpudev = *cdev; 761 762 if (count >= X86_VENDOR_NUM) 763 break; 764 cpu_devs[count] = cpudev; 765 count++; 766 767 #ifdef CONFIG_PROCESSOR_SELECT 768 { 769 unsigned int j; 770 771 for (j = 0; j < 2; j++) { 772 if (!cpudev->c_ident[j]) 773 continue; 774 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 775 cpudev->c_ident[j]); 776 } 777 } 778 #endif 779 } 780 early_identify_cpu(&boot_cpu_data); 781 } 782 783 /* 784 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 785 * unfortunately, that's not true in practice because of early VIA 786 * chips and (more importantly) broken virtualizers that are not easy 787 * to detect. In the latter case it doesn't even *fail* reliably, so 788 * probing for it doesn't even work. Disable it completely on 32-bit 789 * unless we can find a reliable way to detect all the broken cases. 790 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 791 */ 792 static void detect_nopl(struct cpuinfo_x86 *c) 793 { 794 #ifdef CONFIG_X86_32 795 clear_cpu_cap(c, X86_FEATURE_NOPL); 796 #else 797 set_cpu_cap(c, X86_FEATURE_NOPL); 798 #endif 799 } 800 801 static void generic_identify(struct cpuinfo_x86 *c) 802 { 803 c->extended_cpuid_level = 0; 804 805 if (!have_cpuid_p()) 806 identify_cpu_without_cpuid(c); 807 808 /* cyrix could have cpuid enabled via c_identify()*/ 809 if (!have_cpuid_p()) 810 return; 811 812 cpu_detect(c); 813 814 get_cpu_vendor(c); 815 816 get_cpu_cap(c); 817 818 if (c->cpuid_level >= 0x00000001) { 819 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 820 #ifdef CONFIG_X86_32 821 # ifdef CONFIG_X86_HT 822 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 823 # else 824 c->apicid = c->initial_apicid; 825 # endif 826 #endif 827 c->phys_proc_id = c->initial_apicid; 828 } 829 830 get_model_name(c); /* Default name */ 831 832 detect_nopl(c); 833 } 834 835 /* 836 * This does the hard work of actually picking apart the CPU stuff... 837 */ 838 static void identify_cpu(struct cpuinfo_x86 *c) 839 { 840 int i; 841 842 c->loops_per_jiffy = loops_per_jiffy; 843 c->x86_cache_size = -1; 844 c->x86_vendor = X86_VENDOR_UNKNOWN; 845 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 846 c->x86_vendor_id[0] = '\0'; /* Unset */ 847 c->x86_model_id[0] = '\0'; /* Unset */ 848 c->x86_max_cores = 1; 849 c->x86_coreid_bits = 0; 850 #ifdef CONFIG_X86_64 851 c->x86_clflush_size = 64; 852 c->x86_phys_bits = 36; 853 c->x86_virt_bits = 48; 854 #else 855 c->cpuid_level = -1; /* CPUID not detected */ 856 c->x86_clflush_size = 32; 857 c->x86_phys_bits = 32; 858 c->x86_virt_bits = 32; 859 #endif 860 c->x86_cache_alignment = c->x86_clflush_size; 861 memset(&c->x86_capability, 0, sizeof c->x86_capability); 862 863 generic_identify(c); 864 865 if (this_cpu->c_identify) 866 this_cpu->c_identify(c); 867 868 /* Clear/Set all flags overriden by options, after probe */ 869 for (i = 0; i < NCAPINTS; i++) { 870 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 871 c->x86_capability[i] |= cpu_caps_set[i]; 872 } 873 874 #ifdef CONFIG_X86_64 875 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 876 #endif 877 878 /* 879 * Vendor-specific initialization. In this section we 880 * canonicalize the feature flags, meaning if there are 881 * features a certain CPU supports which CPUID doesn't 882 * tell us, CPUID claiming incorrect flags, or other bugs, 883 * we handle them here. 884 * 885 * At the end of this section, c->x86_capability better 886 * indicate the features this CPU genuinely supports! 887 */ 888 if (this_cpu->c_init) 889 this_cpu->c_init(c); 890 891 /* Disable the PN if appropriate */ 892 squash_the_stupid_serial_number(c); 893 894 /* Set up SMEP/SMAP */ 895 setup_smep(c); 896 setup_smap(c); 897 898 /* 899 * The vendor-specific functions might have changed features. 900 * Now we do "generic changes." 901 */ 902 903 /* Filter out anything that depends on CPUID levels we don't have */ 904 filter_cpuid_features(c, true); 905 906 /* If the model name is still unset, do table lookup. */ 907 if (!c->x86_model_id[0]) { 908 const char *p; 909 p = table_lookup_model(c); 910 if (p) 911 strcpy(c->x86_model_id, p); 912 else 913 /* Last resort... */ 914 sprintf(c->x86_model_id, "%02x/%02x", 915 c->x86, c->x86_model); 916 } 917 918 #ifdef CONFIG_X86_64 919 detect_ht(c); 920 #endif 921 922 init_hypervisor(c); 923 x86_init_rdrand(c); 924 925 /* 926 * Clear/Set all flags overriden by options, need do it 927 * before following smp all cpus cap AND. 928 */ 929 for (i = 0; i < NCAPINTS; i++) { 930 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 931 c->x86_capability[i] |= cpu_caps_set[i]; 932 } 933 934 /* 935 * On SMP, boot_cpu_data holds the common feature set between 936 * all CPUs; so make sure that we indicate which features are 937 * common between the CPUs. The first time this routine gets 938 * executed, c == &boot_cpu_data. 939 */ 940 if (c != &boot_cpu_data) { 941 /* AND the already accumulated flags with these */ 942 for (i = 0; i < NCAPINTS; i++) 943 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 944 945 /* OR, i.e. replicate the bug flags */ 946 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 947 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 948 } 949 950 /* Init Machine Check Exception if available. */ 951 mcheck_cpu_init(c); 952 953 select_idle_routine(c); 954 955 #ifdef CONFIG_NUMA 956 numa_add_cpu(smp_processor_id()); 957 #endif 958 } 959 960 #ifdef CONFIG_X86_64 961 #ifdef CONFIG_IA32_EMULATION 962 /* May not be __init: called during resume */ 963 static void syscall32_cpu_init(void) 964 { 965 /* Load these always in case some future AMD CPU supports 966 SYSENTER from compat mode too. */ 967 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 968 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 969 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); 970 971 wrmsrl(MSR_CSTAR, ia32_cstar_target); 972 } 973 #endif /* CONFIG_IA32_EMULATION */ 974 #endif /* CONFIG_X86_64 */ 975 976 #ifdef CONFIG_X86_32 977 void enable_sep_cpu(void) 978 { 979 int cpu = get_cpu(); 980 struct tss_struct *tss = &per_cpu(init_tss, cpu); 981 982 if (!boot_cpu_has(X86_FEATURE_SEP)) { 983 put_cpu(); 984 return; 985 } 986 987 tss->x86_tss.ss1 = __KERNEL_CS; 988 tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss; 989 wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); 990 wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0); 991 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0); 992 put_cpu(); 993 } 994 #endif 995 996 void __init identify_boot_cpu(void) 997 { 998 identify_cpu(&boot_cpu_data); 999 init_amd_e400_c1e_mask(); 1000 #ifdef CONFIG_X86_32 1001 sysenter_setup(); 1002 enable_sep_cpu(); 1003 #endif 1004 cpu_detect_tlb(&boot_cpu_data); 1005 } 1006 1007 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1008 { 1009 BUG_ON(c == &boot_cpu_data); 1010 identify_cpu(c); 1011 #ifdef CONFIG_X86_32 1012 enable_sep_cpu(); 1013 #endif 1014 mtrr_ap_init(); 1015 } 1016 1017 struct msr_range { 1018 unsigned min; 1019 unsigned max; 1020 }; 1021 1022 static const struct msr_range msr_range_array[] = { 1023 { 0x00000000, 0x00000418}, 1024 { 0xc0000000, 0xc000040b}, 1025 { 0xc0010000, 0xc0010142}, 1026 { 0xc0011000, 0xc001103b}, 1027 }; 1028 1029 static void __print_cpu_msr(void) 1030 { 1031 unsigned index_min, index_max; 1032 unsigned index; 1033 u64 val; 1034 int i; 1035 1036 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 1037 index_min = msr_range_array[i].min; 1038 index_max = msr_range_array[i].max; 1039 1040 for (index = index_min; index < index_max; index++) { 1041 if (rdmsrl_safe(index, &val)) 1042 continue; 1043 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 1044 } 1045 } 1046 } 1047 1048 static int show_msr; 1049 1050 static __init int setup_show_msr(char *arg) 1051 { 1052 int num; 1053 1054 get_option(&arg, &num); 1055 1056 if (num > 0) 1057 show_msr = num; 1058 return 1; 1059 } 1060 __setup("show_msr=", setup_show_msr); 1061 1062 static __init int setup_noclflush(char *arg) 1063 { 1064 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1065 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1066 return 1; 1067 } 1068 __setup("noclflush", setup_noclflush); 1069 1070 void print_cpu_info(struct cpuinfo_x86 *c) 1071 { 1072 const char *vendor = NULL; 1073 1074 if (c->x86_vendor < X86_VENDOR_NUM) { 1075 vendor = this_cpu->c_vendor; 1076 } else { 1077 if (c->cpuid_level >= 0) 1078 vendor = c->x86_vendor_id; 1079 } 1080 1081 if (vendor && !strstr(c->x86_model_id, vendor)) 1082 printk(KERN_CONT "%s ", vendor); 1083 1084 if (c->x86_model_id[0]) 1085 printk(KERN_CONT "%s", strim(c->x86_model_id)); 1086 else 1087 printk(KERN_CONT "%d86", c->x86); 1088 1089 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); 1090 1091 if (c->x86_mask || c->cpuid_level >= 0) 1092 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); 1093 else 1094 printk(KERN_CONT ")\n"); 1095 1096 print_cpu_msr(c); 1097 } 1098 1099 void print_cpu_msr(struct cpuinfo_x86 *c) 1100 { 1101 if (c->cpu_index < show_msr) 1102 __print_cpu_msr(); 1103 } 1104 1105 static __init int setup_disablecpuid(char *arg) 1106 { 1107 int bit; 1108 1109 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1110 setup_clear_cpu_cap(bit); 1111 else 1112 return 0; 1113 1114 return 1; 1115 } 1116 __setup("clearcpuid=", setup_disablecpuid); 1117 1118 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1119 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1120 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1121 1122 #ifdef CONFIG_X86_64 1123 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1124 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1125 (unsigned long) debug_idt_table }; 1126 1127 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1128 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1129 1130 /* 1131 * The following four percpu variables are hot. Align current_task to 1132 * cacheline size such that all four fall in the same cacheline. 1133 */ 1134 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1135 &init_task; 1136 EXPORT_PER_CPU_SYMBOL(current_task); 1137 1138 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1139 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1140 1141 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1142 1143 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1144 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1145 1146 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1147 1148 /* 1149 * Special IST stacks which the CPU switches to when it calls 1150 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1151 * limit), all of them are 4K, except the debug stack which 1152 * is 8K. 1153 */ 1154 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1155 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1156 [DEBUG_STACK - 1] = DEBUG_STKSZ 1157 }; 1158 1159 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1160 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1161 1162 /* May not be marked __init: used by software suspend */ 1163 void syscall_init(void) 1164 { 1165 /* 1166 * LSTAR and STAR live in a bit strange symbiosis. 1167 * They both write to the same internal register. STAR allows to 1168 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1169 */ 1170 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1171 wrmsrl(MSR_LSTAR, system_call); 1172 wrmsrl(MSR_CSTAR, ignore_sysret); 1173 1174 #ifdef CONFIG_IA32_EMULATION 1175 syscall32_cpu_init(); 1176 #endif 1177 1178 /* Flags to clear on syscall */ 1179 wrmsrl(MSR_SYSCALL_MASK, 1180 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1181 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1182 } 1183 1184 /* 1185 * Copies of the original ist values from the tss are only accessed during 1186 * debugging, no special alignment required. 1187 */ 1188 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1189 1190 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1191 DEFINE_PER_CPU(int, debug_stack_usage); 1192 1193 int is_debug_stack(unsigned long addr) 1194 { 1195 return __this_cpu_read(debug_stack_usage) || 1196 (addr <= __this_cpu_read(debug_stack_addr) && 1197 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1198 } 1199 NOKPROBE_SYMBOL(is_debug_stack); 1200 1201 DEFINE_PER_CPU(u32, debug_idt_ctr); 1202 1203 void debug_stack_set_zero(void) 1204 { 1205 this_cpu_inc(debug_idt_ctr); 1206 load_current_idt(); 1207 } 1208 NOKPROBE_SYMBOL(debug_stack_set_zero); 1209 1210 void debug_stack_reset(void) 1211 { 1212 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1213 return; 1214 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1215 load_current_idt(); 1216 } 1217 NOKPROBE_SYMBOL(debug_stack_reset); 1218 1219 #else /* CONFIG_X86_64 */ 1220 1221 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1222 EXPORT_PER_CPU_SYMBOL(current_task); 1223 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1224 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1225 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1226 1227 #ifdef CONFIG_CC_STACKPROTECTOR 1228 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1229 #endif 1230 1231 #endif /* CONFIG_X86_64 */ 1232 1233 /* 1234 * Clear all 6 debug registers: 1235 */ 1236 static void clear_all_debug_regs(void) 1237 { 1238 int i; 1239 1240 for (i = 0; i < 8; i++) { 1241 /* Ignore db4, db5 */ 1242 if ((i == 4) || (i == 5)) 1243 continue; 1244 1245 set_debugreg(0, i); 1246 } 1247 } 1248 1249 #ifdef CONFIG_KGDB 1250 /* 1251 * Restore debug regs if using kgdbwait and you have a kernel debugger 1252 * connection established. 1253 */ 1254 static void dbg_restore_debug_regs(void) 1255 { 1256 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1257 arch_kgdb_ops.correct_hw_break(); 1258 } 1259 #else /* ! CONFIG_KGDB */ 1260 #define dbg_restore_debug_regs() 1261 #endif /* ! CONFIG_KGDB */ 1262 1263 static void wait_for_master_cpu(int cpu) 1264 { 1265 #ifdef CONFIG_SMP 1266 /* 1267 * wait for ACK from master CPU before continuing 1268 * with AP initialization 1269 */ 1270 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1271 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1272 cpu_relax(); 1273 #endif 1274 } 1275 1276 /* 1277 * cpu_init() initializes state that is per-CPU. Some data is already 1278 * initialized (naturally) in the bootstrap process, such as the GDT 1279 * and IDT. We reload them nevertheless, this function acts as a 1280 * 'CPU state barrier', nothing should get across. 1281 * A lot of state is already set up in PDA init for 64 bit 1282 */ 1283 #ifdef CONFIG_X86_64 1284 1285 void cpu_init(void) 1286 { 1287 struct orig_ist *oist; 1288 struct task_struct *me; 1289 struct tss_struct *t; 1290 unsigned long v; 1291 int cpu = stack_smp_processor_id(); 1292 int i; 1293 1294 wait_for_master_cpu(cpu); 1295 1296 /* 1297 * Load microcode on this cpu if a valid microcode is available. 1298 * This is early microcode loading procedure. 1299 */ 1300 load_ucode_ap(); 1301 1302 t = &per_cpu(init_tss, cpu); 1303 oist = &per_cpu(orig_ist, cpu); 1304 1305 #ifdef CONFIG_NUMA 1306 if (this_cpu_read(numa_node) == 0 && 1307 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1308 set_numa_node(early_cpu_to_node(cpu)); 1309 #endif 1310 1311 me = current; 1312 1313 pr_debug("Initializing CPU#%d\n", cpu); 1314 1315 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1316 1317 /* 1318 * Initialize the per-CPU GDT with the boot GDT, 1319 * and set up the GDT descriptor: 1320 */ 1321 1322 switch_to_new_gdt(cpu); 1323 loadsegment(fs, 0); 1324 1325 load_current_idt(); 1326 1327 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1328 syscall_init(); 1329 1330 wrmsrl(MSR_FS_BASE, 0); 1331 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1332 barrier(); 1333 1334 x86_configure_nx(); 1335 enable_x2apic(); 1336 1337 /* 1338 * set up and load the per-CPU TSS 1339 */ 1340 if (!oist->ist[0]) { 1341 char *estacks = per_cpu(exception_stacks, cpu); 1342 1343 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1344 estacks += exception_stack_sizes[v]; 1345 oist->ist[v] = t->x86_tss.ist[v] = 1346 (unsigned long)estacks; 1347 if (v == DEBUG_STACK-1) 1348 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1349 } 1350 } 1351 1352 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1353 1354 /* 1355 * <= is required because the CPU will access up to 1356 * 8 bits beyond the end of the IO permission bitmap. 1357 */ 1358 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1359 t->io_bitmap[i] = ~0UL; 1360 1361 atomic_inc(&init_mm.mm_count); 1362 me->active_mm = &init_mm; 1363 BUG_ON(me->mm); 1364 enter_lazy_tlb(&init_mm, me); 1365 1366 load_sp0(t, ¤t->thread); 1367 set_tss_desc(cpu, t); 1368 load_TR_desc(); 1369 load_LDT(&init_mm.context); 1370 1371 clear_all_debug_regs(); 1372 dbg_restore_debug_regs(); 1373 1374 fpu_init(); 1375 1376 if (is_uv_system()) 1377 uv_cpu_init(); 1378 } 1379 1380 #else 1381 1382 void cpu_init(void) 1383 { 1384 int cpu = smp_processor_id(); 1385 struct task_struct *curr = current; 1386 struct tss_struct *t = &per_cpu(init_tss, cpu); 1387 struct thread_struct *thread = &curr->thread; 1388 1389 wait_for_master_cpu(cpu); 1390 1391 show_ucode_info_early(); 1392 1393 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1394 1395 if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) 1396 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1397 1398 load_current_idt(); 1399 switch_to_new_gdt(cpu); 1400 1401 /* 1402 * Set up and load the per-CPU TSS and LDT 1403 */ 1404 atomic_inc(&init_mm.mm_count); 1405 curr->active_mm = &init_mm; 1406 BUG_ON(curr->mm); 1407 enter_lazy_tlb(&init_mm, curr); 1408 1409 load_sp0(t, thread); 1410 set_tss_desc(cpu, t); 1411 load_TR_desc(); 1412 load_LDT(&init_mm.context); 1413 1414 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1415 1416 #ifdef CONFIG_DOUBLEFAULT 1417 /* Set up doublefault TSS pointer in the GDT */ 1418 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1419 #endif 1420 1421 clear_all_debug_regs(); 1422 dbg_restore_debug_regs(); 1423 1424 fpu_init(); 1425 } 1426 #endif 1427 1428 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 1429 void warn_pre_alternatives(void) 1430 { 1431 WARN(1, "You're using static_cpu_has before alternatives have run!\n"); 1432 } 1433 EXPORT_SYMBOL_GPL(warn_pre_alternatives); 1434 #endif 1435 1436 inline bool __static_cpu_has_safe(u16 bit) 1437 { 1438 return boot_cpu_has(bit); 1439 } 1440 EXPORT_SYMBOL_GPL(__static_cpu_has_safe); 1441