1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kprobes.h> 12 #include <linux/kgdb.h> 13 #include <linux/smp.h> 14 #include <linux/io.h> 15 16 #include <asm/stackprotector.h> 17 #include <asm/perf_event.h> 18 #include <asm/mmu_context.h> 19 #include <asm/archrandom.h> 20 #include <asm/hypervisor.h> 21 #include <asm/processor.h> 22 #include <asm/tlbflush.h> 23 #include <asm/debugreg.h> 24 #include <asm/sections.h> 25 #include <asm/vsyscall.h> 26 #include <linux/topology.h> 27 #include <linux/cpumask.h> 28 #include <asm/pgtable.h> 29 #include <linux/atomic.h> 30 #include <asm/proto.h> 31 #include <asm/setup.h> 32 #include <asm/apic.h> 33 #include <asm/desc.h> 34 #include <asm/i387.h> 35 #include <asm/fpu-internal.h> 36 #include <asm/mtrr.h> 37 #include <linux/numa.h> 38 #include <asm/asm.h> 39 #include <asm/cpu.h> 40 #include <asm/mce.h> 41 #include <asm/msr.h> 42 #include <asm/pat.h> 43 #include <asm/microcode.h> 44 #include <asm/microcode_intel.h> 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 #include <asm/uv/uv.h> 48 #endif 49 50 #include "cpu.h" 51 52 /* all of these masks are initialized in setup_cpu_local_masks() */ 53 cpumask_var_t cpu_initialized_mask; 54 cpumask_var_t cpu_callout_mask; 55 cpumask_var_t cpu_callin_mask; 56 57 /* representing cpus for which sibling maps can be computed */ 58 cpumask_var_t cpu_sibling_setup_mask; 59 60 /* correctly size the local cpu masks */ 61 void __init setup_cpu_local_masks(void) 62 { 63 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 64 alloc_bootmem_cpumask_var(&cpu_callin_mask); 65 alloc_bootmem_cpumask_var(&cpu_callout_mask); 66 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 67 } 68 69 static void default_init(struct cpuinfo_x86 *c) 70 { 71 #ifdef CONFIG_X86_64 72 cpu_detect_cache_sizes(c); 73 #else 74 /* Not much we can do here... */ 75 /* Check if at least it has cpuid */ 76 if (c->cpuid_level == -1) { 77 /* No cpuid. It must be an ancient CPU */ 78 if (c->x86 == 4) 79 strcpy(c->x86_model_id, "486"); 80 else if (c->x86 == 3) 81 strcpy(c->x86_model_id, "386"); 82 } 83 #endif 84 } 85 86 static const struct cpu_dev default_cpu = { 87 .c_init = default_init, 88 .c_vendor = "Unknown", 89 .c_x86_vendor = X86_VENDOR_UNKNOWN, 90 }; 91 92 static const struct cpu_dev *this_cpu = &default_cpu; 93 94 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 95 #ifdef CONFIG_X86_64 96 /* 97 * We need valid kernel segments for data and code in long mode too 98 * IRET will check the segment types kkeil 2000/10/28 99 * Also sysret mandates a special GDT layout 100 * 101 * TLS descriptors are currently at a different place compared to i386. 102 * Hopefully nobody expects them at a fixed place (Wine?) 103 */ 104 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 105 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 106 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 107 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 109 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 110 #else 111 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 113 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 115 /* 116 * Segments used for calling PnP BIOS have byte granularity. 117 * They code segments and data segments have fixed 64k limits, 118 * the transfer segment sizes are set at run time. 119 */ 120 /* 32-bit code */ 121 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 122 /* 16-bit code */ 123 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 124 /* 16-bit data */ 125 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 126 /* 16-bit data */ 127 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 128 /* 16-bit data */ 129 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 130 /* 131 * The APM segments have byte granularity and their bases 132 * are set at run time. All have 64k limits. 133 */ 134 /* 32-bit code */ 135 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 136 /* 16-bit code */ 137 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 138 /* data */ 139 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 140 141 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 142 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 143 GDT_STACK_CANARY_INIT 144 #endif 145 } }; 146 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 147 148 static int __init x86_xsave_setup(char *s) 149 { 150 if (strlen(s)) 151 return 0; 152 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 154 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 155 setup_clear_cpu_cap(X86_FEATURE_AVX); 156 setup_clear_cpu_cap(X86_FEATURE_AVX2); 157 return 1; 158 } 159 __setup("noxsave", x86_xsave_setup); 160 161 static int __init x86_xsaveopt_setup(char *s) 162 { 163 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 164 return 1; 165 } 166 __setup("noxsaveopt", x86_xsaveopt_setup); 167 168 static int __init x86_xsaves_setup(char *s) 169 { 170 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 171 return 1; 172 } 173 __setup("noxsaves", x86_xsaves_setup); 174 175 #ifdef CONFIG_X86_32 176 static int cachesize_override = -1; 177 static int disable_x86_serial_nr = 1; 178 179 static int __init cachesize_setup(char *str) 180 { 181 get_option(&str, &cachesize_override); 182 return 1; 183 } 184 __setup("cachesize=", cachesize_setup); 185 186 static int __init x86_fxsr_setup(char *s) 187 { 188 setup_clear_cpu_cap(X86_FEATURE_FXSR); 189 setup_clear_cpu_cap(X86_FEATURE_XMM); 190 return 1; 191 } 192 __setup("nofxsr", x86_fxsr_setup); 193 194 static int __init x86_sep_setup(char *s) 195 { 196 setup_clear_cpu_cap(X86_FEATURE_SEP); 197 return 1; 198 } 199 __setup("nosep", x86_sep_setup); 200 201 /* Standard macro to see if a specific flag is changeable */ 202 static inline int flag_is_changeable_p(u32 flag) 203 { 204 u32 f1, f2; 205 206 /* 207 * Cyrix and IDT cpus allow disabling of CPUID 208 * so the code below may return different results 209 * when it is executed before and after enabling 210 * the CPUID. Add "volatile" to not allow gcc to 211 * optimize the subsequent calls to this function. 212 */ 213 asm volatile ("pushfl \n\t" 214 "pushfl \n\t" 215 "popl %0 \n\t" 216 "movl %0, %1 \n\t" 217 "xorl %2, %0 \n\t" 218 "pushl %0 \n\t" 219 "popfl \n\t" 220 "pushfl \n\t" 221 "popl %0 \n\t" 222 "popfl \n\t" 223 224 : "=&r" (f1), "=&r" (f2) 225 : "ir" (flag)); 226 227 return ((f1^f2) & flag) != 0; 228 } 229 230 /* Probe for the CPUID instruction */ 231 int have_cpuid_p(void) 232 { 233 return flag_is_changeable_p(X86_EFLAGS_ID); 234 } 235 236 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 237 { 238 unsigned long lo, hi; 239 240 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 241 return; 242 243 /* Disable processor serial number: */ 244 245 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 246 lo |= 0x200000; 247 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 248 249 printk(KERN_NOTICE "CPU serial number disabled.\n"); 250 clear_cpu_cap(c, X86_FEATURE_PN); 251 252 /* Disabling the serial number may affect the cpuid level */ 253 c->cpuid_level = cpuid_eax(0); 254 } 255 256 static int __init x86_serial_nr_setup(char *s) 257 { 258 disable_x86_serial_nr = 0; 259 return 1; 260 } 261 __setup("serialnumber", x86_serial_nr_setup); 262 #else 263 static inline int flag_is_changeable_p(u32 flag) 264 { 265 return 1; 266 } 267 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 268 { 269 } 270 #endif 271 272 static __init int setup_disable_smep(char *arg) 273 { 274 setup_clear_cpu_cap(X86_FEATURE_SMEP); 275 return 1; 276 } 277 __setup("nosmep", setup_disable_smep); 278 279 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 280 { 281 if (cpu_has(c, X86_FEATURE_SMEP)) 282 cr4_set_bits(X86_CR4_SMEP); 283 } 284 285 static __init int setup_disable_smap(char *arg) 286 { 287 setup_clear_cpu_cap(X86_FEATURE_SMAP); 288 return 1; 289 } 290 __setup("nosmap", setup_disable_smap); 291 292 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 293 { 294 unsigned long eflags; 295 296 /* This should have been cleared long ago */ 297 raw_local_save_flags(eflags); 298 BUG_ON(eflags & X86_EFLAGS_AC); 299 300 if (cpu_has(c, X86_FEATURE_SMAP)) { 301 #ifdef CONFIG_X86_SMAP 302 cr4_set_bits(X86_CR4_SMAP); 303 #else 304 cr4_clear_bits(X86_CR4_SMAP); 305 #endif 306 } 307 } 308 309 /* 310 * Some CPU features depend on higher CPUID levels, which may not always 311 * be available due to CPUID level capping or broken virtualization 312 * software. Add those features to this table to auto-disable them. 313 */ 314 struct cpuid_dependent_feature { 315 u32 feature; 316 u32 level; 317 }; 318 319 static const struct cpuid_dependent_feature 320 cpuid_dependent_features[] = { 321 { X86_FEATURE_MWAIT, 0x00000005 }, 322 { X86_FEATURE_DCA, 0x00000009 }, 323 { X86_FEATURE_XSAVE, 0x0000000d }, 324 { 0, 0 } 325 }; 326 327 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 328 { 329 const struct cpuid_dependent_feature *df; 330 331 for (df = cpuid_dependent_features; df->feature; df++) { 332 333 if (!cpu_has(c, df->feature)) 334 continue; 335 /* 336 * Note: cpuid_level is set to -1 if unavailable, but 337 * extended_extended_level is set to 0 if unavailable 338 * and the legitimate extended levels are all negative 339 * when signed; hence the weird messing around with 340 * signs here... 341 */ 342 if (!((s32)df->level < 0 ? 343 (u32)df->level > (u32)c->extended_cpuid_level : 344 (s32)df->level > (s32)c->cpuid_level)) 345 continue; 346 347 clear_cpu_cap(c, df->feature); 348 if (!warn) 349 continue; 350 351 printk(KERN_WARNING 352 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 353 x86_cap_flag(df->feature), df->level); 354 } 355 } 356 357 /* 358 * Naming convention should be: <Name> [(<Codename>)] 359 * This table only is used unless init_<vendor>() below doesn't set it; 360 * in particular, if CPUID levels 0x80000002..4 are supported, this 361 * isn't used 362 */ 363 364 /* Look up CPU names by table lookup. */ 365 static const char *table_lookup_model(struct cpuinfo_x86 *c) 366 { 367 #ifdef CONFIG_X86_32 368 const struct legacy_cpu_model_info *info; 369 370 if (c->x86_model >= 16) 371 return NULL; /* Range check */ 372 373 if (!this_cpu) 374 return NULL; 375 376 info = this_cpu->legacy_models; 377 378 while (info->family) { 379 if (info->family == c->x86) 380 return info->model_names[c->x86_model]; 381 info++; 382 } 383 #endif 384 return NULL; /* Not found */ 385 } 386 387 __u32 cpu_caps_cleared[NCAPINTS]; 388 __u32 cpu_caps_set[NCAPINTS]; 389 390 void load_percpu_segment(int cpu) 391 { 392 #ifdef CONFIG_X86_32 393 loadsegment(fs, __KERNEL_PERCPU); 394 #else 395 loadsegment(gs, 0); 396 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 397 #endif 398 load_stack_canary_segment(); 399 } 400 401 /* 402 * Current gdt points %fs at the "master" per-cpu area: after this, 403 * it's on the real one. 404 */ 405 void switch_to_new_gdt(int cpu) 406 { 407 struct desc_ptr gdt_descr; 408 409 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 410 gdt_descr.size = GDT_SIZE - 1; 411 load_gdt(&gdt_descr); 412 /* Reload the per-cpu base */ 413 414 load_percpu_segment(cpu); 415 } 416 417 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 418 419 static void get_model_name(struct cpuinfo_x86 *c) 420 { 421 unsigned int *v; 422 char *p, *q; 423 424 if (c->extended_cpuid_level < 0x80000004) 425 return; 426 427 v = (unsigned int *)c->x86_model_id; 428 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 429 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 430 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 431 c->x86_model_id[48] = 0; 432 433 /* 434 * Intel chips right-justify this string for some dumb reason; 435 * undo that brain damage: 436 */ 437 p = q = &c->x86_model_id[0]; 438 while (*p == ' ') 439 p++; 440 if (p != q) { 441 while (*p) 442 *q++ = *p++; 443 while (q <= &c->x86_model_id[48]) 444 *q++ = '\0'; /* Zero-pad the rest */ 445 } 446 } 447 448 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 449 { 450 unsigned int n, dummy, ebx, ecx, edx, l2size; 451 452 n = c->extended_cpuid_level; 453 454 if (n >= 0x80000005) { 455 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 456 c->x86_cache_size = (ecx>>24) + (edx>>24); 457 #ifdef CONFIG_X86_64 458 /* On K8 L1 TLB is inclusive, so don't count it */ 459 c->x86_tlbsize = 0; 460 #endif 461 } 462 463 if (n < 0x80000006) /* Some chips just has a large L1. */ 464 return; 465 466 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 467 l2size = ecx >> 16; 468 469 #ifdef CONFIG_X86_64 470 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 471 #else 472 /* do processor-specific cache resizing */ 473 if (this_cpu->legacy_cache_size) 474 l2size = this_cpu->legacy_cache_size(c, l2size); 475 476 /* Allow user to override all this if necessary. */ 477 if (cachesize_override != -1) 478 l2size = cachesize_override; 479 480 if (l2size == 0) 481 return; /* Again, no L2 cache is possible */ 482 #endif 483 484 c->x86_cache_size = l2size; 485 } 486 487 u16 __read_mostly tlb_lli_4k[NR_INFO]; 488 u16 __read_mostly tlb_lli_2m[NR_INFO]; 489 u16 __read_mostly tlb_lli_4m[NR_INFO]; 490 u16 __read_mostly tlb_lld_4k[NR_INFO]; 491 u16 __read_mostly tlb_lld_2m[NR_INFO]; 492 u16 __read_mostly tlb_lld_4m[NR_INFO]; 493 u16 __read_mostly tlb_lld_1g[NR_INFO]; 494 495 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 496 { 497 if (this_cpu->c_detect_tlb) 498 this_cpu->c_detect_tlb(c); 499 500 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 501 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 502 tlb_lli_4m[ENTRIES]); 503 504 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 505 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 506 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 507 } 508 509 void detect_ht(struct cpuinfo_x86 *c) 510 { 511 #ifdef CONFIG_X86_HT 512 u32 eax, ebx, ecx, edx; 513 int index_msb, core_bits; 514 static bool printed; 515 516 if (!cpu_has(c, X86_FEATURE_HT)) 517 return; 518 519 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 520 goto out; 521 522 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 523 return; 524 525 cpuid(1, &eax, &ebx, &ecx, &edx); 526 527 smp_num_siblings = (ebx & 0xff0000) >> 16; 528 529 if (smp_num_siblings == 1) { 530 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 531 goto out; 532 } 533 534 if (smp_num_siblings <= 1) 535 goto out; 536 537 index_msb = get_count_order(smp_num_siblings); 538 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 539 540 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 541 542 index_msb = get_count_order(smp_num_siblings); 543 544 core_bits = get_count_order(c->x86_max_cores); 545 546 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 547 ((1 << core_bits) - 1); 548 549 out: 550 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 551 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 552 c->phys_proc_id); 553 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 554 c->cpu_core_id); 555 printed = 1; 556 } 557 #endif 558 } 559 560 static void get_cpu_vendor(struct cpuinfo_x86 *c) 561 { 562 char *v = c->x86_vendor_id; 563 int i; 564 565 for (i = 0; i < X86_VENDOR_NUM; i++) { 566 if (!cpu_devs[i]) 567 break; 568 569 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 570 (cpu_devs[i]->c_ident[1] && 571 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 572 573 this_cpu = cpu_devs[i]; 574 c->x86_vendor = this_cpu->c_x86_vendor; 575 return; 576 } 577 } 578 579 printk_once(KERN_ERR 580 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 581 "CPU: Your system may be unstable.\n", v); 582 583 c->x86_vendor = X86_VENDOR_UNKNOWN; 584 this_cpu = &default_cpu; 585 } 586 587 void cpu_detect(struct cpuinfo_x86 *c) 588 { 589 /* Get vendor name */ 590 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 591 (unsigned int *)&c->x86_vendor_id[0], 592 (unsigned int *)&c->x86_vendor_id[8], 593 (unsigned int *)&c->x86_vendor_id[4]); 594 595 c->x86 = 4; 596 /* Intel-defined flags: level 0x00000001 */ 597 if (c->cpuid_level >= 0x00000001) { 598 u32 junk, tfms, cap0, misc; 599 600 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 601 c->x86 = (tfms >> 8) & 0xf; 602 c->x86_model = (tfms >> 4) & 0xf; 603 c->x86_mask = tfms & 0xf; 604 605 if (c->x86 == 0xf) 606 c->x86 += (tfms >> 20) & 0xff; 607 if (c->x86 >= 0x6) 608 c->x86_model += ((tfms >> 16) & 0xf) << 4; 609 610 if (cap0 & (1<<19)) { 611 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 612 c->x86_cache_alignment = c->x86_clflush_size; 613 } 614 } 615 } 616 617 void get_cpu_cap(struct cpuinfo_x86 *c) 618 { 619 u32 tfms, xlvl; 620 u32 ebx; 621 622 /* Intel-defined flags: level 0x00000001 */ 623 if (c->cpuid_level >= 0x00000001) { 624 u32 capability, excap; 625 626 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 627 c->x86_capability[0] = capability; 628 c->x86_capability[4] = excap; 629 } 630 631 /* Additional Intel-defined flags: level 0x00000007 */ 632 if (c->cpuid_level >= 0x00000007) { 633 u32 eax, ebx, ecx, edx; 634 635 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 636 637 c->x86_capability[9] = ebx; 638 } 639 640 /* Extended state features: level 0x0000000d */ 641 if (c->cpuid_level >= 0x0000000d) { 642 u32 eax, ebx, ecx, edx; 643 644 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 645 646 c->x86_capability[10] = eax; 647 } 648 649 /* Additional Intel-defined flags: level 0x0000000F */ 650 if (c->cpuid_level >= 0x0000000F) { 651 u32 eax, ebx, ecx, edx; 652 653 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 654 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 655 c->x86_capability[11] = edx; 656 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 657 /* will be overridden if occupancy monitoring exists */ 658 c->x86_cache_max_rmid = ebx; 659 660 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 661 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 662 c->x86_capability[12] = edx; 663 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { 664 c->x86_cache_max_rmid = ecx; 665 c->x86_cache_occ_scale = ebx; 666 } 667 } else { 668 c->x86_cache_max_rmid = -1; 669 c->x86_cache_occ_scale = -1; 670 } 671 } 672 673 /* AMD-defined flags: level 0x80000001 */ 674 xlvl = cpuid_eax(0x80000000); 675 c->extended_cpuid_level = xlvl; 676 677 if ((xlvl & 0xffff0000) == 0x80000000) { 678 if (xlvl >= 0x80000001) { 679 c->x86_capability[1] = cpuid_edx(0x80000001); 680 c->x86_capability[6] = cpuid_ecx(0x80000001); 681 } 682 } 683 684 if (c->extended_cpuid_level >= 0x80000008) { 685 u32 eax = cpuid_eax(0x80000008); 686 687 c->x86_virt_bits = (eax >> 8) & 0xff; 688 c->x86_phys_bits = eax & 0xff; 689 } 690 #ifdef CONFIG_X86_32 691 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 692 c->x86_phys_bits = 36; 693 #endif 694 695 if (c->extended_cpuid_level >= 0x80000007) 696 c->x86_power = cpuid_edx(0x80000007); 697 698 init_scattered_cpuid_features(c); 699 } 700 701 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 702 { 703 #ifdef CONFIG_X86_32 704 int i; 705 706 /* 707 * First of all, decide if this is a 486 or higher 708 * It's a 486 if we can modify the AC flag 709 */ 710 if (flag_is_changeable_p(X86_EFLAGS_AC)) 711 c->x86 = 4; 712 else 713 c->x86 = 3; 714 715 for (i = 0; i < X86_VENDOR_NUM; i++) 716 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 717 c->x86_vendor_id[0] = 0; 718 cpu_devs[i]->c_identify(c); 719 if (c->x86_vendor_id[0]) { 720 get_cpu_vendor(c); 721 break; 722 } 723 } 724 #endif 725 } 726 727 /* 728 * Do minimum CPU detection early. 729 * Fields really needed: vendor, cpuid_level, family, model, mask, 730 * cache alignment. 731 * The others are not touched to avoid unwanted side effects. 732 * 733 * WARNING: this function is only called on the BP. Don't add code here 734 * that is supposed to run on all CPUs. 735 */ 736 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 737 { 738 #ifdef CONFIG_X86_64 739 c->x86_clflush_size = 64; 740 c->x86_phys_bits = 36; 741 c->x86_virt_bits = 48; 742 #else 743 c->x86_clflush_size = 32; 744 c->x86_phys_bits = 32; 745 c->x86_virt_bits = 32; 746 #endif 747 c->x86_cache_alignment = c->x86_clflush_size; 748 749 memset(&c->x86_capability, 0, sizeof c->x86_capability); 750 c->extended_cpuid_level = 0; 751 752 if (!have_cpuid_p()) 753 identify_cpu_without_cpuid(c); 754 755 /* cyrix could have cpuid enabled via c_identify()*/ 756 if (!have_cpuid_p()) 757 return; 758 759 cpu_detect(c); 760 get_cpu_vendor(c); 761 get_cpu_cap(c); 762 fpu_detect(c); 763 764 if (this_cpu->c_early_init) 765 this_cpu->c_early_init(c); 766 767 c->cpu_index = 0; 768 filter_cpuid_features(c, false); 769 770 if (this_cpu->c_bsp_init) 771 this_cpu->c_bsp_init(c); 772 773 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 774 } 775 776 void __init early_cpu_init(void) 777 { 778 const struct cpu_dev *const *cdev; 779 int count = 0; 780 781 #ifdef CONFIG_PROCESSOR_SELECT 782 printk(KERN_INFO "KERNEL supported cpus:\n"); 783 #endif 784 785 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 786 const struct cpu_dev *cpudev = *cdev; 787 788 if (count >= X86_VENDOR_NUM) 789 break; 790 cpu_devs[count] = cpudev; 791 count++; 792 793 #ifdef CONFIG_PROCESSOR_SELECT 794 { 795 unsigned int j; 796 797 for (j = 0; j < 2; j++) { 798 if (!cpudev->c_ident[j]) 799 continue; 800 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 801 cpudev->c_ident[j]); 802 } 803 } 804 #endif 805 } 806 early_identify_cpu(&boot_cpu_data); 807 } 808 809 /* 810 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 811 * unfortunately, that's not true in practice because of early VIA 812 * chips and (more importantly) broken virtualizers that are not easy 813 * to detect. In the latter case it doesn't even *fail* reliably, so 814 * probing for it doesn't even work. Disable it completely on 32-bit 815 * unless we can find a reliable way to detect all the broken cases. 816 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 817 */ 818 static void detect_nopl(struct cpuinfo_x86 *c) 819 { 820 #ifdef CONFIG_X86_32 821 clear_cpu_cap(c, X86_FEATURE_NOPL); 822 #else 823 set_cpu_cap(c, X86_FEATURE_NOPL); 824 #endif 825 } 826 827 static void generic_identify(struct cpuinfo_x86 *c) 828 { 829 c->extended_cpuid_level = 0; 830 831 if (!have_cpuid_p()) 832 identify_cpu_without_cpuid(c); 833 834 /* cyrix could have cpuid enabled via c_identify()*/ 835 if (!have_cpuid_p()) 836 return; 837 838 cpu_detect(c); 839 840 get_cpu_vendor(c); 841 842 get_cpu_cap(c); 843 844 if (c->cpuid_level >= 0x00000001) { 845 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 846 #ifdef CONFIG_X86_32 847 # ifdef CONFIG_X86_HT 848 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 849 # else 850 c->apicid = c->initial_apicid; 851 # endif 852 #endif 853 c->phys_proc_id = c->initial_apicid; 854 } 855 856 get_model_name(c); /* Default name */ 857 858 detect_nopl(c); 859 } 860 861 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 862 { 863 /* 864 * The heavy lifting of max_rmid and cache_occ_scale are handled 865 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 866 * in case CQM bits really aren't there in this CPU. 867 */ 868 if (c != &boot_cpu_data) { 869 boot_cpu_data.x86_cache_max_rmid = 870 min(boot_cpu_data.x86_cache_max_rmid, 871 c->x86_cache_max_rmid); 872 } 873 } 874 875 /* 876 * This does the hard work of actually picking apart the CPU stuff... 877 */ 878 static void identify_cpu(struct cpuinfo_x86 *c) 879 { 880 int i; 881 882 c->loops_per_jiffy = loops_per_jiffy; 883 c->x86_cache_size = -1; 884 c->x86_vendor = X86_VENDOR_UNKNOWN; 885 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 886 c->x86_vendor_id[0] = '\0'; /* Unset */ 887 c->x86_model_id[0] = '\0'; /* Unset */ 888 c->x86_max_cores = 1; 889 c->x86_coreid_bits = 0; 890 #ifdef CONFIG_X86_64 891 c->x86_clflush_size = 64; 892 c->x86_phys_bits = 36; 893 c->x86_virt_bits = 48; 894 #else 895 c->cpuid_level = -1; /* CPUID not detected */ 896 c->x86_clflush_size = 32; 897 c->x86_phys_bits = 32; 898 c->x86_virt_bits = 32; 899 #endif 900 c->x86_cache_alignment = c->x86_clflush_size; 901 memset(&c->x86_capability, 0, sizeof c->x86_capability); 902 903 generic_identify(c); 904 905 if (this_cpu->c_identify) 906 this_cpu->c_identify(c); 907 908 /* Clear/Set all flags overriden by options, after probe */ 909 for (i = 0; i < NCAPINTS; i++) { 910 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 911 c->x86_capability[i] |= cpu_caps_set[i]; 912 } 913 914 #ifdef CONFIG_X86_64 915 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 916 #endif 917 918 /* 919 * Vendor-specific initialization. In this section we 920 * canonicalize the feature flags, meaning if there are 921 * features a certain CPU supports which CPUID doesn't 922 * tell us, CPUID claiming incorrect flags, or other bugs, 923 * we handle them here. 924 * 925 * At the end of this section, c->x86_capability better 926 * indicate the features this CPU genuinely supports! 927 */ 928 if (this_cpu->c_init) 929 this_cpu->c_init(c); 930 931 /* Disable the PN if appropriate */ 932 squash_the_stupid_serial_number(c); 933 934 /* Set up SMEP/SMAP */ 935 setup_smep(c); 936 setup_smap(c); 937 938 /* 939 * The vendor-specific functions might have changed features. 940 * Now we do "generic changes." 941 */ 942 943 /* Filter out anything that depends on CPUID levels we don't have */ 944 filter_cpuid_features(c, true); 945 946 /* If the model name is still unset, do table lookup. */ 947 if (!c->x86_model_id[0]) { 948 const char *p; 949 p = table_lookup_model(c); 950 if (p) 951 strcpy(c->x86_model_id, p); 952 else 953 /* Last resort... */ 954 sprintf(c->x86_model_id, "%02x/%02x", 955 c->x86, c->x86_model); 956 } 957 958 #ifdef CONFIG_X86_64 959 detect_ht(c); 960 #endif 961 962 init_hypervisor(c); 963 x86_init_rdrand(c); 964 x86_init_cache_qos(c); 965 966 /* 967 * Clear/Set all flags overriden by options, need do it 968 * before following smp all cpus cap AND. 969 */ 970 for (i = 0; i < NCAPINTS; i++) { 971 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 972 c->x86_capability[i] |= cpu_caps_set[i]; 973 } 974 975 /* 976 * On SMP, boot_cpu_data holds the common feature set between 977 * all CPUs; so make sure that we indicate which features are 978 * common between the CPUs. The first time this routine gets 979 * executed, c == &boot_cpu_data. 980 */ 981 if (c != &boot_cpu_data) { 982 /* AND the already accumulated flags with these */ 983 for (i = 0; i < NCAPINTS; i++) 984 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 985 986 /* OR, i.e. replicate the bug flags */ 987 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 988 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 989 } 990 991 /* Init Machine Check Exception if available. */ 992 mcheck_cpu_init(c); 993 994 select_idle_routine(c); 995 996 #ifdef CONFIG_NUMA 997 numa_add_cpu(smp_processor_id()); 998 #endif 999 } 1000 1001 /* 1002 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1003 * on 32-bit kernels: 1004 */ 1005 #ifdef CONFIG_X86_32 1006 void enable_sep_cpu(void) 1007 { 1008 struct tss_struct *tss; 1009 int cpu; 1010 1011 cpu = get_cpu(); 1012 tss = &per_cpu(cpu_tss, cpu); 1013 1014 if (!boot_cpu_has(X86_FEATURE_SEP)) 1015 goto out; 1016 1017 /* 1018 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1019 * see the big comment in struct x86_hw_tss's definition. 1020 */ 1021 1022 tss->x86_tss.ss1 = __KERNEL_CS; 1023 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1024 1025 wrmsr(MSR_IA32_SYSENTER_ESP, 1026 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1027 0); 1028 1029 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)ia32_sysenter_target, 0); 1030 1031 out: 1032 put_cpu(); 1033 } 1034 #endif 1035 1036 void __init identify_boot_cpu(void) 1037 { 1038 identify_cpu(&boot_cpu_data); 1039 init_amd_e400_c1e_mask(); 1040 #ifdef CONFIG_X86_32 1041 sysenter_setup(); 1042 enable_sep_cpu(); 1043 #endif 1044 cpu_detect_tlb(&boot_cpu_data); 1045 } 1046 1047 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1048 { 1049 BUG_ON(c == &boot_cpu_data); 1050 identify_cpu(c); 1051 #ifdef CONFIG_X86_32 1052 enable_sep_cpu(); 1053 #endif 1054 mtrr_ap_init(); 1055 } 1056 1057 struct msr_range { 1058 unsigned min; 1059 unsigned max; 1060 }; 1061 1062 static const struct msr_range msr_range_array[] = { 1063 { 0x00000000, 0x00000418}, 1064 { 0xc0000000, 0xc000040b}, 1065 { 0xc0010000, 0xc0010142}, 1066 { 0xc0011000, 0xc001103b}, 1067 }; 1068 1069 static void __print_cpu_msr(void) 1070 { 1071 unsigned index_min, index_max; 1072 unsigned index; 1073 u64 val; 1074 int i; 1075 1076 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 1077 index_min = msr_range_array[i].min; 1078 index_max = msr_range_array[i].max; 1079 1080 for (index = index_min; index < index_max; index++) { 1081 if (rdmsrl_safe(index, &val)) 1082 continue; 1083 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 1084 } 1085 } 1086 } 1087 1088 static int show_msr; 1089 1090 static __init int setup_show_msr(char *arg) 1091 { 1092 int num; 1093 1094 get_option(&arg, &num); 1095 1096 if (num > 0) 1097 show_msr = num; 1098 return 1; 1099 } 1100 __setup("show_msr=", setup_show_msr); 1101 1102 static __init int setup_noclflush(char *arg) 1103 { 1104 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1105 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1106 return 1; 1107 } 1108 __setup("noclflush", setup_noclflush); 1109 1110 void print_cpu_info(struct cpuinfo_x86 *c) 1111 { 1112 const char *vendor = NULL; 1113 1114 if (c->x86_vendor < X86_VENDOR_NUM) { 1115 vendor = this_cpu->c_vendor; 1116 } else { 1117 if (c->cpuid_level >= 0) 1118 vendor = c->x86_vendor_id; 1119 } 1120 1121 if (vendor && !strstr(c->x86_model_id, vendor)) 1122 printk(KERN_CONT "%s ", vendor); 1123 1124 if (c->x86_model_id[0]) 1125 printk(KERN_CONT "%s", strim(c->x86_model_id)); 1126 else 1127 printk(KERN_CONT "%d86", c->x86); 1128 1129 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); 1130 1131 if (c->x86_mask || c->cpuid_level >= 0) 1132 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); 1133 else 1134 printk(KERN_CONT ")\n"); 1135 1136 print_cpu_msr(c); 1137 } 1138 1139 void print_cpu_msr(struct cpuinfo_x86 *c) 1140 { 1141 if (c->cpu_index < show_msr) 1142 __print_cpu_msr(); 1143 } 1144 1145 static __init int setup_disablecpuid(char *arg) 1146 { 1147 int bit; 1148 1149 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1150 setup_clear_cpu_cap(bit); 1151 else 1152 return 0; 1153 1154 return 1; 1155 } 1156 __setup("clearcpuid=", setup_disablecpuid); 1157 1158 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1159 (unsigned long)&init_thread_union + THREAD_SIZE; 1160 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1161 1162 #ifdef CONFIG_X86_64 1163 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1164 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1165 (unsigned long) debug_idt_table }; 1166 1167 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1168 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1169 1170 /* 1171 * The following percpu variables are hot. Align current_task to 1172 * cacheline size such that they fall in the same cacheline. 1173 */ 1174 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1175 &init_task; 1176 EXPORT_PER_CPU_SYMBOL(current_task); 1177 1178 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1179 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1180 1181 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1182 1183 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1184 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1185 1186 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1187 1188 /* 1189 * Special IST stacks which the CPU switches to when it calls 1190 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1191 * limit), all of them are 4K, except the debug stack which 1192 * is 8K. 1193 */ 1194 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1195 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1196 [DEBUG_STACK - 1] = DEBUG_STKSZ 1197 }; 1198 1199 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1200 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1201 1202 /* May not be marked __init: used by software suspend */ 1203 void syscall_init(void) 1204 { 1205 /* 1206 * LSTAR and STAR live in a bit strange symbiosis. 1207 * They both write to the same internal register. STAR allows to 1208 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1209 */ 1210 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1211 wrmsrl(MSR_LSTAR, system_call); 1212 1213 #ifdef CONFIG_IA32_EMULATION 1214 wrmsrl(MSR_CSTAR, ia32_cstar_target); 1215 /* 1216 * This only works on Intel CPUs. 1217 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1218 * This does not cause SYSENTER to jump to the wrong location, because 1219 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1220 */ 1221 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1222 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1223 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); 1224 #else 1225 wrmsrl(MSR_CSTAR, ignore_sysret); 1226 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1227 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1228 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1229 #endif 1230 1231 /* Flags to clear on syscall */ 1232 wrmsrl(MSR_SYSCALL_MASK, 1233 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1234 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1235 } 1236 1237 /* 1238 * Copies of the original ist values from the tss are only accessed during 1239 * debugging, no special alignment required. 1240 */ 1241 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1242 1243 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1244 DEFINE_PER_CPU(int, debug_stack_usage); 1245 1246 int is_debug_stack(unsigned long addr) 1247 { 1248 return __this_cpu_read(debug_stack_usage) || 1249 (addr <= __this_cpu_read(debug_stack_addr) && 1250 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1251 } 1252 NOKPROBE_SYMBOL(is_debug_stack); 1253 1254 DEFINE_PER_CPU(u32, debug_idt_ctr); 1255 1256 void debug_stack_set_zero(void) 1257 { 1258 this_cpu_inc(debug_idt_ctr); 1259 load_current_idt(); 1260 } 1261 NOKPROBE_SYMBOL(debug_stack_set_zero); 1262 1263 void debug_stack_reset(void) 1264 { 1265 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1266 return; 1267 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1268 load_current_idt(); 1269 } 1270 NOKPROBE_SYMBOL(debug_stack_reset); 1271 1272 #else /* CONFIG_X86_64 */ 1273 1274 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1275 EXPORT_PER_CPU_SYMBOL(current_task); 1276 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1277 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1278 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1279 1280 /* 1281 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1282 * the top of the kernel stack. Use an extra percpu variable to track the 1283 * top of the kernel stack directly. 1284 */ 1285 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1286 (unsigned long)&init_thread_union + THREAD_SIZE; 1287 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1288 1289 #ifdef CONFIG_CC_STACKPROTECTOR 1290 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1291 #endif 1292 1293 #endif /* CONFIG_X86_64 */ 1294 1295 /* 1296 * Clear all 6 debug registers: 1297 */ 1298 static void clear_all_debug_regs(void) 1299 { 1300 int i; 1301 1302 for (i = 0; i < 8; i++) { 1303 /* Ignore db4, db5 */ 1304 if ((i == 4) || (i == 5)) 1305 continue; 1306 1307 set_debugreg(0, i); 1308 } 1309 } 1310 1311 #ifdef CONFIG_KGDB 1312 /* 1313 * Restore debug regs if using kgdbwait and you have a kernel debugger 1314 * connection established. 1315 */ 1316 static void dbg_restore_debug_regs(void) 1317 { 1318 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1319 arch_kgdb_ops.correct_hw_break(); 1320 } 1321 #else /* ! CONFIG_KGDB */ 1322 #define dbg_restore_debug_regs() 1323 #endif /* ! CONFIG_KGDB */ 1324 1325 static void wait_for_master_cpu(int cpu) 1326 { 1327 #ifdef CONFIG_SMP 1328 /* 1329 * wait for ACK from master CPU before continuing 1330 * with AP initialization 1331 */ 1332 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1333 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1334 cpu_relax(); 1335 #endif 1336 } 1337 1338 /* 1339 * cpu_init() initializes state that is per-CPU. Some data is already 1340 * initialized (naturally) in the bootstrap process, such as the GDT 1341 * and IDT. We reload them nevertheless, this function acts as a 1342 * 'CPU state barrier', nothing should get across. 1343 * A lot of state is already set up in PDA init for 64 bit 1344 */ 1345 #ifdef CONFIG_X86_64 1346 1347 void cpu_init(void) 1348 { 1349 struct orig_ist *oist; 1350 struct task_struct *me; 1351 struct tss_struct *t; 1352 unsigned long v; 1353 int cpu = stack_smp_processor_id(); 1354 int i; 1355 1356 wait_for_master_cpu(cpu); 1357 1358 /* 1359 * Initialize the CR4 shadow before doing anything that could 1360 * try to read it. 1361 */ 1362 cr4_init_shadow(); 1363 1364 /* 1365 * Load microcode on this cpu if a valid microcode is available. 1366 * This is early microcode loading procedure. 1367 */ 1368 load_ucode_ap(); 1369 1370 t = &per_cpu(cpu_tss, cpu); 1371 oist = &per_cpu(orig_ist, cpu); 1372 1373 #ifdef CONFIG_NUMA 1374 if (this_cpu_read(numa_node) == 0 && 1375 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1376 set_numa_node(early_cpu_to_node(cpu)); 1377 #endif 1378 1379 me = current; 1380 1381 pr_debug("Initializing CPU#%d\n", cpu); 1382 1383 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1384 1385 /* 1386 * Initialize the per-CPU GDT with the boot GDT, 1387 * and set up the GDT descriptor: 1388 */ 1389 1390 switch_to_new_gdt(cpu); 1391 loadsegment(fs, 0); 1392 1393 load_current_idt(); 1394 1395 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1396 syscall_init(); 1397 1398 wrmsrl(MSR_FS_BASE, 0); 1399 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1400 barrier(); 1401 1402 x86_configure_nx(); 1403 x2apic_setup(); 1404 1405 /* 1406 * set up and load the per-CPU TSS 1407 */ 1408 if (!oist->ist[0]) { 1409 char *estacks = per_cpu(exception_stacks, cpu); 1410 1411 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1412 estacks += exception_stack_sizes[v]; 1413 oist->ist[v] = t->x86_tss.ist[v] = 1414 (unsigned long)estacks; 1415 if (v == DEBUG_STACK-1) 1416 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1417 } 1418 } 1419 1420 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1421 1422 /* 1423 * <= is required because the CPU will access up to 1424 * 8 bits beyond the end of the IO permission bitmap. 1425 */ 1426 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1427 t->io_bitmap[i] = ~0UL; 1428 1429 atomic_inc(&init_mm.mm_count); 1430 me->active_mm = &init_mm; 1431 BUG_ON(me->mm); 1432 enter_lazy_tlb(&init_mm, me); 1433 1434 load_sp0(t, ¤t->thread); 1435 set_tss_desc(cpu, t); 1436 load_TR_desc(); 1437 load_LDT(&init_mm.context); 1438 1439 clear_all_debug_regs(); 1440 dbg_restore_debug_regs(); 1441 1442 fpu_init(); 1443 1444 if (is_uv_system()) 1445 uv_cpu_init(); 1446 } 1447 1448 #else 1449 1450 void cpu_init(void) 1451 { 1452 int cpu = smp_processor_id(); 1453 struct task_struct *curr = current; 1454 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1455 struct thread_struct *thread = &curr->thread; 1456 1457 wait_for_master_cpu(cpu); 1458 1459 /* 1460 * Initialize the CR4 shadow before doing anything that could 1461 * try to read it. 1462 */ 1463 cr4_init_shadow(); 1464 1465 show_ucode_info_early(); 1466 1467 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1468 1469 if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) 1470 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1471 1472 load_current_idt(); 1473 switch_to_new_gdt(cpu); 1474 1475 /* 1476 * Set up and load the per-CPU TSS and LDT 1477 */ 1478 atomic_inc(&init_mm.mm_count); 1479 curr->active_mm = &init_mm; 1480 BUG_ON(curr->mm); 1481 enter_lazy_tlb(&init_mm, curr); 1482 1483 load_sp0(t, thread); 1484 set_tss_desc(cpu, t); 1485 load_TR_desc(); 1486 load_LDT(&init_mm.context); 1487 1488 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1489 1490 #ifdef CONFIG_DOUBLEFAULT 1491 /* Set up doublefault TSS pointer in the GDT */ 1492 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1493 #endif 1494 1495 clear_all_debug_regs(); 1496 dbg_restore_debug_regs(); 1497 1498 fpu_init(); 1499 } 1500 #endif 1501 1502 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 1503 void warn_pre_alternatives(void) 1504 { 1505 WARN(1, "You're using static_cpu_has before alternatives have run!\n"); 1506 } 1507 EXPORT_SYMBOL_GPL(warn_pre_alternatives); 1508 #endif 1509 1510 inline bool __static_cpu_has_safe(u16 bit) 1511 { 1512 return boot_cpu_has(bit); 1513 } 1514 EXPORT_SYMBOL_GPL(__static_cpu_has_safe); 1515