1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/sched.h> 4 #include <linux/sched/clock.h> 5 6 #include <asm/cpufeature.h> 7 #include <asm/e820/api.h> 8 #include <asm/mtrr.h> 9 #include <asm/msr.h> 10 11 #include "cpu.h" 12 13 #define ACE_PRESENT (1 << 6) 14 #define ACE_ENABLED (1 << 7) 15 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ 16 17 #define RNG_PRESENT (1 << 2) 18 #define RNG_ENABLED (1 << 3) 19 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ 20 21 static void init_c3(struct cpuinfo_x86 *c) 22 { 23 u32 lo, hi; 24 25 /* Test for Centaur Extended Feature Flags presence */ 26 if (cpuid_eax(0xC0000000) >= 0xC0000001) { 27 u32 tmp = cpuid_edx(0xC0000001); 28 29 /* enable ACE unit, if present and disabled */ 30 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { 31 rdmsr(MSR_VIA_FCR, lo, hi); 32 lo |= ACE_FCR; /* enable ACE unit */ 33 wrmsr(MSR_VIA_FCR, lo, hi); 34 pr_info("CPU: Enabled ACE h/w crypto\n"); 35 } 36 37 /* enable RNG unit, if present and disabled */ 38 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { 39 rdmsr(MSR_VIA_RNG, lo, hi); 40 lo |= RNG_ENABLE; /* enable RNG unit */ 41 wrmsr(MSR_VIA_RNG, lo, hi); 42 pr_info("CPU: Enabled h/w RNG\n"); 43 } 44 45 /* store Centaur Extended Feature Flags as 46 * word 5 of the CPU capability bit array 47 */ 48 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); 49 } 50 #ifdef CONFIG_X86_32 51 /* Cyrix III family needs CX8 & PGE explicitly enabled. */ 52 if (c->x86_model >= 6 && c->x86_model <= 13) { 53 rdmsr(MSR_VIA_FCR, lo, hi); 54 lo |= (1<<1 | 1<<7); 55 wrmsr(MSR_VIA_FCR, lo, hi); 56 set_cpu_cap(c, X86_FEATURE_CX8); 57 } 58 59 /* Before Nehemiah, the C3's had 3dNOW! */ 60 if (c->x86_model >= 6 && c->x86_model < 9) 61 set_cpu_cap(c, X86_FEATURE_3DNOW); 62 #endif 63 if (c->x86 == 0x6 && c->x86_model >= 0xf) { 64 c->x86_cache_alignment = c->x86_clflush_size * 2; 65 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 66 } 67 } 68 69 enum { 70 ECX8 = 1<<1, 71 EIERRINT = 1<<2, 72 DPM = 1<<3, 73 DMCE = 1<<4, 74 DSTPCLK = 1<<5, 75 ELINEAR = 1<<6, 76 DSMC = 1<<7, 77 DTLOCK = 1<<8, 78 EDCTLB = 1<<8, 79 EMMX = 1<<9, 80 DPDC = 1<<11, 81 EBRPRED = 1<<12, 82 DIC = 1<<13, 83 DDC = 1<<14, 84 DNA = 1<<15, 85 ERETSTK = 1<<16, 86 E2MMX = 1<<19, 87 EAMD3D = 1<<20, 88 }; 89 90 static void early_init_centaur(struct cpuinfo_x86 *c) 91 { 92 switch (c->x86) { 93 #ifdef CONFIG_X86_32 94 case 5: 95 /* Emulate MTRRs using Centaur's MCR. */ 96 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 97 break; 98 #endif 99 case 6: 100 if (c->x86_model >= 0xf) 101 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 102 break; 103 } 104 #ifdef CONFIG_X86_64 105 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 106 #endif 107 if (c->x86_power & (1 << 8)) { 108 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 109 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 110 } 111 } 112 113 static void init_centaur(struct cpuinfo_x86 *c) 114 { 115 #ifdef CONFIG_X86_32 116 char *name; 117 u32 fcr_set = 0; 118 u32 fcr_clr = 0; 119 u32 lo, hi, newlo; 120 u32 aa, bb, cc, dd; 121 122 /* 123 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 124 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 125 */ 126 clear_cpu_cap(c, 0*32+31); 127 #endif 128 early_init_centaur(c); 129 init_intel_cacheinfo(c); 130 detect_num_cpu_cores(c); 131 #ifdef CONFIG_X86_32 132 detect_ht(c); 133 #endif 134 135 if (c->cpuid_level > 9) { 136 unsigned int eax = cpuid_eax(10); 137 138 /* 139 * Check for version and the number of counters 140 * Version(eax[7:0]) can't be 0; 141 * Counters(eax[15:8]) should be greater than 1; 142 */ 143 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1)) 144 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 145 } 146 147 switch (c->x86) { 148 #ifdef CONFIG_X86_32 149 case 5: 150 switch (c->x86_model) { 151 case 4: 152 name = "C6"; 153 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; 154 fcr_clr = DPDC; 155 pr_notice("Disabling bugged TSC.\n"); 156 clear_cpu_cap(c, X86_FEATURE_TSC); 157 break; 158 case 8: 159 switch (c->x86_stepping) { 160 default: 161 name = "2"; 162 break; 163 case 7 ... 9: 164 name = "2A"; 165 break; 166 case 10 ... 15: 167 name = "2B"; 168 break; 169 } 170 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 171 E2MMX|EAMD3D; 172 fcr_clr = DPDC; 173 break; 174 case 9: 175 name = "3"; 176 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 177 E2MMX|EAMD3D; 178 fcr_clr = DPDC; 179 break; 180 default: 181 name = "??"; 182 } 183 184 rdmsr(MSR_IDT_FCR1, lo, hi); 185 newlo = (lo|fcr_set) & (~fcr_clr); 186 187 if (newlo != lo) { 188 pr_info("Centaur FCR was 0x%X now 0x%X\n", 189 lo, newlo); 190 wrmsr(MSR_IDT_FCR1, newlo, hi); 191 } else { 192 pr_info("Centaur FCR is 0x%X\n", lo); 193 } 194 /* Emulate MTRRs using Centaur's MCR. */ 195 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 196 /* Report CX8 */ 197 set_cpu_cap(c, X86_FEATURE_CX8); 198 /* Set 3DNow! on Winchip 2 and above. */ 199 if (c->x86_model >= 8) 200 set_cpu_cap(c, X86_FEATURE_3DNOW); 201 /* See if we can find out some more. */ 202 if (cpuid_eax(0x80000000) >= 0x80000005) { 203 /* Yes, we can. */ 204 cpuid(0x80000005, &aa, &bb, &cc, &dd); 205 /* Add L1 data and code cache sizes. */ 206 c->x86_cache_size = (cc>>24)+(dd>>24); 207 } 208 sprintf(c->x86_model_id, "WinChip %s", name); 209 break; 210 #endif 211 case 6: 212 init_c3(c); 213 break; 214 } 215 #ifdef CONFIG_X86_64 216 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 217 #endif 218 219 init_ia32_feat_ctl(c); 220 } 221 222 #ifdef CONFIG_X86_32 223 static unsigned int 224 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) 225 { 226 /* VIA C3 CPUs (670-68F) need further shifting. */ 227 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) 228 size >>= 8; 229 230 /* 231 * There's also an erratum in Nehemiah stepping 1, which 232 * returns '65KB' instead of '64KB' 233 * - Note, it seems this may only be in engineering samples. 234 */ 235 if ((c->x86 == 6) && (c->x86_model == 9) && 236 (c->x86_stepping == 1) && (size == 65)) 237 size -= 1; 238 return size; 239 } 240 #endif 241 242 static const struct cpu_dev centaur_cpu_dev = { 243 .c_vendor = "Centaur", 244 .c_ident = { "CentaurHauls" }, 245 .c_early_init = early_init_centaur, 246 .c_init = init_centaur, 247 #ifdef CONFIG_X86_32 248 .legacy_cache_size = centaur_size_cache, 249 #endif 250 .c_x86_vendor = X86_VENDOR_CENTAUR, 251 }; 252 253 cpu_dev_register(centaur_cpu_dev); 254