1 #include <linux/bitops.h> 2 #include <linux/kernel.h> 3 4 #include <asm/processor.h> 5 #include <asm/e820.h> 6 #include <asm/mtrr.h> 7 #include <asm/msr.h> 8 9 #include "cpu.h" 10 11 #define ACE_PRESENT (1 << 6) 12 #define ACE_ENABLED (1 << 7) 13 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ 14 15 #define RNG_PRESENT (1 << 2) 16 #define RNG_ENABLED (1 << 3) 17 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ 18 19 static void init_c3(struct cpuinfo_x86 *c) 20 { 21 u32 lo, hi; 22 23 /* Test for Centaur Extended Feature Flags presence */ 24 if (cpuid_eax(0xC0000000) >= 0xC0000001) { 25 u32 tmp = cpuid_edx(0xC0000001); 26 27 /* enable ACE unit, if present and disabled */ 28 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { 29 rdmsr(MSR_VIA_FCR, lo, hi); 30 lo |= ACE_FCR; /* enable ACE unit */ 31 wrmsr(MSR_VIA_FCR, lo, hi); 32 printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n"); 33 } 34 35 /* enable RNG unit, if present and disabled */ 36 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { 37 rdmsr(MSR_VIA_RNG, lo, hi); 38 lo |= RNG_ENABLE; /* enable RNG unit */ 39 wrmsr(MSR_VIA_RNG, lo, hi); 40 printk(KERN_INFO "CPU: Enabled h/w RNG\n"); 41 } 42 43 /* store Centaur Extended Feature Flags as 44 * word 5 of the CPU capability bit array 45 */ 46 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); 47 } 48 #ifdef CONFIG_X86_32 49 /* Cyrix III family needs CX8 & PGE explicitly enabled. */ 50 if (c->x86_model >= 6 && c->x86_model <= 13) { 51 rdmsr(MSR_VIA_FCR, lo, hi); 52 lo |= (1<<1 | 1<<7); 53 wrmsr(MSR_VIA_FCR, lo, hi); 54 set_cpu_cap(c, X86_FEATURE_CX8); 55 } 56 57 /* Before Nehemiah, the C3's had 3dNOW! */ 58 if (c->x86_model >= 6 && c->x86_model < 9) 59 set_cpu_cap(c, X86_FEATURE_3DNOW); 60 #endif 61 if (c->x86 == 0x6 && c->x86_model >= 0xf) { 62 c->x86_cache_alignment = c->x86_clflush_size * 2; 63 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 64 } 65 66 cpu_detect_cache_sizes(c); 67 } 68 69 enum { 70 ECX8 = 1<<1, 71 EIERRINT = 1<<2, 72 DPM = 1<<3, 73 DMCE = 1<<4, 74 DSTPCLK = 1<<5, 75 ELINEAR = 1<<6, 76 DSMC = 1<<7, 77 DTLOCK = 1<<8, 78 EDCTLB = 1<<8, 79 EMMX = 1<<9, 80 DPDC = 1<<11, 81 EBRPRED = 1<<12, 82 DIC = 1<<13, 83 DDC = 1<<14, 84 DNA = 1<<15, 85 ERETSTK = 1<<16, 86 E2MMX = 1<<19, 87 EAMD3D = 1<<20, 88 }; 89 90 static void early_init_centaur(struct cpuinfo_x86 *c) 91 { 92 switch (c->x86) { 93 #ifdef CONFIG_X86_32 94 case 5: 95 /* Emulate MTRRs using Centaur's MCR. */ 96 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 97 break; 98 #endif 99 case 6: 100 if (c->x86_model >= 0xf) 101 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 102 break; 103 } 104 #ifdef CONFIG_X86_64 105 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 106 #endif 107 } 108 109 static void init_centaur(struct cpuinfo_x86 *c) 110 { 111 #ifdef CONFIG_X86_32 112 char *name; 113 u32 fcr_set = 0; 114 u32 fcr_clr = 0; 115 u32 lo, hi, newlo; 116 u32 aa, bb, cc, dd; 117 118 /* 119 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 120 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 121 */ 122 clear_cpu_cap(c, 0*32+31); 123 #endif 124 early_init_centaur(c); 125 switch (c->x86) { 126 #ifdef CONFIG_X86_32 127 case 5: 128 switch (c->x86_model) { 129 case 4: 130 name = "C6"; 131 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; 132 fcr_clr = DPDC; 133 printk(KERN_NOTICE "Disabling bugged TSC.\n"); 134 clear_cpu_cap(c, X86_FEATURE_TSC); 135 break; 136 case 8: 137 switch (c->x86_mask) { 138 default: 139 name = "2"; 140 break; 141 case 7 ... 9: 142 name = "2A"; 143 break; 144 case 10 ... 15: 145 name = "2B"; 146 break; 147 } 148 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 149 E2MMX|EAMD3D; 150 fcr_clr = DPDC; 151 break; 152 case 9: 153 name = "3"; 154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 155 E2MMX|EAMD3D; 156 fcr_clr = DPDC; 157 break; 158 default: 159 name = "??"; 160 } 161 162 rdmsr(MSR_IDT_FCR1, lo, hi); 163 newlo = (lo|fcr_set) & (~fcr_clr); 164 165 if (newlo != lo) { 166 printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", 167 lo, newlo); 168 wrmsr(MSR_IDT_FCR1, newlo, hi); 169 } else { 170 printk(KERN_INFO "Centaur FCR is 0x%X\n", lo); 171 } 172 /* Emulate MTRRs using Centaur's MCR. */ 173 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 174 /* Report CX8 */ 175 set_cpu_cap(c, X86_FEATURE_CX8); 176 /* Set 3DNow! on Winchip 2 and above. */ 177 if (c->x86_model >= 8) 178 set_cpu_cap(c, X86_FEATURE_3DNOW); 179 /* See if we can find out some more. */ 180 if (cpuid_eax(0x80000000) >= 0x80000005) { 181 /* Yes, we can. */ 182 cpuid(0x80000005, &aa, &bb, &cc, &dd); 183 /* Add L1 data and code cache sizes. */ 184 c->x86_cache_size = (cc>>24)+(dd>>24); 185 } 186 sprintf(c->x86_model_id, "WinChip %s", name); 187 break; 188 #endif 189 case 6: 190 init_c3(c); 191 break; 192 } 193 #ifdef CONFIG_X86_64 194 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 195 #endif 196 } 197 198 #ifdef CONFIG_X86_32 199 static unsigned int 200 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) 201 { 202 /* VIA C3 CPUs (670-68F) need further shifting. */ 203 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) 204 size >>= 8; 205 206 /* 207 * There's also an erratum in Nehemiah stepping 1, which 208 * returns '65KB' instead of '64KB' 209 * - Note, it seems this may only be in engineering samples. 210 */ 211 if ((c->x86 == 6) && (c->x86_model == 9) && 212 (c->x86_mask == 1) && (size == 65)) 213 size -= 1; 214 return size; 215 } 216 #endif 217 218 static const struct cpu_dev centaur_cpu_dev = { 219 .c_vendor = "Centaur", 220 .c_ident = { "CentaurHauls" }, 221 .c_early_init = early_init_centaur, 222 .c_init = init_centaur, 223 #ifdef CONFIG_X86_32 224 .legacy_cache_size = centaur_size_cache, 225 #endif 226 .c_x86_vendor = X86_VENDOR_CENTAUR, 227 }; 228 229 cpu_dev_register(centaur_cpu_dev); 230