1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/sched.h> 4 #include <linux/sched/clock.h> 5 6 #include <asm/cpufeature.h> 7 #include <asm/e820/api.h> 8 #include <asm/mtrr.h> 9 #include <asm/msr.h> 10 11 #include "cpu.h" 12 13 #define ACE_PRESENT (1 << 6) 14 #define ACE_ENABLED (1 << 7) 15 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ 16 17 #define RNG_PRESENT (1 << 2) 18 #define RNG_ENABLED (1 << 3) 19 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ 20 21 static void init_c3(struct cpuinfo_x86 *c) 22 { 23 u32 lo, hi; 24 25 /* Test for Centaur Extended Feature Flags presence */ 26 if (cpuid_eax(0xC0000000) >= 0xC0000001) { 27 u32 tmp = cpuid_edx(0xC0000001); 28 29 /* enable ACE unit, if present and disabled */ 30 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { 31 rdmsr(MSR_VIA_FCR, lo, hi); 32 lo |= ACE_FCR; /* enable ACE unit */ 33 wrmsr(MSR_VIA_FCR, lo, hi); 34 pr_info("CPU: Enabled ACE h/w crypto\n"); 35 } 36 37 /* enable RNG unit, if present and disabled */ 38 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { 39 rdmsr(MSR_VIA_RNG, lo, hi); 40 lo |= RNG_ENABLE; /* enable RNG unit */ 41 wrmsr(MSR_VIA_RNG, lo, hi); 42 pr_info("CPU: Enabled h/w RNG\n"); 43 } 44 45 /* store Centaur Extended Feature Flags as 46 * word 5 of the CPU capability bit array 47 */ 48 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); 49 } 50 #ifdef CONFIG_X86_32 51 /* Cyrix III family needs CX8 & PGE explicitly enabled. */ 52 if (c->x86_model >= 6 && c->x86_model <= 13) { 53 rdmsr(MSR_VIA_FCR, lo, hi); 54 lo |= (1<<1 | 1<<7); 55 wrmsr(MSR_VIA_FCR, lo, hi); 56 set_cpu_cap(c, X86_FEATURE_CX8); 57 } 58 59 /* Before Nehemiah, the C3's had 3dNOW! */ 60 if (c->x86_model >= 6 && c->x86_model < 9) 61 set_cpu_cap(c, X86_FEATURE_3DNOW); 62 #endif 63 if (c->x86 == 0x6 && c->x86_model >= 0xf) { 64 c->x86_cache_alignment = c->x86_clflush_size * 2; 65 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 66 } 67 68 cpu_detect_cache_sizes(c); 69 } 70 71 enum { 72 ECX8 = 1<<1, 73 EIERRINT = 1<<2, 74 DPM = 1<<3, 75 DMCE = 1<<4, 76 DSTPCLK = 1<<5, 77 ELINEAR = 1<<6, 78 DSMC = 1<<7, 79 DTLOCK = 1<<8, 80 EDCTLB = 1<<8, 81 EMMX = 1<<9, 82 DPDC = 1<<11, 83 EBRPRED = 1<<12, 84 DIC = 1<<13, 85 DDC = 1<<14, 86 DNA = 1<<15, 87 ERETSTK = 1<<16, 88 E2MMX = 1<<19, 89 EAMD3D = 1<<20, 90 }; 91 92 static void early_init_centaur(struct cpuinfo_x86 *c) 93 { 94 switch (c->x86) { 95 #ifdef CONFIG_X86_32 96 case 5: 97 /* Emulate MTRRs using Centaur's MCR. */ 98 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 99 break; 100 #endif 101 case 6: 102 if (c->x86_model >= 0xf) 103 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 104 break; 105 } 106 #ifdef CONFIG_X86_64 107 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 108 #endif 109 if (c->x86_power & (1 << 8)) { 110 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 111 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 112 } 113 } 114 115 static void init_centaur(struct cpuinfo_x86 *c) 116 { 117 #ifdef CONFIG_X86_32 118 char *name; 119 u32 fcr_set = 0; 120 u32 fcr_clr = 0; 121 u32 lo, hi, newlo; 122 u32 aa, bb, cc, dd; 123 124 /* 125 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 126 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 127 */ 128 clear_cpu_cap(c, 0*32+31); 129 #endif 130 early_init_centaur(c); 131 switch (c->x86) { 132 #ifdef CONFIG_X86_32 133 case 5: 134 switch (c->x86_model) { 135 case 4: 136 name = "C6"; 137 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; 138 fcr_clr = DPDC; 139 pr_notice("Disabling bugged TSC.\n"); 140 clear_cpu_cap(c, X86_FEATURE_TSC); 141 break; 142 case 8: 143 switch (c->x86_mask) { 144 default: 145 name = "2"; 146 break; 147 case 7 ... 9: 148 name = "2A"; 149 break; 150 case 10 ... 15: 151 name = "2B"; 152 break; 153 } 154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 155 E2MMX|EAMD3D; 156 fcr_clr = DPDC; 157 break; 158 case 9: 159 name = "3"; 160 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 161 E2MMX|EAMD3D; 162 fcr_clr = DPDC; 163 break; 164 default: 165 name = "??"; 166 } 167 168 rdmsr(MSR_IDT_FCR1, lo, hi); 169 newlo = (lo|fcr_set) & (~fcr_clr); 170 171 if (newlo != lo) { 172 pr_info("Centaur FCR was 0x%X now 0x%X\n", 173 lo, newlo); 174 wrmsr(MSR_IDT_FCR1, newlo, hi); 175 } else { 176 pr_info("Centaur FCR is 0x%X\n", lo); 177 } 178 /* Emulate MTRRs using Centaur's MCR. */ 179 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); 180 /* Report CX8 */ 181 set_cpu_cap(c, X86_FEATURE_CX8); 182 /* Set 3DNow! on Winchip 2 and above. */ 183 if (c->x86_model >= 8) 184 set_cpu_cap(c, X86_FEATURE_3DNOW); 185 /* See if we can find out some more. */ 186 if (cpuid_eax(0x80000000) >= 0x80000005) { 187 /* Yes, we can. */ 188 cpuid(0x80000005, &aa, &bb, &cc, &dd); 189 /* Add L1 data and code cache sizes. */ 190 c->x86_cache_size = (cc>>24)+(dd>>24); 191 } 192 sprintf(c->x86_model_id, "WinChip %s", name); 193 break; 194 #endif 195 case 6: 196 init_c3(c); 197 break; 198 } 199 #ifdef CONFIG_X86_64 200 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 201 #endif 202 } 203 204 #ifdef CONFIG_X86_32 205 static unsigned int 206 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) 207 { 208 /* VIA C3 CPUs (670-68F) need further shifting. */ 209 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) 210 size >>= 8; 211 212 /* 213 * There's also an erratum in Nehemiah stepping 1, which 214 * returns '65KB' instead of '64KB' 215 * - Note, it seems this may only be in engineering samples. 216 */ 217 if ((c->x86 == 6) && (c->x86_model == 9) && 218 (c->x86_mask == 1) && (size == 65)) 219 size -= 1; 220 return size; 221 } 222 #endif 223 224 static const struct cpu_dev centaur_cpu_dev = { 225 .c_vendor = "Centaur", 226 .c_ident = { "CentaurHauls" }, 227 .c_early_init = early_init_centaur, 228 .c_init = init_centaur, 229 #ifdef CONFIG_X86_32 230 .legacy_cache_size = centaur_size_cache, 231 #endif 232 .c_x86_vendor = X86_VENDOR_CENTAUR, 233 }; 234 235 cpu_dev_register(centaur_cpu_dev); 236