1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Cyrix stuff, June 1998 by: 6 * - Rafael R. Reilova (moved everything from head.S), 7 * <rreilova@ececs.uc.edu> 8 * - Channing Corn (tests & fixes), 9 * - Andrew D. Balsa (code cleanup). 10 */ 11 #include <linux/init.h> 12 #include <linux/utsname.h> 13 #include <linux/cpu.h> 14 #include <linux/module.h> 15 #include <linux/nospec.h> 16 #include <linux/prctl.h> 17 #include <linux/sched/smt.h> 18 #include <linux/pgtable.h> 19 #include <linux/bpf.h> 20 21 #include <asm/spec-ctrl.h> 22 #include <asm/cmdline.h> 23 #include <asm/bugs.h> 24 #include <asm/processor.h> 25 #include <asm/processor-flags.h> 26 #include <asm/fpu/api.h> 27 #include <asm/msr.h> 28 #include <asm/vmx.h> 29 #include <asm/paravirt.h> 30 #include <asm/alternative.h> 31 #include <asm/set_memory.h> 32 #include <asm/intel-family.h> 33 #include <asm/e820/api.h> 34 #include <asm/hypervisor.h> 35 #include <asm/tlbflush.h> 36 37 #include "cpu.h" 38 39 static void __init spectre_v1_select_mitigation(void); 40 static void __init spectre_v2_select_mitigation(void); 41 static void __init ssb_select_mitigation(void); 42 static void __init l1tf_select_mitigation(void); 43 static void __init mds_select_mitigation(void); 44 static void __init md_clear_update_mitigation(void); 45 static void __init md_clear_select_mitigation(void); 46 static void __init taa_select_mitigation(void); 47 static void __init mmio_select_mitigation(void); 48 static void __init srbds_select_mitigation(void); 49 static void __init l1d_flush_select_mitigation(void); 50 51 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ 52 u64 x86_spec_ctrl_base; 53 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); 54 static DEFINE_MUTEX(spec_ctrl_mutex); 55 56 /* 57 * The vendor and possibly platform specific bits which can be modified in 58 * x86_spec_ctrl_base. 59 */ 60 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; 61 62 /* 63 * AMD specific MSR info for Speculative Store Bypass control. 64 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). 65 */ 66 u64 __ro_after_init x86_amd_ls_cfg_base; 67 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; 68 69 /* Control conditional STIBP in switch_to() */ 70 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); 71 /* Control conditional IBPB in switch_mm() */ 72 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 73 /* Control unconditional IBPB in switch_mm() */ 74 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 75 76 /* Control MDS CPU buffer clear before returning to user space */ 77 DEFINE_STATIC_KEY_FALSE(mds_user_clear); 78 EXPORT_SYMBOL_GPL(mds_user_clear); 79 /* Control MDS CPU buffer clear before idling (halt, mwait) */ 80 DEFINE_STATIC_KEY_FALSE(mds_idle_clear); 81 EXPORT_SYMBOL_GPL(mds_idle_clear); 82 83 /* 84 * Controls whether l1d flush based mitigations are enabled, 85 * based on hw features and admin setting via boot parameter 86 * defaults to false 87 */ 88 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 89 90 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */ 91 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); 92 EXPORT_SYMBOL_GPL(mmio_stale_data_clear); 93 94 void __init check_bugs(void) 95 { 96 identify_boot_cpu(); 97 98 /* 99 * identify_boot_cpu() initialized SMT support information, let the 100 * core code know. 101 */ 102 cpu_smt_check_topology(); 103 104 if (!IS_ENABLED(CONFIG_SMP)) { 105 pr_info("CPU: "); 106 print_cpu_info(&boot_cpu_data); 107 } 108 109 /* 110 * Read the SPEC_CTRL MSR to account for reserved bits which may 111 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD 112 * init code as it is not enumerated and depends on the family. 113 */ 114 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 115 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 116 117 /* Allow STIBP in MSR_SPEC_CTRL if supported */ 118 if (boot_cpu_has(X86_FEATURE_STIBP)) 119 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; 120 121 /* Select the proper CPU mitigations before patching alternatives: */ 122 spectre_v1_select_mitigation(); 123 spectre_v2_select_mitigation(); 124 ssb_select_mitigation(); 125 l1tf_select_mitigation(); 126 md_clear_select_mitigation(); 127 srbds_select_mitigation(); 128 l1d_flush_select_mitigation(); 129 130 arch_smt_update(); 131 132 #ifdef CONFIG_X86_32 133 /* 134 * Check whether we are able to run this kernel safely on SMP. 135 * 136 * - i386 is no longer supported. 137 * - In order to run on anything without a TSC, we need to be 138 * compiled for a i486. 139 */ 140 if (boot_cpu_data.x86 < 4) 141 panic("Kernel requires i486+ for 'invlpg' and other features"); 142 143 init_utsname()->machine[1] = 144 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 145 alternative_instructions(); 146 147 fpu__init_check_bugs(); 148 #else /* CONFIG_X86_64 */ 149 alternative_instructions(); 150 151 /* 152 * Make sure the first 2MB area is not mapped by huge pages 153 * There are typically fixed size MTRRs in there and overlapping 154 * MTRRs into large pages causes slow downs. 155 * 156 * Right now we don't do that with gbpages because there seems 157 * very little benefit for that case. 158 */ 159 if (!direct_gbpages) 160 set_memory_4k((unsigned long)__va(0), 1); 161 #endif 162 } 163 164 void 165 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) 166 { 167 u64 msrval, guestval, hostval = x86_spec_ctrl_base; 168 struct thread_info *ti = current_thread_info(); 169 170 /* Is MSR_SPEC_CTRL implemented ? */ 171 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { 172 /* 173 * Restrict guest_spec_ctrl to supported values. Clear the 174 * modifiable bits in the host base value and or the 175 * modifiable bits from the guest value. 176 */ 177 guestval = hostval & ~x86_spec_ctrl_mask; 178 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; 179 180 /* SSBD controlled in MSR_SPEC_CTRL */ 181 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 182 static_cpu_has(X86_FEATURE_AMD_SSBD)) 183 hostval |= ssbd_tif_to_spec_ctrl(ti->flags); 184 185 /* Conditional STIBP enabled? */ 186 if (static_branch_unlikely(&switch_to_cond_stibp)) 187 hostval |= stibp_tif_to_spec_ctrl(ti->flags); 188 189 if (hostval != guestval) { 190 msrval = setguest ? guestval : hostval; 191 wrmsrl(MSR_IA32_SPEC_CTRL, msrval); 192 } 193 } 194 195 /* 196 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update 197 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. 198 */ 199 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 200 !static_cpu_has(X86_FEATURE_VIRT_SSBD)) 201 return; 202 203 /* 204 * If the host has SSBD mitigation enabled, force it in the host's 205 * virtual MSR value. If its not permanently enabled, evaluate 206 * current's TIF_SSBD thread flag. 207 */ 208 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) 209 hostval = SPEC_CTRL_SSBD; 210 else 211 hostval = ssbd_tif_to_spec_ctrl(ti->flags); 212 213 /* Sanitize the guest value */ 214 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; 215 216 if (hostval != guestval) { 217 unsigned long tif; 218 219 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : 220 ssbd_spec_ctrl_to_tif(hostval); 221 222 speculation_ctrl_update(tif); 223 } 224 } 225 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); 226 227 static void x86_amd_ssb_disable(void) 228 { 229 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; 230 231 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) 232 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); 233 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) 234 wrmsrl(MSR_AMD64_LS_CFG, msrval); 235 } 236 237 #undef pr_fmt 238 #define pr_fmt(fmt) "MDS: " fmt 239 240 /* Default mitigation for MDS-affected CPUs */ 241 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; 242 static bool mds_nosmt __ro_after_init = false; 243 244 static const char * const mds_strings[] = { 245 [MDS_MITIGATION_OFF] = "Vulnerable", 246 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", 247 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", 248 }; 249 250 static void __init mds_select_mitigation(void) 251 { 252 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { 253 mds_mitigation = MDS_MITIGATION_OFF; 254 return; 255 } 256 257 if (mds_mitigation == MDS_MITIGATION_FULL) { 258 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) 259 mds_mitigation = MDS_MITIGATION_VMWERV; 260 261 static_branch_enable(&mds_user_clear); 262 263 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && 264 (mds_nosmt || cpu_mitigations_auto_nosmt())) 265 cpu_smt_disable(false); 266 } 267 } 268 269 static int __init mds_cmdline(char *str) 270 { 271 if (!boot_cpu_has_bug(X86_BUG_MDS)) 272 return 0; 273 274 if (!str) 275 return -EINVAL; 276 277 if (!strcmp(str, "off")) 278 mds_mitigation = MDS_MITIGATION_OFF; 279 else if (!strcmp(str, "full")) 280 mds_mitigation = MDS_MITIGATION_FULL; 281 else if (!strcmp(str, "full,nosmt")) { 282 mds_mitigation = MDS_MITIGATION_FULL; 283 mds_nosmt = true; 284 } 285 286 return 0; 287 } 288 early_param("mds", mds_cmdline); 289 290 #undef pr_fmt 291 #define pr_fmt(fmt) "TAA: " fmt 292 293 enum taa_mitigations { 294 TAA_MITIGATION_OFF, 295 TAA_MITIGATION_UCODE_NEEDED, 296 TAA_MITIGATION_VERW, 297 TAA_MITIGATION_TSX_DISABLED, 298 }; 299 300 /* Default mitigation for TAA-affected CPUs */ 301 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW; 302 static bool taa_nosmt __ro_after_init; 303 304 static const char * const taa_strings[] = { 305 [TAA_MITIGATION_OFF] = "Vulnerable", 306 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 307 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 308 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled", 309 }; 310 311 static void __init taa_select_mitigation(void) 312 { 313 u64 ia32_cap; 314 315 if (!boot_cpu_has_bug(X86_BUG_TAA)) { 316 taa_mitigation = TAA_MITIGATION_OFF; 317 return; 318 } 319 320 /* TSX previously disabled by tsx=off */ 321 if (!boot_cpu_has(X86_FEATURE_RTM)) { 322 taa_mitigation = TAA_MITIGATION_TSX_DISABLED; 323 return; 324 } 325 326 if (cpu_mitigations_off()) { 327 taa_mitigation = TAA_MITIGATION_OFF; 328 return; 329 } 330 331 /* 332 * TAA mitigation via VERW is turned off if both 333 * tsx_async_abort=off and mds=off are specified. 334 */ 335 if (taa_mitigation == TAA_MITIGATION_OFF && 336 mds_mitigation == MDS_MITIGATION_OFF) 337 return; 338 339 if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) 340 taa_mitigation = TAA_MITIGATION_VERW; 341 else 342 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 343 344 /* 345 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1. 346 * A microcode update fixes this behavior to clear CPU buffers. It also 347 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the 348 * ARCH_CAP_TSX_CTRL_MSR bit. 349 * 350 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode 351 * update is required. 352 */ 353 ia32_cap = x86_read_arch_cap_msr(); 354 if ( (ia32_cap & ARCH_CAP_MDS_NO) && 355 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR)) 356 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 357 358 /* 359 * TSX is enabled, select alternate mitigation for TAA which is 360 * the same as MDS. Enable MDS static branch to clear CPU buffers. 361 * 362 * For guests that can't determine whether the correct microcode is 363 * present on host, enable the mitigation for UCODE_NEEDED as well. 364 */ 365 static_branch_enable(&mds_user_clear); 366 367 if (taa_nosmt || cpu_mitigations_auto_nosmt()) 368 cpu_smt_disable(false); 369 } 370 371 static int __init tsx_async_abort_parse_cmdline(char *str) 372 { 373 if (!boot_cpu_has_bug(X86_BUG_TAA)) 374 return 0; 375 376 if (!str) 377 return -EINVAL; 378 379 if (!strcmp(str, "off")) { 380 taa_mitigation = TAA_MITIGATION_OFF; 381 } else if (!strcmp(str, "full")) { 382 taa_mitigation = TAA_MITIGATION_VERW; 383 } else if (!strcmp(str, "full,nosmt")) { 384 taa_mitigation = TAA_MITIGATION_VERW; 385 taa_nosmt = true; 386 } 387 388 return 0; 389 } 390 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline); 391 392 #undef pr_fmt 393 #define pr_fmt(fmt) "MMIO Stale Data: " fmt 394 395 enum mmio_mitigations { 396 MMIO_MITIGATION_OFF, 397 MMIO_MITIGATION_UCODE_NEEDED, 398 MMIO_MITIGATION_VERW, 399 }; 400 401 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ 402 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW; 403 static bool mmio_nosmt __ro_after_init = false; 404 405 static const char * const mmio_strings[] = { 406 [MMIO_MITIGATION_OFF] = "Vulnerable", 407 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 408 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 409 }; 410 411 static void __init mmio_select_mitigation(void) 412 { 413 u64 ia32_cap; 414 415 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) || 416 cpu_mitigations_off()) { 417 mmio_mitigation = MMIO_MITIGATION_OFF; 418 return; 419 } 420 421 if (mmio_mitigation == MMIO_MITIGATION_OFF) 422 return; 423 424 ia32_cap = x86_read_arch_cap_msr(); 425 426 /* 427 * Enable CPU buffer clear mitigation for host and VMM, if also affected 428 * by MDS or TAA. Otherwise, enable mitigation for VMM only. 429 */ 430 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) && 431 boot_cpu_has(X86_FEATURE_RTM))) 432 static_branch_enable(&mds_user_clear); 433 else 434 static_branch_enable(&mmio_stale_data_clear); 435 436 /* 437 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can 438 * be propagated to uncore buffers, clearing the Fill buffers on idle 439 * is required irrespective of SMT state. 440 */ 441 if (!(ia32_cap & ARCH_CAP_FBSDP_NO)) 442 static_branch_enable(&mds_idle_clear); 443 444 /* 445 * Check if the system has the right microcode. 446 * 447 * CPU Fill buffer clear mitigation is enumerated by either an explicit 448 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS 449 * affected systems. 450 */ 451 if ((ia32_cap & ARCH_CAP_FB_CLEAR) || 452 (boot_cpu_has(X86_FEATURE_MD_CLEAR) && 453 boot_cpu_has(X86_FEATURE_FLUSH_L1D) && 454 !(ia32_cap & ARCH_CAP_MDS_NO))) 455 mmio_mitigation = MMIO_MITIGATION_VERW; 456 else 457 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED; 458 459 if (mmio_nosmt || cpu_mitigations_auto_nosmt()) 460 cpu_smt_disable(false); 461 } 462 463 static int __init mmio_stale_data_parse_cmdline(char *str) 464 { 465 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 466 return 0; 467 468 if (!str) 469 return -EINVAL; 470 471 if (!strcmp(str, "off")) { 472 mmio_mitigation = MMIO_MITIGATION_OFF; 473 } else if (!strcmp(str, "full")) { 474 mmio_mitigation = MMIO_MITIGATION_VERW; 475 } else if (!strcmp(str, "full,nosmt")) { 476 mmio_mitigation = MMIO_MITIGATION_VERW; 477 mmio_nosmt = true; 478 } 479 480 return 0; 481 } 482 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline); 483 484 #undef pr_fmt 485 #define pr_fmt(fmt) "" fmt 486 487 static void __init md_clear_update_mitigation(void) 488 { 489 if (cpu_mitigations_off()) 490 return; 491 492 if (!static_key_enabled(&mds_user_clear)) 493 goto out; 494 495 /* 496 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data 497 * mitigation, if necessary. 498 */ 499 if (mds_mitigation == MDS_MITIGATION_OFF && 500 boot_cpu_has_bug(X86_BUG_MDS)) { 501 mds_mitigation = MDS_MITIGATION_FULL; 502 mds_select_mitigation(); 503 } 504 if (taa_mitigation == TAA_MITIGATION_OFF && 505 boot_cpu_has_bug(X86_BUG_TAA)) { 506 taa_mitigation = TAA_MITIGATION_VERW; 507 taa_select_mitigation(); 508 } 509 if (mmio_mitigation == MMIO_MITIGATION_OFF && 510 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) { 511 mmio_mitigation = MMIO_MITIGATION_VERW; 512 mmio_select_mitigation(); 513 } 514 out: 515 if (boot_cpu_has_bug(X86_BUG_MDS)) 516 pr_info("MDS: %s\n", mds_strings[mds_mitigation]); 517 if (boot_cpu_has_bug(X86_BUG_TAA)) 518 pr_info("TAA: %s\n", taa_strings[taa_mitigation]); 519 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 520 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); 521 } 522 523 static void __init md_clear_select_mitigation(void) 524 { 525 mds_select_mitigation(); 526 taa_select_mitigation(); 527 mmio_select_mitigation(); 528 529 /* 530 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update 531 * and print their mitigation after MDS, TAA and MMIO Stale Data 532 * mitigation selection is done. 533 */ 534 md_clear_update_mitigation(); 535 } 536 537 #undef pr_fmt 538 #define pr_fmt(fmt) "SRBDS: " fmt 539 540 enum srbds_mitigations { 541 SRBDS_MITIGATION_OFF, 542 SRBDS_MITIGATION_UCODE_NEEDED, 543 SRBDS_MITIGATION_FULL, 544 SRBDS_MITIGATION_TSX_OFF, 545 SRBDS_MITIGATION_HYPERVISOR, 546 }; 547 548 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL; 549 550 static const char * const srbds_strings[] = { 551 [SRBDS_MITIGATION_OFF] = "Vulnerable", 552 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 553 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode", 554 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled", 555 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", 556 }; 557 558 static bool srbds_off; 559 560 void update_srbds_msr(void) 561 { 562 u64 mcu_ctrl; 563 564 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 565 return; 566 567 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 568 return; 569 570 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) 571 return; 572 573 /* 574 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX 575 * being disabled and it hasn't received the SRBDS MSR microcode. 576 */ 577 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 578 return; 579 580 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 581 582 switch (srbds_mitigation) { 583 case SRBDS_MITIGATION_OFF: 584 case SRBDS_MITIGATION_TSX_OFF: 585 mcu_ctrl |= RNGDS_MITG_DIS; 586 break; 587 case SRBDS_MITIGATION_FULL: 588 mcu_ctrl &= ~RNGDS_MITG_DIS; 589 break; 590 default: 591 break; 592 } 593 594 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 595 } 596 597 static void __init srbds_select_mitigation(void) 598 { 599 u64 ia32_cap; 600 601 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 602 return; 603 604 /* 605 * Check to see if this is one of the MDS_NO systems supporting TSX that 606 * are only exposed to SRBDS when TSX is enabled or when CPU is affected 607 * by Processor MMIO Stale Data vulnerability. 608 */ 609 ia32_cap = x86_read_arch_cap_msr(); 610 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) && 611 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 612 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF; 613 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 614 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR; 615 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 616 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED; 617 else if (cpu_mitigations_off() || srbds_off) 618 srbds_mitigation = SRBDS_MITIGATION_OFF; 619 620 update_srbds_msr(); 621 pr_info("%s\n", srbds_strings[srbds_mitigation]); 622 } 623 624 static int __init srbds_parse_cmdline(char *str) 625 { 626 if (!str) 627 return -EINVAL; 628 629 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 630 return 0; 631 632 srbds_off = !strcmp(str, "off"); 633 return 0; 634 } 635 early_param("srbds", srbds_parse_cmdline); 636 637 #undef pr_fmt 638 #define pr_fmt(fmt) "L1D Flush : " fmt 639 640 enum l1d_flush_mitigations { 641 L1D_FLUSH_OFF = 0, 642 L1D_FLUSH_ON, 643 }; 644 645 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF; 646 647 static void __init l1d_flush_select_mitigation(void) 648 { 649 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) 650 return; 651 652 static_branch_enable(&switch_mm_cond_l1d_flush); 653 pr_info("Conditional flush on switch_mm() enabled\n"); 654 } 655 656 static int __init l1d_flush_parse_cmdline(char *str) 657 { 658 if (!strcmp(str, "on")) 659 l1d_flush_mitigation = L1D_FLUSH_ON; 660 661 return 0; 662 } 663 early_param("l1d_flush", l1d_flush_parse_cmdline); 664 665 #undef pr_fmt 666 #define pr_fmt(fmt) "Spectre V1 : " fmt 667 668 enum spectre_v1_mitigation { 669 SPECTRE_V1_MITIGATION_NONE, 670 SPECTRE_V1_MITIGATION_AUTO, 671 }; 672 673 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = 674 SPECTRE_V1_MITIGATION_AUTO; 675 676 static const char * const spectre_v1_strings[] = { 677 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", 678 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", 679 }; 680 681 /* 682 * Does SMAP provide full mitigation against speculative kernel access to 683 * userspace? 684 */ 685 static bool smap_works_speculatively(void) 686 { 687 if (!boot_cpu_has(X86_FEATURE_SMAP)) 688 return false; 689 690 /* 691 * On CPUs which are vulnerable to Meltdown, SMAP does not 692 * prevent speculative access to user data in the L1 cache. 693 * Consider SMAP to be non-functional as a mitigation on these 694 * CPUs. 695 */ 696 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) 697 return false; 698 699 return true; 700 } 701 702 static void __init spectre_v1_select_mitigation(void) 703 { 704 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { 705 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 706 return; 707 } 708 709 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { 710 /* 711 * With Spectre v1, a user can speculatively control either 712 * path of a conditional swapgs with a user-controlled GS 713 * value. The mitigation is to add lfences to both code paths. 714 * 715 * If FSGSBASE is enabled, the user can put a kernel address in 716 * GS, in which case SMAP provides no protection. 717 * 718 * If FSGSBASE is disabled, the user can only put a user space 719 * address in GS. That makes an attack harder, but still 720 * possible if there's no SMAP protection. 721 */ 722 if (boot_cpu_has(X86_FEATURE_FSGSBASE) || 723 !smap_works_speculatively()) { 724 /* 725 * Mitigation can be provided from SWAPGS itself or 726 * PTI as the CR3 write in the Meltdown mitigation 727 * is serializing. 728 * 729 * If neither is there, mitigate with an LFENCE to 730 * stop speculation through swapgs. 731 */ 732 if (boot_cpu_has_bug(X86_BUG_SWAPGS) && 733 !boot_cpu_has(X86_FEATURE_PTI)) 734 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); 735 736 /* 737 * Enable lfences in the kernel entry (non-swapgs) 738 * paths, to prevent user entry from speculatively 739 * skipping swapgs. 740 */ 741 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); 742 } 743 } 744 745 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); 746 } 747 748 static int __init nospectre_v1_cmdline(char *str) 749 { 750 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 751 return 0; 752 } 753 early_param("nospectre_v1", nospectre_v1_cmdline); 754 755 #undef pr_fmt 756 #define pr_fmt(fmt) "Spectre V2 : " fmt 757 758 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = 759 SPECTRE_V2_NONE; 760 761 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init = 762 SPECTRE_V2_USER_NONE; 763 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init = 764 SPECTRE_V2_USER_NONE; 765 766 #ifdef CONFIG_RETPOLINE 767 static bool spectre_v2_bad_module; 768 769 bool retpoline_module_ok(bool has_retpoline) 770 { 771 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) 772 return true; 773 774 pr_err("System may be vulnerable to spectre v2\n"); 775 spectre_v2_bad_module = true; 776 return false; 777 } 778 779 static inline const char *spectre_v2_module_string(void) 780 { 781 return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; 782 } 783 #else 784 static inline const char *spectre_v2_module_string(void) { return ""; } 785 #endif 786 787 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n" 788 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n" 789 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n" 790 791 #ifdef CONFIG_BPF_SYSCALL 792 void unpriv_ebpf_notify(int new_state) 793 { 794 if (new_state) 795 return; 796 797 /* Unprivileged eBPF is enabled */ 798 799 switch (spectre_v2_enabled) { 800 case SPECTRE_V2_EIBRS: 801 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 802 break; 803 case SPECTRE_V2_EIBRS_LFENCE: 804 if (sched_smt_active()) 805 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 806 break; 807 default: 808 break; 809 } 810 } 811 #endif 812 813 static inline bool match_option(const char *arg, int arglen, const char *opt) 814 { 815 int len = strlen(opt); 816 817 return len == arglen && !strncmp(arg, opt, len); 818 } 819 820 /* The kernel command line selection for spectre v2 */ 821 enum spectre_v2_mitigation_cmd { 822 SPECTRE_V2_CMD_NONE, 823 SPECTRE_V2_CMD_AUTO, 824 SPECTRE_V2_CMD_FORCE, 825 SPECTRE_V2_CMD_RETPOLINE, 826 SPECTRE_V2_CMD_RETPOLINE_GENERIC, 827 SPECTRE_V2_CMD_RETPOLINE_LFENCE, 828 SPECTRE_V2_CMD_EIBRS, 829 SPECTRE_V2_CMD_EIBRS_RETPOLINE, 830 SPECTRE_V2_CMD_EIBRS_LFENCE, 831 }; 832 833 enum spectre_v2_user_cmd { 834 SPECTRE_V2_USER_CMD_NONE, 835 SPECTRE_V2_USER_CMD_AUTO, 836 SPECTRE_V2_USER_CMD_FORCE, 837 SPECTRE_V2_USER_CMD_PRCTL, 838 SPECTRE_V2_USER_CMD_PRCTL_IBPB, 839 SPECTRE_V2_USER_CMD_SECCOMP, 840 SPECTRE_V2_USER_CMD_SECCOMP_IBPB, 841 }; 842 843 static const char * const spectre_v2_user_strings[] = { 844 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", 845 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", 846 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", 847 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", 848 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", 849 }; 850 851 static const struct { 852 const char *option; 853 enum spectre_v2_user_cmd cmd; 854 bool secure; 855 } v2_user_options[] __initconst = { 856 { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, 857 { "off", SPECTRE_V2_USER_CMD_NONE, false }, 858 { "on", SPECTRE_V2_USER_CMD_FORCE, true }, 859 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, 860 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, 861 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, 862 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, 863 }; 864 865 static void __init spec_v2_user_print_cond(const char *reason, bool secure) 866 { 867 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 868 pr_info("spectre_v2_user=%s forced on command line.\n", reason); 869 } 870 871 static enum spectre_v2_user_cmd __init 872 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) 873 { 874 char arg[20]; 875 int ret, i; 876 877 switch (v2_cmd) { 878 case SPECTRE_V2_CMD_NONE: 879 return SPECTRE_V2_USER_CMD_NONE; 880 case SPECTRE_V2_CMD_FORCE: 881 return SPECTRE_V2_USER_CMD_FORCE; 882 default: 883 break; 884 } 885 886 ret = cmdline_find_option(boot_command_line, "spectre_v2_user", 887 arg, sizeof(arg)); 888 if (ret < 0) 889 return SPECTRE_V2_USER_CMD_AUTO; 890 891 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { 892 if (match_option(arg, ret, v2_user_options[i].option)) { 893 spec_v2_user_print_cond(v2_user_options[i].option, 894 v2_user_options[i].secure); 895 return v2_user_options[i].cmd; 896 } 897 } 898 899 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); 900 return SPECTRE_V2_USER_CMD_AUTO; 901 } 902 903 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode) 904 { 905 return (mode == SPECTRE_V2_EIBRS || 906 mode == SPECTRE_V2_EIBRS_RETPOLINE || 907 mode == SPECTRE_V2_EIBRS_LFENCE); 908 } 909 910 static void __init 911 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) 912 { 913 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; 914 bool smt_possible = IS_ENABLED(CONFIG_SMP); 915 enum spectre_v2_user_cmd cmd; 916 917 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) 918 return; 919 920 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || 921 cpu_smt_control == CPU_SMT_NOT_SUPPORTED) 922 smt_possible = false; 923 924 cmd = spectre_v2_parse_user_cmdline(v2_cmd); 925 switch (cmd) { 926 case SPECTRE_V2_USER_CMD_NONE: 927 goto set_mode; 928 case SPECTRE_V2_USER_CMD_FORCE: 929 mode = SPECTRE_V2_USER_STRICT; 930 break; 931 case SPECTRE_V2_USER_CMD_AUTO: 932 case SPECTRE_V2_USER_CMD_PRCTL: 933 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 934 mode = SPECTRE_V2_USER_PRCTL; 935 break; 936 case SPECTRE_V2_USER_CMD_SECCOMP: 937 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 938 if (IS_ENABLED(CONFIG_SECCOMP)) 939 mode = SPECTRE_V2_USER_SECCOMP; 940 else 941 mode = SPECTRE_V2_USER_PRCTL; 942 break; 943 } 944 945 /* Initialize Indirect Branch Prediction Barrier */ 946 if (boot_cpu_has(X86_FEATURE_IBPB)) { 947 setup_force_cpu_cap(X86_FEATURE_USE_IBPB); 948 949 spectre_v2_user_ibpb = mode; 950 switch (cmd) { 951 case SPECTRE_V2_USER_CMD_FORCE: 952 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 953 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 954 static_branch_enable(&switch_mm_always_ibpb); 955 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT; 956 break; 957 case SPECTRE_V2_USER_CMD_PRCTL: 958 case SPECTRE_V2_USER_CMD_AUTO: 959 case SPECTRE_V2_USER_CMD_SECCOMP: 960 static_branch_enable(&switch_mm_cond_ibpb); 961 break; 962 default: 963 break; 964 } 965 966 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", 967 static_key_enabled(&switch_mm_always_ibpb) ? 968 "always-on" : "conditional"); 969 } 970 971 /* 972 * If no STIBP, enhanced IBRS is enabled or SMT impossible, STIBP is not 973 * required. 974 */ 975 if (!boot_cpu_has(X86_FEATURE_STIBP) || 976 !smt_possible || 977 spectre_v2_in_eibrs_mode(spectre_v2_enabled)) 978 return; 979 980 /* 981 * At this point, an STIBP mode other than "off" has been set. 982 * If STIBP support is not being forced, check if STIBP always-on 983 * is preferred. 984 */ 985 if (mode != SPECTRE_V2_USER_STRICT && 986 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) 987 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 988 989 spectre_v2_user_stibp = mode; 990 991 set_mode: 992 pr_info("%s\n", spectre_v2_user_strings[mode]); 993 } 994 995 static const char * const spectre_v2_strings[] = { 996 [SPECTRE_V2_NONE] = "Vulnerable", 997 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", 998 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", 999 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS", 1000 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE", 1001 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines", 1002 }; 1003 1004 static const struct { 1005 const char *option; 1006 enum spectre_v2_mitigation_cmd cmd; 1007 bool secure; 1008 } mitigation_options[] __initconst = { 1009 { "off", SPECTRE_V2_CMD_NONE, false }, 1010 { "on", SPECTRE_V2_CMD_FORCE, true }, 1011 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, 1012 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1013 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1014 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, 1015 { "eibrs", SPECTRE_V2_CMD_EIBRS, false }, 1016 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false }, 1017 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false }, 1018 { "auto", SPECTRE_V2_CMD_AUTO, false }, 1019 }; 1020 1021 static void __init spec_v2_print_cond(const char *reason, bool secure) 1022 { 1023 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1024 pr_info("%s selected on command line.\n", reason); 1025 } 1026 1027 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) 1028 { 1029 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; 1030 char arg[20]; 1031 int ret, i; 1032 1033 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || 1034 cpu_mitigations_off()) 1035 return SPECTRE_V2_CMD_NONE; 1036 1037 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); 1038 if (ret < 0) 1039 return SPECTRE_V2_CMD_AUTO; 1040 1041 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { 1042 if (!match_option(arg, ret, mitigation_options[i].option)) 1043 continue; 1044 cmd = mitigation_options[i].cmd; 1045 break; 1046 } 1047 1048 if (i >= ARRAY_SIZE(mitigation_options)) { 1049 pr_err("unknown option (%s). Switching to AUTO select\n", arg); 1050 return SPECTRE_V2_CMD_AUTO; 1051 } 1052 1053 if ((cmd == SPECTRE_V2_CMD_RETPOLINE || 1054 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1055 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC || 1056 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1057 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1058 !IS_ENABLED(CONFIG_RETPOLINE)) { 1059 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1060 mitigation_options[i].option); 1061 return SPECTRE_V2_CMD_AUTO; 1062 } 1063 1064 if ((cmd == SPECTRE_V2_CMD_EIBRS || 1065 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1066 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1067 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1068 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n", 1069 mitigation_options[i].option); 1070 return SPECTRE_V2_CMD_AUTO; 1071 } 1072 1073 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1074 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) && 1075 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { 1076 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", 1077 mitigation_options[i].option); 1078 return SPECTRE_V2_CMD_AUTO; 1079 } 1080 1081 spec_v2_print_cond(mitigation_options[i].option, 1082 mitigation_options[i].secure); 1083 return cmd; 1084 } 1085 1086 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void) 1087 { 1088 if (!IS_ENABLED(CONFIG_RETPOLINE)) { 1089 pr_err("Kernel not compiled with retpoline; no mitigation available!"); 1090 return SPECTRE_V2_NONE; 1091 } 1092 1093 return SPECTRE_V2_RETPOLINE; 1094 } 1095 1096 static void __init spectre_v2_select_mitigation(void) 1097 { 1098 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); 1099 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; 1100 1101 /* 1102 * If the CPU is not affected and the command line mode is NONE or AUTO 1103 * then nothing to do. 1104 */ 1105 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && 1106 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) 1107 return; 1108 1109 switch (cmd) { 1110 case SPECTRE_V2_CMD_NONE: 1111 return; 1112 1113 case SPECTRE_V2_CMD_FORCE: 1114 case SPECTRE_V2_CMD_AUTO: 1115 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1116 mode = SPECTRE_V2_EIBRS; 1117 break; 1118 } 1119 1120 mode = spectre_v2_select_retpoline(); 1121 break; 1122 1123 case SPECTRE_V2_CMD_RETPOLINE_LFENCE: 1124 pr_err(SPECTRE_V2_LFENCE_MSG); 1125 mode = SPECTRE_V2_LFENCE; 1126 break; 1127 1128 case SPECTRE_V2_CMD_RETPOLINE_GENERIC: 1129 mode = SPECTRE_V2_RETPOLINE; 1130 break; 1131 1132 case SPECTRE_V2_CMD_RETPOLINE: 1133 mode = spectre_v2_select_retpoline(); 1134 break; 1135 1136 case SPECTRE_V2_CMD_EIBRS: 1137 mode = SPECTRE_V2_EIBRS; 1138 break; 1139 1140 case SPECTRE_V2_CMD_EIBRS_LFENCE: 1141 mode = SPECTRE_V2_EIBRS_LFENCE; 1142 break; 1143 1144 case SPECTRE_V2_CMD_EIBRS_RETPOLINE: 1145 mode = SPECTRE_V2_EIBRS_RETPOLINE; 1146 break; 1147 } 1148 1149 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 1150 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 1151 1152 if (spectre_v2_in_eibrs_mode(mode)) { 1153 /* Force it so VMEXIT will restore correctly */ 1154 x86_spec_ctrl_base |= SPEC_CTRL_IBRS; 1155 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 1156 } 1157 1158 switch (mode) { 1159 case SPECTRE_V2_NONE: 1160 case SPECTRE_V2_EIBRS: 1161 break; 1162 1163 case SPECTRE_V2_LFENCE: 1164 case SPECTRE_V2_EIBRS_LFENCE: 1165 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE); 1166 fallthrough; 1167 1168 case SPECTRE_V2_RETPOLINE: 1169 case SPECTRE_V2_EIBRS_RETPOLINE: 1170 setup_force_cpu_cap(X86_FEATURE_RETPOLINE); 1171 break; 1172 } 1173 1174 spectre_v2_enabled = mode; 1175 pr_info("%s\n", spectre_v2_strings[mode]); 1176 1177 /* 1178 * If spectre v2 protection has been enabled, unconditionally fill 1179 * RSB during a context switch; this protects against two independent 1180 * issues: 1181 * 1182 * - RSB underflow (and switch to BTB) on Skylake+ 1183 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs 1184 */ 1185 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); 1186 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); 1187 1188 /* 1189 * Retpoline means the kernel is safe because it has no indirect 1190 * branches. Enhanced IBRS protects firmware too, so, enable restricted 1191 * speculation around firmware calls only when Enhanced IBRS isn't 1192 * supported. 1193 * 1194 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because 1195 * the user might select retpoline on the kernel command line and if 1196 * the CPU supports Enhanced IBRS, kernel might un-intentionally not 1197 * enable IBRS around firmware calls. 1198 */ 1199 if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_eibrs_mode(mode)) { 1200 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); 1201 pr_info("Enabling Restricted Speculation for firmware calls\n"); 1202 } 1203 1204 /* Set up IBPB and STIBP depending on the general spectre V2 command */ 1205 spectre_v2_user_select_mitigation(cmd); 1206 } 1207 1208 static void update_stibp_msr(void * __unused) 1209 { 1210 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 1211 } 1212 1213 /* Update x86_spec_ctrl_base in case SMT state changed. */ 1214 static void update_stibp_strict(void) 1215 { 1216 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; 1217 1218 if (sched_smt_active()) 1219 mask |= SPEC_CTRL_STIBP; 1220 1221 if (mask == x86_spec_ctrl_base) 1222 return; 1223 1224 pr_info("Update user space SMT mitigation: STIBP %s\n", 1225 mask & SPEC_CTRL_STIBP ? "always-on" : "off"); 1226 x86_spec_ctrl_base = mask; 1227 on_each_cpu(update_stibp_msr, NULL, 1); 1228 } 1229 1230 /* Update the static key controlling the evaluation of TIF_SPEC_IB */ 1231 static void update_indir_branch_cond(void) 1232 { 1233 if (sched_smt_active()) 1234 static_branch_enable(&switch_to_cond_stibp); 1235 else 1236 static_branch_disable(&switch_to_cond_stibp); 1237 } 1238 1239 #undef pr_fmt 1240 #define pr_fmt(fmt) fmt 1241 1242 /* Update the static key controlling the MDS CPU buffer clear in idle */ 1243 static void update_mds_branch_idle(void) 1244 { 1245 u64 ia32_cap = x86_read_arch_cap_msr(); 1246 1247 /* 1248 * Enable the idle clearing if SMT is active on CPUs which are 1249 * affected only by MSBDS and not any other MDS variant. 1250 * 1251 * The other variants cannot be mitigated when SMT is enabled, so 1252 * clearing the buffers on idle just to prevent the Store Buffer 1253 * repartitioning leak would be a window dressing exercise. 1254 */ 1255 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) 1256 return; 1257 1258 if (sched_smt_active()) { 1259 static_branch_enable(&mds_idle_clear); 1260 } else if (mmio_mitigation == MMIO_MITIGATION_OFF || 1261 (ia32_cap & ARCH_CAP_FBSDP_NO)) { 1262 static_branch_disable(&mds_idle_clear); 1263 } 1264 } 1265 1266 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" 1267 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n" 1268 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n" 1269 1270 void cpu_bugs_smt_update(void) 1271 { 1272 mutex_lock(&spec_ctrl_mutex); 1273 1274 if (sched_smt_active() && unprivileged_ebpf_enabled() && 1275 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 1276 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 1277 1278 switch (spectre_v2_user_stibp) { 1279 case SPECTRE_V2_USER_NONE: 1280 break; 1281 case SPECTRE_V2_USER_STRICT: 1282 case SPECTRE_V2_USER_STRICT_PREFERRED: 1283 update_stibp_strict(); 1284 break; 1285 case SPECTRE_V2_USER_PRCTL: 1286 case SPECTRE_V2_USER_SECCOMP: 1287 update_indir_branch_cond(); 1288 break; 1289 } 1290 1291 switch (mds_mitigation) { 1292 case MDS_MITIGATION_FULL: 1293 case MDS_MITIGATION_VMWERV: 1294 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) 1295 pr_warn_once(MDS_MSG_SMT); 1296 update_mds_branch_idle(); 1297 break; 1298 case MDS_MITIGATION_OFF: 1299 break; 1300 } 1301 1302 switch (taa_mitigation) { 1303 case TAA_MITIGATION_VERW: 1304 case TAA_MITIGATION_UCODE_NEEDED: 1305 if (sched_smt_active()) 1306 pr_warn_once(TAA_MSG_SMT); 1307 break; 1308 case TAA_MITIGATION_TSX_DISABLED: 1309 case TAA_MITIGATION_OFF: 1310 break; 1311 } 1312 1313 switch (mmio_mitigation) { 1314 case MMIO_MITIGATION_VERW: 1315 case MMIO_MITIGATION_UCODE_NEEDED: 1316 if (sched_smt_active()) 1317 pr_warn_once(MMIO_MSG_SMT); 1318 break; 1319 case MMIO_MITIGATION_OFF: 1320 break; 1321 } 1322 1323 mutex_unlock(&spec_ctrl_mutex); 1324 } 1325 1326 #undef pr_fmt 1327 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt 1328 1329 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; 1330 1331 /* The kernel command line selection */ 1332 enum ssb_mitigation_cmd { 1333 SPEC_STORE_BYPASS_CMD_NONE, 1334 SPEC_STORE_BYPASS_CMD_AUTO, 1335 SPEC_STORE_BYPASS_CMD_ON, 1336 SPEC_STORE_BYPASS_CMD_PRCTL, 1337 SPEC_STORE_BYPASS_CMD_SECCOMP, 1338 }; 1339 1340 static const char * const ssb_strings[] = { 1341 [SPEC_STORE_BYPASS_NONE] = "Vulnerable", 1342 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", 1343 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", 1344 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", 1345 }; 1346 1347 static const struct { 1348 const char *option; 1349 enum ssb_mitigation_cmd cmd; 1350 } ssb_mitigation_options[] __initconst = { 1351 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ 1352 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ 1353 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ 1354 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ 1355 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ 1356 }; 1357 1358 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) 1359 { 1360 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; 1361 char arg[20]; 1362 int ret, i; 1363 1364 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || 1365 cpu_mitigations_off()) { 1366 return SPEC_STORE_BYPASS_CMD_NONE; 1367 } else { 1368 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", 1369 arg, sizeof(arg)); 1370 if (ret < 0) 1371 return SPEC_STORE_BYPASS_CMD_AUTO; 1372 1373 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { 1374 if (!match_option(arg, ret, ssb_mitigation_options[i].option)) 1375 continue; 1376 1377 cmd = ssb_mitigation_options[i].cmd; 1378 break; 1379 } 1380 1381 if (i >= ARRAY_SIZE(ssb_mitigation_options)) { 1382 pr_err("unknown option (%s). Switching to AUTO select\n", arg); 1383 return SPEC_STORE_BYPASS_CMD_AUTO; 1384 } 1385 } 1386 1387 return cmd; 1388 } 1389 1390 static enum ssb_mitigation __init __ssb_select_mitigation(void) 1391 { 1392 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; 1393 enum ssb_mitigation_cmd cmd; 1394 1395 if (!boot_cpu_has(X86_FEATURE_SSBD)) 1396 return mode; 1397 1398 cmd = ssb_parse_cmdline(); 1399 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && 1400 (cmd == SPEC_STORE_BYPASS_CMD_NONE || 1401 cmd == SPEC_STORE_BYPASS_CMD_AUTO)) 1402 return mode; 1403 1404 switch (cmd) { 1405 case SPEC_STORE_BYPASS_CMD_SECCOMP: 1406 /* 1407 * Choose prctl+seccomp as the default mode if seccomp is 1408 * enabled. 1409 */ 1410 if (IS_ENABLED(CONFIG_SECCOMP)) 1411 mode = SPEC_STORE_BYPASS_SECCOMP; 1412 else 1413 mode = SPEC_STORE_BYPASS_PRCTL; 1414 break; 1415 case SPEC_STORE_BYPASS_CMD_ON: 1416 mode = SPEC_STORE_BYPASS_DISABLE; 1417 break; 1418 case SPEC_STORE_BYPASS_CMD_AUTO: 1419 case SPEC_STORE_BYPASS_CMD_PRCTL: 1420 mode = SPEC_STORE_BYPASS_PRCTL; 1421 break; 1422 case SPEC_STORE_BYPASS_CMD_NONE: 1423 break; 1424 } 1425 1426 /* 1427 * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper 1428 * bit in the mask to allow guests to use the mitigation even in the 1429 * case where the host does not enable it. 1430 */ 1431 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || 1432 static_cpu_has(X86_FEATURE_AMD_SSBD)) { 1433 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; 1434 } 1435 1436 /* 1437 * We have three CPU feature flags that are in play here: 1438 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. 1439 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass 1440 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation 1441 */ 1442 if (mode == SPEC_STORE_BYPASS_DISABLE) { 1443 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); 1444 /* 1445 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may 1446 * use a completely different MSR and bit dependent on family. 1447 */ 1448 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 1449 !static_cpu_has(X86_FEATURE_AMD_SSBD)) { 1450 x86_amd_ssb_disable(); 1451 } else { 1452 x86_spec_ctrl_base |= SPEC_CTRL_SSBD; 1453 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 1454 } 1455 } 1456 1457 return mode; 1458 } 1459 1460 static void ssb_select_mitigation(void) 1461 { 1462 ssb_mode = __ssb_select_mitigation(); 1463 1464 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1465 pr_info("%s\n", ssb_strings[ssb_mode]); 1466 } 1467 1468 #undef pr_fmt 1469 #define pr_fmt(fmt) "Speculation prctl: " fmt 1470 1471 static void task_update_spec_tif(struct task_struct *tsk) 1472 { 1473 /* Force the update of the real TIF bits */ 1474 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); 1475 1476 /* 1477 * Immediately update the speculation control MSRs for the current 1478 * task, but for a non-current task delay setting the CPU 1479 * mitigation until it is scheduled next. 1480 * 1481 * This can only happen for SECCOMP mitigation. For PRCTL it's 1482 * always the current task. 1483 */ 1484 if (tsk == current) 1485 speculation_ctrl_update_current(); 1486 } 1487 1488 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl) 1489 { 1490 1491 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 1492 return -EPERM; 1493 1494 switch (ctrl) { 1495 case PR_SPEC_ENABLE: 1496 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 1497 return 0; 1498 case PR_SPEC_DISABLE: 1499 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 1500 return 0; 1501 default: 1502 return -ERANGE; 1503 } 1504 } 1505 1506 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) 1507 { 1508 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && 1509 ssb_mode != SPEC_STORE_BYPASS_SECCOMP) 1510 return -ENXIO; 1511 1512 switch (ctrl) { 1513 case PR_SPEC_ENABLE: 1514 /* If speculation is force disabled, enable is not allowed */ 1515 if (task_spec_ssb_force_disable(task)) 1516 return -EPERM; 1517 task_clear_spec_ssb_disable(task); 1518 task_clear_spec_ssb_noexec(task); 1519 task_update_spec_tif(task); 1520 break; 1521 case PR_SPEC_DISABLE: 1522 task_set_spec_ssb_disable(task); 1523 task_clear_spec_ssb_noexec(task); 1524 task_update_spec_tif(task); 1525 break; 1526 case PR_SPEC_FORCE_DISABLE: 1527 task_set_spec_ssb_disable(task); 1528 task_set_spec_ssb_force_disable(task); 1529 task_clear_spec_ssb_noexec(task); 1530 task_update_spec_tif(task); 1531 break; 1532 case PR_SPEC_DISABLE_NOEXEC: 1533 if (task_spec_ssb_force_disable(task)) 1534 return -EPERM; 1535 task_set_spec_ssb_disable(task); 1536 task_set_spec_ssb_noexec(task); 1537 task_update_spec_tif(task); 1538 break; 1539 default: 1540 return -ERANGE; 1541 } 1542 return 0; 1543 } 1544 1545 static bool is_spec_ib_user_controlled(void) 1546 { 1547 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL || 1548 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 1549 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL || 1550 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP; 1551 } 1552 1553 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 1554 { 1555 switch (ctrl) { 1556 case PR_SPEC_ENABLE: 1557 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1558 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1559 return 0; 1560 1561 /* 1562 * With strict mode for both IBPB and STIBP, the instruction 1563 * code paths avoid checking this task flag and instead, 1564 * unconditionally run the instruction. However, STIBP and IBPB 1565 * are independent and either can be set to conditionally 1566 * enabled regardless of the mode of the other. 1567 * 1568 * If either is set to conditional, allow the task flag to be 1569 * updated, unless it was force-disabled by a previous prctl 1570 * call. Currently, this is possible on an AMD CPU which has the 1571 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the 1572 * kernel is booted with 'spectre_v2_user=seccomp', then 1573 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and 1574 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED. 1575 */ 1576 if (!is_spec_ib_user_controlled() || 1577 task_spec_ib_force_disable(task)) 1578 return -EPERM; 1579 1580 task_clear_spec_ib_disable(task); 1581 task_update_spec_tif(task); 1582 break; 1583 case PR_SPEC_DISABLE: 1584 case PR_SPEC_FORCE_DISABLE: 1585 /* 1586 * Indirect branch speculation is always allowed when 1587 * mitigation is force disabled. 1588 */ 1589 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1590 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1591 return -EPERM; 1592 1593 if (!is_spec_ib_user_controlled()) 1594 return 0; 1595 1596 task_set_spec_ib_disable(task); 1597 if (ctrl == PR_SPEC_FORCE_DISABLE) 1598 task_set_spec_ib_force_disable(task); 1599 task_update_spec_tif(task); 1600 break; 1601 default: 1602 return -ERANGE; 1603 } 1604 return 0; 1605 } 1606 1607 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, 1608 unsigned long ctrl) 1609 { 1610 switch (which) { 1611 case PR_SPEC_STORE_BYPASS: 1612 return ssb_prctl_set(task, ctrl); 1613 case PR_SPEC_INDIRECT_BRANCH: 1614 return ib_prctl_set(task, ctrl); 1615 case PR_SPEC_L1D_FLUSH: 1616 return l1d_flush_prctl_set(task, ctrl); 1617 default: 1618 return -ENODEV; 1619 } 1620 } 1621 1622 #ifdef CONFIG_SECCOMP 1623 void arch_seccomp_spec_mitigate(struct task_struct *task) 1624 { 1625 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) 1626 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); 1627 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 1628 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) 1629 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); 1630 } 1631 #endif 1632 1633 static int l1d_flush_prctl_get(struct task_struct *task) 1634 { 1635 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 1636 return PR_SPEC_FORCE_DISABLE; 1637 1638 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH)) 1639 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1640 else 1641 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1642 } 1643 1644 static int ssb_prctl_get(struct task_struct *task) 1645 { 1646 switch (ssb_mode) { 1647 case SPEC_STORE_BYPASS_DISABLE: 1648 return PR_SPEC_DISABLE; 1649 case SPEC_STORE_BYPASS_SECCOMP: 1650 case SPEC_STORE_BYPASS_PRCTL: 1651 if (task_spec_ssb_force_disable(task)) 1652 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 1653 if (task_spec_ssb_noexec(task)) 1654 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC; 1655 if (task_spec_ssb_disable(task)) 1656 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1657 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1658 default: 1659 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1660 return PR_SPEC_ENABLE; 1661 return PR_SPEC_NOT_AFFECTED; 1662 } 1663 } 1664 1665 static int ib_prctl_get(struct task_struct *task) 1666 { 1667 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) 1668 return PR_SPEC_NOT_AFFECTED; 1669 1670 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1671 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1672 return PR_SPEC_ENABLE; 1673 else if (is_spec_ib_user_controlled()) { 1674 if (task_spec_ib_force_disable(task)) 1675 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 1676 if (task_spec_ib_disable(task)) 1677 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1678 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1679 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT || 1680 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 1681 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED) 1682 return PR_SPEC_DISABLE; 1683 else 1684 return PR_SPEC_NOT_AFFECTED; 1685 } 1686 1687 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) 1688 { 1689 switch (which) { 1690 case PR_SPEC_STORE_BYPASS: 1691 return ssb_prctl_get(task); 1692 case PR_SPEC_INDIRECT_BRANCH: 1693 return ib_prctl_get(task); 1694 case PR_SPEC_L1D_FLUSH: 1695 return l1d_flush_prctl_get(task); 1696 default: 1697 return -ENODEV; 1698 } 1699 } 1700 1701 void x86_spec_ctrl_setup_ap(void) 1702 { 1703 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 1704 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 1705 1706 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) 1707 x86_amd_ssb_disable(); 1708 } 1709 1710 bool itlb_multihit_kvm_mitigation; 1711 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); 1712 1713 #undef pr_fmt 1714 #define pr_fmt(fmt) "L1TF: " fmt 1715 1716 /* Default mitigation for L1TF-affected CPUs */ 1717 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; 1718 #if IS_ENABLED(CONFIG_KVM_INTEL) 1719 EXPORT_SYMBOL_GPL(l1tf_mitigation); 1720 #endif 1721 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 1722 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); 1723 1724 /* 1725 * These CPUs all support 44bits physical address space internally in the 1726 * cache but CPUID can report a smaller number of physical address bits. 1727 * 1728 * The L1TF mitigation uses the top most address bit for the inversion of 1729 * non present PTEs. When the installed memory reaches into the top most 1730 * address bit due to memory holes, which has been observed on machines 1731 * which report 36bits physical address bits and have 32G RAM installed, 1732 * then the mitigation range check in l1tf_select_mitigation() triggers. 1733 * This is a false positive because the mitigation is still possible due to 1734 * the fact that the cache uses 44bit internally. Use the cache bits 1735 * instead of the reported physical bits and adjust them on the affected 1736 * machines to 44bit if the reported bits are less than 44. 1737 */ 1738 static void override_cache_bits(struct cpuinfo_x86 *c) 1739 { 1740 if (c->x86 != 6) 1741 return; 1742 1743 switch (c->x86_model) { 1744 case INTEL_FAM6_NEHALEM: 1745 case INTEL_FAM6_WESTMERE: 1746 case INTEL_FAM6_SANDYBRIDGE: 1747 case INTEL_FAM6_IVYBRIDGE: 1748 case INTEL_FAM6_HASWELL: 1749 case INTEL_FAM6_HASWELL_L: 1750 case INTEL_FAM6_HASWELL_G: 1751 case INTEL_FAM6_BROADWELL: 1752 case INTEL_FAM6_BROADWELL_G: 1753 case INTEL_FAM6_SKYLAKE_L: 1754 case INTEL_FAM6_SKYLAKE: 1755 case INTEL_FAM6_KABYLAKE_L: 1756 case INTEL_FAM6_KABYLAKE: 1757 if (c->x86_cache_bits < 44) 1758 c->x86_cache_bits = 44; 1759 break; 1760 } 1761 } 1762 1763 static void __init l1tf_select_mitigation(void) 1764 { 1765 u64 half_pa; 1766 1767 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 1768 return; 1769 1770 if (cpu_mitigations_off()) 1771 l1tf_mitigation = L1TF_MITIGATION_OFF; 1772 else if (cpu_mitigations_auto_nosmt()) 1773 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 1774 1775 override_cache_bits(&boot_cpu_data); 1776 1777 switch (l1tf_mitigation) { 1778 case L1TF_MITIGATION_OFF: 1779 case L1TF_MITIGATION_FLUSH_NOWARN: 1780 case L1TF_MITIGATION_FLUSH: 1781 break; 1782 case L1TF_MITIGATION_FLUSH_NOSMT: 1783 case L1TF_MITIGATION_FULL: 1784 cpu_smt_disable(false); 1785 break; 1786 case L1TF_MITIGATION_FULL_FORCE: 1787 cpu_smt_disable(true); 1788 break; 1789 } 1790 1791 #if CONFIG_PGTABLE_LEVELS == 2 1792 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); 1793 return; 1794 #endif 1795 1796 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; 1797 if (l1tf_mitigation != L1TF_MITIGATION_OFF && 1798 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { 1799 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); 1800 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", 1801 half_pa); 1802 pr_info("However, doing so will make a part of your RAM unusable.\n"); 1803 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); 1804 return; 1805 } 1806 1807 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); 1808 } 1809 1810 static int __init l1tf_cmdline(char *str) 1811 { 1812 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 1813 return 0; 1814 1815 if (!str) 1816 return -EINVAL; 1817 1818 if (!strcmp(str, "off")) 1819 l1tf_mitigation = L1TF_MITIGATION_OFF; 1820 else if (!strcmp(str, "flush,nowarn")) 1821 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; 1822 else if (!strcmp(str, "flush")) 1823 l1tf_mitigation = L1TF_MITIGATION_FLUSH; 1824 else if (!strcmp(str, "flush,nosmt")) 1825 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 1826 else if (!strcmp(str, "full")) 1827 l1tf_mitigation = L1TF_MITIGATION_FULL; 1828 else if (!strcmp(str, "full,force")) 1829 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; 1830 1831 return 0; 1832 } 1833 early_param("l1tf", l1tf_cmdline); 1834 1835 #undef pr_fmt 1836 #define pr_fmt(fmt) fmt 1837 1838 #ifdef CONFIG_SYSFS 1839 1840 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" 1841 1842 #if IS_ENABLED(CONFIG_KVM_INTEL) 1843 static const char * const l1tf_vmx_states[] = { 1844 [VMENTER_L1D_FLUSH_AUTO] = "auto", 1845 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", 1846 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", 1847 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", 1848 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", 1849 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" 1850 }; 1851 1852 static ssize_t l1tf_show_state(char *buf) 1853 { 1854 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) 1855 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); 1856 1857 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || 1858 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && 1859 sched_smt_active())) { 1860 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, 1861 l1tf_vmx_states[l1tf_vmx_mitigation]); 1862 } 1863 1864 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, 1865 l1tf_vmx_states[l1tf_vmx_mitigation], 1866 sched_smt_active() ? "vulnerable" : "disabled"); 1867 } 1868 1869 static ssize_t itlb_multihit_show_state(char *buf) 1870 { 1871 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 1872 !boot_cpu_has(X86_FEATURE_VMX)) 1873 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n"); 1874 else if (!(cr4_read_shadow() & X86_CR4_VMXE)) 1875 return sprintf(buf, "KVM: Mitigation: VMX disabled\n"); 1876 else if (itlb_multihit_kvm_mitigation) 1877 return sprintf(buf, "KVM: Mitigation: Split huge pages\n"); 1878 else 1879 return sprintf(buf, "KVM: Vulnerable\n"); 1880 } 1881 #else 1882 static ssize_t l1tf_show_state(char *buf) 1883 { 1884 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); 1885 } 1886 1887 static ssize_t itlb_multihit_show_state(char *buf) 1888 { 1889 return sprintf(buf, "Processor vulnerable\n"); 1890 } 1891 #endif 1892 1893 static ssize_t mds_show_state(char *buf) 1894 { 1895 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 1896 return sprintf(buf, "%s; SMT Host state unknown\n", 1897 mds_strings[mds_mitigation]); 1898 } 1899 1900 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { 1901 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 1902 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : 1903 sched_smt_active() ? "mitigated" : "disabled")); 1904 } 1905 1906 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 1907 sched_smt_active() ? "vulnerable" : "disabled"); 1908 } 1909 1910 static ssize_t tsx_async_abort_show_state(char *buf) 1911 { 1912 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) || 1913 (taa_mitigation == TAA_MITIGATION_OFF)) 1914 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]); 1915 1916 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 1917 return sprintf(buf, "%s; SMT Host state unknown\n", 1918 taa_strings[taa_mitigation]); 1919 } 1920 1921 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation], 1922 sched_smt_active() ? "vulnerable" : "disabled"); 1923 } 1924 1925 static ssize_t mmio_stale_data_show_state(char *buf) 1926 { 1927 if (mmio_mitigation == MMIO_MITIGATION_OFF) 1928 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]); 1929 1930 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 1931 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 1932 mmio_strings[mmio_mitigation]); 1933 } 1934 1935 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation], 1936 sched_smt_active() ? "vulnerable" : "disabled"); 1937 } 1938 1939 static char *stibp_state(void) 1940 { 1941 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled)) 1942 return ""; 1943 1944 switch (spectre_v2_user_stibp) { 1945 case SPECTRE_V2_USER_NONE: 1946 return ", STIBP: disabled"; 1947 case SPECTRE_V2_USER_STRICT: 1948 return ", STIBP: forced"; 1949 case SPECTRE_V2_USER_STRICT_PREFERRED: 1950 return ", STIBP: always-on"; 1951 case SPECTRE_V2_USER_PRCTL: 1952 case SPECTRE_V2_USER_SECCOMP: 1953 if (static_key_enabled(&switch_to_cond_stibp)) 1954 return ", STIBP: conditional"; 1955 } 1956 return ""; 1957 } 1958 1959 static char *ibpb_state(void) 1960 { 1961 if (boot_cpu_has(X86_FEATURE_IBPB)) { 1962 if (static_key_enabled(&switch_mm_always_ibpb)) 1963 return ", IBPB: always-on"; 1964 if (static_key_enabled(&switch_mm_cond_ibpb)) 1965 return ", IBPB: conditional"; 1966 return ", IBPB: disabled"; 1967 } 1968 return ""; 1969 } 1970 1971 static ssize_t spectre_v2_show_state(char *buf) 1972 { 1973 if (spectre_v2_enabled == SPECTRE_V2_LFENCE) 1974 return sprintf(buf, "Vulnerable: LFENCE\n"); 1975 1976 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 1977 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n"); 1978 1979 if (sched_smt_active() && unprivileged_ebpf_enabled() && 1980 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 1981 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n"); 1982 1983 return sprintf(buf, "%s%s%s%s%s%s\n", 1984 spectre_v2_strings[spectre_v2_enabled], 1985 ibpb_state(), 1986 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", 1987 stibp_state(), 1988 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", 1989 spectre_v2_module_string()); 1990 } 1991 1992 static ssize_t srbds_show_state(char *buf) 1993 { 1994 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]); 1995 } 1996 1997 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, 1998 char *buf, unsigned int bug) 1999 { 2000 if (!boot_cpu_has_bug(bug)) 2001 return sprintf(buf, "Not affected\n"); 2002 2003 switch (bug) { 2004 case X86_BUG_CPU_MELTDOWN: 2005 if (boot_cpu_has(X86_FEATURE_PTI)) 2006 return sprintf(buf, "Mitigation: PTI\n"); 2007 2008 if (hypervisor_is_type(X86_HYPER_XEN_PV)) 2009 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); 2010 2011 break; 2012 2013 case X86_BUG_SPECTRE_V1: 2014 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); 2015 2016 case X86_BUG_SPECTRE_V2: 2017 return spectre_v2_show_state(buf); 2018 2019 case X86_BUG_SPEC_STORE_BYPASS: 2020 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); 2021 2022 case X86_BUG_L1TF: 2023 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) 2024 return l1tf_show_state(buf); 2025 break; 2026 2027 case X86_BUG_MDS: 2028 return mds_show_state(buf); 2029 2030 case X86_BUG_TAA: 2031 return tsx_async_abort_show_state(buf); 2032 2033 case X86_BUG_ITLB_MULTIHIT: 2034 return itlb_multihit_show_state(buf); 2035 2036 case X86_BUG_SRBDS: 2037 return srbds_show_state(buf); 2038 2039 case X86_BUG_MMIO_STALE_DATA: 2040 return mmio_stale_data_show_state(buf); 2041 2042 default: 2043 break; 2044 } 2045 2046 return sprintf(buf, "Vulnerable\n"); 2047 } 2048 2049 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) 2050 { 2051 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); 2052 } 2053 2054 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) 2055 { 2056 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); 2057 } 2058 2059 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) 2060 { 2061 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); 2062 } 2063 2064 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) 2065 { 2066 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); 2067 } 2068 2069 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) 2070 { 2071 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); 2072 } 2073 2074 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) 2075 { 2076 return cpu_show_common(dev, attr, buf, X86_BUG_MDS); 2077 } 2078 2079 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) 2080 { 2081 return cpu_show_common(dev, attr, buf, X86_BUG_TAA); 2082 } 2083 2084 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) 2085 { 2086 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT); 2087 } 2088 2089 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) 2090 { 2091 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS); 2092 } 2093 2094 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf) 2095 { 2096 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); 2097 } 2098 #endif 2099