1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Cyrix stuff, June 1998 by: 6 * - Rafael R. Reilova (moved everything from head.S), 7 * <rreilova@ececs.uc.edu> 8 * - Channing Corn (tests & fixes), 9 * - Andrew D. Balsa (code cleanup). 10 */ 11 #include <linux/init.h> 12 #include <linux/utsname.h> 13 #include <linux/cpu.h> 14 #include <linux/module.h> 15 #include <linux/nospec.h> 16 #include <linux/prctl.h> 17 #include <linux/sched/smt.h> 18 #include <linux/pgtable.h> 19 #include <linux/bpf.h> 20 21 #include <asm/spec-ctrl.h> 22 #include <asm/cmdline.h> 23 #include <asm/bugs.h> 24 #include <asm/processor.h> 25 #include <asm/processor-flags.h> 26 #include <asm/fpu/api.h> 27 #include <asm/msr.h> 28 #include <asm/vmx.h> 29 #include <asm/paravirt.h> 30 #include <asm/alternative.h> 31 #include <asm/set_memory.h> 32 #include <asm/intel-family.h> 33 #include <asm/e820/api.h> 34 #include <asm/hypervisor.h> 35 #include <asm/tlbflush.h> 36 37 #include "cpu.h" 38 39 static void __init spectre_v1_select_mitigation(void); 40 static void __init spectre_v2_select_mitigation(void); 41 static void __init retbleed_select_mitigation(void); 42 static void __init spectre_v2_user_select_mitigation(void); 43 static void __init ssb_select_mitigation(void); 44 static void __init l1tf_select_mitigation(void); 45 static void __init mds_select_mitigation(void); 46 static void __init md_clear_update_mitigation(void); 47 static void __init md_clear_select_mitigation(void); 48 static void __init taa_select_mitigation(void); 49 static void __init mmio_select_mitigation(void); 50 static void __init srbds_select_mitigation(void); 51 static void __init l1d_flush_select_mitigation(void); 52 53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */ 54 u64 x86_spec_ctrl_base; 55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); 56 57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */ 58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current); 59 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current); 60 61 static DEFINE_MUTEX(spec_ctrl_mutex); 62 63 /* 64 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ 65 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). 66 */ 67 void write_spec_ctrl_current(u64 val, bool force) 68 { 69 if (this_cpu_read(x86_spec_ctrl_current) == val) 70 return; 71 72 this_cpu_write(x86_spec_ctrl_current, val); 73 74 /* 75 * When KERNEL_IBRS this MSR is written on return-to-user, unless 76 * forced the update can be delayed until that time. 77 */ 78 if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 79 wrmsrl(MSR_IA32_SPEC_CTRL, val); 80 } 81 82 u64 spec_ctrl_current(void) 83 { 84 return this_cpu_read(x86_spec_ctrl_current); 85 } 86 EXPORT_SYMBOL_GPL(spec_ctrl_current); 87 88 /* 89 * AMD specific MSR info for Speculative Store Bypass control. 90 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). 91 */ 92 u64 __ro_after_init x86_amd_ls_cfg_base; 93 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; 94 95 /* Control conditional STIBP in switch_to() */ 96 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); 97 /* Control conditional IBPB in switch_mm() */ 98 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 99 /* Control unconditional IBPB in switch_mm() */ 100 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 101 102 /* Control MDS CPU buffer clear before returning to user space */ 103 DEFINE_STATIC_KEY_FALSE(mds_user_clear); 104 EXPORT_SYMBOL_GPL(mds_user_clear); 105 /* Control MDS CPU buffer clear before idling (halt, mwait) */ 106 DEFINE_STATIC_KEY_FALSE(mds_idle_clear); 107 EXPORT_SYMBOL_GPL(mds_idle_clear); 108 109 /* 110 * Controls whether l1d flush based mitigations are enabled, 111 * based on hw features and admin setting via boot parameter 112 * defaults to false 113 */ 114 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 115 116 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */ 117 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); 118 EXPORT_SYMBOL_GPL(mmio_stale_data_clear); 119 120 void __init check_bugs(void) 121 { 122 identify_boot_cpu(); 123 124 /* 125 * identify_boot_cpu() initialized SMT support information, let the 126 * core code know. 127 */ 128 cpu_smt_check_topology(); 129 130 if (!IS_ENABLED(CONFIG_SMP)) { 131 pr_info("CPU: "); 132 print_cpu_info(&boot_cpu_data); 133 } 134 135 /* 136 * Read the SPEC_CTRL MSR to account for reserved bits which may 137 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD 138 * init code as it is not enumerated and depends on the family. 139 */ 140 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 141 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 142 143 /* Select the proper CPU mitigations before patching alternatives: */ 144 spectre_v1_select_mitigation(); 145 spectre_v2_select_mitigation(); 146 /* 147 * retbleed_select_mitigation() relies on the state set by 148 * spectre_v2_select_mitigation(); specifically it wants to know about 149 * spectre_v2=ibrs. 150 */ 151 retbleed_select_mitigation(); 152 /* 153 * spectre_v2_user_select_mitigation() relies on the state set by 154 * retbleed_select_mitigation(); specifically the STIBP selection is 155 * forced for UNRET. 156 */ 157 spectre_v2_user_select_mitigation(); 158 ssb_select_mitigation(); 159 l1tf_select_mitigation(); 160 md_clear_select_mitigation(); 161 srbds_select_mitigation(); 162 l1d_flush_select_mitigation(); 163 164 arch_smt_update(); 165 166 #ifdef CONFIG_X86_32 167 /* 168 * Check whether we are able to run this kernel safely on SMP. 169 * 170 * - i386 is no longer supported. 171 * - In order to run on anything without a TSC, we need to be 172 * compiled for a i486. 173 */ 174 if (boot_cpu_data.x86 < 4) 175 panic("Kernel requires i486+ for 'invlpg' and other features"); 176 177 init_utsname()->machine[1] = 178 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 179 alternative_instructions(); 180 181 fpu__init_check_bugs(); 182 #else /* CONFIG_X86_64 */ 183 alternative_instructions(); 184 185 /* 186 * Make sure the first 2MB area is not mapped by huge pages 187 * There are typically fixed size MTRRs in there and overlapping 188 * MTRRs into large pages causes slow downs. 189 * 190 * Right now we don't do that with gbpages because there seems 191 * very little benefit for that case. 192 */ 193 if (!direct_gbpages) 194 set_memory_4k((unsigned long)__va(0), 1); 195 #endif 196 } 197 198 /* 199 * NOTE: This function is *only* called for SVM. VMX spec_ctrl handling is 200 * done in vmenter.S. 201 */ 202 void 203 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) 204 { 205 u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current(); 206 struct thread_info *ti = current_thread_info(); 207 208 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { 209 if (hostval != guestval) { 210 msrval = setguest ? guestval : hostval; 211 wrmsrl(MSR_IA32_SPEC_CTRL, msrval); 212 } 213 } 214 215 /* 216 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update 217 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. 218 */ 219 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 220 !static_cpu_has(X86_FEATURE_VIRT_SSBD)) 221 return; 222 223 /* 224 * If the host has SSBD mitigation enabled, force it in the host's 225 * virtual MSR value. If its not permanently enabled, evaluate 226 * current's TIF_SSBD thread flag. 227 */ 228 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) 229 hostval = SPEC_CTRL_SSBD; 230 else 231 hostval = ssbd_tif_to_spec_ctrl(ti->flags); 232 233 /* Sanitize the guest value */ 234 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; 235 236 if (hostval != guestval) { 237 unsigned long tif; 238 239 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : 240 ssbd_spec_ctrl_to_tif(hostval); 241 242 speculation_ctrl_update(tif); 243 } 244 } 245 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); 246 247 static void x86_amd_ssb_disable(void) 248 { 249 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; 250 251 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) 252 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); 253 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) 254 wrmsrl(MSR_AMD64_LS_CFG, msrval); 255 } 256 257 #undef pr_fmt 258 #define pr_fmt(fmt) "MDS: " fmt 259 260 /* Default mitigation for MDS-affected CPUs */ 261 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; 262 static bool mds_nosmt __ro_after_init = false; 263 264 static const char * const mds_strings[] = { 265 [MDS_MITIGATION_OFF] = "Vulnerable", 266 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", 267 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", 268 }; 269 270 static void __init mds_select_mitigation(void) 271 { 272 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { 273 mds_mitigation = MDS_MITIGATION_OFF; 274 return; 275 } 276 277 if (mds_mitigation == MDS_MITIGATION_FULL) { 278 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) 279 mds_mitigation = MDS_MITIGATION_VMWERV; 280 281 static_branch_enable(&mds_user_clear); 282 283 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && 284 (mds_nosmt || cpu_mitigations_auto_nosmt())) 285 cpu_smt_disable(false); 286 } 287 } 288 289 static int __init mds_cmdline(char *str) 290 { 291 if (!boot_cpu_has_bug(X86_BUG_MDS)) 292 return 0; 293 294 if (!str) 295 return -EINVAL; 296 297 if (!strcmp(str, "off")) 298 mds_mitigation = MDS_MITIGATION_OFF; 299 else if (!strcmp(str, "full")) 300 mds_mitigation = MDS_MITIGATION_FULL; 301 else if (!strcmp(str, "full,nosmt")) { 302 mds_mitigation = MDS_MITIGATION_FULL; 303 mds_nosmt = true; 304 } 305 306 return 0; 307 } 308 early_param("mds", mds_cmdline); 309 310 #undef pr_fmt 311 #define pr_fmt(fmt) "TAA: " fmt 312 313 enum taa_mitigations { 314 TAA_MITIGATION_OFF, 315 TAA_MITIGATION_UCODE_NEEDED, 316 TAA_MITIGATION_VERW, 317 TAA_MITIGATION_TSX_DISABLED, 318 }; 319 320 /* Default mitigation for TAA-affected CPUs */ 321 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW; 322 static bool taa_nosmt __ro_after_init; 323 324 static const char * const taa_strings[] = { 325 [TAA_MITIGATION_OFF] = "Vulnerable", 326 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 327 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 328 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled", 329 }; 330 331 static void __init taa_select_mitigation(void) 332 { 333 u64 ia32_cap; 334 335 if (!boot_cpu_has_bug(X86_BUG_TAA)) { 336 taa_mitigation = TAA_MITIGATION_OFF; 337 return; 338 } 339 340 /* TSX previously disabled by tsx=off */ 341 if (!boot_cpu_has(X86_FEATURE_RTM)) { 342 taa_mitigation = TAA_MITIGATION_TSX_DISABLED; 343 return; 344 } 345 346 if (cpu_mitigations_off()) { 347 taa_mitigation = TAA_MITIGATION_OFF; 348 return; 349 } 350 351 /* 352 * TAA mitigation via VERW is turned off if both 353 * tsx_async_abort=off and mds=off are specified. 354 */ 355 if (taa_mitigation == TAA_MITIGATION_OFF && 356 mds_mitigation == MDS_MITIGATION_OFF) 357 return; 358 359 if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) 360 taa_mitigation = TAA_MITIGATION_VERW; 361 else 362 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 363 364 /* 365 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1. 366 * A microcode update fixes this behavior to clear CPU buffers. It also 367 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the 368 * ARCH_CAP_TSX_CTRL_MSR bit. 369 * 370 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode 371 * update is required. 372 */ 373 ia32_cap = x86_read_arch_cap_msr(); 374 if ( (ia32_cap & ARCH_CAP_MDS_NO) && 375 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR)) 376 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 377 378 /* 379 * TSX is enabled, select alternate mitigation for TAA which is 380 * the same as MDS. Enable MDS static branch to clear CPU buffers. 381 * 382 * For guests that can't determine whether the correct microcode is 383 * present on host, enable the mitigation for UCODE_NEEDED as well. 384 */ 385 static_branch_enable(&mds_user_clear); 386 387 if (taa_nosmt || cpu_mitigations_auto_nosmt()) 388 cpu_smt_disable(false); 389 } 390 391 static int __init tsx_async_abort_parse_cmdline(char *str) 392 { 393 if (!boot_cpu_has_bug(X86_BUG_TAA)) 394 return 0; 395 396 if (!str) 397 return -EINVAL; 398 399 if (!strcmp(str, "off")) { 400 taa_mitigation = TAA_MITIGATION_OFF; 401 } else if (!strcmp(str, "full")) { 402 taa_mitigation = TAA_MITIGATION_VERW; 403 } else if (!strcmp(str, "full,nosmt")) { 404 taa_mitigation = TAA_MITIGATION_VERW; 405 taa_nosmt = true; 406 } 407 408 return 0; 409 } 410 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline); 411 412 #undef pr_fmt 413 #define pr_fmt(fmt) "MMIO Stale Data: " fmt 414 415 enum mmio_mitigations { 416 MMIO_MITIGATION_OFF, 417 MMIO_MITIGATION_UCODE_NEEDED, 418 MMIO_MITIGATION_VERW, 419 }; 420 421 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ 422 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW; 423 static bool mmio_nosmt __ro_after_init = false; 424 425 static const char * const mmio_strings[] = { 426 [MMIO_MITIGATION_OFF] = "Vulnerable", 427 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 428 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 429 }; 430 431 static void __init mmio_select_mitigation(void) 432 { 433 u64 ia32_cap; 434 435 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) || 436 cpu_mitigations_off()) { 437 mmio_mitigation = MMIO_MITIGATION_OFF; 438 return; 439 } 440 441 if (mmio_mitigation == MMIO_MITIGATION_OFF) 442 return; 443 444 ia32_cap = x86_read_arch_cap_msr(); 445 446 /* 447 * Enable CPU buffer clear mitigation for host and VMM, if also affected 448 * by MDS or TAA. Otherwise, enable mitigation for VMM only. 449 */ 450 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) && 451 boot_cpu_has(X86_FEATURE_RTM))) 452 static_branch_enable(&mds_user_clear); 453 else 454 static_branch_enable(&mmio_stale_data_clear); 455 456 /* 457 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can 458 * be propagated to uncore buffers, clearing the Fill buffers on idle 459 * is required irrespective of SMT state. 460 */ 461 if (!(ia32_cap & ARCH_CAP_FBSDP_NO)) 462 static_branch_enable(&mds_idle_clear); 463 464 /* 465 * Check if the system has the right microcode. 466 * 467 * CPU Fill buffer clear mitigation is enumerated by either an explicit 468 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS 469 * affected systems. 470 */ 471 if ((ia32_cap & ARCH_CAP_FB_CLEAR) || 472 (boot_cpu_has(X86_FEATURE_MD_CLEAR) && 473 boot_cpu_has(X86_FEATURE_FLUSH_L1D) && 474 !(ia32_cap & ARCH_CAP_MDS_NO))) 475 mmio_mitigation = MMIO_MITIGATION_VERW; 476 else 477 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED; 478 479 if (mmio_nosmt || cpu_mitigations_auto_nosmt()) 480 cpu_smt_disable(false); 481 } 482 483 static int __init mmio_stale_data_parse_cmdline(char *str) 484 { 485 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 486 return 0; 487 488 if (!str) 489 return -EINVAL; 490 491 if (!strcmp(str, "off")) { 492 mmio_mitigation = MMIO_MITIGATION_OFF; 493 } else if (!strcmp(str, "full")) { 494 mmio_mitigation = MMIO_MITIGATION_VERW; 495 } else if (!strcmp(str, "full,nosmt")) { 496 mmio_mitigation = MMIO_MITIGATION_VERW; 497 mmio_nosmt = true; 498 } 499 500 return 0; 501 } 502 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline); 503 504 #undef pr_fmt 505 #define pr_fmt(fmt) "" fmt 506 507 static void __init md_clear_update_mitigation(void) 508 { 509 if (cpu_mitigations_off()) 510 return; 511 512 if (!static_key_enabled(&mds_user_clear)) 513 goto out; 514 515 /* 516 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data 517 * mitigation, if necessary. 518 */ 519 if (mds_mitigation == MDS_MITIGATION_OFF && 520 boot_cpu_has_bug(X86_BUG_MDS)) { 521 mds_mitigation = MDS_MITIGATION_FULL; 522 mds_select_mitigation(); 523 } 524 if (taa_mitigation == TAA_MITIGATION_OFF && 525 boot_cpu_has_bug(X86_BUG_TAA)) { 526 taa_mitigation = TAA_MITIGATION_VERW; 527 taa_select_mitigation(); 528 } 529 if (mmio_mitigation == MMIO_MITIGATION_OFF && 530 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) { 531 mmio_mitigation = MMIO_MITIGATION_VERW; 532 mmio_select_mitigation(); 533 } 534 out: 535 if (boot_cpu_has_bug(X86_BUG_MDS)) 536 pr_info("MDS: %s\n", mds_strings[mds_mitigation]); 537 if (boot_cpu_has_bug(X86_BUG_TAA)) 538 pr_info("TAA: %s\n", taa_strings[taa_mitigation]); 539 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 540 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); 541 } 542 543 static void __init md_clear_select_mitigation(void) 544 { 545 mds_select_mitigation(); 546 taa_select_mitigation(); 547 mmio_select_mitigation(); 548 549 /* 550 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update 551 * and print their mitigation after MDS, TAA and MMIO Stale Data 552 * mitigation selection is done. 553 */ 554 md_clear_update_mitigation(); 555 } 556 557 #undef pr_fmt 558 #define pr_fmt(fmt) "SRBDS: " fmt 559 560 enum srbds_mitigations { 561 SRBDS_MITIGATION_OFF, 562 SRBDS_MITIGATION_UCODE_NEEDED, 563 SRBDS_MITIGATION_FULL, 564 SRBDS_MITIGATION_TSX_OFF, 565 SRBDS_MITIGATION_HYPERVISOR, 566 }; 567 568 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL; 569 570 static const char * const srbds_strings[] = { 571 [SRBDS_MITIGATION_OFF] = "Vulnerable", 572 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 573 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode", 574 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled", 575 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", 576 }; 577 578 static bool srbds_off; 579 580 void update_srbds_msr(void) 581 { 582 u64 mcu_ctrl; 583 584 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 585 return; 586 587 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 588 return; 589 590 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) 591 return; 592 593 /* 594 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX 595 * being disabled and it hasn't received the SRBDS MSR microcode. 596 */ 597 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 598 return; 599 600 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 601 602 switch (srbds_mitigation) { 603 case SRBDS_MITIGATION_OFF: 604 case SRBDS_MITIGATION_TSX_OFF: 605 mcu_ctrl |= RNGDS_MITG_DIS; 606 break; 607 case SRBDS_MITIGATION_FULL: 608 mcu_ctrl &= ~RNGDS_MITG_DIS; 609 break; 610 default: 611 break; 612 } 613 614 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 615 } 616 617 static void __init srbds_select_mitigation(void) 618 { 619 u64 ia32_cap; 620 621 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 622 return; 623 624 /* 625 * Check to see if this is one of the MDS_NO systems supporting TSX that 626 * are only exposed to SRBDS when TSX is enabled or when CPU is affected 627 * by Processor MMIO Stale Data vulnerability. 628 */ 629 ia32_cap = x86_read_arch_cap_msr(); 630 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) && 631 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 632 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF; 633 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 634 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR; 635 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 636 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED; 637 else if (cpu_mitigations_off() || srbds_off) 638 srbds_mitigation = SRBDS_MITIGATION_OFF; 639 640 update_srbds_msr(); 641 pr_info("%s\n", srbds_strings[srbds_mitigation]); 642 } 643 644 static int __init srbds_parse_cmdline(char *str) 645 { 646 if (!str) 647 return -EINVAL; 648 649 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 650 return 0; 651 652 srbds_off = !strcmp(str, "off"); 653 return 0; 654 } 655 early_param("srbds", srbds_parse_cmdline); 656 657 #undef pr_fmt 658 #define pr_fmt(fmt) "L1D Flush : " fmt 659 660 enum l1d_flush_mitigations { 661 L1D_FLUSH_OFF = 0, 662 L1D_FLUSH_ON, 663 }; 664 665 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF; 666 667 static void __init l1d_flush_select_mitigation(void) 668 { 669 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) 670 return; 671 672 static_branch_enable(&switch_mm_cond_l1d_flush); 673 pr_info("Conditional flush on switch_mm() enabled\n"); 674 } 675 676 static int __init l1d_flush_parse_cmdline(char *str) 677 { 678 if (!strcmp(str, "on")) 679 l1d_flush_mitigation = L1D_FLUSH_ON; 680 681 return 0; 682 } 683 early_param("l1d_flush", l1d_flush_parse_cmdline); 684 685 #undef pr_fmt 686 #define pr_fmt(fmt) "Spectre V1 : " fmt 687 688 enum spectre_v1_mitigation { 689 SPECTRE_V1_MITIGATION_NONE, 690 SPECTRE_V1_MITIGATION_AUTO, 691 }; 692 693 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = 694 SPECTRE_V1_MITIGATION_AUTO; 695 696 static const char * const spectre_v1_strings[] = { 697 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", 698 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", 699 }; 700 701 /* 702 * Does SMAP provide full mitigation against speculative kernel access to 703 * userspace? 704 */ 705 static bool smap_works_speculatively(void) 706 { 707 if (!boot_cpu_has(X86_FEATURE_SMAP)) 708 return false; 709 710 /* 711 * On CPUs which are vulnerable to Meltdown, SMAP does not 712 * prevent speculative access to user data in the L1 cache. 713 * Consider SMAP to be non-functional as a mitigation on these 714 * CPUs. 715 */ 716 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) 717 return false; 718 719 return true; 720 } 721 722 static void __init spectre_v1_select_mitigation(void) 723 { 724 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { 725 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 726 return; 727 } 728 729 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { 730 /* 731 * With Spectre v1, a user can speculatively control either 732 * path of a conditional swapgs with a user-controlled GS 733 * value. The mitigation is to add lfences to both code paths. 734 * 735 * If FSGSBASE is enabled, the user can put a kernel address in 736 * GS, in which case SMAP provides no protection. 737 * 738 * If FSGSBASE is disabled, the user can only put a user space 739 * address in GS. That makes an attack harder, but still 740 * possible if there's no SMAP protection. 741 */ 742 if (boot_cpu_has(X86_FEATURE_FSGSBASE) || 743 !smap_works_speculatively()) { 744 /* 745 * Mitigation can be provided from SWAPGS itself or 746 * PTI as the CR3 write in the Meltdown mitigation 747 * is serializing. 748 * 749 * If neither is there, mitigate with an LFENCE to 750 * stop speculation through swapgs. 751 */ 752 if (boot_cpu_has_bug(X86_BUG_SWAPGS) && 753 !boot_cpu_has(X86_FEATURE_PTI)) 754 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); 755 756 /* 757 * Enable lfences in the kernel entry (non-swapgs) 758 * paths, to prevent user entry from speculatively 759 * skipping swapgs. 760 */ 761 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); 762 } 763 } 764 765 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); 766 } 767 768 static int __init nospectre_v1_cmdline(char *str) 769 { 770 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 771 return 0; 772 } 773 early_param("nospectre_v1", nospectre_v1_cmdline); 774 775 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = 776 SPECTRE_V2_NONE; 777 778 #undef pr_fmt 779 #define pr_fmt(fmt) "RETBleed: " fmt 780 781 enum retbleed_mitigation { 782 RETBLEED_MITIGATION_NONE, 783 RETBLEED_MITIGATION_UNRET, 784 RETBLEED_MITIGATION_IBPB, 785 RETBLEED_MITIGATION_IBRS, 786 RETBLEED_MITIGATION_EIBRS, 787 }; 788 789 enum retbleed_mitigation_cmd { 790 RETBLEED_CMD_OFF, 791 RETBLEED_CMD_AUTO, 792 RETBLEED_CMD_UNRET, 793 RETBLEED_CMD_IBPB, 794 }; 795 796 static const char * const retbleed_strings[] = { 797 [RETBLEED_MITIGATION_NONE] = "Vulnerable", 798 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk", 799 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB", 800 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS", 801 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS", 802 }; 803 804 static enum retbleed_mitigation retbleed_mitigation __ro_after_init = 805 RETBLEED_MITIGATION_NONE; 806 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init = 807 RETBLEED_CMD_AUTO; 808 809 static int __ro_after_init retbleed_nosmt = false; 810 811 static int __init retbleed_parse_cmdline(char *str) 812 { 813 if (!str) 814 return -EINVAL; 815 816 while (str) { 817 char *next = strchr(str, ','); 818 if (next) { 819 *next = 0; 820 next++; 821 } 822 823 if (!strcmp(str, "off")) { 824 retbleed_cmd = RETBLEED_CMD_OFF; 825 } else if (!strcmp(str, "auto")) { 826 retbleed_cmd = RETBLEED_CMD_AUTO; 827 } else if (!strcmp(str, "unret")) { 828 retbleed_cmd = RETBLEED_CMD_UNRET; 829 } else if (!strcmp(str, "ibpb")) { 830 retbleed_cmd = RETBLEED_CMD_IBPB; 831 } else if (!strcmp(str, "nosmt")) { 832 retbleed_nosmt = true; 833 } else { 834 pr_err("Ignoring unknown retbleed option (%s).", str); 835 } 836 837 str = next; 838 } 839 840 return 0; 841 } 842 early_param("retbleed", retbleed_parse_cmdline); 843 844 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n" 845 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n" 846 847 static void __init retbleed_select_mitigation(void) 848 { 849 bool mitigate_smt = false; 850 851 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off()) 852 return; 853 854 switch (retbleed_cmd) { 855 case RETBLEED_CMD_OFF: 856 return; 857 858 case RETBLEED_CMD_UNRET: 859 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) { 860 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 861 } else { 862 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n"); 863 goto do_cmd_auto; 864 } 865 break; 866 867 case RETBLEED_CMD_IBPB: 868 if (!boot_cpu_has(X86_FEATURE_IBPB)) { 869 pr_err("WARNING: CPU does not support IBPB.\n"); 870 goto do_cmd_auto; 871 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) { 872 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 873 } else { 874 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n"); 875 goto do_cmd_auto; 876 } 877 break; 878 879 do_cmd_auto: 880 case RETBLEED_CMD_AUTO: 881 default: 882 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 883 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { 884 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) 885 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 886 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB)) 887 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 888 } 889 890 /* 891 * The Intel mitigation (IBRS or eIBRS) was already selected in 892 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will 893 * be set accordingly below. 894 */ 895 896 break; 897 } 898 899 switch (retbleed_mitigation) { 900 case RETBLEED_MITIGATION_UNRET: 901 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 902 setup_force_cpu_cap(X86_FEATURE_UNRET); 903 904 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 905 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 906 pr_err(RETBLEED_UNTRAIN_MSG); 907 908 mitigate_smt = true; 909 break; 910 911 case RETBLEED_MITIGATION_IBPB: 912 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); 913 mitigate_smt = true; 914 break; 915 916 default: 917 break; 918 } 919 920 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) && 921 (retbleed_nosmt || cpu_mitigations_auto_nosmt())) 922 cpu_smt_disable(false); 923 924 /* 925 * Let IBRS trump all on Intel without affecting the effects of the 926 * retbleed= cmdline option. 927 */ 928 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 929 switch (spectre_v2_enabled) { 930 case SPECTRE_V2_IBRS: 931 retbleed_mitigation = RETBLEED_MITIGATION_IBRS; 932 break; 933 case SPECTRE_V2_EIBRS: 934 case SPECTRE_V2_EIBRS_RETPOLINE: 935 case SPECTRE_V2_EIBRS_LFENCE: 936 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS; 937 break; 938 default: 939 pr_err(RETBLEED_INTEL_MSG); 940 } 941 } 942 943 pr_info("%s\n", retbleed_strings[retbleed_mitigation]); 944 } 945 946 #undef pr_fmt 947 #define pr_fmt(fmt) "Spectre V2 : " fmt 948 949 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init = 950 SPECTRE_V2_USER_NONE; 951 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init = 952 SPECTRE_V2_USER_NONE; 953 954 #ifdef CONFIG_RETPOLINE 955 static bool spectre_v2_bad_module; 956 957 bool retpoline_module_ok(bool has_retpoline) 958 { 959 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) 960 return true; 961 962 pr_err("System may be vulnerable to spectre v2\n"); 963 spectre_v2_bad_module = true; 964 return false; 965 } 966 967 static inline const char *spectre_v2_module_string(void) 968 { 969 return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; 970 } 971 #else 972 static inline const char *spectre_v2_module_string(void) { return ""; } 973 #endif 974 975 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n" 976 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n" 977 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n" 978 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n" 979 980 #ifdef CONFIG_BPF_SYSCALL 981 void unpriv_ebpf_notify(int new_state) 982 { 983 if (new_state) 984 return; 985 986 /* Unprivileged eBPF is enabled */ 987 988 switch (spectre_v2_enabled) { 989 case SPECTRE_V2_EIBRS: 990 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 991 break; 992 case SPECTRE_V2_EIBRS_LFENCE: 993 if (sched_smt_active()) 994 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 995 break; 996 default: 997 break; 998 } 999 } 1000 #endif 1001 1002 static inline bool match_option(const char *arg, int arglen, const char *opt) 1003 { 1004 int len = strlen(opt); 1005 1006 return len == arglen && !strncmp(arg, opt, len); 1007 } 1008 1009 /* The kernel command line selection for spectre v2 */ 1010 enum spectre_v2_mitigation_cmd { 1011 SPECTRE_V2_CMD_NONE, 1012 SPECTRE_V2_CMD_AUTO, 1013 SPECTRE_V2_CMD_FORCE, 1014 SPECTRE_V2_CMD_RETPOLINE, 1015 SPECTRE_V2_CMD_RETPOLINE_GENERIC, 1016 SPECTRE_V2_CMD_RETPOLINE_LFENCE, 1017 SPECTRE_V2_CMD_EIBRS, 1018 SPECTRE_V2_CMD_EIBRS_RETPOLINE, 1019 SPECTRE_V2_CMD_EIBRS_LFENCE, 1020 SPECTRE_V2_CMD_IBRS, 1021 }; 1022 1023 enum spectre_v2_user_cmd { 1024 SPECTRE_V2_USER_CMD_NONE, 1025 SPECTRE_V2_USER_CMD_AUTO, 1026 SPECTRE_V2_USER_CMD_FORCE, 1027 SPECTRE_V2_USER_CMD_PRCTL, 1028 SPECTRE_V2_USER_CMD_PRCTL_IBPB, 1029 SPECTRE_V2_USER_CMD_SECCOMP, 1030 SPECTRE_V2_USER_CMD_SECCOMP_IBPB, 1031 }; 1032 1033 static const char * const spectre_v2_user_strings[] = { 1034 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", 1035 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", 1036 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", 1037 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", 1038 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", 1039 }; 1040 1041 static const struct { 1042 const char *option; 1043 enum spectre_v2_user_cmd cmd; 1044 bool secure; 1045 } v2_user_options[] __initconst = { 1046 { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, 1047 { "off", SPECTRE_V2_USER_CMD_NONE, false }, 1048 { "on", SPECTRE_V2_USER_CMD_FORCE, true }, 1049 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, 1050 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, 1051 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, 1052 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, 1053 }; 1054 1055 static void __init spec_v2_user_print_cond(const char *reason, bool secure) 1056 { 1057 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1058 pr_info("spectre_v2_user=%s forced on command line.\n", reason); 1059 } 1060 1061 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd; 1062 1063 static enum spectre_v2_user_cmd __init 1064 spectre_v2_parse_user_cmdline(void) 1065 { 1066 char arg[20]; 1067 int ret, i; 1068 1069 switch (spectre_v2_cmd) { 1070 case SPECTRE_V2_CMD_NONE: 1071 return SPECTRE_V2_USER_CMD_NONE; 1072 case SPECTRE_V2_CMD_FORCE: 1073 return SPECTRE_V2_USER_CMD_FORCE; 1074 default: 1075 break; 1076 } 1077 1078 ret = cmdline_find_option(boot_command_line, "spectre_v2_user", 1079 arg, sizeof(arg)); 1080 if (ret < 0) 1081 return SPECTRE_V2_USER_CMD_AUTO; 1082 1083 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { 1084 if (match_option(arg, ret, v2_user_options[i].option)) { 1085 spec_v2_user_print_cond(v2_user_options[i].option, 1086 v2_user_options[i].secure); 1087 return v2_user_options[i].cmd; 1088 } 1089 } 1090 1091 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); 1092 return SPECTRE_V2_USER_CMD_AUTO; 1093 } 1094 1095 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) 1096 { 1097 return mode == SPECTRE_V2_IBRS || 1098 mode == SPECTRE_V2_EIBRS || 1099 mode == SPECTRE_V2_EIBRS_RETPOLINE || 1100 mode == SPECTRE_V2_EIBRS_LFENCE; 1101 } 1102 1103 static void __init 1104 spectre_v2_user_select_mitigation(void) 1105 { 1106 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; 1107 bool smt_possible = IS_ENABLED(CONFIG_SMP); 1108 enum spectre_v2_user_cmd cmd; 1109 1110 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) 1111 return; 1112 1113 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || 1114 cpu_smt_control == CPU_SMT_NOT_SUPPORTED) 1115 smt_possible = false; 1116 1117 cmd = spectre_v2_parse_user_cmdline(); 1118 switch (cmd) { 1119 case SPECTRE_V2_USER_CMD_NONE: 1120 goto set_mode; 1121 case SPECTRE_V2_USER_CMD_FORCE: 1122 mode = SPECTRE_V2_USER_STRICT; 1123 break; 1124 case SPECTRE_V2_USER_CMD_AUTO: 1125 case SPECTRE_V2_USER_CMD_PRCTL: 1126 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1127 mode = SPECTRE_V2_USER_PRCTL; 1128 break; 1129 case SPECTRE_V2_USER_CMD_SECCOMP: 1130 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1131 if (IS_ENABLED(CONFIG_SECCOMP)) 1132 mode = SPECTRE_V2_USER_SECCOMP; 1133 else 1134 mode = SPECTRE_V2_USER_PRCTL; 1135 break; 1136 } 1137 1138 /* Initialize Indirect Branch Prediction Barrier */ 1139 if (boot_cpu_has(X86_FEATURE_IBPB)) { 1140 setup_force_cpu_cap(X86_FEATURE_USE_IBPB); 1141 1142 spectre_v2_user_ibpb = mode; 1143 switch (cmd) { 1144 case SPECTRE_V2_USER_CMD_FORCE: 1145 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1146 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1147 static_branch_enable(&switch_mm_always_ibpb); 1148 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT; 1149 break; 1150 case SPECTRE_V2_USER_CMD_PRCTL: 1151 case SPECTRE_V2_USER_CMD_AUTO: 1152 case SPECTRE_V2_USER_CMD_SECCOMP: 1153 static_branch_enable(&switch_mm_cond_ibpb); 1154 break; 1155 default: 1156 break; 1157 } 1158 1159 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", 1160 static_key_enabled(&switch_mm_always_ibpb) ? 1161 "always-on" : "conditional"); 1162 } 1163 1164 /* 1165 * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible, 1166 * STIBP is not required. 1167 */ 1168 if (!boot_cpu_has(X86_FEATURE_STIBP) || 1169 !smt_possible || 1170 spectre_v2_in_ibrs_mode(spectre_v2_enabled)) 1171 return; 1172 1173 /* 1174 * At this point, an STIBP mode other than "off" has been set. 1175 * If STIBP support is not being forced, check if STIBP always-on 1176 * is preferred. 1177 */ 1178 if (mode != SPECTRE_V2_USER_STRICT && 1179 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) 1180 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1181 1182 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) { 1183 if (mode != SPECTRE_V2_USER_STRICT && 1184 mode != SPECTRE_V2_USER_STRICT_PREFERRED) 1185 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n"); 1186 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1187 } 1188 1189 spectre_v2_user_stibp = mode; 1190 1191 set_mode: 1192 pr_info("%s\n", spectre_v2_user_strings[mode]); 1193 } 1194 1195 static const char * const spectre_v2_strings[] = { 1196 [SPECTRE_V2_NONE] = "Vulnerable", 1197 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", 1198 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", 1199 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS", 1200 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE", 1201 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines", 1202 [SPECTRE_V2_IBRS] = "Mitigation: IBRS", 1203 }; 1204 1205 static const struct { 1206 const char *option; 1207 enum spectre_v2_mitigation_cmd cmd; 1208 bool secure; 1209 } mitigation_options[] __initconst = { 1210 { "off", SPECTRE_V2_CMD_NONE, false }, 1211 { "on", SPECTRE_V2_CMD_FORCE, true }, 1212 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, 1213 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1214 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1215 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, 1216 { "eibrs", SPECTRE_V2_CMD_EIBRS, false }, 1217 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false }, 1218 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false }, 1219 { "auto", SPECTRE_V2_CMD_AUTO, false }, 1220 { "ibrs", SPECTRE_V2_CMD_IBRS, false }, 1221 }; 1222 1223 static void __init spec_v2_print_cond(const char *reason, bool secure) 1224 { 1225 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1226 pr_info("%s selected on command line.\n", reason); 1227 } 1228 1229 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) 1230 { 1231 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; 1232 char arg[20]; 1233 int ret, i; 1234 1235 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || 1236 cpu_mitigations_off()) 1237 return SPECTRE_V2_CMD_NONE; 1238 1239 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); 1240 if (ret < 0) 1241 return SPECTRE_V2_CMD_AUTO; 1242 1243 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { 1244 if (!match_option(arg, ret, mitigation_options[i].option)) 1245 continue; 1246 cmd = mitigation_options[i].cmd; 1247 break; 1248 } 1249 1250 if (i >= ARRAY_SIZE(mitigation_options)) { 1251 pr_err("unknown option (%s). Switching to AUTO select\n", arg); 1252 return SPECTRE_V2_CMD_AUTO; 1253 } 1254 1255 if ((cmd == SPECTRE_V2_CMD_RETPOLINE || 1256 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1257 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC || 1258 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1259 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1260 !IS_ENABLED(CONFIG_RETPOLINE)) { 1261 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1262 mitigation_options[i].option); 1263 return SPECTRE_V2_CMD_AUTO; 1264 } 1265 1266 if ((cmd == SPECTRE_V2_CMD_EIBRS || 1267 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1268 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1269 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1270 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n", 1271 mitigation_options[i].option); 1272 return SPECTRE_V2_CMD_AUTO; 1273 } 1274 1275 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1276 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) && 1277 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { 1278 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", 1279 mitigation_options[i].option); 1280 return SPECTRE_V2_CMD_AUTO; 1281 } 1282 1283 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) { 1284 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1285 mitigation_options[i].option); 1286 return SPECTRE_V2_CMD_AUTO; 1287 } 1288 1289 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 1290 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n", 1291 mitigation_options[i].option); 1292 return SPECTRE_V2_CMD_AUTO; 1293 } 1294 1295 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) { 1296 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n", 1297 mitigation_options[i].option); 1298 return SPECTRE_V2_CMD_AUTO; 1299 } 1300 1301 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) { 1302 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n", 1303 mitigation_options[i].option); 1304 return SPECTRE_V2_CMD_AUTO; 1305 } 1306 1307 spec_v2_print_cond(mitigation_options[i].option, 1308 mitigation_options[i].secure); 1309 return cmd; 1310 } 1311 1312 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void) 1313 { 1314 if (!IS_ENABLED(CONFIG_RETPOLINE)) { 1315 pr_err("Kernel not compiled with retpoline; no mitigation available!"); 1316 return SPECTRE_V2_NONE; 1317 } 1318 1319 return SPECTRE_V2_RETPOLINE; 1320 } 1321 1322 /* Disable in-kernel use of non-RSB RET predictors */ 1323 static void __init spec_ctrl_disable_kernel_rrsba(void) 1324 { 1325 u64 ia32_cap; 1326 1327 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL)) 1328 return; 1329 1330 ia32_cap = x86_read_arch_cap_msr(); 1331 1332 if (ia32_cap & ARCH_CAP_RRSBA) { 1333 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S; 1334 write_spec_ctrl_current(x86_spec_ctrl_base, true); 1335 } 1336 } 1337 1338 static void __init spectre_v2_select_mitigation(void) 1339 { 1340 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); 1341 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; 1342 1343 /* 1344 * If the CPU is not affected and the command line mode is NONE or AUTO 1345 * then nothing to do. 1346 */ 1347 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && 1348 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) 1349 return; 1350 1351 switch (cmd) { 1352 case SPECTRE_V2_CMD_NONE: 1353 return; 1354 1355 case SPECTRE_V2_CMD_FORCE: 1356 case SPECTRE_V2_CMD_AUTO: 1357 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1358 mode = SPECTRE_V2_EIBRS; 1359 break; 1360 } 1361 1362 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) && 1363 boot_cpu_has_bug(X86_BUG_RETBLEED) && 1364 retbleed_cmd != RETBLEED_CMD_OFF && 1365 boot_cpu_has(X86_FEATURE_IBRS) && 1366 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 1367 mode = SPECTRE_V2_IBRS; 1368 break; 1369 } 1370 1371 mode = spectre_v2_select_retpoline(); 1372 break; 1373 1374 case SPECTRE_V2_CMD_RETPOLINE_LFENCE: 1375 pr_err(SPECTRE_V2_LFENCE_MSG); 1376 mode = SPECTRE_V2_LFENCE; 1377 break; 1378 1379 case SPECTRE_V2_CMD_RETPOLINE_GENERIC: 1380 mode = SPECTRE_V2_RETPOLINE; 1381 break; 1382 1383 case SPECTRE_V2_CMD_RETPOLINE: 1384 mode = spectre_v2_select_retpoline(); 1385 break; 1386 1387 case SPECTRE_V2_CMD_IBRS: 1388 mode = SPECTRE_V2_IBRS; 1389 break; 1390 1391 case SPECTRE_V2_CMD_EIBRS: 1392 mode = SPECTRE_V2_EIBRS; 1393 break; 1394 1395 case SPECTRE_V2_CMD_EIBRS_LFENCE: 1396 mode = SPECTRE_V2_EIBRS_LFENCE; 1397 break; 1398 1399 case SPECTRE_V2_CMD_EIBRS_RETPOLINE: 1400 mode = SPECTRE_V2_EIBRS_RETPOLINE; 1401 break; 1402 } 1403 1404 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 1405 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 1406 1407 if (spectre_v2_in_ibrs_mode(mode)) { 1408 x86_spec_ctrl_base |= SPEC_CTRL_IBRS; 1409 write_spec_ctrl_current(x86_spec_ctrl_base, true); 1410 } 1411 1412 switch (mode) { 1413 case SPECTRE_V2_NONE: 1414 case SPECTRE_V2_EIBRS: 1415 break; 1416 1417 case SPECTRE_V2_IBRS: 1418 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS); 1419 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) 1420 pr_warn(SPECTRE_V2_IBRS_PERF_MSG); 1421 break; 1422 1423 case SPECTRE_V2_LFENCE: 1424 case SPECTRE_V2_EIBRS_LFENCE: 1425 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE); 1426 fallthrough; 1427 1428 case SPECTRE_V2_RETPOLINE: 1429 case SPECTRE_V2_EIBRS_RETPOLINE: 1430 setup_force_cpu_cap(X86_FEATURE_RETPOLINE); 1431 break; 1432 } 1433 1434 /* 1435 * Disable alternate RSB predictions in kernel when indirect CALLs and 1436 * JMPs gets protection against BHI and Intramode-BTI, but RET 1437 * prediction from a non-RSB predictor is still a risk. 1438 */ 1439 if (mode == SPECTRE_V2_EIBRS_LFENCE || 1440 mode == SPECTRE_V2_EIBRS_RETPOLINE || 1441 mode == SPECTRE_V2_RETPOLINE) 1442 spec_ctrl_disable_kernel_rrsba(); 1443 1444 spectre_v2_enabled = mode; 1445 pr_info("%s\n", spectre_v2_strings[mode]); 1446 1447 /* 1448 * If Spectre v2 protection has been enabled, fill the RSB during a 1449 * context switch. In general there are two types of RSB attacks 1450 * across context switches, for which the CALLs/RETs may be unbalanced. 1451 * 1452 * 1) RSB underflow 1453 * 1454 * Some Intel parts have "bottomless RSB". When the RSB is empty, 1455 * speculated return targets may come from the branch predictor, 1456 * which could have a user-poisoned BTB or BHB entry. 1457 * 1458 * AMD has it even worse: *all* returns are speculated from the BTB, 1459 * regardless of the state of the RSB. 1460 * 1461 * When IBRS or eIBRS is enabled, the "user -> kernel" attack 1462 * scenario is mitigated by the IBRS branch prediction isolation 1463 * properties, so the RSB buffer filling wouldn't be necessary to 1464 * protect against this type of attack. 1465 * 1466 * The "user -> user" attack scenario is mitigated by RSB filling. 1467 * 1468 * 2) Poisoned RSB entry 1469 * 1470 * If the 'next' in-kernel return stack is shorter than 'prev', 1471 * 'next' could be tricked into speculating with a user-poisoned RSB 1472 * entry. 1473 * 1474 * The "user -> kernel" attack scenario is mitigated by SMEP and 1475 * eIBRS. 1476 * 1477 * The "user -> user" scenario, also known as SpectreBHB, requires 1478 * RSB clearing. 1479 * 1480 * So to mitigate all cases, unconditionally fill RSB on context 1481 * switches. 1482 * 1483 * FIXME: Is this pointless for retbleed-affected AMD? 1484 */ 1485 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); 1486 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); 1487 1488 /* 1489 * Similar to context switches, there are two types of RSB attacks 1490 * after vmexit: 1491 * 1492 * 1) RSB underflow 1493 * 1494 * 2) Poisoned RSB entry 1495 * 1496 * When retpoline is enabled, both are mitigated by filling/clearing 1497 * the RSB. 1498 * 1499 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch 1500 * prediction isolation protections, RSB still needs to be cleared 1501 * because of #2. Note that SMEP provides no protection here, unlike 1502 * user-space-poisoned RSB entries. 1503 * 1504 * eIBRS, on the other hand, has RSB-poisoning protections, so it 1505 * doesn't need RSB clearing after vmexit. 1506 */ 1507 if (boot_cpu_has(X86_FEATURE_RETPOLINE) || 1508 boot_cpu_has(X86_FEATURE_KERNEL_IBRS)) 1509 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT); 1510 1511 /* 1512 * Retpoline protects the kernel, but doesn't protect firmware. IBRS 1513 * and Enhanced IBRS protect firmware too, so enable IBRS around 1514 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise 1515 * enabled. 1516 * 1517 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because 1518 * the user might select retpoline on the kernel command line and if 1519 * the CPU supports Enhanced IBRS, kernel might un-intentionally not 1520 * enable IBRS around firmware calls. 1521 */ 1522 if (boot_cpu_has_bug(X86_BUG_RETBLEED) && 1523 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1524 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) { 1525 1526 if (retbleed_cmd != RETBLEED_CMD_IBPB) { 1527 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW); 1528 pr_info("Enabling Speculation Barrier for firmware calls\n"); 1529 } 1530 1531 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) { 1532 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); 1533 pr_info("Enabling Restricted Speculation for firmware calls\n"); 1534 } 1535 1536 /* Set up IBPB and STIBP depending on the general spectre V2 command */ 1537 spectre_v2_cmd = cmd; 1538 } 1539 1540 static void update_stibp_msr(void * __unused) 1541 { 1542 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP); 1543 write_spec_ctrl_current(val, true); 1544 } 1545 1546 /* Update x86_spec_ctrl_base in case SMT state changed. */ 1547 static void update_stibp_strict(void) 1548 { 1549 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; 1550 1551 if (sched_smt_active()) 1552 mask |= SPEC_CTRL_STIBP; 1553 1554 if (mask == x86_spec_ctrl_base) 1555 return; 1556 1557 pr_info("Update user space SMT mitigation: STIBP %s\n", 1558 mask & SPEC_CTRL_STIBP ? "always-on" : "off"); 1559 x86_spec_ctrl_base = mask; 1560 on_each_cpu(update_stibp_msr, NULL, 1); 1561 } 1562 1563 /* Update the static key controlling the evaluation of TIF_SPEC_IB */ 1564 static void update_indir_branch_cond(void) 1565 { 1566 if (sched_smt_active()) 1567 static_branch_enable(&switch_to_cond_stibp); 1568 else 1569 static_branch_disable(&switch_to_cond_stibp); 1570 } 1571 1572 #undef pr_fmt 1573 #define pr_fmt(fmt) fmt 1574 1575 /* Update the static key controlling the MDS CPU buffer clear in idle */ 1576 static void update_mds_branch_idle(void) 1577 { 1578 u64 ia32_cap = x86_read_arch_cap_msr(); 1579 1580 /* 1581 * Enable the idle clearing if SMT is active on CPUs which are 1582 * affected only by MSBDS and not any other MDS variant. 1583 * 1584 * The other variants cannot be mitigated when SMT is enabled, so 1585 * clearing the buffers on idle just to prevent the Store Buffer 1586 * repartitioning leak would be a window dressing exercise. 1587 */ 1588 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) 1589 return; 1590 1591 if (sched_smt_active()) { 1592 static_branch_enable(&mds_idle_clear); 1593 } else if (mmio_mitigation == MMIO_MITIGATION_OFF || 1594 (ia32_cap & ARCH_CAP_FBSDP_NO)) { 1595 static_branch_disable(&mds_idle_clear); 1596 } 1597 } 1598 1599 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" 1600 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n" 1601 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n" 1602 1603 void cpu_bugs_smt_update(void) 1604 { 1605 mutex_lock(&spec_ctrl_mutex); 1606 1607 if (sched_smt_active() && unprivileged_ebpf_enabled() && 1608 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 1609 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 1610 1611 switch (spectre_v2_user_stibp) { 1612 case SPECTRE_V2_USER_NONE: 1613 break; 1614 case SPECTRE_V2_USER_STRICT: 1615 case SPECTRE_V2_USER_STRICT_PREFERRED: 1616 update_stibp_strict(); 1617 break; 1618 case SPECTRE_V2_USER_PRCTL: 1619 case SPECTRE_V2_USER_SECCOMP: 1620 update_indir_branch_cond(); 1621 break; 1622 } 1623 1624 switch (mds_mitigation) { 1625 case MDS_MITIGATION_FULL: 1626 case MDS_MITIGATION_VMWERV: 1627 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) 1628 pr_warn_once(MDS_MSG_SMT); 1629 update_mds_branch_idle(); 1630 break; 1631 case MDS_MITIGATION_OFF: 1632 break; 1633 } 1634 1635 switch (taa_mitigation) { 1636 case TAA_MITIGATION_VERW: 1637 case TAA_MITIGATION_UCODE_NEEDED: 1638 if (sched_smt_active()) 1639 pr_warn_once(TAA_MSG_SMT); 1640 break; 1641 case TAA_MITIGATION_TSX_DISABLED: 1642 case TAA_MITIGATION_OFF: 1643 break; 1644 } 1645 1646 switch (mmio_mitigation) { 1647 case MMIO_MITIGATION_VERW: 1648 case MMIO_MITIGATION_UCODE_NEEDED: 1649 if (sched_smt_active()) 1650 pr_warn_once(MMIO_MSG_SMT); 1651 break; 1652 case MMIO_MITIGATION_OFF: 1653 break; 1654 } 1655 1656 mutex_unlock(&spec_ctrl_mutex); 1657 } 1658 1659 #undef pr_fmt 1660 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt 1661 1662 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; 1663 1664 /* The kernel command line selection */ 1665 enum ssb_mitigation_cmd { 1666 SPEC_STORE_BYPASS_CMD_NONE, 1667 SPEC_STORE_BYPASS_CMD_AUTO, 1668 SPEC_STORE_BYPASS_CMD_ON, 1669 SPEC_STORE_BYPASS_CMD_PRCTL, 1670 SPEC_STORE_BYPASS_CMD_SECCOMP, 1671 }; 1672 1673 static const char * const ssb_strings[] = { 1674 [SPEC_STORE_BYPASS_NONE] = "Vulnerable", 1675 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", 1676 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", 1677 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", 1678 }; 1679 1680 static const struct { 1681 const char *option; 1682 enum ssb_mitigation_cmd cmd; 1683 } ssb_mitigation_options[] __initconst = { 1684 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ 1685 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ 1686 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ 1687 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ 1688 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ 1689 }; 1690 1691 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) 1692 { 1693 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; 1694 char arg[20]; 1695 int ret, i; 1696 1697 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || 1698 cpu_mitigations_off()) { 1699 return SPEC_STORE_BYPASS_CMD_NONE; 1700 } else { 1701 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", 1702 arg, sizeof(arg)); 1703 if (ret < 0) 1704 return SPEC_STORE_BYPASS_CMD_AUTO; 1705 1706 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { 1707 if (!match_option(arg, ret, ssb_mitigation_options[i].option)) 1708 continue; 1709 1710 cmd = ssb_mitigation_options[i].cmd; 1711 break; 1712 } 1713 1714 if (i >= ARRAY_SIZE(ssb_mitigation_options)) { 1715 pr_err("unknown option (%s). Switching to AUTO select\n", arg); 1716 return SPEC_STORE_BYPASS_CMD_AUTO; 1717 } 1718 } 1719 1720 return cmd; 1721 } 1722 1723 static enum ssb_mitigation __init __ssb_select_mitigation(void) 1724 { 1725 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; 1726 enum ssb_mitigation_cmd cmd; 1727 1728 if (!boot_cpu_has(X86_FEATURE_SSBD)) 1729 return mode; 1730 1731 cmd = ssb_parse_cmdline(); 1732 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && 1733 (cmd == SPEC_STORE_BYPASS_CMD_NONE || 1734 cmd == SPEC_STORE_BYPASS_CMD_AUTO)) 1735 return mode; 1736 1737 switch (cmd) { 1738 case SPEC_STORE_BYPASS_CMD_SECCOMP: 1739 /* 1740 * Choose prctl+seccomp as the default mode if seccomp is 1741 * enabled. 1742 */ 1743 if (IS_ENABLED(CONFIG_SECCOMP)) 1744 mode = SPEC_STORE_BYPASS_SECCOMP; 1745 else 1746 mode = SPEC_STORE_BYPASS_PRCTL; 1747 break; 1748 case SPEC_STORE_BYPASS_CMD_ON: 1749 mode = SPEC_STORE_BYPASS_DISABLE; 1750 break; 1751 case SPEC_STORE_BYPASS_CMD_AUTO: 1752 case SPEC_STORE_BYPASS_CMD_PRCTL: 1753 mode = SPEC_STORE_BYPASS_PRCTL; 1754 break; 1755 case SPEC_STORE_BYPASS_CMD_NONE: 1756 break; 1757 } 1758 1759 /* 1760 * We have three CPU feature flags that are in play here: 1761 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. 1762 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass 1763 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation 1764 */ 1765 if (mode == SPEC_STORE_BYPASS_DISABLE) { 1766 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); 1767 /* 1768 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may 1769 * use a completely different MSR and bit dependent on family. 1770 */ 1771 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 1772 !static_cpu_has(X86_FEATURE_AMD_SSBD)) { 1773 x86_amd_ssb_disable(); 1774 } else { 1775 x86_spec_ctrl_base |= SPEC_CTRL_SSBD; 1776 write_spec_ctrl_current(x86_spec_ctrl_base, true); 1777 } 1778 } 1779 1780 return mode; 1781 } 1782 1783 static void ssb_select_mitigation(void) 1784 { 1785 ssb_mode = __ssb_select_mitigation(); 1786 1787 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1788 pr_info("%s\n", ssb_strings[ssb_mode]); 1789 } 1790 1791 #undef pr_fmt 1792 #define pr_fmt(fmt) "Speculation prctl: " fmt 1793 1794 static void task_update_spec_tif(struct task_struct *tsk) 1795 { 1796 /* Force the update of the real TIF bits */ 1797 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); 1798 1799 /* 1800 * Immediately update the speculation control MSRs for the current 1801 * task, but for a non-current task delay setting the CPU 1802 * mitigation until it is scheduled next. 1803 * 1804 * This can only happen for SECCOMP mitigation. For PRCTL it's 1805 * always the current task. 1806 */ 1807 if (tsk == current) 1808 speculation_ctrl_update_current(); 1809 } 1810 1811 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl) 1812 { 1813 1814 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 1815 return -EPERM; 1816 1817 switch (ctrl) { 1818 case PR_SPEC_ENABLE: 1819 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 1820 return 0; 1821 case PR_SPEC_DISABLE: 1822 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 1823 return 0; 1824 default: 1825 return -ERANGE; 1826 } 1827 } 1828 1829 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) 1830 { 1831 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && 1832 ssb_mode != SPEC_STORE_BYPASS_SECCOMP) 1833 return -ENXIO; 1834 1835 switch (ctrl) { 1836 case PR_SPEC_ENABLE: 1837 /* If speculation is force disabled, enable is not allowed */ 1838 if (task_spec_ssb_force_disable(task)) 1839 return -EPERM; 1840 task_clear_spec_ssb_disable(task); 1841 task_clear_spec_ssb_noexec(task); 1842 task_update_spec_tif(task); 1843 break; 1844 case PR_SPEC_DISABLE: 1845 task_set_spec_ssb_disable(task); 1846 task_clear_spec_ssb_noexec(task); 1847 task_update_spec_tif(task); 1848 break; 1849 case PR_SPEC_FORCE_DISABLE: 1850 task_set_spec_ssb_disable(task); 1851 task_set_spec_ssb_force_disable(task); 1852 task_clear_spec_ssb_noexec(task); 1853 task_update_spec_tif(task); 1854 break; 1855 case PR_SPEC_DISABLE_NOEXEC: 1856 if (task_spec_ssb_force_disable(task)) 1857 return -EPERM; 1858 task_set_spec_ssb_disable(task); 1859 task_set_spec_ssb_noexec(task); 1860 task_update_spec_tif(task); 1861 break; 1862 default: 1863 return -ERANGE; 1864 } 1865 return 0; 1866 } 1867 1868 static bool is_spec_ib_user_controlled(void) 1869 { 1870 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL || 1871 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 1872 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL || 1873 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP; 1874 } 1875 1876 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 1877 { 1878 switch (ctrl) { 1879 case PR_SPEC_ENABLE: 1880 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1881 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1882 return 0; 1883 1884 /* 1885 * With strict mode for both IBPB and STIBP, the instruction 1886 * code paths avoid checking this task flag and instead, 1887 * unconditionally run the instruction. However, STIBP and IBPB 1888 * are independent and either can be set to conditionally 1889 * enabled regardless of the mode of the other. 1890 * 1891 * If either is set to conditional, allow the task flag to be 1892 * updated, unless it was force-disabled by a previous prctl 1893 * call. Currently, this is possible on an AMD CPU which has the 1894 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the 1895 * kernel is booted with 'spectre_v2_user=seccomp', then 1896 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and 1897 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED. 1898 */ 1899 if (!is_spec_ib_user_controlled() || 1900 task_spec_ib_force_disable(task)) 1901 return -EPERM; 1902 1903 task_clear_spec_ib_disable(task); 1904 task_update_spec_tif(task); 1905 break; 1906 case PR_SPEC_DISABLE: 1907 case PR_SPEC_FORCE_DISABLE: 1908 /* 1909 * Indirect branch speculation is always allowed when 1910 * mitigation is force disabled. 1911 */ 1912 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1913 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1914 return -EPERM; 1915 1916 if (!is_spec_ib_user_controlled()) 1917 return 0; 1918 1919 task_set_spec_ib_disable(task); 1920 if (ctrl == PR_SPEC_FORCE_DISABLE) 1921 task_set_spec_ib_force_disable(task); 1922 task_update_spec_tif(task); 1923 break; 1924 default: 1925 return -ERANGE; 1926 } 1927 return 0; 1928 } 1929 1930 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, 1931 unsigned long ctrl) 1932 { 1933 switch (which) { 1934 case PR_SPEC_STORE_BYPASS: 1935 return ssb_prctl_set(task, ctrl); 1936 case PR_SPEC_INDIRECT_BRANCH: 1937 return ib_prctl_set(task, ctrl); 1938 case PR_SPEC_L1D_FLUSH: 1939 return l1d_flush_prctl_set(task, ctrl); 1940 default: 1941 return -ENODEV; 1942 } 1943 } 1944 1945 #ifdef CONFIG_SECCOMP 1946 void arch_seccomp_spec_mitigate(struct task_struct *task) 1947 { 1948 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) 1949 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); 1950 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 1951 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) 1952 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); 1953 } 1954 #endif 1955 1956 static int l1d_flush_prctl_get(struct task_struct *task) 1957 { 1958 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 1959 return PR_SPEC_FORCE_DISABLE; 1960 1961 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH)) 1962 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1963 else 1964 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1965 } 1966 1967 static int ssb_prctl_get(struct task_struct *task) 1968 { 1969 switch (ssb_mode) { 1970 case SPEC_STORE_BYPASS_DISABLE: 1971 return PR_SPEC_DISABLE; 1972 case SPEC_STORE_BYPASS_SECCOMP: 1973 case SPEC_STORE_BYPASS_PRCTL: 1974 if (task_spec_ssb_force_disable(task)) 1975 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 1976 if (task_spec_ssb_noexec(task)) 1977 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC; 1978 if (task_spec_ssb_disable(task)) 1979 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1980 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1981 default: 1982 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1983 return PR_SPEC_ENABLE; 1984 return PR_SPEC_NOT_AFFECTED; 1985 } 1986 } 1987 1988 static int ib_prctl_get(struct task_struct *task) 1989 { 1990 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) 1991 return PR_SPEC_NOT_AFFECTED; 1992 1993 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1994 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1995 return PR_SPEC_ENABLE; 1996 else if (is_spec_ib_user_controlled()) { 1997 if (task_spec_ib_force_disable(task)) 1998 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 1999 if (task_spec_ib_disable(task)) 2000 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 2001 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 2002 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT || 2003 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 2004 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED) 2005 return PR_SPEC_DISABLE; 2006 else 2007 return PR_SPEC_NOT_AFFECTED; 2008 } 2009 2010 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) 2011 { 2012 switch (which) { 2013 case PR_SPEC_STORE_BYPASS: 2014 return ssb_prctl_get(task); 2015 case PR_SPEC_INDIRECT_BRANCH: 2016 return ib_prctl_get(task); 2017 case PR_SPEC_L1D_FLUSH: 2018 return l1d_flush_prctl_get(task); 2019 default: 2020 return -ENODEV; 2021 } 2022 } 2023 2024 void x86_spec_ctrl_setup_ap(void) 2025 { 2026 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 2027 write_spec_ctrl_current(x86_spec_ctrl_base, true); 2028 2029 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) 2030 x86_amd_ssb_disable(); 2031 } 2032 2033 bool itlb_multihit_kvm_mitigation; 2034 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); 2035 2036 #undef pr_fmt 2037 #define pr_fmt(fmt) "L1TF: " fmt 2038 2039 /* Default mitigation for L1TF-affected CPUs */ 2040 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; 2041 #if IS_ENABLED(CONFIG_KVM_INTEL) 2042 EXPORT_SYMBOL_GPL(l1tf_mitigation); 2043 #endif 2044 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 2045 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); 2046 2047 /* 2048 * These CPUs all support 44bits physical address space internally in the 2049 * cache but CPUID can report a smaller number of physical address bits. 2050 * 2051 * The L1TF mitigation uses the top most address bit for the inversion of 2052 * non present PTEs. When the installed memory reaches into the top most 2053 * address bit due to memory holes, which has been observed on machines 2054 * which report 36bits physical address bits and have 32G RAM installed, 2055 * then the mitigation range check in l1tf_select_mitigation() triggers. 2056 * This is a false positive because the mitigation is still possible due to 2057 * the fact that the cache uses 44bit internally. Use the cache bits 2058 * instead of the reported physical bits and adjust them on the affected 2059 * machines to 44bit if the reported bits are less than 44. 2060 */ 2061 static void override_cache_bits(struct cpuinfo_x86 *c) 2062 { 2063 if (c->x86 != 6) 2064 return; 2065 2066 switch (c->x86_model) { 2067 case INTEL_FAM6_NEHALEM: 2068 case INTEL_FAM6_WESTMERE: 2069 case INTEL_FAM6_SANDYBRIDGE: 2070 case INTEL_FAM6_IVYBRIDGE: 2071 case INTEL_FAM6_HASWELL: 2072 case INTEL_FAM6_HASWELL_L: 2073 case INTEL_FAM6_HASWELL_G: 2074 case INTEL_FAM6_BROADWELL: 2075 case INTEL_FAM6_BROADWELL_G: 2076 case INTEL_FAM6_SKYLAKE_L: 2077 case INTEL_FAM6_SKYLAKE: 2078 case INTEL_FAM6_KABYLAKE_L: 2079 case INTEL_FAM6_KABYLAKE: 2080 if (c->x86_cache_bits < 44) 2081 c->x86_cache_bits = 44; 2082 break; 2083 } 2084 } 2085 2086 static void __init l1tf_select_mitigation(void) 2087 { 2088 u64 half_pa; 2089 2090 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2091 return; 2092 2093 if (cpu_mitigations_off()) 2094 l1tf_mitigation = L1TF_MITIGATION_OFF; 2095 else if (cpu_mitigations_auto_nosmt()) 2096 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2097 2098 override_cache_bits(&boot_cpu_data); 2099 2100 switch (l1tf_mitigation) { 2101 case L1TF_MITIGATION_OFF: 2102 case L1TF_MITIGATION_FLUSH_NOWARN: 2103 case L1TF_MITIGATION_FLUSH: 2104 break; 2105 case L1TF_MITIGATION_FLUSH_NOSMT: 2106 case L1TF_MITIGATION_FULL: 2107 cpu_smt_disable(false); 2108 break; 2109 case L1TF_MITIGATION_FULL_FORCE: 2110 cpu_smt_disable(true); 2111 break; 2112 } 2113 2114 #if CONFIG_PGTABLE_LEVELS == 2 2115 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); 2116 return; 2117 #endif 2118 2119 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; 2120 if (l1tf_mitigation != L1TF_MITIGATION_OFF && 2121 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { 2122 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); 2123 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", 2124 half_pa); 2125 pr_info("However, doing so will make a part of your RAM unusable.\n"); 2126 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); 2127 return; 2128 } 2129 2130 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); 2131 } 2132 2133 static int __init l1tf_cmdline(char *str) 2134 { 2135 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2136 return 0; 2137 2138 if (!str) 2139 return -EINVAL; 2140 2141 if (!strcmp(str, "off")) 2142 l1tf_mitigation = L1TF_MITIGATION_OFF; 2143 else if (!strcmp(str, "flush,nowarn")) 2144 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; 2145 else if (!strcmp(str, "flush")) 2146 l1tf_mitigation = L1TF_MITIGATION_FLUSH; 2147 else if (!strcmp(str, "flush,nosmt")) 2148 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2149 else if (!strcmp(str, "full")) 2150 l1tf_mitigation = L1TF_MITIGATION_FULL; 2151 else if (!strcmp(str, "full,force")) 2152 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; 2153 2154 return 0; 2155 } 2156 early_param("l1tf", l1tf_cmdline); 2157 2158 #undef pr_fmt 2159 #define pr_fmt(fmt) fmt 2160 2161 #ifdef CONFIG_SYSFS 2162 2163 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" 2164 2165 #if IS_ENABLED(CONFIG_KVM_INTEL) 2166 static const char * const l1tf_vmx_states[] = { 2167 [VMENTER_L1D_FLUSH_AUTO] = "auto", 2168 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", 2169 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", 2170 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", 2171 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", 2172 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" 2173 }; 2174 2175 static ssize_t l1tf_show_state(char *buf) 2176 { 2177 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) 2178 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); 2179 2180 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || 2181 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && 2182 sched_smt_active())) { 2183 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, 2184 l1tf_vmx_states[l1tf_vmx_mitigation]); 2185 } 2186 2187 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, 2188 l1tf_vmx_states[l1tf_vmx_mitigation], 2189 sched_smt_active() ? "vulnerable" : "disabled"); 2190 } 2191 2192 static ssize_t itlb_multihit_show_state(char *buf) 2193 { 2194 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2195 !boot_cpu_has(X86_FEATURE_VMX)) 2196 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n"); 2197 else if (!(cr4_read_shadow() & X86_CR4_VMXE)) 2198 return sprintf(buf, "KVM: Mitigation: VMX disabled\n"); 2199 else if (itlb_multihit_kvm_mitigation) 2200 return sprintf(buf, "KVM: Mitigation: Split huge pages\n"); 2201 else 2202 return sprintf(buf, "KVM: Vulnerable\n"); 2203 } 2204 #else 2205 static ssize_t l1tf_show_state(char *buf) 2206 { 2207 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); 2208 } 2209 2210 static ssize_t itlb_multihit_show_state(char *buf) 2211 { 2212 return sprintf(buf, "Processor vulnerable\n"); 2213 } 2214 #endif 2215 2216 static ssize_t mds_show_state(char *buf) 2217 { 2218 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2219 return sprintf(buf, "%s; SMT Host state unknown\n", 2220 mds_strings[mds_mitigation]); 2221 } 2222 2223 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { 2224 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2225 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : 2226 sched_smt_active() ? "mitigated" : "disabled")); 2227 } 2228 2229 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2230 sched_smt_active() ? "vulnerable" : "disabled"); 2231 } 2232 2233 static ssize_t tsx_async_abort_show_state(char *buf) 2234 { 2235 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) || 2236 (taa_mitigation == TAA_MITIGATION_OFF)) 2237 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]); 2238 2239 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2240 return sprintf(buf, "%s; SMT Host state unknown\n", 2241 taa_strings[taa_mitigation]); 2242 } 2243 2244 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation], 2245 sched_smt_active() ? "vulnerable" : "disabled"); 2246 } 2247 2248 static ssize_t mmio_stale_data_show_state(char *buf) 2249 { 2250 if (mmio_mitigation == MMIO_MITIGATION_OFF) 2251 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]); 2252 2253 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2254 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2255 mmio_strings[mmio_mitigation]); 2256 } 2257 2258 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation], 2259 sched_smt_active() ? "vulnerable" : "disabled"); 2260 } 2261 2262 static char *stibp_state(void) 2263 { 2264 if (spectre_v2_in_ibrs_mode(spectre_v2_enabled)) 2265 return ""; 2266 2267 switch (spectre_v2_user_stibp) { 2268 case SPECTRE_V2_USER_NONE: 2269 return ", STIBP: disabled"; 2270 case SPECTRE_V2_USER_STRICT: 2271 return ", STIBP: forced"; 2272 case SPECTRE_V2_USER_STRICT_PREFERRED: 2273 return ", STIBP: always-on"; 2274 case SPECTRE_V2_USER_PRCTL: 2275 case SPECTRE_V2_USER_SECCOMP: 2276 if (static_key_enabled(&switch_to_cond_stibp)) 2277 return ", STIBP: conditional"; 2278 } 2279 return ""; 2280 } 2281 2282 static char *ibpb_state(void) 2283 { 2284 if (boot_cpu_has(X86_FEATURE_IBPB)) { 2285 if (static_key_enabled(&switch_mm_always_ibpb)) 2286 return ", IBPB: always-on"; 2287 if (static_key_enabled(&switch_mm_cond_ibpb)) 2288 return ", IBPB: conditional"; 2289 return ", IBPB: disabled"; 2290 } 2291 return ""; 2292 } 2293 2294 static ssize_t spectre_v2_show_state(char *buf) 2295 { 2296 if (spectre_v2_enabled == SPECTRE_V2_LFENCE) 2297 return sprintf(buf, "Vulnerable: LFENCE\n"); 2298 2299 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 2300 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n"); 2301 2302 if (sched_smt_active() && unprivileged_ebpf_enabled() && 2303 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 2304 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n"); 2305 2306 return sprintf(buf, "%s%s%s%s%s%s\n", 2307 spectre_v2_strings[spectre_v2_enabled], 2308 ibpb_state(), 2309 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", 2310 stibp_state(), 2311 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", 2312 spectre_v2_module_string()); 2313 } 2314 2315 static ssize_t srbds_show_state(char *buf) 2316 { 2317 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]); 2318 } 2319 2320 static ssize_t retbleed_show_state(char *buf) 2321 { 2322 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) { 2323 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 2324 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 2325 return sprintf(buf, "Vulnerable: untrained return thunk on non-Zen uarch\n"); 2326 2327 return sprintf(buf, "%s; SMT %s\n", 2328 retbleed_strings[retbleed_mitigation], 2329 !sched_smt_active() ? "disabled" : 2330 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 2331 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ? 2332 "enabled with STIBP protection" : "vulnerable"); 2333 } 2334 2335 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]); 2336 } 2337 2338 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, 2339 char *buf, unsigned int bug) 2340 { 2341 if (!boot_cpu_has_bug(bug)) 2342 return sprintf(buf, "Not affected\n"); 2343 2344 switch (bug) { 2345 case X86_BUG_CPU_MELTDOWN: 2346 if (boot_cpu_has(X86_FEATURE_PTI)) 2347 return sprintf(buf, "Mitigation: PTI\n"); 2348 2349 if (hypervisor_is_type(X86_HYPER_XEN_PV)) 2350 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); 2351 2352 break; 2353 2354 case X86_BUG_SPECTRE_V1: 2355 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); 2356 2357 case X86_BUG_SPECTRE_V2: 2358 return spectre_v2_show_state(buf); 2359 2360 case X86_BUG_SPEC_STORE_BYPASS: 2361 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); 2362 2363 case X86_BUG_L1TF: 2364 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) 2365 return l1tf_show_state(buf); 2366 break; 2367 2368 case X86_BUG_MDS: 2369 return mds_show_state(buf); 2370 2371 case X86_BUG_TAA: 2372 return tsx_async_abort_show_state(buf); 2373 2374 case X86_BUG_ITLB_MULTIHIT: 2375 return itlb_multihit_show_state(buf); 2376 2377 case X86_BUG_SRBDS: 2378 return srbds_show_state(buf); 2379 2380 case X86_BUG_MMIO_STALE_DATA: 2381 return mmio_stale_data_show_state(buf); 2382 2383 case X86_BUG_RETBLEED: 2384 return retbleed_show_state(buf); 2385 2386 default: 2387 break; 2388 } 2389 2390 return sprintf(buf, "Vulnerable\n"); 2391 } 2392 2393 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) 2394 { 2395 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); 2396 } 2397 2398 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) 2399 { 2400 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); 2401 } 2402 2403 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) 2404 { 2405 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); 2406 } 2407 2408 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) 2409 { 2410 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); 2411 } 2412 2413 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) 2414 { 2415 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); 2416 } 2417 2418 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) 2419 { 2420 return cpu_show_common(dev, attr, buf, X86_BUG_MDS); 2421 } 2422 2423 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) 2424 { 2425 return cpu_show_common(dev, attr, buf, X86_BUG_TAA); 2426 } 2427 2428 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) 2429 { 2430 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT); 2431 } 2432 2433 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) 2434 { 2435 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS); 2436 } 2437 2438 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf) 2439 { 2440 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); 2441 } 2442 2443 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf) 2444 { 2445 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED); 2446 } 2447 #endif 2448