1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Cyrix stuff, June 1998 by: 6 * - Rafael R. Reilova (moved everything from head.S), 7 * <rreilova@ececs.uc.edu> 8 * - Channing Corn (tests & fixes), 9 * - Andrew D. Balsa (code cleanup). 10 */ 11 #include <linux/init.h> 12 #include <linux/utsname.h> 13 #include <linux/cpu.h> 14 #include <linux/module.h> 15 #include <linux/nospec.h> 16 #include <linux/prctl.h> 17 #include <linux/sched/smt.h> 18 #include <linux/pgtable.h> 19 #include <linux/bpf.h> 20 21 #include <asm/spec-ctrl.h> 22 #include <asm/cmdline.h> 23 #include <asm/bugs.h> 24 #include <asm/processor.h> 25 #include <asm/processor-flags.h> 26 #include <asm/fpu/api.h> 27 #include <asm/msr.h> 28 #include <asm/vmx.h> 29 #include <asm/paravirt.h> 30 #include <asm/alternative.h> 31 #include <asm/set_memory.h> 32 #include <asm/intel-family.h> 33 #include <asm/e820/api.h> 34 #include <asm/hypervisor.h> 35 #include <asm/tlbflush.h> 36 37 #include "cpu.h" 38 39 static void __init spectre_v1_select_mitigation(void); 40 static void __init spectre_v2_select_mitigation(void); 41 static void __init retbleed_select_mitigation(void); 42 static void __init spectre_v2_user_select_mitigation(void); 43 static void __init ssb_select_mitigation(void); 44 static void __init l1tf_select_mitigation(void); 45 static void __init mds_select_mitigation(void); 46 static void __init md_clear_update_mitigation(void); 47 static void __init md_clear_select_mitigation(void); 48 static void __init taa_select_mitigation(void); 49 static void __init mmio_select_mitigation(void); 50 static void __init srbds_select_mitigation(void); 51 static void __init l1d_flush_select_mitigation(void); 52 53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */ 54 u64 x86_spec_ctrl_base; 55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); 56 57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */ 58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current); 59 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current); 60 61 static DEFINE_MUTEX(spec_ctrl_mutex); 62 63 /* 64 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ 65 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). 66 */ 67 void write_spec_ctrl_current(u64 val, bool force) 68 { 69 if (this_cpu_read(x86_spec_ctrl_current) == val) 70 return; 71 72 this_cpu_write(x86_spec_ctrl_current, val); 73 74 /* 75 * When KERNEL_IBRS this MSR is written on return-to-user, unless 76 * forced the update can be delayed until that time. 77 */ 78 if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 79 wrmsrl(MSR_IA32_SPEC_CTRL, val); 80 } 81 82 u64 spec_ctrl_current(void) 83 { 84 return this_cpu_read(x86_spec_ctrl_current); 85 } 86 EXPORT_SYMBOL_GPL(spec_ctrl_current); 87 88 /* 89 * AMD specific MSR info for Speculative Store Bypass control. 90 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). 91 */ 92 u64 __ro_after_init x86_amd_ls_cfg_base; 93 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; 94 95 /* Control conditional STIBP in switch_to() */ 96 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); 97 /* Control conditional IBPB in switch_mm() */ 98 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 99 /* Control unconditional IBPB in switch_mm() */ 100 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 101 102 /* Control MDS CPU buffer clear before returning to user space */ 103 DEFINE_STATIC_KEY_FALSE(mds_user_clear); 104 EXPORT_SYMBOL_GPL(mds_user_clear); 105 /* Control MDS CPU buffer clear before idling (halt, mwait) */ 106 DEFINE_STATIC_KEY_FALSE(mds_idle_clear); 107 EXPORT_SYMBOL_GPL(mds_idle_clear); 108 109 /* 110 * Controls whether l1d flush based mitigations are enabled, 111 * based on hw features and admin setting via boot parameter 112 * defaults to false 113 */ 114 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 115 116 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */ 117 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); 118 EXPORT_SYMBOL_GPL(mmio_stale_data_clear); 119 120 void __init check_bugs(void) 121 { 122 identify_boot_cpu(); 123 124 /* 125 * identify_boot_cpu() initialized SMT support information, let the 126 * core code know. 127 */ 128 cpu_smt_check_topology(); 129 130 if (!IS_ENABLED(CONFIG_SMP)) { 131 pr_info("CPU: "); 132 print_cpu_info(&boot_cpu_data); 133 } 134 135 /* 136 * Read the SPEC_CTRL MSR to account for reserved bits which may 137 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD 138 * init code as it is not enumerated and depends on the family. 139 */ 140 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 141 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 142 143 /* Select the proper CPU mitigations before patching alternatives: */ 144 spectre_v1_select_mitigation(); 145 spectre_v2_select_mitigation(); 146 /* 147 * retbleed_select_mitigation() relies on the state set by 148 * spectre_v2_select_mitigation(); specifically it wants to know about 149 * spectre_v2=ibrs. 150 */ 151 retbleed_select_mitigation(); 152 /* 153 * spectre_v2_user_select_mitigation() relies on the state set by 154 * retbleed_select_mitigation(); specifically the STIBP selection is 155 * forced for UNRET. 156 */ 157 spectre_v2_user_select_mitigation(); 158 ssb_select_mitigation(); 159 l1tf_select_mitigation(); 160 md_clear_select_mitigation(); 161 srbds_select_mitigation(); 162 l1d_flush_select_mitigation(); 163 164 arch_smt_update(); 165 166 #ifdef CONFIG_X86_32 167 /* 168 * Check whether we are able to run this kernel safely on SMP. 169 * 170 * - i386 is no longer supported. 171 * - In order to run on anything without a TSC, we need to be 172 * compiled for a i486. 173 */ 174 if (boot_cpu_data.x86 < 4) 175 panic("Kernel requires i486+ for 'invlpg' and other features"); 176 177 init_utsname()->machine[1] = 178 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 179 alternative_instructions(); 180 181 fpu__init_check_bugs(); 182 #else /* CONFIG_X86_64 */ 183 alternative_instructions(); 184 185 /* 186 * Make sure the first 2MB area is not mapped by huge pages 187 * There are typically fixed size MTRRs in there and overlapping 188 * MTRRs into large pages causes slow downs. 189 * 190 * Right now we don't do that with gbpages because there seems 191 * very little benefit for that case. 192 */ 193 if (!direct_gbpages) 194 set_memory_4k((unsigned long)__va(0), 1); 195 #endif 196 } 197 198 /* 199 * NOTE: This function is *only* called for SVM. VMX spec_ctrl handling is 200 * done in vmenter.S. 201 */ 202 void 203 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) 204 { 205 u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current(); 206 struct thread_info *ti = current_thread_info(); 207 208 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { 209 if (hostval != guestval) { 210 msrval = setguest ? guestval : hostval; 211 wrmsrl(MSR_IA32_SPEC_CTRL, msrval); 212 } 213 } 214 215 /* 216 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update 217 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. 218 */ 219 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 220 !static_cpu_has(X86_FEATURE_VIRT_SSBD)) 221 return; 222 223 /* 224 * If the host has SSBD mitigation enabled, force it in the host's 225 * virtual MSR value. If its not permanently enabled, evaluate 226 * current's TIF_SSBD thread flag. 227 */ 228 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) 229 hostval = SPEC_CTRL_SSBD; 230 else 231 hostval = ssbd_tif_to_spec_ctrl(ti->flags); 232 233 /* Sanitize the guest value */ 234 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; 235 236 if (hostval != guestval) { 237 unsigned long tif; 238 239 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : 240 ssbd_spec_ctrl_to_tif(hostval); 241 242 speculation_ctrl_update(tif); 243 } 244 } 245 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); 246 247 static void x86_amd_ssb_disable(void) 248 { 249 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; 250 251 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) 252 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); 253 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) 254 wrmsrl(MSR_AMD64_LS_CFG, msrval); 255 } 256 257 #undef pr_fmt 258 #define pr_fmt(fmt) "MDS: " fmt 259 260 /* Default mitigation for MDS-affected CPUs */ 261 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; 262 static bool mds_nosmt __ro_after_init = false; 263 264 static const char * const mds_strings[] = { 265 [MDS_MITIGATION_OFF] = "Vulnerable", 266 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", 267 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", 268 }; 269 270 static void __init mds_select_mitigation(void) 271 { 272 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { 273 mds_mitigation = MDS_MITIGATION_OFF; 274 return; 275 } 276 277 if (mds_mitigation == MDS_MITIGATION_FULL) { 278 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) 279 mds_mitigation = MDS_MITIGATION_VMWERV; 280 281 static_branch_enable(&mds_user_clear); 282 283 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && 284 (mds_nosmt || cpu_mitigations_auto_nosmt())) 285 cpu_smt_disable(false); 286 } 287 } 288 289 static int __init mds_cmdline(char *str) 290 { 291 if (!boot_cpu_has_bug(X86_BUG_MDS)) 292 return 0; 293 294 if (!str) 295 return -EINVAL; 296 297 if (!strcmp(str, "off")) 298 mds_mitigation = MDS_MITIGATION_OFF; 299 else if (!strcmp(str, "full")) 300 mds_mitigation = MDS_MITIGATION_FULL; 301 else if (!strcmp(str, "full,nosmt")) { 302 mds_mitigation = MDS_MITIGATION_FULL; 303 mds_nosmt = true; 304 } 305 306 return 0; 307 } 308 early_param("mds", mds_cmdline); 309 310 #undef pr_fmt 311 #define pr_fmt(fmt) "TAA: " fmt 312 313 enum taa_mitigations { 314 TAA_MITIGATION_OFF, 315 TAA_MITIGATION_UCODE_NEEDED, 316 TAA_MITIGATION_VERW, 317 TAA_MITIGATION_TSX_DISABLED, 318 }; 319 320 /* Default mitigation for TAA-affected CPUs */ 321 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW; 322 static bool taa_nosmt __ro_after_init; 323 324 static const char * const taa_strings[] = { 325 [TAA_MITIGATION_OFF] = "Vulnerable", 326 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 327 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 328 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled", 329 }; 330 331 static void __init taa_select_mitigation(void) 332 { 333 u64 ia32_cap; 334 335 if (!boot_cpu_has_bug(X86_BUG_TAA)) { 336 taa_mitigation = TAA_MITIGATION_OFF; 337 return; 338 } 339 340 /* TSX previously disabled by tsx=off */ 341 if (!boot_cpu_has(X86_FEATURE_RTM)) { 342 taa_mitigation = TAA_MITIGATION_TSX_DISABLED; 343 return; 344 } 345 346 if (cpu_mitigations_off()) { 347 taa_mitigation = TAA_MITIGATION_OFF; 348 return; 349 } 350 351 /* 352 * TAA mitigation via VERW is turned off if both 353 * tsx_async_abort=off and mds=off are specified. 354 */ 355 if (taa_mitigation == TAA_MITIGATION_OFF && 356 mds_mitigation == MDS_MITIGATION_OFF) 357 return; 358 359 if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) 360 taa_mitigation = TAA_MITIGATION_VERW; 361 else 362 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 363 364 /* 365 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1. 366 * A microcode update fixes this behavior to clear CPU buffers. It also 367 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the 368 * ARCH_CAP_TSX_CTRL_MSR bit. 369 * 370 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode 371 * update is required. 372 */ 373 ia32_cap = x86_read_arch_cap_msr(); 374 if ( (ia32_cap & ARCH_CAP_MDS_NO) && 375 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR)) 376 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; 377 378 /* 379 * TSX is enabled, select alternate mitigation for TAA which is 380 * the same as MDS. Enable MDS static branch to clear CPU buffers. 381 * 382 * For guests that can't determine whether the correct microcode is 383 * present on host, enable the mitigation for UCODE_NEEDED as well. 384 */ 385 static_branch_enable(&mds_user_clear); 386 387 if (taa_nosmt || cpu_mitigations_auto_nosmt()) 388 cpu_smt_disable(false); 389 } 390 391 static int __init tsx_async_abort_parse_cmdline(char *str) 392 { 393 if (!boot_cpu_has_bug(X86_BUG_TAA)) 394 return 0; 395 396 if (!str) 397 return -EINVAL; 398 399 if (!strcmp(str, "off")) { 400 taa_mitigation = TAA_MITIGATION_OFF; 401 } else if (!strcmp(str, "full")) { 402 taa_mitigation = TAA_MITIGATION_VERW; 403 } else if (!strcmp(str, "full,nosmt")) { 404 taa_mitigation = TAA_MITIGATION_VERW; 405 taa_nosmt = true; 406 } 407 408 return 0; 409 } 410 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline); 411 412 #undef pr_fmt 413 #define pr_fmt(fmt) "MMIO Stale Data: " fmt 414 415 enum mmio_mitigations { 416 MMIO_MITIGATION_OFF, 417 MMIO_MITIGATION_UCODE_NEEDED, 418 MMIO_MITIGATION_VERW, 419 }; 420 421 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ 422 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW; 423 static bool mmio_nosmt __ro_after_init = false; 424 425 static const char * const mmio_strings[] = { 426 [MMIO_MITIGATION_OFF] = "Vulnerable", 427 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", 428 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", 429 }; 430 431 static void __init mmio_select_mitigation(void) 432 { 433 u64 ia32_cap; 434 435 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) || 436 cpu_mitigations_off()) { 437 mmio_mitigation = MMIO_MITIGATION_OFF; 438 return; 439 } 440 441 if (mmio_mitigation == MMIO_MITIGATION_OFF) 442 return; 443 444 ia32_cap = x86_read_arch_cap_msr(); 445 446 /* 447 * Enable CPU buffer clear mitigation for host and VMM, if also affected 448 * by MDS or TAA. Otherwise, enable mitigation for VMM only. 449 */ 450 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) && 451 boot_cpu_has(X86_FEATURE_RTM))) 452 static_branch_enable(&mds_user_clear); 453 else 454 static_branch_enable(&mmio_stale_data_clear); 455 456 /* 457 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can 458 * be propagated to uncore buffers, clearing the Fill buffers on idle 459 * is required irrespective of SMT state. 460 */ 461 if (!(ia32_cap & ARCH_CAP_FBSDP_NO)) 462 static_branch_enable(&mds_idle_clear); 463 464 /* 465 * Check if the system has the right microcode. 466 * 467 * CPU Fill buffer clear mitigation is enumerated by either an explicit 468 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS 469 * affected systems. 470 */ 471 if ((ia32_cap & ARCH_CAP_FB_CLEAR) || 472 (boot_cpu_has(X86_FEATURE_MD_CLEAR) && 473 boot_cpu_has(X86_FEATURE_FLUSH_L1D) && 474 !(ia32_cap & ARCH_CAP_MDS_NO))) 475 mmio_mitigation = MMIO_MITIGATION_VERW; 476 else 477 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED; 478 479 if (mmio_nosmt || cpu_mitigations_auto_nosmt()) 480 cpu_smt_disable(false); 481 } 482 483 static int __init mmio_stale_data_parse_cmdline(char *str) 484 { 485 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 486 return 0; 487 488 if (!str) 489 return -EINVAL; 490 491 if (!strcmp(str, "off")) { 492 mmio_mitigation = MMIO_MITIGATION_OFF; 493 } else if (!strcmp(str, "full")) { 494 mmio_mitigation = MMIO_MITIGATION_VERW; 495 } else if (!strcmp(str, "full,nosmt")) { 496 mmio_mitigation = MMIO_MITIGATION_VERW; 497 mmio_nosmt = true; 498 } 499 500 return 0; 501 } 502 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline); 503 504 #undef pr_fmt 505 #define pr_fmt(fmt) "" fmt 506 507 static void __init md_clear_update_mitigation(void) 508 { 509 if (cpu_mitigations_off()) 510 return; 511 512 if (!static_key_enabled(&mds_user_clear)) 513 goto out; 514 515 /* 516 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data 517 * mitigation, if necessary. 518 */ 519 if (mds_mitigation == MDS_MITIGATION_OFF && 520 boot_cpu_has_bug(X86_BUG_MDS)) { 521 mds_mitigation = MDS_MITIGATION_FULL; 522 mds_select_mitigation(); 523 } 524 if (taa_mitigation == TAA_MITIGATION_OFF && 525 boot_cpu_has_bug(X86_BUG_TAA)) { 526 taa_mitigation = TAA_MITIGATION_VERW; 527 taa_select_mitigation(); 528 } 529 if (mmio_mitigation == MMIO_MITIGATION_OFF && 530 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) { 531 mmio_mitigation = MMIO_MITIGATION_VERW; 532 mmio_select_mitigation(); 533 } 534 out: 535 if (boot_cpu_has_bug(X86_BUG_MDS)) 536 pr_info("MDS: %s\n", mds_strings[mds_mitigation]); 537 if (boot_cpu_has_bug(X86_BUG_TAA)) 538 pr_info("TAA: %s\n", taa_strings[taa_mitigation]); 539 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 540 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); 541 } 542 543 static void __init md_clear_select_mitigation(void) 544 { 545 mds_select_mitigation(); 546 taa_select_mitigation(); 547 mmio_select_mitigation(); 548 549 /* 550 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update 551 * and print their mitigation after MDS, TAA and MMIO Stale Data 552 * mitigation selection is done. 553 */ 554 md_clear_update_mitigation(); 555 } 556 557 #undef pr_fmt 558 #define pr_fmt(fmt) "SRBDS: " fmt 559 560 enum srbds_mitigations { 561 SRBDS_MITIGATION_OFF, 562 SRBDS_MITIGATION_UCODE_NEEDED, 563 SRBDS_MITIGATION_FULL, 564 SRBDS_MITIGATION_TSX_OFF, 565 SRBDS_MITIGATION_HYPERVISOR, 566 }; 567 568 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL; 569 570 static const char * const srbds_strings[] = { 571 [SRBDS_MITIGATION_OFF] = "Vulnerable", 572 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", 573 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode", 574 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled", 575 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", 576 }; 577 578 static bool srbds_off; 579 580 void update_srbds_msr(void) 581 { 582 u64 mcu_ctrl; 583 584 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 585 return; 586 587 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 588 return; 589 590 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) 591 return; 592 593 /* 594 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX 595 * being disabled and it hasn't received the SRBDS MSR microcode. 596 */ 597 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 598 return; 599 600 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 601 602 switch (srbds_mitigation) { 603 case SRBDS_MITIGATION_OFF: 604 case SRBDS_MITIGATION_TSX_OFF: 605 mcu_ctrl |= RNGDS_MITG_DIS; 606 break; 607 case SRBDS_MITIGATION_FULL: 608 mcu_ctrl &= ~RNGDS_MITG_DIS; 609 break; 610 default: 611 break; 612 } 613 614 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 615 } 616 617 static void __init srbds_select_mitigation(void) 618 { 619 u64 ia32_cap; 620 621 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 622 return; 623 624 /* 625 * Check to see if this is one of the MDS_NO systems supporting TSX that 626 * are only exposed to SRBDS when TSX is enabled or when CPU is affected 627 * by Processor MMIO Stale Data vulnerability. 628 */ 629 ia32_cap = x86_read_arch_cap_msr(); 630 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) && 631 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) 632 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF; 633 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 634 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR; 635 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 636 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED; 637 else if (cpu_mitigations_off() || srbds_off) 638 srbds_mitigation = SRBDS_MITIGATION_OFF; 639 640 update_srbds_msr(); 641 pr_info("%s\n", srbds_strings[srbds_mitigation]); 642 } 643 644 static int __init srbds_parse_cmdline(char *str) 645 { 646 if (!str) 647 return -EINVAL; 648 649 if (!boot_cpu_has_bug(X86_BUG_SRBDS)) 650 return 0; 651 652 srbds_off = !strcmp(str, "off"); 653 return 0; 654 } 655 early_param("srbds", srbds_parse_cmdline); 656 657 #undef pr_fmt 658 #define pr_fmt(fmt) "L1D Flush : " fmt 659 660 enum l1d_flush_mitigations { 661 L1D_FLUSH_OFF = 0, 662 L1D_FLUSH_ON, 663 }; 664 665 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF; 666 667 static void __init l1d_flush_select_mitigation(void) 668 { 669 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) 670 return; 671 672 static_branch_enable(&switch_mm_cond_l1d_flush); 673 pr_info("Conditional flush on switch_mm() enabled\n"); 674 } 675 676 static int __init l1d_flush_parse_cmdline(char *str) 677 { 678 if (!strcmp(str, "on")) 679 l1d_flush_mitigation = L1D_FLUSH_ON; 680 681 return 0; 682 } 683 early_param("l1d_flush", l1d_flush_parse_cmdline); 684 685 #undef pr_fmt 686 #define pr_fmt(fmt) "Spectre V1 : " fmt 687 688 enum spectre_v1_mitigation { 689 SPECTRE_V1_MITIGATION_NONE, 690 SPECTRE_V1_MITIGATION_AUTO, 691 }; 692 693 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = 694 SPECTRE_V1_MITIGATION_AUTO; 695 696 static const char * const spectre_v1_strings[] = { 697 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", 698 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", 699 }; 700 701 /* 702 * Does SMAP provide full mitigation against speculative kernel access to 703 * userspace? 704 */ 705 static bool smap_works_speculatively(void) 706 { 707 if (!boot_cpu_has(X86_FEATURE_SMAP)) 708 return false; 709 710 /* 711 * On CPUs which are vulnerable to Meltdown, SMAP does not 712 * prevent speculative access to user data in the L1 cache. 713 * Consider SMAP to be non-functional as a mitigation on these 714 * CPUs. 715 */ 716 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) 717 return false; 718 719 return true; 720 } 721 722 static void __init spectre_v1_select_mitigation(void) 723 { 724 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { 725 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 726 return; 727 } 728 729 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { 730 /* 731 * With Spectre v1, a user can speculatively control either 732 * path of a conditional swapgs with a user-controlled GS 733 * value. The mitigation is to add lfences to both code paths. 734 * 735 * If FSGSBASE is enabled, the user can put a kernel address in 736 * GS, in which case SMAP provides no protection. 737 * 738 * If FSGSBASE is disabled, the user can only put a user space 739 * address in GS. That makes an attack harder, but still 740 * possible if there's no SMAP protection. 741 */ 742 if (boot_cpu_has(X86_FEATURE_FSGSBASE) || 743 !smap_works_speculatively()) { 744 /* 745 * Mitigation can be provided from SWAPGS itself or 746 * PTI as the CR3 write in the Meltdown mitigation 747 * is serializing. 748 * 749 * If neither is there, mitigate with an LFENCE to 750 * stop speculation through swapgs. 751 */ 752 if (boot_cpu_has_bug(X86_BUG_SWAPGS) && 753 !boot_cpu_has(X86_FEATURE_PTI)) 754 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); 755 756 /* 757 * Enable lfences in the kernel entry (non-swapgs) 758 * paths, to prevent user entry from speculatively 759 * skipping swapgs. 760 */ 761 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); 762 } 763 } 764 765 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); 766 } 767 768 static int __init nospectre_v1_cmdline(char *str) 769 { 770 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; 771 return 0; 772 } 773 early_param("nospectre_v1", nospectre_v1_cmdline); 774 775 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = 776 SPECTRE_V2_NONE; 777 778 #undef pr_fmt 779 #define pr_fmt(fmt) "RETBleed: " fmt 780 781 enum retbleed_mitigation { 782 RETBLEED_MITIGATION_NONE, 783 RETBLEED_MITIGATION_UNRET, 784 RETBLEED_MITIGATION_IBPB, 785 RETBLEED_MITIGATION_IBRS, 786 RETBLEED_MITIGATION_EIBRS, 787 }; 788 789 enum retbleed_mitigation_cmd { 790 RETBLEED_CMD_OFF, 791 RETBLEED_CMD_AUTO, 792 RETBLEED_CMD_UNRET, 793 RETBLEED_CMD_IBPB, 794 }; 795 796 static const char * const retbleed_strings[] = { 797 [RETBLEED_MITIGATION_NONE] = "Vulnerable", 798 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk", 799 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB", 800 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS", 801 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS", 802 }; 803 804 static enum retbleed_mitigation retbleed_mitigation __ro_after_init = 805 RETBLEED_MITIGATION_NONE; 806 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init = 807 RETBLEED_CMD_AUTO; 808 809 static int __ro_after_init retbleed_nosmt = false; 810 811 static int __init retbleed_parse_cmdline(char *str) 812 { 813 if (!str) 814 return -EINVAL; 815 816 while (str) { 817 char *next = strchr(str, ','); 818 if (next) { 819 *next = 0; 820 next++; 821 } 822 823 if (!strcmp(str, "off")) { 824 retbleed_cmd = RETBLEED_CMD_OFF; 825 } else if (!strcmp(str, "auto")) { 826 retbleed_cmd = RETBLEED_CMD_AUTO; 827 } else if (!strcmp(str, "unret")) { 828 retbleed_cmd = RETBLEED_CMD_UNRET; 829 } else if (!strcmp(str, "ibpb")) { 830 retbleed_cmd = RETBLEED_CMD_IBPB; 831 } else if (!strcmp(str, "nosmt")) { 832 retbleed_nosmt = true; 833 } else { 834 pr_err("Ignoring unknown retbleed option (%s).", str); 835 } 836 837 str = next; 838 } 839 840 return 0; 841 } 842 early_param("retbleed", retbleed_parse_cmdline); 843 844 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n" 845 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n" 846 847 static void __init retbleed_select_mitigation(void) 848 { 849 bool mitigate_smt = false; 850 851 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off()) 852 return; 853 854 switch (retbleed_cmd) { 855 case RETBLEED_CMD_OFF: 856 return; 857 858 case RETBLEED_CMD_UNRET: 859 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) { 860 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 861 } else { 862 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n"); 863 goto do_cmd_auto; 864 } 865 break; 866 867 case RETBLEED_CMD_IBPB: 868 if (!boot_cpu_has(X86_FEATURE_IBPB)) { 869 pr_err("WARNING: CPU does not support IBPB.\n"); 870 goto do_cmd_auto; 871 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) { 872 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 873 } else { 874 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n"); 875 goto do_cmd_auto; 876 } 877 break; 878 879 do_cmd_auto: 880 case RETBLEED_CMD_AUTO: 881 default: 882 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 883 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { 884 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) 885 retbleed_mitigation = RETBLEED_MITIGATION_UNRET; 886 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB)) 887 retbleed_mitigation = RETBLEED_MITIGATION_IBPB; 888 } 889 890 /* 891 * The Intel mitigation (IBRS or eIBRS) was already selected in 892 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will 893 * be set accordingly below. 894 */ 895 896 break; 897 } 898 899 switch (retbleed_mitigation) { 900 case RETBLEED_MITIGATION_UNRET: 901 setup_force_cpu_cap(X86_FEATURE_RETHUNK); 902 setup_force_cpu_cap(X86_FEATURE_UNRET); 903 904 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 905 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 906 pr_err(RETBLEED_UNTRAIN_MSG); 907 908 mitigate_smt = true; 909 break; 910 911 case RETBLEED_MITIGATION_IBPB: 912 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); 913 mitigate_smt = true; 914 break; 915 916 default: 917 break; 918 } 919 920 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) && 921 (retbleed_nosmt || cpu_mitigations_auto_nosmt())) 922 cpu_smt_disable(false); 923 924 /* 925 * Let IBRS trump all on Intel without affecting the effects of the 926 * retbleed= cmdline option. 927 */ 928 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 929 switch (spectre_v2_enabled) { 930 case SPECTRE_V2_IBRS: 931 retbleed_mitigation = RETBLEED_MITIGATION_IBRS; 932 break; 933 case SPECTRE_V2_EIBRS: 934 case SPECTRE_V2_EIBRS_RETPOLINE: 935 case SPECTRE_V2_EIBRS_LFENCE: 936 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS; 937 break; 938 default: 939 pr_err(RETBLEED_INTEL_MSG); 940 } 941 } 942 943 pr_info("%s\n", retbleed_strings[retbleed_mitigation]); 944 } 945 946 #undef pr_fmt 947 #define pr_fmt(fmt) "Spectre V2 : " fmt 948 949 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init = 950 SPECTRE_V2_USER_NONE; 951 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init = 952 SPECTRE_V2_USER_NONE; 953 954 #ifdef CONFIG_RETPOLINE 955 static bool spectre_v2_bad_module; 956 957 bool retpoline_module_ok(bool has_retpoline) 958 { 959 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) 960 return true; 961 962 pr_err("System may be vulnerable to spectre v2\n"); 963 spectre_v2_bad_module = true; 964 return false; 965 } 966 967 static inline const char *spectre_v2_module_string(void) 968 { 969 return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; 970 } 971 #else 972 static inline const char *spectre_v2_module_string(void) { return ""; } 973 #endif 974 975 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n" 976 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n" 977 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n" 978 979 #ifdef CONFIG_BPF_SYSCALL 980 void unpriv_ebpf_notify(int new_state) 981 { 982 if (new_state) 983 return; 984 985 /* Unprivileged eBPF is enabled */ 986 987 switch (spectre_v2_enabled) { 988 case SPECTRE_V2_EIBRS: 989 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 990 break; 991 case SPECTRE_V2_EIBRS_LFENCE: 992 if (sched_smt_active()) 993 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 994 break; 995 default: 996 break; 997 } 998 } 999 #endif 1000 1001 static inline bool match_option(const char *arg, int arglen, const char *opt) 1002 { 1003 int len = strlen(opt); 1004 1005 return len == arglen && !strncmp(arg, opt, len); 1006 } 1007 1008 /* The kernel command line selection for spectre v2 */ 1009 enum spectre_v2_mitigation_cmd { 1010 SPECTRE_V2_CMD_NONE, 1011 SPECTRE_V2_CMD_AUTO, 1012 SPECTRE_V2_CMD_FORCE, 1013 SPECTRE_V2_CMD_RETPOLINE, 1014 SPECTRE_V2_CMD_RETPOLINE_GENERIC, 1015 SPECTRE_V2_CMD_RETPOLINE_LFENCE, 1016 SPECTRE_V2_CMD_EIBRS, 1017 SPECTRE_V2_CMD_EIBRS_RETPOLINE, 1018 SPECTRE_V2_CMD_EIBRS_LFENCE, 1019 SPECTRE_V2_CMD_IBRS, 1020 }; 1021 1022 enum spectre_v2_user_cmd { 1023 SPECTRE_V2_USER_CMD_NONE, 1024 SPECTRE_V2_USER_CMD_AUTO, 1025 SPECTRE_V2_USER_CMD_FORCE, 1026 SPECTRE_V2_USER_CMD_PRCTL, 1027 SPECTRE_V2_USER_CMD_PRCTL_IBPB, 1028 SPECTRE_V2_USER_CMD_SECCOMP, 1029 SPECTRE_V2_USER_CMD_SECCOMP_IBPB, 1030 }; 1031 1032 static const char * const spectre_v2_user_strings[] = { 1033 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", 1034 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", 1035 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", 1036 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", 1037 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", 1038 }; 1039 1040 static const struct { 1041 const char *option; 1042 enum spectre_v2_user_cmd cmd; 1043 bool secure; 1044 } v2_user_options[] __initconst = { 1045 { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, 1046 { "off", SPECTRE_V2_USER_CMD_NONE, false }, 1047 { "on", SPECTRE_V2_USER_CMD_FORCE, true }, 1048 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, 1049 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, 1050 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, 1051 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, 1052 }; 1053 1054 static void __init spec_v2_user_print_cond(const char *reason, bool secure) 1055 { 1056 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1057 pr_info("spectre_v2_user=%s forced on command line.\n", reason); 1058 } 1059 1060 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd; 1061 1062 static enum spectre_v2_user_cmd __init 1063 spectre_v2_parse_user_cmdline(void) 1064 { 1065 char arg[20]; 1066 int ret, i; 1067 1068 switch (spectre_v2_cmd) { 1069 case SPECTRE_V2_CMD_NONE: 1070 return SPECTRE_V2_USER_CMD_NONE; 1071 case SPECTRE_V2_CMD_FORCE: 1072 return SPECTRE_V2_USER_CMD_FORCE; 1073 default: 1074 break; 1075 } 1076 1077 ret = cmdline_find_option(boot_command_line, "spectre_v2_user", 1078 arg, sizeof(arg)); 1079 if (ret < 0) 1080 return SPECTRE_V2_USER_CMD_AUTO; 1081 1082 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { 1083 if (match_option(arg, ret, v2_user_options[i].option)) { 1084 spec_v2_user_print_cond(v2_user_options[i].option, 1085 v2_user_options[i].secure); 1086 return v2_user_options[i].cmd; 1087 } 1088 } 1089 1090 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); 1091 return SPECTRE_V2_USER_CMD_AUTO; 1092 } 1093 1094 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) 1095 { 1096 return mode == SPECTRE_V2_IBRS || 1097 mode == SPECTRE_V2_EIBRS || 1098 mode == SPECTRE_V2_EIBRS_RETPOLINE || 1099 mode == SPECTRE_V2_EIBRS_LFENCE; 1100 } 1101 1102 static void __init 1103 spectre_v2_user_select_mitigation(void) 1104 { 1105 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; 1106 bool smt_possible = IS_ENABLED(CONFIG_SMP); 1107 enum spectre_v2_user_cmd cmd; 1108 1109 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) 1110 return; 1111 1112 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || 1113 cpu_smt_control == CPU_SMT_NOT_SUPPORTED) 1114 smt_possible = false; 1115 1116 cmd = spectre_v2_parse_user_cmdline(); 1117 switch (cmd) { 1118 case SPECTRE_V2_USER_CMD_NONE: 1119 goto set_mode; 1120 case SPECTRE_V2_USER_CMD_FORCE: 1121 mode = SPECTRE_V2_USER_STRICT; 1122 break; 1123 case SPECTRE_V2_USER_CMD_AUTO: 1124 case SPECTRE_V2_USER_CMD_PRCTL: 1125 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1126 mode = SPECTRE_V2_USER_PRCTL; 1127 break; 1128 case SPECTRE_V2_USER_CMD_SECCOMP: 1129 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1130 if (IS_ENABLED(CONFIG_SECCOMP)) 1131 mode = SPECTRE_V2_USER_SECCOMP; 1132 else 1133 mode = SPECTRE_V2_USER_PRCTL; 1134 break; 1135 } 1136 1137 /* Initialize Indirect Branch Prediction Barrier */ 1138 if (boot_cpu_has(X86_FEATURE_IBPB)) { 1139 setup_force_cpu_cap(X86_FEATURE_USE_IBPB); 1140 1141 spectre_v2_user_ibpb = mode; 1142 switch (cmd) { 1143 case SPECTRE_V2_USER_CMD_FORCE: 1144 case SPECTRE_V2_USER_CMD_PRCTL_IBPB: 1145 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: 1146 static_branch_enable(&switch_mm_always_ibpb); 1147 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT; 1148 break; 1149 case SPECTRE_V2_USER_CMD_PRCTL: 1150 case SPECTRE_V2_USER_CMD_AUTO: 1151 case SPECTRE_V2_USER_CMD_SECCOMP: 1152 static_branch_enable(&switch_mm_cond_ibpb); 1153 break; 1154 default: 1155 break; 1156 } 1157 1158 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", 1159 static_key_enabled(&switch_mm_always_ibpb) ? 1160 "always-on" : "conditional"); 1161 } 1162 1163 /* 1164 * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible, 1165 * STIBP is not required. 1166 */ 1167 if (!boot_cpu_has(X86_FEATURE_STIBP) || 1168 !smt_possible || 1169 spectre_v2_in_ibrs_mode(spectre_v2_enabled)) 1170 return; 1171 1172 /* 1173 * At this point, an STIBP mode other than "off" has been set. 1174 * If STIBP support is not being forced, check if STIBP always-on 1175 * is preferred. 1176 */ 1177 if (mode != SPECTRE_V2_USER_STRICT && 1178 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) 1179 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1180 1181 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) { 1182 if (mode != SPECTRE_V2_USER_STRICT && 1183 mode != SPECTRE_V2_USER_STRICT_PREFERRED) 1184 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n"); 1185 mode = SPECTRE_V2_USER_STRICT_PREFERRED; 1186 } 1187 1188 spectre_v2_user_stibp = mode; 1189 1190 set_mode: 1191 pr_info("%s\n", spectre_v2_user_strings[mode]); 1192 } 1193 1194 static const char * const spectre_v2_strings[] = { 1195 [SPECTRE_V2_NONE] = "Vulnerable", 1196 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", 1197 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", 1198 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS", 1199 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE", 1200 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines", 1201 [SPECTRE_V2_IBRS] = "Mitigation: IBRS", 1202 }; 1203 1204 static const struct { 1205 const char *option; 1206 enum spectre_v2_mitigation_cmd cmd; 1207 bool secure; 1208 } mitigation_options[] __initconst = { 1209 { "off", SPECTRE_V2_CMD_NONE, false }, 1210 { "on", SPECTRE_V2_CMD_FORCE, true }, 1211 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, 1212 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1213 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false }, 1214 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, 1215 { "eibrs", SPECTRE_V2_CMD_EIBRS, false }, 1216 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false }, 1217 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false }, 1218 { "auto", SPECTRE_V2_CMD_AUTO, false }, 1219 { "ibrs", SPECTRE_V2_CMD_IBRS, false }, 1220 }; 1221 1222 static void __init spec_v2_print_cond(const char *reason, bool secure) 1223 { 1224 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) 1225 pr_info("%s selected on command line.\n", reason); 1226 } 1227 1228 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) 1229 { 1230 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; 1231 char arg[20]; 1232 int ret, i; 1233 1234 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || 1235 cpu_mitigations_off()) 1236 return SPECTRE_V2_CMD_NONE; 1237 1238 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); 1239 if (ret < 0) 1240 return SPECTRE_V2_CMD_AUTO; 1241 1242 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { 1243 if (!match_option(arg, ret, mitigation_options[i].option)) 1244 continue; 1245 cmd = mitigation_options[i].cmd; 1246 break; 1247 } 1248 1249 if (i >= ARRAY_SIZE(mitigation_options)) { 1250 pr_err("unknown option (%s). Switching to AUTO select\n", arg); 1251 return SPECTRE_V2_CMD_AUTO; 1252 } 1253 1254 if ((cmd == SPECTRE_V2_CMD_RETPOLINE || 1255 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1256 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC || 1257 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1258 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1259 !IS_ENABLED(CONFIG_RETPOLINE)) { 1260 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1261 mitigation_options[i].option); 1262 return SPECTRE_V2_CMD_AUTO; 1263 } 1264 1265 if ((cmd == SPECTRE_V2_CMD_EIBRS || 1266 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || 1267 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && 1268 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1269 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n", 1270 mitigation_options[i].option); 1271 return SPECTRE_V2_CMD_AUTO; 1272 } 1273 1274 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || 1275 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) && 1276 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { 1277 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", 1278 mitigation_options[i].option); 1279 return SPECTRE_V2_CMD_AUTO; 1280 } 1281 1282 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) { 1283 pr_err("%s selected but not compiled in. Switching to AUTO select\n", 1284 mitigation_options[i].option); 1285 return SPECTRE_V2_CMD_AUTO; 1286 } 1287 1288 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 1289 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n", 1290 mitigation_options[i].option); 1291 return SPECTRE_V2_CMD_AUTO; 1292 } 1293 1294 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) { 1295 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n", 1296 mitigation_options[i].option); 1297 return SPECTRE_V2_CMD_AUTO; 1298 } 1299 1300 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) { 1301 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n", 1302 mitigation_options[i].option); 1303 return SPECTRE_V2_CMD_AUTO; 1304 } 1305 1306 spec_v2_print_cond(mitigation_options[i].option, 1307 mitigation_options[i].secure); 1308 return cmd; 1309 } 1310 1311 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void) 1312 { 1313 if (!IS_ENABLED(CONFIG_RETPOLINE)) { 1314 pr_err("Kernel not compiled with retpoline; no mitigation available!"); 1315 return SPECTRE_V2_NONE; 1316 } 1317 1318 return SPECTRE_V2_RETPOLINE; 1319 } 1320 1321 /* Disable in-kernel use of non-RSB RET predictors */ 1322 static void __init spec_ctrl_disable_kernel_rrsba(void) 1323 { 1324 u64 ia32_cap; 1325 1326 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL)) 1327 return; 1328 1329 ia32_cap = x86_read_arch_cap_msr(); 1330 1331 if (ia32_cap & ARCH_CAP_RRSBA) { 1332 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S; 1333 write_spec_ctrl_current(x86_spec_ctrl_base, true); 1334 } 1335 } 1336 1337 static void __init spectre_v2_select_mitigation(void) 1338 { 1339 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); 1340 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; 1341 1342 /* 1343 * If the CPU is not affected and the command line mode is NONE or AUTO 1344 * then nothing to do. 1345 */ 1346 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && 1347 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) 1348 return; 1349 1350 switch (cmd) { 1351 case SPECTRE_V2_CMD_NONE: 1352 return; 1353 1354 case SPECTRE_V2_CMD_FORCE: 1355 case SPECTRE_V2_CMD_AUTO: 1356 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { 1357 mode = SPECTRE_V2_EIBRS; 1358 break; 1359 } 1360 1361 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) && 1362 boot_cpu_has_bug(X86_BUG_RETBLEED) && 1363 retbleed_cmd != RETBLEED_CMD_OFF && 1364 boot_cpu_has(X86_FEATURE_IBRS) && 1365 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { 1366 mode = SPECTRE_V2_IBRS; 1367 break; 1368 } 1369 1370 mode = spectre_v2_select_retpoline(); 1371 break; 1372 1373 case SPECTRE_V2_CMD_RETPOLINE_LFENCE: 1374 pr_err(SPECTRE_V2_LFENCE_MSG); 1375 mode = SPECTRE_V2_LFENCE; 1376 break; 1377 1378 case SPECTRE_V2_CMD_RETPOLINE_GENERIC: 1379 mode = SPECTRE_V2_RETPOLINE; 1380 break; 1381 1382 case SPECTRE_V2_CMD_RETPOLINE: 1383 mode = spectre_v2_select_retpoline(); 1384 break; 1385 1386 case SPECTRE_V2_CMD_IBRS: 1387 mode = SPECTRE_V2_IBRS; 1388 break; 1389 1390 case SPECTRE_V2_CMD_EIBRS: 1391 mode = SPECTRE_V2_EIBRS; 1392 break; 1393 1394 case SPECTRE_V2_CMD_EIBRS_LFENCE: 1395 mode = SPECTRE_V2_EIBRS_LFENCE; 1396 break; 1397 1398 case SPECTRE_V2_CMD_EIBRS_RETPOLINE: 1399 mode = SPECTRE_V2_EIBRS_RETPOLINE; 1400 break; 1401 } 1402 1403 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 1404 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); 1405 1406 if (spectre_v2_in_ibrs_mode(mode)) { 1407 x86_spec_ctrl_base |= SPEC_CTRL_IBRS; 1408 write_spec_ctrl_current(x86_spec_ctrl_base, true); 1409 } 1410 1411 switch (mode) { 1412 case SPECTRE_V2_NONE: 1413 case SPECTRE_V2_EIBRS: 1414 break; 1415 1416 case SPECTRE_V2_IBRS: 1417 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS); 1418 break; 1419 1420 case SPECTRE_V2_LFENCE: 1421 case SPECTRE_V2_EIBRS_LFENCE: 1422 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE); 1423 fallthrough; 1424 1425 case SPECTRE_V2_RETPOLINE: 1426 case SPECTRE_V2_EIBRS_RETPOLINE: 1427 setup_force_cpu_cap(X86_FEATURE_RETPOLINE); 1428 break; 1429 } 1430 1431 /* 1432 * Disable alternate RSB predictions in kernel when indirect CALLs and 1433 * JMPs gets protection against BHI and Intramode-BTI, but RET 1434 * prediction from a non-RSB predictor is still a risk. 1435 */ 1436 if (mode == SPECTRE_V2_EIBRS_LFENCE || 1437 mode == SPECTRE_V2_EIBRS_RETPOLINE || 1438 mode == SPECTRE_V2_RETPOLINE) 1439 spec_ctrl_disable_kernel_rrsba(); 1440 1441 spectre_v2_enabled = mode; 1442 pr_info("%s\n", spectre_v2_strings[mode]); 1443 1444 /* 1445 * If Spectre v2 protection has been enabled, fill the RSB during a 1446 * context switch. In general there are two types of RSB attacks 1447 * across context switches, for which the CALLs/RETs may be unbalanced. 1448 * 1449 * 1) RSB underflow 1450 * 1451 * Some Intel parts have "bottomless RSB". When the RSB is empty, 1452 * speculated return targets may come from the branch predictor, 1453 * which could have a user-poisoned BTB or BHB entry. 1454 * 1455 * AMD has it even worse: *all* returns are speculated from the BTB, 1456 * regardless of the state of the RSB. 1457 * 1458 * When IBRS or eIBRS is enabled, the "user -> kernel" attack 1459 * scenario is mitigated by the IBRS branch prediction isolation 1460 * properties, so the RSB buffer filling wouldn't be necessary to 1461 * protect against this type of attack. 1462 * 1463 * The "user -> user" attack scenario is mitigated by RSB filling. 1464 * 1465 * 2) Poisoned RSB entry 1466 * 1467 * If the 'next' in-kernel return stack is shorter than 'prev', 1468 * 'next' could be tricked into speculating with a user-poisoned RSB 1469 * entry. 1470 * 1471 * The "user -> kernel" attack scenario is mitigated by SMEP and 1472 * eIBRS. 1473 * 1474 * The "user -> user" scenario, also known as SpectreBHB, requires 1475 * RSB clearing. 1476 * 1477 * So to mitigate all cases, unconditionally fill RSB on context 1478 * switches. 1479 * 1480 * FIXME: Is this pointless for retbleed-affected AMD? 1481 */ 1482 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); 1483 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); 1484 1485 /* 1486 * Similar to context switches, there are two types of RSB attacks 1487 * after vmexit: 1488 * 1489 * 1) RSB underflow 1490 * 1491 * 2) Poisoned RSB entry 1492 * 1493 * When retpoline is enabled, both are mitigated by filling/clearing 1494 * the RSB. 1495 * 1496 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch 1497 * prediction isolation protections, RSB still needs to be cleared 1498 * because of #2. Note that SMEP provides no protection here, unlike 1499 * user-space-poisoned RSB entries. 1500 * 1501 * eIBRS, on the other hand, has RSB-poisoning protections, so it 1502 * doesn't need RSB clearing after vmexit. 1503 */ 1504 if (boot_cpu_has(X86_FEATURE_RETPOLINE) || 1505 boot_cpu_has(X86_FEATURE_KERNEL_IBRS)) 1506 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT); 1507 1508 /* 1509 * Retpoline protects the kernel, but doesn't protect firmware. IBRS 1510 * and Enhanced IBRS protect firmware too, so enable IBRS around 1511 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise 1512 * enabled. 1513 * 1514 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because 1515 * the user might select retpoline on the kernel command line and if 1516 * the CPU supports Enhanced IBRS, kernel might un-intentionally not 1517 * enable IBRS around firmware calls. 1518 */ 1519 if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) { 1520 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); 1521 pr_info("Enabling Restricted Speculation for firmware calls\n"); 1522 } 1523 1524 /* Set up IBPB and STIBP depending on the general spectre V2 command */ 1525 spectre_v2_cmd = cmd; 1526 } 1527 1528 static void update_stibp_msr(void * __unused) 1529 { 1530 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP); 1531 write_spec_ctrl_current(val, true); 1532 } 1533 1534 /* Update x86_spec_ctrl_base in case SMT state changed. */ 1535 static void update_stibp_strict(void) 1536 { 1537 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; 1538 1539 if (sched_smt_active()) 1540 mask |= SPEC_CTRL_STIBP; 1541 1542 if (mask == x86_spec_ctrl_base) 1543 return; 1544 1545 pr_info("Update user space SMT mitigation: STIBP %s\n", 1546 mask & SPEC_CTRL_STIBP ? "always-on" : "off"); 1547 x86_spec_ctrl_base = mask; 1548 on_each_cpu(update_stibp_msr, NULL, 1); 1549 } 1550 1551 /* Update the static key controlling the evaluation of TIF_SPEC_IB */ 1552 static void update_indir_branch_cond(void) 1553 { 1554 if (sched_smt_active()) 1555 static_branch_enable(&switch_to_cond_stibp); 1556 else 1557 static_branch_disable(&switch_to_cond_stibp); 1558 } 1559 1560 #undef pr_fmt 1561 #define pr_fmt(fmt) fmt 1562 1563 /* Update the static key controlling the MDS CPU buffer clear in idle */ 1564 static void update_mds_branch_idle(void) 1565 { 1566 u64 ia32_cap = x86_read_arch_cap_msr(); 1567 1568 /* 1569 * Enable the idle clearing if SMT is active on CPUs which are 1570 * affected only by MSBDS and not any other MDS variant. 1571 * 1572 * The other variants cannot be mitigated when SMT is enabled, so 1573 * clearing the buffers on idle just to prevent the Store Buffer 1574 * repartitioning leak would be a window dressing exercise. 1575 */ 1576 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) 1577 return; 1578 1579 if (sched_smt_active()) { 1580 static_branch_enable(&mds_idle_clear); 1581 } else if (mmio_mitigation == MMIO_MITIGATION_OFF || 1582 (ia32_cap & ARCH_CAP_FBSDP_NO)) { 1583 static_branch_disable(&mds_idle_clear); 1584 } 1585 } 1586 1587 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" 1588 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n" 1589 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n" 1590 1591 void cpu_bugs_smt_update(void) 1592 { 1593 mutex_lock(&spec_ctrl_mutex); 1594 1595 if (sched_smt_active() && unprivileged_ebpf_enabled() && 1596 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 1597 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG); 1598 1599 switch (spectre_v2_user_stibp) { 1600 case SPECTRE_V2_USER_NONE: 1601 break; 1602 case SPECTRE_V2_USER_STRICT: 1603 case SPECTRE_V2_USER_STRICT_PREFERRED: 1604 update_stibp_strict(); 1605 break; 1606 case SPECTRE_V2_USER_PRCTL: 1607 case SPECTRE_V2_USER_SECCOMP: 1608 update_indir_branch_cond(); 1609 break; 1610 } 1611 1612 switch (mds_mitigation) { 1613 case MDS_MITIGATION_FULL: 1614 case MDS_MITIGATION_VMWERV: 1615 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) 1616 pr_warn_once(MDS_MSG_SMT); 1617 update_mds_branch_idle(); 1618 break; 1619 case MDS_MITIGATION_OFF: 1620 break; 1621 } 1622 1623 switch (taa_mitigation) { 1624 case TAA_MITIGATION_VERW: 1625 case TAA_MITIGATION_UCODE_NEEDED: 1626 if (sched_smt_active()) 1627 pr_warn_once(TAA_MSG_SMT); 1628 break; 1629 case TAA_MITIGATION_TSX_DISABLED: 1630 case TAA_MITIGATION_OFF: 1631 break; 1632 } 1633 1634 switch (mmio_mitigation) { 1635 case MMIO_MITIGATION_VERW: 1636 case MMIO_MITIGATION_UCODE_NEEDED: 1637 if (sched_smt_active()) 1638 pr_warn_once(MMIO_MSG_SMT); 1639 break; 1640 case MMIO_MITIGATION_OFF: 1641 break; 1642 } 1643 1644 mutex_unlock(&spec_ctrl_mutex); 1645 } 1646 1647 #undef pr_fmt 1648 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt 1649 1650 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; 1651 1652 /* The kernel command line selection */ 1653 enum ssb_mitigation_cmd { 1654 SPEC_STORE_BYPASS_CMD_NONE, 1655 SPEC_STORE_BYPASS_CMD_AUTO, 1656 SPEC_STORE_BYPASS_CMD_ON, 1657 SPEC_STORE_BYPASS_CMD_PRCTL, 1658 SPEC_STORE_BYPASS_CMD_SECCOMP, 1659 }; 1660 1661 static const char * const ssb_strings[] = { 1662 [SPEC_STORE_BYPASS_NONE] = "Vulnerable", 1663 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", 1664 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", 1665 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", 1666 }; 1667 1668 static const struct { 1669 const char *option; 1670 enum ssb_mitigation_cmd cmd; 1671 } ssb_mitigation_options[] __initconst = { 1672 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ 1673 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ 1674 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ 1675 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ 1676 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ 1677 }; 1678 1679 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) 1680 { 1681 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; 1682 char arg[20]; 1683 int ret, i; 1684 1685 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || 1686 cpu_mitigations_off()) { 1687 return SPEC_STORE_BYPASS_CMD_NONE; 1688 } else { 1689 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", 1690 arg, sizeof(arg)); 1691 if (ret < 0) 1692 return SPEC_STORE_BYPASS_CMD_AUTO; 1693 1694 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { 1695 if (!match_option(arg, ret, ssb_mitigation_options[i].option)) 1696 continue; 1697 1698 cmd = ssb_mitigation_options[i].cmd; 1699 break; 1700 } 1701 1702 if (i >= ARRAY_SIZE(ssb_mitigation_options)) { 1703 pr_err("unknown option (%s). Switching to AUTO select\n", arg); 1704 return SPEC_STORE_BYPASS_CMD_AUTO; 1705 } 1706 } 1707 1708 return cmd; 1709 } 1710 1711 static enum ssb_mitigation __init __ssb_select_mitigation(void) 1712 { 1713 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; 1714 enum ssb_mitigation_cmd cmd; 1715 1716 if (!boot_cpu_has(X86_FEATURE_SSBD)) 1717 return mode; 1718 1719 cmd = ssb_parse_cmdline(); 1720 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && 1721 (cmd == SPEC_STORE_BYPASS_CMD_NONE || 1722 cmd == SPEC_STORE_BYPASS_CMD_AUTO)) 1723 return mode; 1724 1725 switch (cmd) { 1726 case SPEC_STORE_BYPASS_CMD_SECCOMP: 1727 /* 1728 * Choose prctl+seccomp as the default mode if seccomp is 1729 * enabled. 1730 */ 1731 if (IS_ENABLED(CONFIG_SECCOMP)) 1732 mode = SPEC_STORE_BYPASS_SECCOMP; 1733 else 1734 mode = SPEC_STORE_BYPASS_PRCTL; 1735 break; 1736 case SPEC_STORE_BYPASS_CMD_ON: 1737 mode = SPEC_STORE_BYPASS_DISABLE; 1738 break; 1739 case SPEC_STORE_BYPASS_CMD_AUTO: 1740 case SPEC_STORE_BYPASS_CMD_PRCTL: 1741 mode = SPEC_STORE_BYPASS_PRCTL; 1742 break; 1743 case SPEC_STORE_BYPASS_CMD_NONE: 1744 break; 1745 } 1746 1747 /* 1748 * We have three CPU feature flags that are in play here: 1749 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. 1750 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass 1751 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation 1752 */ 1753 if (mode == SPEC_STORE_BYPASS_DISABLE) { 1754 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); 1755 /* 1756 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may 1757 * use a completely different MSR and bit dependent on family. 1758 */ 1759 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 1760 !static_cpu_has(X86_FEATURE_AMD_SSBD)) { 1761 x86_amd_ssb_disable(); 1762 } else { 1763 x86_spec_ctrl_base |= SPEC_CTRL_SSBD; 1764 write_spec_ctrl_current(x86_spec_ctrl_base, true); 1765 } 1766 } 1767 1768 return mode; 1769 } 1770 1771 static void ssb_select_mitigation(void) 1772 { 1773 ssb_mode = __ssb_select_mitigation(); 1774 1775 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1776 pr_info("%s\n", ssb_strings[ssb_mode]); 1777 } 1778 1779 #undef pr_fmt 1780 #define pr_fmt(fmt) "Speculation prctl: " fmt 1781 1782 static void task_update_spec_tif(struct task_struct *tsk) 1783 { 1784 /* Force the update of the real TIF bits */ 1785 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); 1786 1787 /* 1788 * Immediately update the speculation control MSRs for the current 1789 * task, but for a non-current task delay setting the CPU 1790 * mitigation until it is scheduled next. 1791 * 1792 * This can only happen for SECCOMP mitigation. For PRCTL it's 1793 * always the current task. 1794 */ 1795 if (tsk == current) 1796 speculation_ctrl_update_current(); 1797 } 1798 1799 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl) 1800 { 1801 1802 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 1803 return -EPERM; 1804 1805 switch (ctrl) { 1806 case PR_SPEC_ENABLE: 1807 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 1808 return 0; 1809 case PR_SPEC_DISABLE: 1810 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); 1811 return 0; 1812 default: 1813 return -ERANGE; 1814 } 1815 } 1816 1817 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) 1818 { 1819 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && 1820 ssb_mode != SPEC_STORE_BYPASS_SECCOMP) 1821 return -ENXIO; 1822 1823 switch (ctrl) { 1824 case PR_SPEC_ENABLE: 1825 /* If speculation is force disabled, enable is not allowed */ 1826 if (task_spec_ssb_force_disable(task)) 1827 return -EPERM; 1828 task_clear_spec_ssb_disable(task); 1829 task_clear_spec_ssb_noexec(task); 1830 task_update_spec_tif(task); 1831 break; 1832 case PR_SPEC_DISABLE: 1833 task_set_spec_ssb_disable(task); 1834 task_clear_spec_ssb_noexec(task); 1835 task_update_spec_tif(task); 1836 break; 1837 case PR_SPEC_FORCE_DISABLE: 1838 task_set_spec_ssb_disable(task); 1839 task_set_spec_ssb_force_disable(task); 1840 task_clear_spec_ssb_noexec(task); 1841 task_update_spec_tif(task); 1842 break; 1843 case PR_SPEC_DISABLE_NOEXEC: 1844 if (task_spec_ssb_force_disable(task)) 1845 return -EPERM; 1846 task_set_spec_ssb_disable(task); 1847 task_set_spec_ssb_noexec(task); 1848 task_update_spec_tif(task); 1849 break; 1850 default: 1851 return -ERANGE; 1852 } 1853 return 0; 1854 } 1855 1856 static bool is_spec_ib_user_controlled(void) 1857 { 1858 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL || 1859 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 1860 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL || 1861 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP; 1862 } 1863 1864 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 1865 { 1866 switch (ctrl) { 1867 case PR_SPEC_ENABLE: 1868 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1869 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1870 return 0; 1871 1872 /* 1873 * With strict mode for both IBPB and STIBP, the instruction 1874 * code paths avoid checking this task flag and instead, 1875 * unconditionally run the instruction. However, STIBP and IBPB 1876 * are independent and either can be set to conditionally 1877 * enabled regardless of the mode of the other. 1878 * 1879 * If either is set to conditional, allow the task flag to be 1880 * updated, unless it was force-disabled by a previous prctl 1881 * call. Currently, this is possible on an AMD CPU which has the 1882 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the 1883 * kernel is booted with 'spectre_v2_user=seccomp', then 1884 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and 1885 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED. 1886 */ 1887 if (!is_spec_ib_user_controlled() || 1888 task_spec_ib_force_disable(task)) 1889 return -EPERM; 1890 1891 task_clear_spec_ib_disable(task); 1892 task_update_spec_tif(task); 1893 break; 1894 case PR_SPEC_DISABLE: 1895 case PR_SPEC_FORCE_DISABLE: 1896 /* 1897 * Indirect branch speculation is always allowed when 1898 * mitigation is force disabled. 1899 */ 1900 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1901 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1902 return -EPERM; 1903 1904 if (!is_spec_ib_user_controlled()) 1905 return 0; 1906 1907 task_set_spec_ib_disable(task); 1908 if (ctrl == PR_SPEC_FORCE_DISABLE) 1909 task_set_spec_ib_force_disable(task); 1910 task_update_spec_tif(task); 1911 break; 1912 default: 1913 return -ERANGE; 1914 } 1915 return 0; 1916 } 1917 1918 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, 1919 unsigned long ctrl) 1920 { 1921 switch (which) { 1922 case PR_SPEC_STORE_BYPASS: 1923 return ssb_prctl_set(task, ctrl); 1924 case PR_SPEC_INDIRECT_BRANCH: 1925 return ib_prctl_set(task, ctrl); 1926 case PR_SPEC_L1D_FLUSH: 1927 return l1d_flush_prctl_set(task, ctrl); 1928 default: 1929 return -ENODEV; 1930 } 1931 } 1932 1933 #ifdef CONFIG_SECCOMP 1934 void arch_seccomp_spec_mitigate(struct task_struct *task) 1935 { 1936 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) 1937 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); 1938 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP || 1939 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) 1940 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); 1941 } 1942 #endif 1943 1944 static int l1d_flush_prctl_get(struct task_struct *task) 1945 { 1946 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush)) 1947 return PR_SPEC_FORCE_DISABLE; 1948 1949 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH)) 1950 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1951 else 1952 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1953 } 1954 1955 static int ssb_prctl_get(struct task_struct *task) 1956 { 1957 switch (ssb_mode) { 1958 case SPEC_STORE_BYPASS_DISABLE: 1959 return PR_SPEC_DISABLE; 1960 case SPEC_STORE_BYPASS_SECCOMP: 1961 case SPEC_STORE_BYPASS_PRCTL: 1962 if (task_spec_ssb_force_disable(task)) 1963 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 1964 if (task_spec_ssb_noexec(task)) 1965 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC; 1966 if (task_spec_ssb_disable(task)) 1967 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1968 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1969 default: 1970 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1971 return PR_SPEC_ENABLE; 1972 return PR_SPEC_NOT_AFFECTED; 1973 } 1974 } 1975 1976 static int ib_prctl_get(struct task_struct *task) 1977 { 1978 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) 1979 return PR_SPEC_NOT_AFFECTED; 1980 1981 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE && 1982 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE) 1983 return PR_SPEC_ENABLE; 1984 else if (is_spec_ib_user_controlled()) { 1985 if (task_spec_ib_force_disable(task)) 1986 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; 1987 if (task_spec_ib_disable(task)) 1988 return PR_SPEC_PRCTL | PR_SPEC_DISABLE; 1989 return PR_SPEC_PRCTL | PR_SPEC_ENABLE; 1990 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT || 1991 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 1992 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED) 1993 return PR_SPEC_DISABLE; 1994 else 1995 return PR_SPEC_NOT_AFFECTED; 1996 } 1997 1998 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) 1999 { 2000 switch (which) { 2001 case PR_SPEC_STORE_BYPASS: 2002 return ssb_prctl_get(task); 2003 case PR_SPEC_INDIRECT_BRANCH: 2004 return ib_prctl_get(task); 2005 case PR_SPEC_L1D_FLUSH: 2006 return l1d_flush_prctl_get(task); 2007 default: 2008 return -ENODEV; 2009 } 2010 } 2011 2012 void x86_spec_ctrl_setup_ap(void) 2013 { 2014 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) 2015 write_spec_ctrl_current(x86_spec_ctrl_base, true); 2016 2017 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) 2018 x86_amd_ssb_disable(); 2019 } 2020 2021 bool itlb_multihit_kvm_mitigation; 2022 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); 2023 2024 #undef pr_fmt 2025 #define pr_fmt(fmt) "L1TF: " fmt 2026 2027 /* Default mitigation for L1TF-affected CPUs */ 2028 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; 2029 #if IS_ENABLED(CONFIG_KVM_INTEL) 2030 EXPORT_SYMBOL_GPL(l1tf_mitigation); 2031 #endif 2032 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 2033 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); 2034 2035 /* 2036 * These CPUs all support 44bits physical address space internally in the 2037 * cache but CPUID can report a smaller number of physical address bits. 2038 * 2039 * The L1TF mitigation uses the top most address bit for the inversion of 2040 * non present PTEs. When the installed memory reaches into the top most 2041 * address bit due to memory holes, which has been observed on machines 2042 * which report 36bits physical address bits and have 32G RAM installed, 2043 * then the mitigation range check in l1tf_select_mitigation() triggers. 2044 * This is a false positive because the mitigation is still possible due to 2045 * the fact that the cache uses 44bit internally. Use the cache bits 2046 * instead of the reported physical bits and adjust them on the affected 2047 * machines to 44bit if the reported bits are less than 44. 2048 */ 2049 static void override_cache_bits(struct cpuinfo_x86 *c) 2050 { 2051 if (c->x86 != 6) 2052 return; 2053 2054 switch (c->x86_model) { 2055 case INTEL_FAM6_NEHALEM: 2056 case INTEL_FAM6_WESTMERE: 2057 case INTEL_FAM6_SANDYBRIDGE: 2058 case INTEL_FAM6_IVYBRIDGE: 2059 case INTEL_FAM6_HASWELL: 2060 case INTEL_FAM6_HASWELL_L: 2061 case INTEL_FAM6_HASWELL_G: 2062 case INTEL_FAM6_BROADWELL: 2063 case INTEL_FAM6_BROADWELL_G: 2064 case INTEL_FAM6_SKYLAKE_L: 2065 case INTEL_FAM6_SKYLAKE: 2066 case INTEL_FAM6_KABYLAKE_L: 2067 case INTEL_FAM6_KABYLAKE: 2068 if (c->x86_cache_bits < 44) 2069 c->x86_cache_bits = 44; 2070 break; 2071 } 2072 } 2073 2074 static void __init l1tf_select_mitigation(void) 2075 { 2076 u64 half_pa; 2077 2078 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2079 return; 2080 2081 if (cpu_mitigations_off()) 2082 l1tf_mitigation = L1TF_MITIGATION_OFF; 2083 else if (cpu_mitigations_auto_nosmt()) 2084 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2085 2086 override_cache_bits(&boot_cpu_data); 2087 2088 switch (l1tf_mitigation) { 2089 case L1TF_MITIGATION_OFF: 2090 case L1TF_MITIGATION_FLUSH_NOWARN: 2091 case L1TF_MITIGATION_FLUSH: 2092 break; 2093 case L1TF_MITIGATION_FLUSH_NOSMT: 2094 case L1TF_MITIGATION_FULL: 2095 cpu_smt_disable(false); 2096 break; 2097 case L1TF_MITIGATION_FULL_FORCE: 2098 cpu_smt_disable(true); 2099 break; 2100 } 2101 2102 #if CONFIG_PGTABLE_LEVELS == 2 2103 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); 2104 return; 2105 #endif 2106 2107 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; 2108 if (l1tf_mitigation != L1TF_MITIGATION_OFF && 2109 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { 2110 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); 2111 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", 2112 half_pa); 2113 pr_info("However, doing so will make a part of your RAM unusable.\n"); 2114 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); 2115 return; 2116 } 2117 2118 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); 2119 } 2120 2121 static int __init l1tf_cmdline(char *str) 2122 { 2123 if (!boot_cpu_has_bug(X86_BUG_L1TF)) 2124 return 0; 2125 2126 if (!str) 2127 return -EINVAL; 2128 2129 if (!strcmp(str, "off")) 2130 l1tf_mitigation = L1TF_MITIGATION_OFF; 2131 else if (!strcmp(str, "flush,nowarn")) 2132 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; 2133 else if (!strcmp(str, "flush")) 2134 l1tf_mitigation = L1TF_MITIGATION_FLUSH; 2135 else if (!strcmp(str, "flush,nosmt")) 2136 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; 2137 else if (!strcmp(str, "full")) 2138 l1tf_mitigation = L1TF_MITIGATION_FULL; 2139 else if (!strcmp(str, "full,force")) 2140 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; 2141 2142 return 0; 2143 } 2144 early_param("l1tf", l1tf_cmdline); 2145 2146 #undef pr_fmt 2147 #define pr_fmt(fmt) fmt 2148 2149 #ifdef CONFIG_SYSFS 2150 2151 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" 2152 2153 #if IS_ENABLED(CONFIG_KVM_INTEL) 2154 static const char * const l1tf_vmx_states[] = { 2155 [VMENTER_L1D_FLUSH_AUTO] = "auto", 2156 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", 2157 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", 2158 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", 2159 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", 2160 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" 2161 }; 2162 2163 static ssize_t l1tf_show_state(char *buf) 2164 { 2165 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) 2166 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); 2167 2168 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || 2169 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && 2170 sched_smt_active())) { 2171 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, 2172 l1tf_vmx_states[l1tf_vmx_mitigation]); 2173 } 2174 2175 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, 2176 l1tf_vmx_states[l1tf_vmx_mitigation], 2177 sched_smt_active() ? "vulnerable" : "disabled"); 2178 } 2179 2180 static ssize_t itlb_multihit_show_state(char *buf) 2181 { 2182 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2183 !boot_cpu_has(X86_FEATURE_VMX)) 2184 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n"); 2185 else if (!(cr4_read_shadow() & X86_CR4_VMXE)) 2186 return sprintf(buf, "KVM: Mitigation: VMX disabled\n"); 2187 else if (itlb_multihit_kvm_mitigation) 2188 return sprintf(buf, "KVM: Mitigation: Split huge pages\n"); 2189 else 2190 return sprintf(buf, "KVM: Vulnerable\n"); 2191 } 2192 #else 2193 static ssize_t l1tf_show_state(char *buf) 2194 { 2195 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); 2196 } 2197 2198 static ssize_t itlb_multihit_show_state(char *buf) 2199 { 2200 return sprintf(buf, "Processor vulnerable\n"); 2201 } 2202 #endif 2203 2204 static ssize_t mds_show_state(char *buf) 2205 { 2206 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2207 return sprintf(buf, "%s; SMT Host state unknown\n", 2208 mds_strings[mds_mitigation]); 2209 } 2210 2211 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { 2212 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2213 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : 2214 sched_smt_active() ? "mitigated" : "disabled")); 2215 } 2216 2217 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], 2218 sched_smt_active() ? "vulnerable" : "disabled"); 2219 } 2220 2221 static ssize_t tsx_async_abort_show_state(char *buf) 2222 { 2223 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) || 2224 (taa_mitigation == TAA_MITIGATION_OFF)) 2225 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]); 2226 2227 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2228 return sprintf(buf, "%s; SMT Host state unknown\n", 2229 taa_strings[taa_mitigation]); 2230 } 2231 2232 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation], 2233 sched_smt_active() ? "vulnerable" : "disabled"); 2234 } 2235 2236 static ssize_t mmio_stale_data_show_state(char *buf) 2237 { 2238 if (mmio_mitigation == MMIO_MITIGATION_OFF) 2239 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]); 2240 2241 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 2242 return sysfs_emit(buf, "%s; SMT Host state unknown\n", 2243 mmio_strings[mmio_mitigation]); 2244 } 2245 2246 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation], 2247 sched_smt_active() ? "vulnerable" : "disabled"); 2248 } 2249 2250 static char *stibp_state(void) 2251 { 2252 if (spectre_v2_in_ibrs_mode(spectre_v2_enabled)) 2253 return ""; 2254 2255 switch (spectre_v2_user_stibp) { 2256 case SPECTRE_V2_USER_NONE: 2257 return ", STIBP: disabled"; 2258 case SPECTRE_V2_USER_STRICT: 2259 return ", STIBP: forced"; 2260 case SPECTRE_V2_USER_STRICT_PREFERRED: 2261 return ", STIBP: always-on"; 2262 case SPECTRE_V2_USER_PRCTL: 2263 case SPECTRE_V2_USER_SECCOMP: 2264 if (static_key_enabled(&switch_to_cond_stibp)) 2265 return ", STIBP: conditional"; 2266 } 2267 return ""; 2268 } 2269 2270 static char *ibpb_state(void) 2271 { 2272 if (boot_cpu_has(X86_FEATURE_IBPB)) { 2273 if (static_key_enabled(&switch_mm_always_ibpb)) 2274 return ", IBPB: always-on"; 2275 if (static_key_enabled(&switch_mm_cond_ibpb)) 2276 return ", IBPB: conditional"; 2277 return ", IBPB: disabled"; 2278 } 2279 return ""; 2280 } 2281 2282 static ssize_t spectre_v2_show_state(char *buf) 2283 { 2284 if (spectre_v2_enabled == SPECTRE_V2_LFENCE) 2285 return sprintf(buf, "Vulnerable: LFENCE\n"); 2286 2287 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) 2288 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n"); 2289 2290 if (sched_smt_active() && unprivileged_ebpf_enabled() && 2291 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE) 2292 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n"); 2293 2294 return sprintf(buf, "%s%s%s%s%s%s\n", 2295 spectre_v2_strings[spectre_v2_enabled], 2296 ibpb_state(), 2297 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", 2298 stibp_state(), 2299 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", 2300 spectre_v2_module_string()); 2301 } 2302 2303 static ssize_t srbds_show_state(char *buf) 2304 { 2305 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]); 2306 } 2307 2308 static ssize_t retbleed_show_state(char *buf) 2309 { 2310 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) { 2311 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 2312 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) 2313 return sprintf(buf, "Vulnerable: untrained return thunk on non-Zen uarch\n"); 2314 2315 return sprintf(buf, "%s; SMT %s\n", 2316 retbleed_strings[retbleed_mitigation], 2317 !sched_smt_active() ? "disabled" : 2318 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT || 2319 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ? 2320 "enabled with STIBP protection" : "vulnerable"); 2321 } 2322 2323 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]); 2324 } 2325 2326 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, 2327 char *buf, unsigned int bug) 2328 { 2329 if (!boot_cpu_has_bug(bug)) 2330 return sprintf(buf, "Not affected\n"); 2331 2332 switch (bug) { 2333 case X86_BUG_CPU_MELTDOWN: 2334 if (boot_cpu_has(X86_FEATURE_PTI)) 2335 return sprintf(buf, "Mitigation: PTI\n"); 2336 2337 if (hypervisor_is_type(X86_HYPER_XEN_PV)) 2338 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); 2339 2340 break; 2341 2342 case X86_BUG_SPECTRE_V1: 2343 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); 2344 2345 case X86_BUG_SPECTRE_V2: 2346 return spectre_v2_show_state(buf); 2347 2348 case X86_BUG_SPEC_STORE_BYPASS: 2349 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); 2350 2351 case X86_BUG_L1TF: 2352 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) 2353 return l1tf_show_state(buf); 2354 break; 2355 2356 case X86_BUG_MDS: 2357 return mds_show_state(buf); 2358 2359 case X86_BUG_TAA: 2360 return tsx_async_abort_show_state(buf); 2361 2362 case X86_BUG_ITLB_MULTIHIT: 2363 return itlb_multihit_show_state(buf); 2364 2365 case X86_BUG_SRBDS: 2366 return srbds_show_state(buf); 2367 2368 case X86_BUG_MMIO_STALE_DATA: 2369 return mmio_stale_data_show_state(buf); 2370 2371 case X86_BUG_RETBLEED: 2372 return retbleed_show_state(buf); 2373 2374 default: 2375 break; 2376 } 2377 2378 return sprintf(buf, "Vulnerable\n"); 2379 } 2380 2381 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) 2382 { 2383 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); 2384 } 2385 2386 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) 2387 { 2388 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); 2389 } 2390 2391 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) 2392 { 2393 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); 2394 } 2395 2396 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) 2397 { 2398 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); 2399 } 2400 2401 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) 2402 { 2403 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); 2404 } 2405 2406 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) 2407 { 2408 return cpu_show_common(dev, attr, buf, X86_BUG_MDS); 2409 } 2410 2411 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) 2412 { 2413 return cpu_show_common(dev, attr, buf, X86_BUG_TAA); 2414 } 2415 2416 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) 2417 { 2418 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT); 2419 } 2420 2421 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) 2422 { 2423 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS); 2424 } 2425 2426 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf) 2427 { 2428 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); 2429 } 2430 2431 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf) 2432 { 2433 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED); 2434 } 2435 #endif 2436