1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/mm.h> 4 5 #include <linux/io.h> 6 #include <asm/processor.h> 7 #include <asm/apic.h> 8 #include <asm/cpu.h> 9 #include <asm/pci-direct.h> 10 11 #ifdef CONFIG_X86_64 12 # include <asm/numa_64.h> 13 # include <asm/mmconfig.h> 14 # include <asm/cacheflush.h> 15 #endif 16 17 #include "cpu.h" 18 19 #ifdef CONFIG_X86_32 20 /* 21 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 22 * misexecution of code under Linux. Owners of such processors should 23 * contact AMD for precise details and a CPU swap. 24 * 25 * See http://www.multimania.com/poulot/k6bug.html 26 * http://www.amd.com/K6/k6docs/revgd.html 27 * 28 * The following test is erm.. interesting. AMD neglected to up 29 * the chip setting when fixing the bug but they also tweaked some 30 * performance at the same time.. 31 */ 32 33 extern void vide(void); 34 __asm__(".align 4\nvide: ret"); 35 36 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) 37 { 38 /* 39 * General Systems BIOSen alias the cpu frequency registers 40 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 41 * drivers subsequently pokes it, and changes the CPU speed. 42 * Workaround : Remove the unneeded alias. 43 */ 44 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 45 #define CBAR_ENB (0x80000000) 46 #define CBAR_KEY (0X000000CB) 47 if (c->x86_model == 9 || c->x86_model == 10) { 48 if (inl(CBAR) & CBAR_ENB) 49 outl(0 | CBAR_KEY, CBAR); 50 } 51 } 52 53 54 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) 55 { 56 u32 l, h; 57 int mbytes = num_physpages >> (20-PAGE_SHIFT); 58 59 if (c->x86_model < 6) { 60 /* Based on AMD doc 20734R - June 2000 */ 61 if (c->x86_model == 0) { 62 clear_cpu_cap(c, X86_FEATURE_APIC); 63 set_cpu_cap(c, X86_FEATURE_PGE); 64 } 65 return; 66 } 67 68 if (c->x86_model == 6 && c->x86_mask == 1) { 69 const int K6_BUG_LOOP = 1000000; 70 int n; 71 void (*f_vide)(void); 72 unsigned long d, d2; 73 74 printk(KERN_INFO "AMD K6 stepping B detected - "); 75 76 /* 77 * It looks like AMD fixed the 2.6.2 bug and improved indirect 78 * calls at the same time. 79 */ 80 81 n = K6_BUG_LOOP; 82 f_vide = vide; 83 rdtscl(d); 84 while (n--) 85 f_vide(); 86 rdtscl(d2); 87 d = d2-d; 88 89 if (d > 20*K6_BUG_LOOP) 90 printk(KERN_CONT 91 "system stability may be impaired when more than 32 MB are used.\n"); 92 else 93 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 94 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 95 } 96 97 /* K6 with old style WHCR */ 98 if (c->x86_model < 8 || 99 (c->x86_model == 8 && c->x86_mask < 8)) { 100 /* We can only write allocate on the low 508Mb */ 101 if (mbytes > 508) 102 mbytes = 508; 103 104 rdmsr(MSR_K6_WHCR, l, h); 105 if ((l&0x0000FFFF) == 0) { 106 unsigned long flags; 107 l = (1<<0)|((mbytes/4)<<1); 108 local_irq_save(flags); 109 wbinvd(); 110 wrmsr(MSR_K6_WHCR, l, h); 111 local_irq_restore(flags); 112 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 113 mbytes); 114 } 115 return; 116 } 117 118 if ((c->x86_model == 8 && c->x86_mask > 7) || 119 c->x86_model == 9 || c->x86_model == 13) { 120 /* The more serious chips .. */ 121 122 if (mbytes > 4092) 123 mbytes = 4092; 124 125 rdmsr(MSR_K6_WHCR, l, h); 126 if ((l&0xFFFF0000) == 0) { 127 unsigned long flags; 128 l = ((mbytes>>2)<<22)|(1<<16); 129 local_irq_save(flags); 130 wbinvd(); 131 wrmsr(MSR_K6_WHCR, l, h); 132 local_irq_restore(flags); 133 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 134 mbytes); 135 } 136 137 return; 138 } 139 140 if (c->x86_model == 10) { 141 /* AMD Geode LX is model 10 */ 142 /* placeholder for any needed mods */ 143 return; 144 } 145 } 146 147 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) 148 { 149 #ifdef CONFIG_SMP 150 /* calling is from identify_secondary_cpu() ? */ 151 if (!c->cpu_index) 152 return; 153 154 /* 155 * Certain Athlons might work (for various values of 'work') in SMP 156 * but they are not certified as MP capable. 157 */ 158 /* Athlon 660/661 is valid. */ 159 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 160 (c->x86_mask == 1))) 161 goto valid_k7; 162 163 /* Duron 670 is valid */ 164 if ((c->x86_model == 7) && (c->x86_mask == 0)) 165 goto valid_k7; 166 167 /* 168 * Athlon 662, Duron 671, and Athlon >model 7 have capability 169 * bit. It's worth noting that the A5 stepping (662) of some 170 * Athlon XP's have the MP bit set. 171 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 172 * more. 173 */ 174 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 175 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 176 (c->x86_model > 7)) 177 if (cpu_has_mp) 178 goto valid_k7; 179 180 /* If we get here, not a certified SMP capable AMD system. */ 181 182 /* 183 * Don't taint if we are running SMP kernel on a single non-MP 184 * approved Athlon 185 */ 186 WARN_ONCE(1, "WARNING: This combination of AMD" 187 " processors is not suitable for SMP.\n"); 188 if (!test_taint(TAINT_UNSAFE_SMP)) 189 add_taint(TAINT_UNSAFE_SMP); 190 191 valid_k7: 192 ; 193 #endif 194 } 195 196 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 197 { 198 u32 l, h; 199 200 /* 201 * Bit 15 of Athlon specific MSR 15, needs to be 0 202 * to enable SSE on Palomino/Morgan/Barton CPU's. 203 * If the BIOS didn't enable it already, enable it here. 204 */ 205 if (c->x86_model >= 6 && c->x86_model <= 10) { 206 if (!cpu_has(c, X86_FEATURE_XMM)) { 207 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 208 rdmsr(MSR_K7_HWCR, l, h); 209 l &= ~0x00008000; 210 wrmsr(MSR_K7_HWCR, l, h); 211 set_cpu_cap(c, X86_FEATURE_XMM); 212 } 213 } 214 215 /* 216 * It's been determined by AMD that Athlons since model 8 stepping 1 217 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 218 * As per AMD technical note 27212 0.2 219 */ 220 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 221 rdmsr(MSR_K7_CLK_CTL, l, h); 222 if ((l & 0xfff00000) != 0x20000000) { 223 printk(KERN_INFO 224 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 225 l, ((l & 0x000fffff)|0x20000000)); 226 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 227 } 228 } 229 230 set_cpu_cap(c, X86_FEATURE_K7); 231 232 amd_k7_smp_check(c); 233 } 234 #endif 235 236 #ifdef CONFIG_NUMA 237 /* 238 * To workaround broken NUMA config. Read the comment in 239 * srat_detect_node(). 240 */ 241 static int __cpuinit nearby_node(int apicid) 242 { 243 int i, node; 244 245 for (i = apicid - 1; i >= 0; i--) { 246 node = __apicid_to_node[i]; 247 if (node != NUMA_NO_NODE && node_online(node)) 248 return node; 249 } 250 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 251 node = __apicid_to_node[i]; 252 if (node != NUMA_NO_NODE && node_online(node)) 253 return node; 254 } 255 return first_node(node_online_map); /* Shouldn't happen */ 256 } 257 #endif 258 259 /* 260 * Fixup core topology information for 261 * (1) AMD multi-node processors 262 * Assumption: Number of cores in each internal node is the same. 263 * (2) AMD processors supporting compute units 264 */ 265 #ifdef CONFIG_X86_HT 266 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) 267 { 268 u32 nodes, cores_per_cu = 1; 269 u8 node_id; 270 int cpu = smp_processor_id(); 271 272 /* get information required for multi-node processors */ 273 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 274 u32 eax, ebx, ecx, edx; 275 276 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 277 nodes = ((ecx >> 8) & 7) + 1; 278 node_id = ecx & 7; 279 280 /* get compute unit information */ 281 smp_num_siblings = ((ebx >> 8) & 3) + 1; 282 c->compute_unit_id = ebx & 0xff; 283 cores_per_cu += ((ebx >> 8) & 3); 284 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 285 u64 value; 286 287 rdmsrl(MSR_FAM10H_NODE_ID, value); 288 nodes = ((value >> 3) & 7) + 1; 289 node_id = value & 7; 290 } else 291 return; 292 293 /* fixup multi-node processor information */ 294 if (nodes > 1) { 295 u32 cores_per_node; 296 u32 cus_per_node; 297 298 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 299 cores_per_node = c->x86_max_cores / nodes; 300 cus_per_node = cores_per_node / cores_per_cu; 301 302 /* store NodeID, use llc_shared_map to store sibling info */ 303 per_cpu(cpu_llc_id, cpu) = node_id; 304 305 /* core id has to be in the [0 .. cores_per_node - 1] range */ 306 c->cpu_core_id %= cores_per_node; 307 c->compute_unit_id %= cus_per_node; 308 } 309 } 310 #endif 311 312 /* 313 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 314 * Assumes number of cores is a power of two. 315 */ 316 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 317 { 318 #ifdef CONFIG_X86_HT 319 unsigned bits; 320 int cpu = smp_processor_id(); 321 322 bits = c->x86_coreid_bits; 323 /* Low order bits define the core id (index of core in socket) */ 324 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 325 /* Convert the initial APIC ID into the socket ID */ 326 c->phys_proc_id = c->initial_apicid >> bits; 327 /* use socket ID also for last level cache */ 328 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 329 amd_get_topology(c); 330 #endif 331 } 332 333 int amd_get_nb_id(int cpu) 334 { 335 int id = 0; 336 #ifdef CONFIG_SMP 337 id = per_cpu(cpu_llc_id, cpu); 338 #endif 339 return id; 340 } 341 EXPORT_SYMBOL_GPL(amd_get_nb_id); 342 343 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 344 { 345 #ifdef CONFIG_NUMA 346 int cpu = smp_processor_id(); 347 int node; 348 unsigned apicid = c->apicid; 349 350 node = numa_cpu_node(cpu); 351 if (node == NUMA_NO_NODE) 352 node = per_cpu(cpu_llc_id, cpu); 353 354 if (!node_online(node)) { 355 /* 356 * Two possibilities here: 357 * 358 * - The CPU is missing memory and no node was created. In 359 * that case try picking one from a nearby CPU. 360 * 361 * - The APIC IDs differ from the HyperTransport node IDs 362 * which the K8 northbridge parsing fills in. Assume 363 * they are all increased by a constant offset, but in 364 * the same order as the HT nodeids. If that doesn't 365 * result in a usable node fall back to the path for the 366 * previous case. 367 * 368 * This workaround operates directly on the mapping between 369 * APIC ID and NUMA node, assuming certain relationship 370 * between APIC ID, HT node ID and NUMA topology. As going 371 * through CPU mapping may alter the outcome, directly 372 * access __apicid_to_node[]. 373 */ 374 int ht_nodeid = c->initial_apicid; 375 376 if (ht_nodeid >= 0 && 377 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 378 node = __apicid_to_node[ht_nodeid]; 379 /* Pick a nearby node */ 380 if (!node_online(node)) 381 node = nearby_node(apicid); 382 } 383 numa_set_node(cpu, node); 384 #endif 385 } 386 387 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 388 { 389 #ifdef CONFIG_X86_HT 390 unsigned bits, ecx; 391 392 /* Multi core CPU? */ 393 if (c->extended_cpuid_level < 0x80000008) 394 return; 395 396 ecx = cpuid_ecx(0x80000008); 397 398 c->x86_max_cores = (ecx & 0xff) + 1; 399 400 /* CPU telling us the core id bits shift? */ 401 bits = (ecx >> 12) & 0xF; 402 403 /* Otherwise recompute */ 404 if (bits == 0) { 405 while ((1 << bits) < c->x86_max_cores) 406 bits++; 407 } 408 409 c->x86_coreid_bits = bits; 410 #endif 411 } 412 413 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 414 { 415 early_init_amd_mc(c); 416 417 /* 418 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 419 * with P/T states and does not stop in deep C-states 420 */ 421 if (c->x86_power & (1 << 8)) { 422 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 423 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 424 } 425 426 #ifdef CONFIG_X86_64 427 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 428 #else 429 /* Set MTRR capability flag if appropriate */ 430 if (c->x86 == 5) 431 if (c->x86_model == 13 || c->x86_model == 9 || 432 (c->x86_model == 8 && c->x86_mask >= 8)) 433 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 434 #endif 435 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 436 /* check CPU config space for extended APIC ID */ 437 if (cpu_has_apic && c->x86 >= 0xf) { 438 unsigned int val; 439 val = read_pci_config(0, 24, 0, 0x68); 440 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 441 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 442 } 443 #endif 444 445 /* We need to do the following only once */ 446 if (c != &boot_cpu_data) 447 return; 448 449 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 450 451 if (c->x86 > 0x10 || 452 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 453 u64 val; 454 455 rdmsrl(MSR_K7_HWCR, val); 456 if (!(val & BIT(24))) 457 printk(KERN_WARNING FW_BUG "TSC doesn't count " 458 "with P0 frequency!\n"); 459 } 460 } 461 } 462 463 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 464 { 465 #ifdef CONFIG_SMP 466 unsigned long long value; 467 468 /* 469 * Disable TLB flush filter by setting HWCR.FFDIS on K8 470 * bit 6 of msr C001_0015 471 * 472 * Errata 63 for SH-B3 steppings 473 * Errata 122 for all steppings (F+ have it disabled by default) 474 */ 475 if (c->x86 == 0xf) { 476 rdmsrl(MSR_K7_HWCR, value); 477 value |= 1 << 6; 478 wrmsrl(MSR_K7_HWCR, value); 479 } 480 #endif 481 482 early_init_amd(c); 483 484 /* 485 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 486 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 487 */ 488 clear_cpu_cap(c, 0*32+31); 489 490 #ifdef CONFIG_X86_64 491 /* On C+ stepping K8 rep microcode works well for copy/memset */ 492 if (c->x86 == 0xf) { 493 u32 level; 494 495 level = cpuid_eax(1); 496 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 497 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 498 499 /* 500 * Some BIOSes incorrectly force this feature, but only K8 501 * revision D (model = 0x14) and later actually support it. 502 * (AMD Erratum #110, docId: 25759). 503 */ 504 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 505 u64 val; 506 507 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 508 if (!rdmsrl_amd_safe(0xc001100d, &val)) { 509 val &= ~(1ULL << 32); 510 wrmsrl_amd_safe(0xc001100d, val); 511 } 512 } 513 514 } 515 if (c->x86 >= 0x10) 516 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 517 518 /* get apicid instead of initial apic id from cpuid */ 519 c->apicid = hard_smp_processor_id(); 520 #else 521 522 /* 523 * FIXME: We should handle the K5 here. Set up the write 524 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 525 * no bus pipeline) 526 */ 527 528 switch (c->x86) { 529 case 4: 530 init_amd_k5(c); 531 break; 532 case 5: 533 init_amd_k6(c); 534 break; 535 case 6: /* An Athlon/Duron */ 536 init_amd_k7(c); 537 break; 538 } 539 540 /* K6s reports MCEs but don't actually have all the MSRs */ 541 if (c->x86 < 6) 542 clear_cpu_cap(c, X86_FEATURE_MCE); 543 #endif 544 545 /* Enable workaround for FXSAVE leak */ 546 if (c->x86 >= 6) 547 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 548 549 if (!c->x86_model_id[0]) { 550 switch (c->x86) { 551 case 0xf: 552 /* Should distinguish Models here, but this is only 553 a fallback anyways. */ 554 strcpy(c->x86_model_id, "Hammer"); 555 break; 556 } 557 } 558 559 cpu_detect_cache_sizes(c); 560 561 /* Multi core CPU? */ 562 if (c->extended_cpuid_level >= 0x80000008) { 563 amd_detect_cmp(c); 564 srat_detect_node(c); 565 } 566 567 #ifdef CONFIG_X86_32 568 detect_ht(c); 569 #endif 570 571 if (c->extended_cpuid_level >= 0x80000006) { 572 if (cpuid_edx(0x80000006) & 0xf000) 573 num_cache_leaves = 4; 574 else 575 num_cache_leaves = 3; 576 } 577 578 if (c->x86 >= 0xf) 579 set_cpu_cap(c, X86_FEATURE_K8); 580 581 if (cpu_has_xmm2) { 582 /* MFENCE stops RDTSC speculation */ 583 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 584 } 585 586 #ifdef CONFIG_X86_64 587 if (c->x86 == 0x10) { 588 /* do this for boot cpu */ 589 if (c == &boot_cpu_data) 590 check_enable_amd_mmconf_dmi(); 591 592 fam10h_check_enable_mmcfg(); 593 } 594 595 if (c == &boot_cpu_data && c->x86 >= 0xf) { 596 unsigned long long tseg; 597 598 /* 599 * Split up direct mapping around the TSEG SMM area. 600 * Don't do it for gbpages because there seems very little 601 * benefit in doing so. 602 */ 603 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 604 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 605 if ((tseg>>PMD_SHIFT) < 606 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || 607 ((tseg>>PMD_SHIFT) < 608 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && 609 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) 610 set_memory_4k((unsigned long)__va(tseg), 1); 611 } 612 } 613 #endif 614 615 /* As a rule processors have APIC timer running in deep C states */ 616 if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400)) 617 set_cpu_cap(c, X86_FEATURE_ARAT); 618 } 619 620 #ifdef CONFIG_X86_32 621 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, 622 unsigned int size) 623 { 624 /* AMD errata T13 (order #21922) */ 625 if ((c->x86 == 6)) { 626 /* Duron Rev A0 */ 627 if (c->x86_model == 3 && c->x86_mask == 0) 628 size = 64; 629 /* Tbird rev A1/A2 */ 630 if (c->x86_model == 4 && 631 (c->x86_mask == 0 || c->x86_mask == 1)) 632 size = 256; 633 } 634 return size; 635 } 636 #endif 637 638 static const struct cpu_dev __cpuinitconst amd_cpu_dev = { 639 .c_vendor = "AMD", 640 .c_ident = { "AuthenticAMD" }, 641 #ifdef CONFIG_X86_32 642 .c_models = { 643 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 644 { 645 [3] = "486 DX/2", 646 [7] = "486 DX/2-WB", 647 [8] = "486 DX/4", 648 [9] = "486 DX/4-WB", 649 [14] = "Am5x86-WT", 650 [15] = "Am5x86-WB" 651 } 652 }, 653 }, 654 .c_size_cache = amd_size_cache, 655 #endif 656 .c_early_init = early_init_amd, 657 .c_init = init_amd, 658 .c_x86_vendor = X86_VENDOR_AMD, 659 }; 660 661 cpu_dev_register(amd_cpu_dev); 662 663 /* 664 * AMD errata checking 665 * 666 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 667 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 668 * have an OSVW id assigned, which it takes as first argument. Both take a 669 * variable number of family-specific model-stepping ranges created by 670 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const 671 * int[] in arch/x86/include/asm/processor.h. 672 * 673 * Example: 674 * 675 * const int amd_erratum_319[] = 676 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 677 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 678 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 679 */ 680 681 const int amd_erratum_400[] = 682 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 683 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 684 EXPORT_SYMBOL_GPL(amd_erratum_400); 685 686 const int amd_erratum_383[] = 687 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 688 EXPORT_SYMBOL_GPL(amd_erratum_383); 689 690 bool cpu_has_amd_erratum(const int *erratum) 691 { 692 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); 693 int osvw_id = *erratum++; 694 u32 range; 695 u32 ms; 696 697 /* 698 * If called early enough that current_cpu_data hasn't been initialized 699 * yet, fall back to boot_cpu_data. 700 */ 701 if (cpu->x86 == 0) 702 cpu = &boot_cpu_data; 703 704 if (cpu->x86_vendor != X86_VENDOR_AMD) 705 return false; 706 707 if (osvw_id >= 0 && osvw_id < 65536 && 708 cpu_has(cpu, X86_FEATURE_OSVW)) { 709 u64 osvw_len; 710 711 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 712 if (osvw_id < osvw_len) { 713 u64 osvw_bits; 714 715 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 716 osvw_bits); 717 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 718 } 719 } 720 721 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 722 ms = (cpu->x86_model << 4) | cpu->x86_mask; 723 while ((range = *erratum++)) 724 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 725 (ms >= AMD_MODEL_RANGE_START(range)) && 726 (ms <= AMD_MODEL_RANGE_END(range))) 727 return true; 728 729 return false; 730 } 731 732 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); 733