1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/random.h> 10 #include <asm/processor.h> 11 #include <asm/apic.h> 12 #include <asm/cacheinfo.h> 13 #include <asm/cpu.h> 14 #include <asm/spec-ctrl.h> 15 #include <asm/smp.h> 16 #include <asm/pci-direct.h> 17 #include <asm/delay.h> 18 19 #ifdef CONFIG_X86_64 20 # include <asm/mmconfig.h> 21 # include <asm/set_memory.h> 22 #endif 23 24 #include "cpu.h" 25 26 static const int amd_erratum_383[]; 27 static const int amd_erratum_400[]; 28 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 29 30 /* 31 * nodes_per_socket: Stores the number of nodes per socket. 32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 33 * Node Identifiers[10:8] 34 */ 35 static u32 nodes_per_socket = 1; 36 37 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 38 { 39 u32 gprs[8] = { 0 }; 40 int err; 41 42 WARN_ONCE((boot_cpu_data.x86 != 0xf), 43 "%s should only be used on K8!\n", __func__); 44 45 gprs[1] = msr; 46 gprs[7] = 0x9c5a203a; 47 48 err = rdmsr_safe_regs(gprs); 49 50 *p = gprs[0] | ((u64)gprs[2] << 32); 51 52 return err; 53 } 54 55 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 56 { 57 u32 gprs[8] = { 0 }; 58 59 WARN_ONCE((boot_cpu_data.x86 != 0xf), 60 "%s should only be used on K8!\n", __func__); 61 62 gprs[0] = (u32)val; 63 gprs[1] = msr; 64 gprs[2] = val >> 32; 65 gprs[7] = 0x9c5a203a; 66 67 return wrmsr_safe_regs(gprs); 68 } 69 70 /* 71 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 72 * misexecution of code under Linux. Owners of such processors should 73 * contact AMD for precise details and a CPU swap. 74 * 75 * See http://www.multimania.com/poulot/k6bug.html 76 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 77 * (Publication # 21266 Issue Date: August 1998) 78 * 79 * The following test is erm.. interesting. AMD neglected to up 80 * the chip setting when fixing the bug but they also tweaked some 81 * performance at the same time.. 82 */ 83 84 extern __visible void vide(void); 85 __asm__(".globl vide\n" 86 ".type vide, @function\n" 87 ".align 4\n" 88 "vide: ret\n"); 89 90 static void init_amd_k5(struct cpuinfo_x86 *c) 91 { 92 #ifdef CONFIG_X86_32 93 /* 94 * General Systems BIOSen alias the cpu frequency registers 95 * of the Elan at 0x000df000. Unfortunately, one of the Linux 96 * drivers subsequently pokes it, and changes the CPU speed. 97 * Workaround : Remove the unneeded alias. 98 */ 99 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 100 #define CBAR_ENB (0x80000000) 101 #define CBAR_KEY (0X000000CB) 102 if (c->x86_model == 9 || c->x86_model == 10) { 103 if (inl(CBAR) & CBAR_ENB) 104 outl(0 | CBAR_KEY, CBAR); 105 } 106 #endif 107 } 108 109 static void init_amd_k6(struct cpuinfo_x86 *c) 110 { 111 #ifdef CONFIG_X86_32 112 u32 l, h; 113 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 114 115 if (c->x86_model < 6) { 116 /* Based on AMD doc 20734R - June 2000 */ 117 if (c->x86_model == 0) { 118 clear_cpu_cap(c, X86_FEATURE_APIC); 119 set_cpu_cap(c, X86_FEATURE_PGE); 120 } 121 return; 122 } 123 124 if (c->x86_model == 6 && c->x86_stepping == 1) { 125 const int K6_BUG_LOOP = 1000000; 126 int n; 127 void (*f_vide)(void); 128 u64 d, d2; 129 130 pr_info("AMD K6 stepping B detected - "); 131 132 /* 133 * It looks like AMD fixed the 2.6.2 bug and improved indirect 134 * calls at the same time. 135 */ 136 137 n = K6_BUG_LOOP; 138 f_vide = vide; 139 OPTIMIZER_HIDE_VAR(f_vide); 140 d = rdtsc(); 141 while (n--) 142 f_vide(); 143 d2 = rdtsc(); 144 d = d2-d; 145 146 if (d > 20*K6_BUG_LOOP) 147 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 148 else 149 pr_cont("probably OK (after B9730xxxx).\n"); 150 } 151 152 /* K6 with old style WHCR */ 153 if (c->x86_model < 8 || 154 (c->x86_model == 8 && c->x86_stepping < 8)) { 155 /* We can only write allocate on the low 508Mb */ 156 if (mbytes > 508) 157 mbytes = 508; 158 159 rdmsr(MSR_K6_WHCR, l, h); 160 if ((l&0x0000FFFF) == 0) { 161 unsigned long flags; 162 l = (1<<0)|((mbytes/4)<<1); 163 local_irq_save(flags); 164 wbinvd(); 165 wrmsr(MSR_K6_WHCR, l, h); 166 local_irq_restore(flags); 167 pr_info("Enabling old style K6 write allocation for %d Mb\n", 168 mbytes); 169 } 170 return; 171 } 172 173 if ((c->x86_model == 8 && c->x86_stepping > 7) || 174 c->x86_model == 9 || c->x86_model == 13) { 175 /* The more serious chips .. */ 176 177 if (mbytes > 4092) 178 mbytes = 4092; 179 180 rdmsr(MSR_K6_WHCR, l, h); 181 if ((l&0xFFFF0000) == 0) { 182 unsigned long flags; 183 l = ((mbytes>>2)<<22)|(1<<16); 184 local_irq_save(flags); 185 wbinvd(); 186 wrmsr(MSR_K6_WHCR, l, h); 187 local_irq_restore(flags); 188 pr_info("Enabling new style K6 write allocation for %d Mb\n", 189 mbytes); 190 } 191 192 return; 193 } 194 195 if (c->x86_model == 10) { 196 /* AMD Geode LX is model 10 */ 197 /* placeholder for any needed mods */ 198 return; 199 } 200 #endif 201 } 202 203 static void init_amd_k7(struct cpuinfo_x86 *c) 204 { 205 #ifdef CONFIG_X86_32 206 u32 l, h; 207 208 /* 209 * Bit 15 of Athlon specific MSR 15, needs to be 0 210 * to enable SSE on Palomino/Morgan/Barton CPU's. 211 * If the BIOS didn't enable it already, enable it here. 212 */ 213 if (c->x86_model >= 6 && c->x86_model <= 10) { 214 if (!cpu_has(c, X86_FEATURE_XMM)) { 215 pr_info("Enabling disabled K7/SSE Support.\n"); 216 msr_clear_bit(MSR_K7_HWCR, 15); 217 set_cpu_cap(c, X86_FEATURE_XMM); 218 } 219 } 220 221 /* 222 * It's been determined by AMD that Athlons since model 8 stepping 1 223 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 224 * As per AMD technical note 27212 0.2 225 */ 226 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 227 rdmsr(MSR_K7_CLK_CTL, l, h); 228 if ((l & 0xfff00000) != 0x20000000) { 229 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 230 l, ((l & 0x000fffff)|0x20000000)); 231 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 232 } 233 } 234 235 set_cpu_cap(c, X86_FEATURE_K7); 236 237 /* calling is from identify_secondary_cpu() ? */ 238 if (!c->cpu_index) 239 return; 240 241 /* 242 * Certain Athlons might work (for various values of 'work') in SMP 243 * but they are not certified as MP capable. 244 */ 245 /* Athlon 660/661 is valid. */ 246 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 247 (c->x86_stepping == 1))) 248 return; 249 250 /* Duron 670 is valid */ 251 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 252 return; 253 254 /* 255 * Athlon 662, Duron 671, and Athlon >model 7 have capability 256 * bit. It's worth noting that the A5 stepping (662) of some 257 * Athlon XP's have the MP bit set. 258 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 259 * more. 260 */ 261 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 262 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 263 (c->x86_model > 7)) 264 if (cpu_has(c, X86_FEATURE_MP)) 265 return; 266 267 /* If we get here, not a certified SMP capable AMD system. */ 268 269 /* 270 * Don't taint if we are running SMP kernel on a single non-MP 271 * approved Athlon 272 */ 273 WARN_ONCE(1, "WARNING: This combination of AMD" 274 " processors is not suitable for SMP.\n"); 275 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 276 #endif 277 } 278 279 #ifdef CONFIG_NUMA 280 /* 281 * To workaround broken NUMA config. Read the comment in 282 * srat_detect_node(). 283 */ 284 static int nearby_node(int apicid) 285 { 286 int i, node; 287 288 for (i = apicid - 1; i >= 0; i--) { 289 node = __apicid_to_node[i]; 290 if (node != NUMA_NO_NODE && node_online(node)) 291 return node; 292 } 293 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 294 node = __apicid_to_node[i]; 295 if (node != NUMA_NO_NODE && node_online(node)) 296 return node; 297 } 298 return first_node(node_online_map); /* Shouldn't happen */ 299 } 300 #endif 301 302 /* 303 * Fix up cpu_core_id for pre-F17h systems to be in the 304 * [0 .. cores_per_node - 1] range. Not really needed but 305 * kept so as not to break existing setups. 306 */ 307 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 308 { 309 u32 cus_per_node; 310 311 if (c->x86 >= 0x17) 312 return; 313 314 cus_per_node = c->x86_max_cores / nodes_per_socket; 315 c->cpu_core_id %= cus_per_node; 316 } 317 318 /* 319 * Fixup core topology information for 320 * (1) AMD multi-node processors 321 * Assumption: Number of cores in each internal node is the same. 322 * (2) AMD processors supporting compute units 323 */ 324 static void amd_get_topology(struct cpuinfo_x86 *c) 325 { 326 u8 node_id; 327 int cpu = smp_processor_id(); 328 329 /* get information required for multi-node processors */ 330 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 331 int err; 332 u32 eax, ebx, ecx, edx; 333 334 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 335 336 node_id = ecx & 0xff; 337 smp_num_siblings = ((ebx >> 8) & 0xff) + 1; 338 339 if (c->x86 == 0x15) 340 c->cu_id = ebx & 0xff; 341 342 if (c->x86 >= 0x17) { 343 c->cpu_core_id = ebx & 0xff; 344 345 if (smp_num_siblings > 1) 346 c->x86_max_cores /= smp_num_siblings; 347 } 348 349 /* 350 * In case leaf B is available, use it to derive 351 * topology information. 352 */ 353 err = detect_extended_topology(c); 354 if (!err) 355 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 356 357 cacheinfo_amd_init_llc_id(c, cpu, node_id); 358 359 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 360 u64 value; 361 362 rdmsrl(MSR_FAM10H_NODE_ID, value); 363 node_id = value & 7; 364 365 per_cpu(cpu_llc_id, cpu) = node_id; 366 } else 367 return; 368 369 if (nodes_per_socket > 1) { 370 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 371 legacy_fixup_core_id(c); 372 } 373 } 374 375 /* 376 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 377 * Assumes number of cores is a power of two. 378 */ 379 static void amd_detect_cmp(struct cpuinfo_x86 *c) 380 { 381 unsigned bits; 382 int cpu = smp_processor_id(); 383 384 bits = c->x86_coreid_bits; 385 /* Low order bits define the core id (index of core in socket) */ 386 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 387 /* Convert the initial APIC ID into the socket ID */ 388 c->phys_proc_id = c->initial_apicid >> bits; 389 /* use socket ID also for last level cache */ 390 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 391 } 392 393 u16 amd_get_nb_id(int cpu) 394 { 395 return per_cpu(cpu_llc_id, cpu); 396 } 397 EXPORT_SYMBOL_GPL(amd_get_nb_id); 398 399 u32 amd_get_nodes_per_socket(void) 400 { 401 return nodes_per_socket; 402 } 403 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 404 405 static void srat_detect_node(struct cpuinfo_x86 *c) 406 { 407 #ifdef CONFIG_NUMA 408 int cpu = smp_processor_id(); 409 int node; 410 unsigned apicid = c->apicid; 411 412 node = numa_cpu_node(cpu); 413 if (node == NUMA_NO_NODE) 414 node = per_cpu(cpu_llc_id, cpu); 415 416 /* 417 * On multi-fabric platform (e.g. Numascale NumaChip) a 418 * platform-specific handler needs to be called to fixup some 419 * IDs of the CPU. 420 */ 421 if (x86_cpuinit.fixup_cpu_id) 422 x86_cpuinit.fixup_cpu_id(c, node); 423 424 if (!node_online(node)) { 425 /* 426 * Two possibilities here: 427 * 428 * - The CPU is missing memory and no node was created. In 429 * that case try picking one from a nearby CPU. 430 * 431 * - The APIC IDs differ from the HyperTransport node IDs 432 * which the K8 northbridge parsing fills in. Assume 433 * they are all increased by a constant offset, but in 434 * the same order as the HT nodeids. If that doesn't 435 * result in a usable node fall back to the path for the 436 * previous case. 437 * 438 * This workaround operates directly on the mapping between 439 * APIC ID and NUMA node, assuming certain relationship 440 * between APIC ID, HT node ID and NUMA topology. As going 441 * through CPU mapping may alter the outcome, directly 442 * access __apicid_to_node[]. 443 */ 444 int ht_nodeid = c->initial_apicid; 445 446 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 447 node = __apicid_to_node[ht_nodeid]; 448 /* Pick a nearby node */ 449 if (!node_online(node)) 450 node = nearby_node(apicid); 451 } 452 numa_set_node(cpu, node); 453 #endif 454 } 455 456 static void early_init_amd_mc(struct cpuinfo_x86 *c) 457 { 458 #ifdef CONFIG_SMP 459 unsigned bits, ecx; 460 461 /* Multi core CPU? */ 462 if (c->extended_cpuid_level < 0x80000008) 463 return; 464 465 ecx = cpuid_ecx(0x80000008); 466 467 c->x86_max_cores = (ecx & 0xff) + 1; 468 469 /* CPU telling us the core id bits shift? */ 470 bits = (ecx >> 12) & 0xF; 471 472 /* Otherwise recompute */ 473 if (bits == 0) { 474 while ((1 << bits) < c->x86_max_cores) 475 bits++; 476 } 477 478 c->x86_coreid_bits = bits; 479 #endif 480 } 481 482 static void bsp_init_amd(struct cpuinfo_x86 *c) 483 { 484 485 #ifdef CONFIG_X86_64 486 if (c->x86 >= 0xf) { 487 unsigned long long tseg; 488 489 /* 490 * Split up direct mapping around the TSEG SMM area. 491 * Don't do it for gbpages because there seems very little 492 * benefit in doing so. 493 */ 494 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 495 unsigned long pfn = tseg >> PAGE_SHIFT; 496 497 pr_debug("tseg: %010llx\n", tseg); 498 if (pfn_range_is_mapped(pfn, pfn + 1)) 499 set_memory_4k((unsigned long)__va(tseg), 1); 500 } 501 } 502 #endif 503 504 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 505 506 if (c->x86 > 0x10 || 507 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 508 u64 val; 509 510 rdmsrl(MSR_K7_HWCR, val); 511 if (!(val & BIT(24))) 512 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 513 } 514 } 515 516 if (c->x86 == 0x15) { 517 unsigned long upperbit; 518 u32 cpuid, assoc; 519 520 cpuid = cpuid_edx(0x80000005); 521 assoc = cpuid >> 16 & 0xff; 522 upperbit = ((cpuid >> 24) << 10) / assoc; 523 524 va_align.mask = (upperbit - 1) & PAGE_MASK; 525 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 526 527 /* A random value per boot for bit slice [12:upper_bit) */ 528 va_align.bits = get_random_int() & va_align.mask; 529 } 530 531 if (cpu_has(c, X86_FEATURE_MWAITX)) 532 use_mwaitx_delay(); 533 534 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 535 u32 ecx; 536 537 ecx = cpuid_ecx(0x8000001e); 538 nodes_per_socket = ((ecx >> 8) & 7) + 1; 539 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 540 u64 value; 541 542 rdmsrl(MSR_FAM10H_NODE_ID, value); 543 nodes_per_socket = ((value >> 3) & 7) + 1; 544 } 545 546 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 547 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 548 c->x86 >= 0x15 && c->x86 <= 0x17) { 549 unsigned int bit; 550 551 switch (c->x86) { 552 case 0x15: bit = 54; break; 553 case 0x16: bit = 33; break; 554 case 0x17: bit = 10; break; 555 default: return; 556 } 557 /* 558 * Try to cache the base value so further operations can 559 * avoid RMW. If that faults, do not enable SSBD. 560 */ 561 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 562 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 563 setup_force_cpu_cap(X86_FEATURE_SSBD); 564 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 565 } 566 } 567 } 568 569 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 570 { 571 u64 msr; 572 573 /* 574 * BIOS support is required for SME and SEV. 575 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 576 * the SME physical address space reduction value. 577 * If BIOS has not enabled SME then don't advertise the 578 * SME feature (set in scattered.c). 579 * For SEV: If BIOS has not enabled SEV then don't advertise the 580 * SEV feature (set in scattered.c). 581 * 582 * In all cases, since support for SME and SEV requires long mode, 583 * don't advertise the feature under CONFIG_X86_32. 584 */ 585 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 586 /* Check if memory encryption is enabled */ 587 rdmsrl(MSR_K8_SYSCFG, msr); 588 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 589 goto clear_all; 590 591 /* 592 * Always adjust physical address bits. Even though this 593 * will be a value above 32-bits this is still done for 594 * CONFIG_X86_32 so that accurate values are reported. 595 */ 596 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 597 598 if (IS_ENABLED(CONFIG_X86_32)) 599 goto clear_all; 600 601 rdmsrl(MSR_K7_HWCR, msr); 602 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 603 goto clear_sev; 604 605 return; 606 607 clear_all: 608 clear_cpu_cap(c, X86_FEATURE_SME); 609 clear_sev: 610 clear_cpu_cap(c, X86_FEATURE_SEV); 611 } 612 } 613 614 static void early_init_amd(struct cpuinfo_x86 *c) 615 { 616 u32 dummy; 617 618 early_init_amd_mc(c); 619 620 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 621 622 /* 623 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 624 * with P/T states and does not stop in deep C-states 625 */ 626 if (c->x86_power & (1 << 8)) { 627 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 628 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 629 } 630 631 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 632 if (c->x86_power & BIT(12)) 633 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 634 635 #ifdef CONFIG_X86_64 636 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 637 #else 638 /* Set MTRR capability flag if appropriate */ 639 if (c->x86 == 5) 640 if (c->x86_model == 13 || c->x86_model == 9 || 641 (c->x86_model == 8 && c->x86_stepping >= 8)) 642 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 643 #endif 644 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 645 /* 646 * ApicID can always be treated as an 8-bit value for AMD APIC versions 647 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 648 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 649 * after 16h. 650 */ 651 if (boot_cpu_has(X86_FEATURE_APIC)) { 652 if (c->x86 > 0x16) 653 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 654 else if (c->x86 >= 0xf) { 655 /* check CPU config space for extended APIC ID */ 656 unsigned int val; 657 658 val = read_pci_config(0, 24, 0, 0x68); 659 if ((val >> 17 & 0x3) == 0x3) 660 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 661 } 662 } 663 #endif 664 665 /* 666 * This is only needed to tell the kernel whether to use VMCALL 667 * and VMMCALL. VMMCALL is never executed except under virt, so 668 * we can set it unconditionally. 669 */ 670 set_cpu_cap(c, X86_FEATURE_VMMCALL); 671 672 /* F16h erratum 793, CVE-2013-6885 */ 673 if (c->x86 == 0x16 && c->x86_model <= 0xf) 674 msr_set_bit(MSR_AMD64_LS_CFG, 15); 675 676 /* 677 * Check whether the machine is affected by erratum 400. This is 678 * used to select the proper idle routine and to enable the check 679 * whether the machine is affected in arch_post_acpi_init(), which 680 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 681 */ 682 if (cpu_has_amd_erratum(c, amd_erratum_400)) 683 set_cpu_bug(c, X86_BUG_AMD_E400); 684 685 early_detect_mem_encrypt(c); 686 } 687 688 static void init_amd_k8(struct cpuinfo_x86 *c) 689 { 690 u32 level; 691 u64 value; 692 693 /* On C+ stepping K8 rep microcode works well for copy/memset */ 694 level = cpuid_eax(1); 695 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 696 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 697 698 /* 699 * Some BIOSes incorrectly force this feature, but only K8 revision D 700 * (model = 0x14) and later actually support it. 701 * (AMD Erratum #110, docId: 25759). 702 */ 703 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 704 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 705 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 706 value &= ~BIT_64(32); 707 wrmsrl_amd_safe(0xc001100d, value); 708 } 709 } 710 711 if (!c->x86_model_id[0]) 712 strcpy(c->x86_model_id, "Hammer"); 713 714 #ifdef CONFIG_SMP 715 /* 716 * Disable TLB flush filter by setting HWCR.FFDIS on K8 717 * bit 6 of msr C001_0015 718 * 719 * Errata 63 for SH-B3 steppings 720 * Errata 122 for all steppings (F+ have it disabled by default) 721 */ 722 msr_set_bit(MSR_K7_HWCR, 6); 723 #endif 724 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 725 } 726 727 static void init_amd_gh(struct cpuinfo_x86 *c) 728 { 729 #ifdef CONFIG_MMCONF_FAM10H 730 /* do this for boot cpu */ 731 if (c == &boot_cpu_data) 732 check_enable_amd_mmconf_dmi(); 733 734 fam10h_check_enable_mmcfg(); 735 #endif 736 737 /* 738 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 739 * is always needed when GART is enabled, even in a kernel which has no 740 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 741 * If it doesn't, we do it here as suggested by the BKDG. 742 * 743 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 744 */ 745 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 746 747 /* 748 * On family 10h BIOS may not have properly enabled WC+ support, causing 749 * it to be converted to CD memtype. This may result in performance 750 * degradation for certain nested-paging guests. Prevent this conversion 751 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 752 * 753 * NOTE: we want to use the _safe accessors so as not to #GP kvm 754 * guests on older kvm hosts. 755 */ 756 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 757 758 if (cpu_has_amd_erratum(c, amd_erratum_383)) 759 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 760 } 761 762 #define MSR_AMD64_DE_CFG 0xC0011029 763 764 static void init_amd_ln(struct cpuinfo_x86 *c) 765 { 766 /* 767 * Apply erratum 665 fix unconditionally so machines without a BIOS 768 * fix work. 769 */ 770 msr_set_bit(MSR_AMD64_DE_CFG, 31); 771 } 772 773 static void init_amd_bd(struct cpuinfo_x86 *c) 774 { 775 u64 value; 776 777 /* re-enable TopologyExtensions if switched off by BIOS */ 778 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && 779 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 780 781 if (msr_set_bit(0xc0011005, 54) > 0) { 782 rdmsrl(0xc0011005, value); 783 if (value & BIT_64(54)) { 784 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 785 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 786 } 787 } 788 } 789 790 /* 791 * The way access filter has a performance penalty on some workloads. 792 * Disable it on the affected CPUs. 793 */ 794 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 795 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 796 value |= 0x1E; 797 wrmsrl_safe(MSR_F15H_IC_CFG, value); 798 } 799 } 800 } 801 802 static void init_amd_zn(struct cpuinfo_x86 *c) 803 { 804 set_cpu_cap(c, X86_FEATURE_ZEN); 805 /* 806 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects 807 * all up to and including B1. 808 */ 809 if (c->x86_model <= 1 && c->x86_stepping <= 1) 810 set_cpu_cap(c, X86_FEATURE_CPB); 811 } 812 813 static void init_amd(struct cpuinfo_x86 *c) 814 { 815 early_init_amd(c); 816 817 /* 818 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 819 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 820 */ 821 clear_cpu_cap(c, 0*32+31); 822 823 if (c->x86 >= 0x10) 824 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 825 826 /* get apicid instead of initial apic id from cpuid */ 827 c->apicid = hard_smp_processor_id(); 828 829 /* K6s reports MCEs but don't actually have all the MSRs */ 830 if (c->x86 < 6) 831 clear_cpu_cap(c, X86_FEATURE_MCE); 832 833 switch (c->x86) { 834 case 4: init_amd_k5(c); break; 835 case 5: init_amd_k6(c); break; 836 case 6: init_amd_k7(c); break; 837 case 0xf: init_amd_k8(c); break; 838 case 0x10: init_amd_gh(c); break; 839 case 0x12: init_amd_ln(c); break; 840 case 0x15: init_amd_bd(c); break; 841 case 0x17: init_amd_zn(c); break; 842 } 843 844 /* 845 * Enable workaround for FXSAVE leak on CPUs 846 * without a XSaveErPtr feature 847 */ 848 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 849 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 850 851 cpu_detect_cache_sizes(c); 852 853 /* Multi core CPU? */ 854 if (c->extended_cpuid_level >= 0x80000008) { 855 amd_detect_cmp(c); 856 amd_get_topology(c); 857 srat_detect_node(c); 858 } 859 860 #ifdef CONFIG_X86_32 861 detect_ht(c); 862 #endif 863 864 init_amd_cacheinfo(c); 865 866 if (c->x86 >= 0xf) 867 set_cpu_cap(c, X86_FEATURE_K8); 868 869 if (cpu_has(c, X86_FEATURE_XMM2)) { 870 unsigned long long val; 871 int ret; 872 873 /* 874 * A serializing LFENCE has less overhead than MFENCE, so 875 * use it for execution serialization. On families which 876 * don't have that MSR, LFENCE is already serializing. 877 * msr_set_bit() uses the safe accessors, too, even if the MSR 878 * is not present. 879 */ 880 msr_set_bit(MSR_F10H_DECFG, 881 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 882 883 /* 884 * Verify that the MSR write was successful (could be running 885 * under a hypervisor) and only then assume that LFENCE is 886 * serializing. 887 */ 888 ret = rdmsrl_safe(MSR_F10H_DECFG, &val); 889 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { 890 /* A serializing LFENCE stops RDTSC speculation */ 891 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 892 } else { 893 /* MFENCE stops RDTSC speculation */ 894 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 895 } 896 } 897 898 /* 899 * Family 0x12 and above processors have APIC timer 900 * running in deep C states. 901 */ 902 if (c->x86 > 0x11) 903 set_cpu_cap(c, X86_FEATURE_ARAT); 904 905 /* 3DNow or LM implies PREFETCHW */ 906 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 907 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 908 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 909 910 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 911 if (!cpu_has(c, X86_FEATURE_XENPV)) 912 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 913 } 914 915 #ifdef CONFIG_X86_32 916 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 917 { 918 /* AMD errata T13 (order #21922) */ 919 if ((c->x86 == 6)) { 920 /* Duron Rev A0 */ 921 if (c->x86_model == 3 && c->x86_stepping == 0) 922 size = 64; 923 /* Tbird rev A1/A2 */ 924 if (c->x86_model == 4 && 925 (c->x86_stepping == 0 || c->x86_stepping == 1)) 926 size = 256; 927 } 928 return size; 929 } 930 #endif 931 932 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 933 { 934 u32 ebx, eax, ecx, edx; 935 u16 mask = 0xfff; 936 937 if (c->x86 < 0xf) 938 return; 939 940 if (c->extended_cpuid_level < 0x80000006) 941 return; 942 943 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 944 945 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 946 tlb_lli_4k[ENTRIES] = ebx & mask; 947 948 /* 949 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 950 * characteristics from the CPUID function 0x80000005 instead. 951 */ 952 if (c->x86 == 0xf) { 953 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 954 mask = 0xff; 955 } 956 957 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 958 if (!((eax >> 16) & mask)) 959 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 960 else 961 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 962 963 /* a 4M entry uses two 2M entries */ 964 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 965 966 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 967 if (!(eax & mask)) { 968 /* Erratum 658 */ 969 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 970 tlb_lli_2m[ENTRIES] = 1024; 971 } else { 972 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 973 tlb_lli_2m[ENTRIES] = eax & 0xff; 974 } 975 } else 976 tlb_lli_2m[ENTRIES] = eax & mask; 977 978 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 979 } 980 981 static const struct cpu_dev amd_cpu_dev = { 982 .c_vendor = "AMD", 983 .c_ident = { "AuthenticAMD" }, 984 #ifdef CONFIG_X86_32 985 .legacy_models = { 986 { .family = 4, .model_names = 987 { 988 [3] = "486 DX/2", 989 [7] = "486 DX/2-WB", 990 [8] = "486 DX/4", 991 [9] = "486 DX/4-WB", 992 [14] = "Am5x86-WT", 993 [15] = "Am5x86-WB" 994 } 995 }, 996 }, 997 .legacy_cache_size = amd_size_cache, 998 #endif 999 .c_early_init = early_init_amd, 1000 .c_detect_tlb = cpu_detect_tlb_amd, 1001 .c_bsp_init = bsp_init_amd, 1002 .c_init = init_amd, 1003 .c_x86_vendor = X86_VENDOR_AMD, 1004 }; 1005 1006 cpu_dev_register(amd_cpu_dev); 1007 1008 /* 1009 * AMD errata checking 1010 * 1011 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1012 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1013 * have an OSVW id assigned, which it takes as first argument. Both take a 1014 * variable number of family-specific model-stepping ranges created by 1015 * AMD_MODEL_RANGE(). 1016 * 1017 * Example: 1018 * 1019 * const int amd_erratum_319[] = 1020 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1021 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1022 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1023 */ 1024 1025 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1026 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1027 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1028 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1029 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1030 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1031 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1032 1033 static const int amd_erratum_400[] = 1034 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1035 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1036 1037 static const int amd_erratum_383[] = 1038 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1039 1040 1041 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1042 { 1043 int osvw_id = *erratum++; 1044 u32 range; 1045 u32 ms; 1046 1047 if (osvw_id >= 0 && osvw_id < 65536 && 1048 cpu_has(cpu, X86_FEATURE_OSVW)) { 1049 u64 osvw_len; 1050 1051 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1052 if (osvw_id < osvw_len) { 1053 u64 osvw_bits; 1054 1055 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1056 osvw_bits); 1057 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1058 } 1059 } 1060 1061 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1062 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1063 while ((range = *erratum++)) 1064 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1065 (ms >= AMD_MODEL_RANGE_START(range)) && 1066 (ms <= AMD_MODEL_RANGE_END(range))) 1067 return true; 1068 1069 return false; 1070 } 1071 1072 void set_dr_addr_mask(unsigned long mask, int dr) 1073 { 1074 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1075 return; 1076 1077 switch (dr) { 1078 case 0: 1079 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1080 break; 1081 case 1: 1082 case 2: 1083 case 3: 1084 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1085 break; 1086 default: 1087 break; 1088 } 1089 } 1090