1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/mm.h> 4 5 #include <linux/io.h> 6 #include <asm/processor.h> 7 #include <asm/apic.h> 8 #include <asm/cpu.h> 9 #include <asm/pci-direct.h> 10 11 #ifdef CONFIG_X86_64 12 # include <asm/numa_64.h> 13 # include <asm/mmconfig.h> 14 # include <asm/cacheflush.h> 15 #endif 16 17 #include "cpu.h" 18 19 #ifdef CONFIG_X86_32 20 /* 21 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 22 * misexecution of code under Linux. Owners of such processors should 23 * contact AMD for precise details and a CPU swap. 24 * 25 * See http://www.multimania.com/poulot/k6bug.html 26 * http://www.amd.com/K6/k6docs/revgd.html 27 * 28 * The following test is erm.. interesting. AMD neglected to up 29 * the chip setting when fixing the bug but they also tweaked some 30 * performance at the same time.. 31 */ 32 33 extern void vide(void); 34 __asm__(".align 4\nvide: ret"); 35 36 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) 37 { 38 /* 39 * General Systems BIOSen alias the cpu frequency registers 40 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 41 * drivers subsequently pokes it, and changes the CPU speed. 42 * Workaround : Remove the unneeded alias. 43 */ 44 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 45 #define CBAR_ENB (0x80000000) 46 #define CBAR_KEY (0X000000CB) 47 if (c->x86_model == 9 || c->x86_model == 10) { 48 if (inl(CBAR) & CBAR_ENB) 49 outl(0 | CBAR_KEY, CBAR); 50 } 51 } 52 53 54 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) 55 { 56 u32 l, h; 57 int mbytes = num_physpages >> (20-PAGE_SHIFT); 58 59 if (c->x86_model < 6) { 60 /* Based on AMD doc 20734R - June 2000 */ 61 if (c->x86_model == 0) { 62 clear_cpu_cap(c, X86_FEATURE_APIC); 63 set_cpu_cap(c, X86_FEATURE_PGE); 64 } 65 return; 66 } 67 68 if (c->x86_model == 6 && c->x86_mask == 1) { 69 const int K6_BUG_LOOP = 1000000; 70 int n; 71 void (*f_vide)(void); 72 unsigned long d, d2; 73 74 printk(KERN_INFO "AMD K6 stepping B detected - "); 75 76 /* 77 * It looks like AMD fixed the 2.6.2 bug and improved indirect 78 * calls at the same time. 79 */ 80 81 n = K6_BUG_LOOP; 82 f_vide = vide; 83 rdtscl(d); 84 while (n--) 85 f_vide(); 86 rdtscl(d2); 87 d = d2-d; 88 89 if (d > 20*K6_BUG_LOOP) 90 printk(KERN_CONT 91 "system stability may be impaired when more than 32 MB are used.\n"); 92 else 93 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 94 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 95 } 96 97 /* K6 with old style WHCR */ 98 if (c->x86_model < 8 || 99 (c->x86_model == 8 && c->x86_mask < 8)) { 100 /* We can only write allocate on the low 508Mb */ 101 if (mbytes > 508) 102 mbytes = 508; 103 104 rdmsr(MSR_K6_WHCR, l, h); 105 if ((l&0x0000FFFF) == 0) { 106 unsigned long flags; 107 l = (1<<0)|((mbytes/4)<<1); 108 local_irq_save(flags); 109 wbinvd(); 110 wrmsr(MSR_K6_WHCR, l, h); 111 local_irq_restore(flags); 112 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 113 mbytes); 114 } 115 return; 116 } 117 118 if ((c->x86_model == 8 && c->x86_mask > 7) || 119 c->x86_model == 9 || c->x86_model == 13) { 120 /* The more serious chips .. */ 121 122 if (mbytes > 4092) 123 mbytes = 4092; 124 125 rdmsr(MSR_K6_WHCR, l, h); 126 if ((l&0xFFFF0000) == 0) { 127 unsigned long flags; 128 l = ((mbytes>>2)<<22)|(1<<16); 129 local_irq_save(flags); 130 wbinvd(); 131 wrmsr(MSR_K6_WHCR, l, h); 132 local_irq_restore(flags); 133 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 134 mbytes); 135 } 136 137 return; 138 } 139 140 if (c->x86_model == 10) { 141 /* AMD Geode LX is model 10 */ 142 /* placeholder for any needed mods */ 143 return; 144 } 145 } 146 147 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) 148 { 149 #ifdef CONFIG_SMP 150 /* calling is from identify_secondary_cpu() ? */ 151 if (!c->cpu_index) 152 return; 153 154 /* 155 * Certain Athlons might work (for various values of 'work') in SMP 156 * but they are not certified as MP capable. 157 */ 158 /* Athlon 660/661 is valid. */ 159 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 160 (c->x86_mask == 1))) 161 goto valid_k7; 162 163 /* Duron 670 is valid */ 164 if ((c->x86_model == 7) && (c->x86_mask == 0)) 165 goto valid_k7; 166 167 /* 168 * Athlon 662, Duron 671, and Athlon >model 7 have capability 169 * bit. It's worth noting that the A5 stepping (662) of some 170 * Athlon XP's have the MP bit set. 171 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 172 * more. 173 */ 174 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 175 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 176 (c->x86_model > 7)) 177 if (cpu_has_mp) 178 goto valid_k7; 179 180 /* If we get here, not a certified SMP capable AMD system. */ 181 182 /* 183 * Don't taint if we are running SMP kernel on a single non-MP 184 * approved Athlon 185 */ 186 WARN_ONCE(1, "WARNING: This combination of AMD" 187 " processors is not suitable for SMP.\n"); 188 if (!test_taint(TAINT_UNSAFE_SMP)) 189 add_taint(TAINT_UNSAFE_SMP); 190 191 valid_k7: 192 ; 193 #endif 194 } 195 196 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 197 { 198 u32 l, h; 199 200 /* 201 * Bit 15 of Athlon specific MSR 15, needs to be 0 202 * to enable SSE on Palomino/Morgan/Barton CPU's. 203 * If the BIOS didn't enable it already, enable it here. 204 */ 205 if (c->x86_model >= 6 && c->x86_model <= 10) { 206 if (!cpu_has(c, X86_FEATURE_XMM)) { 207 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 208 rdmsr(MSR_K7_HWCR, l, h); 209 l &= ~0x00008000; 210 wrmsr(MSR_K7_HWCR, l, h); 211 set_cpu_cap(c, X86_FEATURE_XMM); 212 } 213 } 214 215 /* 216 * It's been determined by AMD that Athlons since model 8 stepping 1 217 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 218 * As per AMD technical note 27212 0.2 219 */ 220 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 221 rdmsr(MSR_K7_CLK_CTL, l, h); 222 if ((l & 0xfff00000) != 0x20000000) { 223 printk(KERN_INFO 224 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 225 l, ((l & 0x000fffff)|0x20000000)); 226 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 227 } 228 } 229 230 set_cpu_cap(c, X86_FEATURE_K7); 231 232 amd_k7_smp_check(c); 233 } 234 #endif 235 236 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 237 static int __cpuinit nearby_node(int apicid) 238 { 239 int i, node; 240 241 for (i = apicid - 1; i >= 0; i--) { 242 node = apicid_to_node[i]; 243 if (node != NUMA_NO_NODE && node_online(node)) 244 return node; 245 } 246 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 247 node = apicid_to_node[i]; 248 if (node != NUMA_NO_NODE && node_online(node)) 249 return node; 250 } 251 return first_node(node_online_map); /* Shouldn't happen */ 252 } 253 #endif 254 255 /* 256 * Fixup core topology information for 257 * (1) AMD multi-node processors 258 * Assumption: Number of cores in each internal node is the same. 259 * (2) AMD processors supporting compute units 260 */ 261 #ifdef CONFIG_X86_HT 262 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) 263 { 264 u32 nodes; 265 u8 node_id; 266 int cpu = smp_processor_id(); 267 268 /* get information required for multi-node processors */ 269 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 270 u32 eax, ebx, ecx, edx; 271 272 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 273 nodes = ((ecx >> 8) & 7) + 1; 274 node_id = ecx & 7; 275 276 /* get compute unit information */ 277 smp_num_siblings = ((ebx >> 8) & 3) + 1; 278 c->compute_unit_id = ebx & 0xff; 279 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 280 u64 value; 281 282 rdmsrl(MSR_FAM10H_NODE_ID, value); 283 nodes = ((value >> 3) & 7) + 1; 284 node_id = value & 7; 285 } else 286 return; 287 288 /* fixup multi-node processor information */ 289 if (nodes > 1) { 290 u32 cores_per_node; 291 292 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 293 cores_per_node = c->x86_max_cores / nodes; 294 295 /* store NodeID, use llc_shared_map to store sibling info */ 296 per_cpu(cpu_llc_id, cpu) = node_id; 297 298 /* core id to be in range from 0 to (cores_per_node - 1) */ 299 c->cpu_core_id = c->cpu_core_id % cores_per_node; 300 } 301 } 302 #endif 303 304 /* 305 * On a AMD dual core setup the lower bits of the APIC id distingush the cores. 306 * Assumes number of cores is a power of two. 307 */ 308 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 309 { 310 #ifdef CONFIG_X86_HT 311 unsigned bits; 312 int cpu = smp_processor_id(); 313 314 bits = c->x86_coreid_bits; 315 /* Low order bits define the core id (index of core in socket) */ 316 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 317 /* Convert the initial APIC ID into the socket ID */ 318 c->phys_proc_id = c->initial_apicid >> bits; 319 /* use socket ID also for last level cache */ 320 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 321 amd_get_topology(c); 322 #endif 323 } 324 325 int amd_get_nb_id(int cpu) 326 { 327 int id = 0; 328 #ifdef CONFIG_SMP 329 id = per_cpu(cpu_llc_id, cpu); 330 #endif 331 return id; 332 } 333 EXPORT_SYMBOL_GPL(amd_get_nb_id); 334 335 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) 336 { 337 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 338 int cpu = smp_processor_id(); 339 int node; 340 unsigned apicid = c->apicid; 341 342 node = per_cpu(cpu_llc_id, cpu); 343 344 if (apicid_to_node[apicid] != NUMA_NO_NODE) 345 node = apicid_to_node[apicid]; 346 if (!node_online(node)) { 347 /* Two possibilities here: 348 - The CPU is missing memory and no node was created. 349 In that case try picking one from a nearby CPU 350 - The APIC IDs differ from the HyperTransport node IDs 351 which the K8 northbridge parsing fills in. 352 Assume they are all increased by a constant offset, 353 but in the same order as the HT nodeids. 354 If that doesn't result in a usable node fall back to the 355 path for the previous case. */ 356 357 int ht_nodeid = c->initial_apicid; 358 359 if (ht_nodeid >= 0 && 360 apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 361 node = apicid_to_node[ht_nodeid]; 362 /* Pick a nearby node */ 363 if (!node_online(node)) 364 node = nearby_node(apicid); 365 } 366 numa_set_node(cpu, node); 367 #endif 368 } 369 370 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 371 { 372 #ifdef CONFIG_X86_HT 373 unsigned bits, ecx; 374 375 /* Multi core CPU? */ 376 if (c->extended_cpuid_level < 0x80000008) 377 return; 378 379 ecx = cpuid_ecx(0x80000008); 380 381 c->x86_max_cores = (ecx & 0xff) + 1; 382 383 /* CPU telling us the core id bits shift? */ 384 bits = (ecx >> 12) & 0xF; 385 386 /* Otherwise recompute */ 387 if (bits == 0) { 388 while ((1 << bits) < c->x86_max_cores) 389 bits++; 390 } 391 392 c->x86_coreid_bits = bits; 393 #endif 394 } 395 396 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 397 { 398 early_init_amd_mc(c); 399 400 /* 401 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 402 * with P/T states and does not stop in deep C-states 403 */ 404 if (c->x86_power & (1 << 8)) { 405 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 406 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 407 } 408 409 #ifdef CONFIG_X86_64 410 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 411 #else 412 /* Set MTRR capability flag if appropriate */ 413 if (c->x86 == 5) 414 if (c->x86_model == 13 || c->x86_model == 9 || 415 (c->x86_model == 8 && c->x86_mask >= 8)) 416 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 417 #endif 418 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 419 /* check CPU config space for extended APIC ID */ 420 if (cpu_has_apic && c->x86 >= 0xf) { 421 unsigned int val; 422 val = read_pci_config(0, 24, 0, 0x68); 423 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 424 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 425 } 426 #endif 427 428 /* We need to do the following only once */ 429 if (c != &boot_cpu_data) 430 return; 431 432 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 433 434 if (c->x86 > 0x10 || 435 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 436 u64 val; 437 438 rdmsrl(MSR_K7_HWCR, val); 439 if (!(val & BIT(24))) 440 printk(KERN_WARNING FW_BUG "TSC doesn't count " 441 "with P0 frequency!\n"); 442 } 443 } 444 } 445 446 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 447 { 448 #ifdef CONFIG_SMP 449 unsigned long long value; 450 451 /* 452 * Disable TLB flush filter by setting HWCR.FFDIS on K8 453 * bit 6 of msr C001_0015 454 * 455 * Errata 63 for SH-B3 steppings 456 * Errata 122 for all steppings (F+ have it disabled by default) 457 */ 458 if (c->x86 == 0xf) { 459 rdmsrl(MSR_K7_HWCR, value); 460 value |= 1 << 6; 461 wrmsrl(MSR_K7_HWCR, value); 462 } 463 #endif 464 465 early_init_amd(c); 466 467 /* 468 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 469 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 470 */ 471 clear_cpu_cap(c, 0*32+31); 472 473 #ifdef CONFIG_X86_64 474 /* On C+ stepping K8 rep microcode works well for copy/memset */ 475 if (c->x86 == 0xf) { 476 u32 level; 477 478 level = cpuid_eax(1); 479 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 480 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 481 482 /* 483 * Some BIOSes incorrectly force this feature, but only K8 484 * revision D (model = 0x14) and later actually support it. 485 * (AMD Erratum #110, docId: 25759). 486 */ 487 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 488 u64 val; 489 490 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 491 if (!rdmsrl_amd_safe(0xc001100d, &val)) { 492 val &= ~(1ULL << 32); 493 wrmsrl_amd_safe(0xc001100d, val); 494 } 495 } 496 497 } 498 if (c->x86 >= 0x10) 499 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 500 501 /* get apicid instead of initial apic id from cpuid */ 502 c->apicid = hard_smp_processor_id(); 503 #else 504 505 /* 506 * FIXME: We should handle the K5 here. Set up the write 507 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 508 * no bus pipeline) 509 */ 510 511 switch (c->x86) { 512 case 4: 513 init_amd_k5(c); 514 break; 515 case 5: 516 init_amd_k6(c); 517 break; 518 case 6: /* An Athlon/Duron */ 519 init_amd_k7(c); 520 break; 521 } 522 523 /* K6s reports MCEs but don't actually have all the MSRs */ 524 if (c->x86 < 6) 525 clear_cpu_cap(c, X86_FEATURE_MCE); 526 #endif 527 528 /* Enable workaround for FXSAVE leak */ 529 if (c->x86 >= 6) 530 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 531 532 if (!c->x86_model_id[0]) { 533 switch (c->x86) { 534 case 0xf: 535 /* Should distinguish Models here, but this is only 536 a fallback anyways. */ 537 strcpy(c->x86_model_id, "Hammer"); 538 break; 539 } 540 } 541 542 cpu_detect_cache_sizes(c); 543 544 /* Multi core CPU? */ 545 if (c->extended_cpuid_level >= 0x80000008) { 546 amd_detect_cmp(c); 547 srat_detect_node(c); 548 } 549 550 #ifdef CONFIG_X86_32 551 detect_ht(c); 552 #endif 553 554 if (c->extended_cpuid_level >= 0x80000006) { 555 if (cpuid_edx(0x80000006) & 0xf000) 556 num_cache_leaves = 4; 557 else 558 num_cache_leaves = 3; 559 } 560 561 if (c->x86 >= 0xf) 562 set_cpu_cap(c, X86_FEATURE_K8); 563 564 if (cpu_has_xmm2) { 565 /* MFENCE stops RDTSC speculation */ 566 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 567 } 568 569 #ifdef CONFIG_X86_64 570 if (c->x86 == 0x10) { 571 /* do this for boot cpu */ 572 if (c == &boot_cpu_data) 573 check_enable_amd_mmconf_dmi(); 574 575 fam10h_check_enable_mmcfg(); 576 } 577 578 if (c == &boot_cpu_data && c->x86 >= 0xf) { 579 unsigned long long tseg; 580 581 /* 582 * Split up direct mapping around the TSEG SMM area. 583 * Don't do it for gbpages because there seems very little 584 * benefit in doing so. 585 */ 586 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 587 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 588 if ((tseg>>PMD_SHIFT) < 589 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || 590 ((tseg>>PMD_SHIFT) < 591 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && 592 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) 593 set_memory_4k((unsigned long)__va(tseg), 1); 594 } 595 } 596 #endif 597 } 598 599 #ifdef CONFIG_X86_32 600 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, 601 unsigned int size) 602 { 603 /* AMD errata T13 (order #21922) */ 604 if ((c->x86 == 6)) { 605 /* Duron Rev A0 */ 606 if (c->x86_model == 3 && c->x86_mask == 0) 607 size = 64; 608 /* Tbird rev A1/A2 */ 609 if (c->x86_model == 4 && 610 (c->x86_mask == 0 || c->x86_mask == 1)) 611 size = 256; 612 } 613 return size; 614 } 615 #endif 616 617 static const struct cpu_dev __cpuinitconst amd_cpu_dev = { 618 .c_vendor = "AMD", 619 .c_ident = { "AuthenticAMD" }, 620 #ifdef CONFIG_X86_32 621 .c_models = { 622 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 623 { 624 [3] = "486 DX/2", 625 [7] = "486 DX/2-WB", 626 [8] = "486 DX/4", 627 [9] = "486 DX/4-WB", 628 [14] = "Am5x86-WT", 629 [15] = "Am5x86-WB" 630 } 631 }, 632 }, 633 .c_size_cache = amd_size_cache, 634 #endif 635 .c_early_init = early_init_amd, 636 .c_init = init_amd, 637 .c_x86_vendor = X86_VENDOR_AMD, 638 }; 639 640 cpu_dev_register(amd_cpu_dev); 641 642 /* 643 * AMD errata checking 644 * 645 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 646 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 647 * have an OSVW id assigned, which it takes as first argument. Both take a 648 * variable number of family-specific model-stepping ranges created by 649 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const 650 * int[] in arch/x86/include/asm/processor.h. 651 * 652 * Example: 653 * 654 * const int amd_erratum_319[] = 655 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 656 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 657 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 658 */ 659 660 const int amd_erratum_400[] = 661 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 662 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 663 EXPORT_SYMBOL_GPL(amd_erratum_400); 664 665 const int amd_erratum_383[] = 666 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 667 EXPORT_SYMBOL_GPL(amd_erratum_383); 668 669 bool cpu_has_amd_erratum(const int *erratum) 670 { 671 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); 672 int osvw_id = *erratum++; 673 u32 range; 674 u32 ms; 675 676 /* 677 * If called early enough that current_cpu_data hasn't been initialized 678 * yet, fall back to boot_cpu_data. 679 */ 680 if (cpu->x86 == 0) 681 cpu = &boot_cpu_data; 682 683 if (cpu->x86_vendor != X86_VENDOR_AMD) 684 return false; 685 686 if (osvw_id >= 0 && osvw_id < 65536 && 687 cpu_has(cpu, X86_FEATURE_OSVW)) { 688 u64 osvw_len; 689 690 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 691 if (osvw_id < osvw_len) { 692 u64 osvw_bits; 693 694 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 695 osvw_bits); 696 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 697 } 698 } 699 700 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 701 ms = (cpu->x86_model << 4) | cpu->x86_mask; 702 while ((range = *erratum++)) 703 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 704 (ms >= AMD_MODEL_RANGE_START(range)) && 705 (ms <= AMD_MODEL_RANGE_END(range))) 706 return true; 707 708 return false; 709 } 710 711 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); 712