1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/random.h> 10 #include <asm/processor.h> 11 #include <asm/apic.h> 12 #include <asm/cacheinfo.h> 13 #include <asm/cpu.h> 14 #include <asm/spec-ctrl.h> 15 #include <asm/smp.h> 16 #include <asm/pci-direct.h> 17 #include <asm/delay.h> 18 #include <asm/debugreg.h> 19 20 #ifdef CONFIG_X86_64 21 # include <asm/mmconfig.h> 22 # include <asm/set_memory.h> 23 #endif 24 25 #include "cpu.h" 26 27 static const int amd_erratum_383[]; 28 static const int amd_erratum_400[]; 29 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 30 31 /* 32 * nodes_per_socket: Stores the number of nodes per socket. 33 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 34 * Node Identifiers[10:8] 35 */ 36 static u32 nodes_per_socket = 1; 37 38 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 39 { 40 u32 gprs[8] = { 0 }; 41 int err; 42 43 WARN_ONCE((boot_cpu_data.x86 != 0xf), 44 "%s should only be used on K8!\n", __func__); 45 46 gprs[1] = msr; 47 gprs[7] = 0x9c5a203a; 48 49 err = rdmsr_safe_regs(gprs); 50 51 *p = gprs[0] | ((u64)gprs[2] << 32); 52 53 return err; 54 } 55 56 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 57 { 58 u32 gprs[8] = { 0 }; 59 60 WARN_ONCE((boot_cpu_data.x86 != 0xf), 61 "%s should only be used on K8!\n", __func__); 62 63 gprs[0] = (u32)val; 64 gprs[1] = msr; 65 gprs[2] = val >> 32; 66 gprs[7] = 0x9c5a203a; 67 68 return wrmsr_safe_regs(gprs); 69 } 70 71 /* 72 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 73 * misexecution of code under Linux. Owners of such processors should 74 * contact AMD for precise details and a CPU swap. 75 * 76 * See http://www.multimania.com/poulot/k6bug.html 77 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 78 * (Publication # 21266 Issue Date: August 1998) 79 * 80 * The following test is erm.. interesting. AMD neglected to up 81 * the chip setting when fixing the bug but they also tweaked some 82 * performance at the same time.. 83 */ 84 85 extern __visible void vide(void); 86 __asm__(".globl vide\n" 87 ".type vide, @function\n" 88 ".align 4\n" 89 "vide: ret\n"); 90 91 static void init_amd_k5(struct cpuinfo_x86 *c) 92 { 93 #ifdef CONFIG_X86_32 94 /* 95 * General Systems BIOSen alias the cpu frequency registers 96 * of the Elan at 0x000df000. Unfortunately, one of the Linux 97 * drivers subsequently pokes it, and changes the CPU speed. 98 * Workaround : Remove the unneeded alias. 99 */ 100 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 101 #define CBAR_ENB (0x80000000) 102 #define CBAR_KEY (0X000000CB) 103 if (c->x86_model == 9 || c->x86_model == 10) { 104 if (inl(CBAR) & CBAR_ENB) 105 outl(0 | CBAR_KEY, CBAR); 106 } 107 #endif 108 } 109 110 static void init_amd_k6(struct cpuinfo_x86 *c) 111 { 112 #ifdef CONFIG_X86_32 113 u32 l, h; 114 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 115 116 if (c->x86_model < 6) { 117 /* Based on AMD doc 20734R - June 2000 */ 118 if (c->x86_model == 0) { 119 clear_cpu_cap(c, X86_FEATURE_APIC); 120 set_cpu_cap(c, X86_FEATURE_PGE); 121 } 122 return; 123 } 124 125 if (c->x86_model == 6 && c->x86_stepping == 1) { 126 const int K6_BUG_LOOP = 1000000; 127 int n; 128 void (*f_vide)(void); 129 u64 d, d2; 130 131 pr_info("AMD K6 stepping B detected - "); 132 133 /* 134 * It looks like AMD fixed the 2.6.2 bug and improved indirect 135 * calls at the same time. 136 */ 137 138 n = K6_BUG_LOOP; 139 f_vide = vide; 140 OPTIMIZER_HIDE_VAR(f_vide); 141 d = rdtsc(); 142 while (n--) 143 f_vide(); 144 d2 = rdtsc(); 145 d = d2-d; 146 147 if (d > 20*K6_BUG_LOOP) 148 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 149 else 150 pr_cont("probably OK (after B9730xxxx).\n"); 151 } 152 153 /* K6 with old style WHCR */ 154 if (c->x86_model < 8 || 155 (c->x86_model == 8 && c->x86_stepping < 8)) { 156 /* We can only write allocate on the low 508Mb */ 157 if (mbytes > 508) 158 mbytes = 508; 159 160 rdmsr(MSR_K6_WHCR, l, h); 161 if ((l&0x0000FFFF) == 0) { 162 unsigned long flags; 163 l = (1<<0)|((mbytes/4)<<1); 164 local_irq_save(flags); 165 wbinvd(); 166 wrmsr(MSR_K6_WHCR, l, h); 167 local_irq_restore(flags); 168 pr_info("Enabling old style K6 write allocation for %d Mb\n", 169 mbytes); 170 } 171 return; 172 } 173 174 if ((c->x86_model == 8 && c->x86_stepping > 7) || 175 c->x86_model == 9 || c->x86_model == 13) { 176 /* The more serious chips .. */ 177 178 if (mbytes > 4092) 179 mbytes = 4092; 180 181 rdmsr(MSR_K6_WHCR, l, h); 182 if ((l&0xFFFF0000) == 0) { 183 unsigned long flags; 184 l = ((mbytes>>2)<<22)|(1<<16); 185 local_irq_save(flags); 186 wbinvd(); 187 wrmsr(MSR_K6_WHCR, l, h); 188 local_irq_restore(flags); 189 pr_info("Enabling new style K6 write allocation for %d Mb\n", 190 mbytes); 191 } 192 193 return; 194 } 195 196 if (c->x86_model == 10) { 197 /* AMD Geode LX is model 10 */ 198 /* placeholder for any needed mods */ 199 return; 200 } 201 #endif 202 } 203 204 static void init_amd_k7(struct cpuinfo_x86 *c) 205 { 206 #ifdef CONFIG_X86_32 207 u32 l, h; 208 209 /* 210 * Bit 15 of Athlon specific MSR 15, needs to be 0 211 * to enable SSE on Palomino/Morgan/Barton CPU's. 212 * If the BIOS didn't enable it already, enable it here. 213 */ 214 if (c->x86_model >= 6 && c->x86_model <= 10) { 215 if (!cpu_has(c, X86_FEATURE_XMM)) { 216 pr_info("Enabling disabled K7/SSE Support.\n"); 217 msr_clear_bit(MSR_K7_HWCR, 15); 218 set_cpu_cap(c, X86_FEATURE_XMM); 219 } 220 } 221 222 /* 223 * It's been determined by AMD that Athlons since model 8 stepping 1 224 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 225 * As per AMD technical note 27212 0.2 226 */ 227 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 228 rdmsr(MSR_K7_CLK_CTL, l, h); 229 if ((l & 0xfff00000) != 0x20000000) { 230 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 231 l, ((l & 0x000fffff)|0x20000000)); 232 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 233 } 234 } 235 236 /* calling is from identify_secondary_cpu() ? */ 237 if (!c->cpu_index) 238 return; 239 240 /* 241 * Certain Athlons might work (for various values of 'work') in SMP 242 * but they are not certified as MP capable. 243 */ 244 /* Athlon 660/661 is valid. */ 245 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 246 (c->x86_stepping == 1))) 247 return; 248 249 /* Duron 670 is valid */ 250 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 251 return; 252 253 /* 254 * Athlon 662, Duron 671, and Athlon >model 7 have capability 255 * bit. It's worth noting that the A5 stepping (662) of some 256 * Athlon XP's have the MP bit set. 257 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 258 * more. 259 */ 260 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 261 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 262 (c->x86_model > 7)) 263 if (cpu_has(c, X86_FEATURE_MP)) 264 return; 265 266 /* If we get here, not a certified SMP capable AMD system. */ 267 268 /* 269 * Don't taint if we are running SMP kernel on a single non-MP 270 * approved Athlon 271 */ 272 WARN_ONCE(1, "WARNING: This combination of AMD" 273 " processors is not suitable for SMP.\n"); 274 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 275 #endif 276 } 277 278 #ifdef CONFIG_NUMA 279 /* 280 * To workaround broken NUMA config. Read the comment in 281 * srat_detect_node(). 282 */ 283 static int nearby_node(int apicid) 284 { 285 int i, node; 286 287 for (i = apicid - 1; i >= 0; i--) { 288 node = __apicid_to_node[i]; 289 if (node != NUMA_NO_NODE && node_online(node)) 290 return node; 291 } 292 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 293 node = __apicid_to_node[i]; 294 if (node != NUMA_NO_NODE && node_online(node)) 295 return node; 296 } 297 return first_node(node_online_map); /* Shouldn't happen */ 298 } 299 #endif 300 301 /* 302 * Fix up cpu_core_id for pre-F17h systems to be in the 303 * [0 .. cores_per_node - 1] range. Not really needed but 304 * kept so as not to break existing setups. 305 */ 306 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 307 { 308 u32 cus_per_node; 309 310 if (c->x86 >= 0x17) 311 return; 312 313 cus_per_node = c->x86_max_cores / nodes_per_socket; 314 c->cpu_core_id %= cus_per_node; 315 } 316 317 318 static void amd_get_topology_early(struct cpuinfo_x86 *c) 319 { 320 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 321 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 322 } 323 324 /* 325 * Fixup core topology information for 326 * (1) AMD multi-node processors 327 * Assumption: Number of cores in each internal node is the same. 328 * (2) AMD processors supporting compute units 329 */ 330 static void amd_get_topology(struct cpuinfo_x86 *c) 331 { 332 u8 node_id; 333 int cpu = smp_processor_id(); 334 335 /* get information required for multi-node processors */ 336 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 337 int err; 338 u32 eax, ebx, ecx, edx; 339 340 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 341 342 node_id = ecx & 0xff; 343 344 if (c->x86 == 0x15) 345 c->cu_id = ebx & 0xff; 346 347 if (c->x86 >= 0x17) { 348 c->cpu_core_id = ebx & 0xff; 349 350 if (smp_num_siblings > 1) 351 c->x86_max_cores /= smp_num_siblings; 352 } 353 354 /* 355 * In case leaf B is available, use it to derive 356 * topology information. 357 */ 358 err = detect_extended_topology(c); 359 if (!err) 360 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 361 362 cacheinfo_amd_init_llc_id(c, cpu, node_id); 363 364 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 365 u64 value; 366 367 rdmsrl(MSR_FAM10H_NODE_ID, value); 368 node_id = value & 7; 369 370 per_cpu(cpu_llc_id, cpu) = node_id; 371 } else 372 return; 373 374 if (nodes_per_socket > 1) { 375 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 376 legacy_fixup_core_id(c); 377 } 378 } 379 380 /* 381 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 382 * Assumes number of cores is a power of two. 383 */ 384 static void amd_detect_cmp(struct cpuinfo_x86 *c) 385 { 386 unsigned bits; 387 int cpu = smp_processor_id(); 388 389 bits = c->x86_coreid_bits; 390 /* Low order bits define the core id (index of core in socket) */ 391 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 392 /* Convert the initial APIC ID into the socket ID */ 393 c->phys_proc_id = c->initial_apicid >> bits; 394 /* use socket ID also for last level cache */ 395 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 396 } 397 398 u16 amd_get_nb_id(int cpu) 399 { 400 return per_cpu(cpu_llc_id, cpu); 401 } 402 EXPORT_SYMBOL_GPL(amd_get_nb_id); 403 404 u32 amd_get_nodes_per_socket(void) 405 { 406 return nodes_per_socket; 407 } 408 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 409 410 static void srat_detect_node(struct cpuinfo_x86 *c) 411 { 412 #ifdef CONFIG_NUMA 413 int cpu = smp_processor_id(); 414 int node; 415 unsigned apicid = c->apicid; 416 417 node = numa_cpu_node(cpu); 418 if (node == NUMA_NO_NODE) 419 node = per_cpu(cpu_llc_id, cpu); 420 421 /* 422 * On multi-fabric platform (e.g. Numascale NumaChip) a 423 * platform-specific handler needs to be called to fixup some 424 * IDs of the CPU. 425 */ 426 if (x86_cpuinit.fixup_cpu_id) 427 x86_cpuinit.fixup_cpu_id(c, node); 428 429 if (!node_online(node)) { 430 /* 431 * Two possibilities here: 432 * 433 * - The CPU is missing memory and no node was created. In 434 * that case try picking one from a nearby CPU. 435 * 436 * - The APIC IDs differ from the HyperTransport node IDs 437 * which the K8 northbridge parsing fills in. Assume 438 * they are all increased by a constant offset, but in 439 * the same order as the HT nodeids. If that doesn't 440 * result in a usable node fall back to the path for the 441 * previous case. 442 * 443 * This workaround operates directly on the mapping between 444 * APIC ID and NUMA node, assuming certain relationship 445 * between APIC ID, HT node ID and NUMA topology. As going 446 * through CPU mapping may alter the outcome, directly 447 * access __apicid_to_node[]. 448 */ 449 int ht_nodeid = c->initial_apicid; 450 451 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 452 node = __apicid_to_node[ht_nodeid]; 453 /* Pick a nearby node */ 454 if (!node_online(node)) 455 node = nearby_node(apicid); 456 } 457 numa_set_node(cpu, node); 458 #endif 459 } 460 461 static void early_init_amd_mc(struct cpuinfo_x86 *c) 462 { 463 #ifdef CONFIG_SMP 464 unsigned bits, ecx; 465 466 /* Multi core CPU? */ 467 if (c->extended_cpuid_level < 0x80000008) 468 return; 469 470 ecx = cpuid_ecx(0x80000008); 471 472 c->x86_max_cores = (ecx & 0xff) + 1; 473 474 /* CPU telling us the core id bits shift? */ 475 bits = (ecx >> 12) & 0xF; 476 477 /* Otherwise recompute */ 478 if (bits == 0) { 479 while ((1 << bits) < c->x86_max_cores) 480 bits++; 481 } 482 483 c->x86_coreid_bits = bits; 484 #endif 485 } 486 487 static void bsp_init_amd(struct cpuinfo_x86 *c) 488 { 489 490 #ifdef CONFIG_X86_64 491 if (c->x86 >= 0xf) { 492 unsigned long long tseg; 493 494 /* 495 * Split up direct mapping around the TSEG SMM area. 496 * Don't do it for gbpages because there seems very little 497 * benefit in doing so. 498 */ 499 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 500 unsigned long pfn = tseg >> PAGE_SHIFT; 501 502 pr_debug("tseg: %010llx\n", tseg); 503 if (pfn_range_is_mapped(pfn, pfn + 1)) 504 set_memory_4k((unsigned long)__va(tseg), 1); 505 } 506 } 507 #endif 508 509 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 510 511 if (c->x86 > 0x10 || 512 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 513 u64 val; 514 515 rdmsrl(MSR_K7_HWCR, val); 516 if (!(val & BIT(24))) 517 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 518 } 519 } 520 521 if (c->x86 == 0x15) { 522 unsigned long upperbit; 523 u32 cpuid, assoc; 524 525 cpuid = cpuid_edx(0x80000005); 526 assoc = cpuid >> 16 & 0xff; 527 upperbit = ((cpuid >> 24) << 10) / assoc; 528 529 va_align.mask = (upperbit - 1) & PAGE_MASK; 530 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 531 532 /* A random value per boot for bit slice [12:upper_bit) */ 533 va_align.bits = get_random_int() & va_align.mask; 534 } 535 536 if (cpu_has(c, X86_FEATURE_MWAITX)) 537 use_mwaitx_delay(); 538 539 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 540 u32 ecx; 541 542 ecx = cpuid_ecx(0x8000001e); 543 nodes_per_socket = ((ecx >> 8) & 7) + 1; 544 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 545 u64 value; 546 547 rdmsrl(MSR_FAM10H_NODE_ID, value); 548 nodes_per_socket = ((value >> 3) & 7) + 1; 549 } 550 551 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 552 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 553 c->x86 >= 0x15 && c->x86 <= 0x17) { 554 unsigned int bit; 555 556 switch (c->x86) { 557 case 0x15: bit = 54; break; 558 case 0x16: bit = 33; break; 559 case 0x17: bit = 10; break; 560 default: return; 561 } 562 /* 563 * Try to cache the base value so further operations can 564 * avoid RMW. If that faults, do not enable SSBD. 565 */ 566 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 567 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 568 setup_force_cpu_cap(X86_FEATURE_SSBD); 569 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 570 } 571 } 572 } 573 574 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 575 { 576 u64 msr; 577 578 /* 579 * BIOS support is required for SME and SEV. 580 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 581 * the SME physical address space reduction value. 582 * If BIOS has not enabled SME then don't advertise the 583 * SME feature (set in scattered.c). 584 * For SEV: If BIOS has not enabled SEV then don't advertise the 585 * SEV feature (set in scattered.c). 586 * 587 * In all cases, since support for SME and SEV requires long mode, 588 * don't advertise the feature under CONFIG_X86_32. 589 */ 590 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 591 /* Check if memory encryption is enabled */ 592 rdmsrl(MSR_K8_SYSCFG, msr); 593 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 594 goto clear_all; 595 596 /* 597 * Always adjust physical address bits. Even though this 598 * will be a value above 32-bits this is still done for 599 * CONFIG_X86_32 so that accurate values are reported. 600 */ 601 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 602 603 if (IS_ENABLED(CONFIG_X86_32)) 604 goto clear_all; 605 606 rdmsrl(MSR_K7_HWCR, msr); 607 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 608 goto clear_sev; 609 610 return; 611 612 clear_all: 613 clear_cpu_cap(c, X86_FEATURE_SME); 614 clear_sev: 615 clear_cpu_cap(c, X86_FEATURE_SEV); 616 } 617 } 618 619 static void early_init_amd(struct cpuinfo_x86 *c) 620 { 621 u64 value; 622 u32 dummy; 623 624 early_init_amd_mc(c); 625 626 #ifdef CONFIG_X86_32 627 if (c->x86 == 6) 628 set_cpu_cap(c, X86_FEATURE_K7); 629 #endif 630 631 if (c->x86 >= 0xf) 632 set_cpu_cap(c, X86_FEATURE_K8); 633 634 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 635 636 /* 637 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 638 * with P/T states and does not stop in deep C-states 639 */ 640 if (c->x86_power & (1 << 8)) { 641 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 642 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 643 } 644 645 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 646 if (c->x86_power & BIT(12)) 647 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 648 649 #ifdef CONFIG_X86_64 650 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 651 #else 652 /* Set MTRR capability flag if appropriate */ 653 if (c->x86 == 5) 654 if (c->x86_model == 13 || c->x86_model == 9 || 655 (c->x86_model == 8 && c->x86_stepping >= 8)) 656 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 657 #endif 658 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 659 /* 660 * ApicID can always be treated as an 8-bit value for AMD APIC versions 661 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 662 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 663 * after 16h. 664 */ 665 if (boot_cpu_has(X86_FEATURE_APIC)) { 666 if (c->x86 > 0x16) 667 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 668 else if (c->x86 >= 0xf) { 669 /* check CPU config space for extended APIC ID */ 670 unsigned int val; 671 672 val = read_pci_config(0, 24, 0, 0x68); 673 if ((val >> 17 & 0x3) == 0x3) 674 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 675 } 676 } 677 #endif 678 679 /* 680 * This is only needed to tell the kernel whether to use VMCALL 681 * and VMMCALL. VMMCALL is never executed except under virt, so 682 * we can set it unconditionally. 683 */ 684 set_cpu_cap(c, X86_FEATURE_VMMCALL); 685 686 /* F16h erratum 793, CVE-2013-6885 */ 687 if (c->x86 == 0x16 && c->x86_model <= 0xf) 688 msr_set_bit(MSR_AMD64_LS_CFG, 15); 689 690 /* 691 * Check whether the machine is affected by erratum 400. This is 692 * used to select the proper idle routine and to enable the check 693 * whether the machine is affected in arch_post_acpi_init(), which 694 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 695 */ 696 if (cpu_has_amd_erratum(c, amd_erratum_400)) 697 set_cpu_bug(c, X86_BUG_AMD_E400); 698 699 early_detect_mem_encrypt(c); 700 701 /* Re-enable TopologyExtensions if switched off by BIOS */ 702 if (c->x86 == 0x15 && 703 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 704 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 705 706 if (msr_set_bit(0xc0011005, 54) > 0) { 707 rdmsrl(0xc0011005, value); 708 if (value & BIT_64(54)) { 709 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 710 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 711 } 712 } 713 } 714 715 amd_get_topology_early(c); 716 } 717 718 static void init_amd_k8(struct cpuinfo_x86 *c) 719 { 720 u32 level; 721 u64 value; 722 723 /* On C+ stepping K8 rep microcode works well for copy/memset */ 724 level = cpuid_eax(1); 725 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 726 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 727 728 /* 729 * Some BIOSes incorrectly force this feature, but only K8 revision D 730 * (model = 0x14) and later actually support it. 731 * (AMD Erratum #110, docId: 25759). 732 */ 733 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 734 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 735 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 736 value &= ~BIT_64(32); 737 wrmsrl_amd_safe(0xc001100d, value); 738 } 739 } 740 741 if (!c->x86_model_id[0]) 742 strcpy(c->x86_model_id, "Hammer"); 743 744 #ifdef CONFIG_SMP 745 /* 746 * Disable TLB flush filter by setting HWCR.FFDIS on K8 747 * bit 6 of msr C001_0015 748 * 749 * Errata 63 for SH-B3 steppings 750 * Errata 122 for all steppings (F+ have it disabled by default) 751 */ 752 msr_set_bit(MSR_K7_HWCR, 6); 753 #endif 754 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 755 } 756 757 static void init_amd_gh(struct cpuinfo_x86 *c) 758 { 759 #ifdef CONFIG_MMCONF_FAM10H 760 /* do this for boot cpu */ 761 if (c == &boot_cpu_data) 762 check_enable_amd_mmconf_dmi(); 763 764 fam10h_check_enable_mmcfg(); 765 #endif 766 767 /* 768 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 769 * is always needed when GART is enabled, even in a kernel which has no 770 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 771 * If it doesn't, we do it here as suggested by the BKDG. 772 * 773 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 774 */ 775 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 776 777 /* 778 * On family 10h BIOS may not have properly enabled WC+ support, causing 779 * it to be converted to CD memtype. This may result in performance 780 * degradation for certain nested-paging guests. Prevent this conversion 781 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 782 * 783 * NOTE: we want to use the _safe accessors so as not to #GP kvm 784 * guests on older kvm hosts. 785 */ 786 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 787 788 if (cpu_has_amd_erratum(c, amd_erratum_383)) 789 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 790 } 791 792 #define MSR_AMD64_DE_CFG 0xC0011029 793 794 static void init_amd_ln(struct cpuinfo_x86 *c) 795 { 796 /* 797 * Apply erratum 665 fix unconditionally so machines without a BIOS 798 * fix work. 799 */ 800 msr_set_bit(MSR_AMD64_DE_CFG, 31); 801 } 802 803 static void init_amd_bd(struct cpuinfo_x86 *c) 804 { 805 u64 value; 806 807 /* 808 * The way access filter has a performance penalty on some workloads. 809 * Disable it on the affected CPUs. 810 */ 811 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 812 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 813 value |= 0x1E; 814 wrmsrl_safe(MSR_F15H_IC_CFG, value); 815 } 816 } 817 } 818 819 static void init_amd_zn(struct cpuinfo_x86 *c) 820 { 821 set_cpu_cap(c, X86_FEATURE_ZEN); 822 823 /* Fix erratum 1076: CPB feature bit not being set in CPUID. */ 824 if (!cpu_has(c, X86_FEATURE_CPB)) 825 set_cpu_cap(c, X86_FEATURE_CPB); 826 } 827 828 static void init_amd(struct cpuinfo_x86 *c) 829 { 830 early_init_amd(c); 831 832 /* 833 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 834 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 835 */ 836 clear_cpu_cap(c, 0*32+31); 837 838 if (c->x86 >= 0x10) 839 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 840 841 /* get apicid instead of initial apic id from cpuid */ 842 c->apicid = hard_smp_processor_id(); 843 844 /* K6s reports MCEs but don't actually have all the MSRs */ 845 if (c->x86 < 6) 846 clear_cpu_cap(c, X86_FEATURE_MCE); 847 848 switch (c->x86) { 849 case 4: init_amd_k5(c); break; 850 case 5: init_amd_k6(c); break; 851 case 6: init_amd_k7(c); break; 852 case 0xf: init_amd_k8(c); break; 853 case 0x10: init_amd_gh(c); break; 854 case 0x12: init_amd_ln(c); break; 855 case 0x15: init_amd_bd(c); break; 856 case 0x17: init_amd_zn(c); break; 857 } 858 859 /* 860 * Enable workaround for FXSAVE leak on CPUs 861 * without a XSaveErPtr feature 862 */ 863 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 864 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 865 866 cpu_detect_cache_sizes(c); 867 868 amd_detect_cmp(c); 869 amd_get_topology(c); 870 srat_detect_node(c); 871 872 init_amd_cacheinfo(c); 873 874 if (cpu_has(c, X86_FEATURE_XMM2)) { 875 unsigned long long val; 876 int ret; 877 878 /* 879 * A serializing LFENCE has less overhead than MFENCE, so 880 * use it for execution serialization. On families which 881 * don't have that MSR, LFENCE is already serializing. 882 * msr_set_bit() uses the safe accessors, too, even if the MSR 883 * is not present. 884 */ 885 msr_set_bit(MSR_F10H_DECFG, 886 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 887 888 /* 889 * Verify that the MSR write was successful (could be running 890 * under a hypervisor) and only then assume that LFENCE is 891 * serializing. 892 */ 893 ret = rdmsrl_safe(MSR_F10H_DECFG, &val); 894 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { 895 /* A serializing LFENCE stops RDTSC speculation */ 896 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 897 } else { 898 /* MFENCE stops RDTSC speculation */ 899 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 900 } 901 } 902 903 /* 904 * Family 0x12 and above processors have APIC timer 905 * running in deep C states. 906 */ 907 if (c->x86 > 0x11) 908 set_cpu_cap(c, X86_FEATURE_ARAT); 909 910 /* 3DNow or LM implies PREFETCHW */ 911 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 912 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 913 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 914 915 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 916 if (!cpu_has(c, X86_FEATURE_XENPV)) 917 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 918 } 919 920 #ifdef CONFIG_X86_32 921 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 922 { 923 /* AMD errata T13 (order #21922) */ 924 if (c->x86 == 6) { 925 /* Duron Rev A0 */ 926 if (c->x86_model == 3 && c->x86_stepping == 0) 927 size = 64; 928 /* Tbird rev A1/A2 */ 929 if (c->x86_model == 4 && 930 (c->x86_stepping == 0 || c->x86_stepping == 1)) 931 size = 256; 932 } 933 return size; 934 } 935 #endif 936 937 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 938 { 939 u32 ebx, eax, ecx, edx; 940 u16 mask = 0xfff; 941 942 if (c->x86 < 0xf) 943 return; 944 945 if (c->extended_cpuid_level < 0x80000006) 946 return; 947 948 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 949 950 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 951 tlb_lli_4k[ENTRIES] = ebx & mask; 952 953 /* 954 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 955 * characteristics from the CPUID function 0x80000005 instead. 956 */ 957 if (c->x86 == 0xf) { 958 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 959 mask = 0xff; 960 } 961 962 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 963 if (!((eax >> 16) & mask)) 964 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 965 else 966 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 967 968 /* a 4M entry uses two 2M entries */ 969 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 970 971 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 972 if (!(eax & mask)) { 973 /* Erratum 658 */ 974 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 975 tlb_lli_2m[ENTRIES] = 1024; 976 } else { 977 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 978 tlb_lli_2m[ENTRIES] = eax & 0xff; 979 } 980 } else 981 tlb_lli_2m[ENTRIES] = eax & mask; 982 983 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 984 } 985 986 static const struct cpu_dev amd_cpu_dev = { 987 .c_vendor = "AMD", 988 .c_ident = { "AuthenticAMD" }, 989 #ifdef CONFIG_X86_32 990 .legacy_models = { 991 { .family = 4, .model_names = 992 { 993 [3] = "486 DX/2", 994 [7] = "486 DX/2-WB", 995 [8] = "486 DX/4", 996 [9] = "486 DX/4-WB", 997 [14] = "Am5x86-WT", 998 [15] = "Am5x86-WB" 999 } 1000 }, 1001 }, 1002 .legacy_cache_size = amd_size_cache, 1003 #endif 1004 .c_early_init = early_init_amd, 1005 .c_detect_tlb = cpu_detect_tlb_amd, 1006 .c_bsp_init = bsp_init_amd, 1007 .c_init = init_amd, 1008 .c_x86_vendor = X86_VENDOR_AMD, 1009 }; 1010 1011 cpu_dev_register(amd_cpu_dev); 1012 1013 /* 1014 * AMD errata checking 1015 * 1016 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1017 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1018 * have an OSVW id assigned, which it takes as first argument. Both take a 1019 * variable number of family-specific model-stepping ranges created by 1020 * AMD_MODEL_RANGE(). 1021 * 1022 * Example: 1023 * 1024 * const int amd_erratum_319[] = 1025 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1026 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1027 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1028 */ 1029 1030 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1031 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1032 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1033 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1034 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1035 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1036 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1037 1038 static const int amd_erratum_400[] = 1039 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1040 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1041 1042 static const int amd_erratum_383[] = 1043 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1044 1045 1046 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1047 { 1048 int osvw_id = *erratum++; 1049 u32 range; 1050 u32 ms; 1051 1052 if (osvw_id >= 0 && osvw_id < 65536 && 1053 cpu_has(cpu, X86_FEATURE_OSVW)) { 1054 u64 osvw_len; 1055 1056 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1057 if (osvw_id < osvw_len) { 1058 u64 osvw_bits; 1059 1060 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1061 osvw_bits); 1062 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1063 } 1064 } 1065 1066 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1067 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1068 while ((range = *erratum++)) 1069 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1070 (ms >= AMD_MODEL_RANGE_START(range)) && 1071 (ms <= AMD_MODEL_RANGE_END(range))) 1072 return true; 1073 1074 return false; 1075 } 1076 1077 void set_dr_addr_mask(unsigned long mask, int dr) 1078 { 1079 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1080 return; 1081 1082 switch (dr) { 1083 case 0: 1084 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1085 break; 1086 case 1: 1087 case 2: 1088 case 3: 1089 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1090 break; 1091 default: 1092 break; 1093 } 1094 } 1095