1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/random.h> 9 #include <asm/processor.h> 10 #include <asm/apic.h> 11 #include <asm/cpu.h> 12 #include <asm/smp.h> 13 #include <asm/pci-direct.h> 14 #include <asm/delay.h> 15 16 #ifdef CONFIG_X86_64 17 # include <asm/mmconfig.h> 18 # include <asm/cacheflush.h> 19 #endif 20 21 #include "cpu.h" 22 23 /* 24 * nodes_per_socket: Stores the number of nodes per socket. 25 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 26 * Node Identifiers[10:8] 27 */ 28 static u32 nodes_per_socket = 1; 29 30 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 31 { 32 u32 gprs[8] = { 0 }; 33 int err; 34 35 WARN_ONCE((boot_cpu_data.x86 != 0xf), 36 "%s should only be used on K8!\n", __func__); 37 38 gprs[1] = msr; 39 gprs[7] = 0x9c5a203a; 40 41 err = rdmsr_safe_regs(gprs); 42 43 *p = gprs[0] | ((u64)gprs[2] << 32); 44 45 return err; 46 } 47 48 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 49 { 50 u32 gprs[8] = { 0 }; 51 52 WARN_ONCE((boot_cpu_data.x86 != 0xf), 53 "%s should only be used on K8!\n", __func__); 54 55 gprs[0] = (u32)val; 56 gprs[1] = msr; 57 gprs[2] = val >> 32; 58 gprs[7] = 0x9c5a203a; 59 60 return wrmsr_safe_regs(gprs); 61 } 62 63 /* 64 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 65 * misexecution of code under Linux. Owners of such processors should 66 * contact AMD for precise details and a CPU swap. 67 * 68 * See http://www.multimania.com/poulot/k6bug.html 69 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 70 * (Publication # 21266 Issue Date: August 1998) 71 * 72 * The following test is erm.. interesting. AMD neglected to up 73 * the chip setting when fixing the bug but they also tweaked some 74 * performance at the same time.. 75 */ 76 77 extern __visible void vide(void); 78 __asm__(".globl vide\n\t.align 4\nvide: ret"); 79 80 static void init_amd_k5(struct cpuinfo_x86 *c) 81 { 82 #ifdef CONFIG_X86_32 83 /* 84 * General Systems BIOSen alias the cpu frequency registers 85 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 86 * drivers subsequently pokes it, and changes the CPU speed. 87 * Workaround : Remove the unneeded alias. 88 */ 89 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 90 #define CBAR_ENB (0x80000000) 91 #define CBAR_KEY (0X000000CB) 92 if (c->x86_model == 9 || c->x86_model == 10) { 93 if (inl(CBAR) & CBAR_ENB) 94 outl(0 | CBAR_KEY, CBAR); 95 } 96 #endif 97 } 98 99 static void init_amd_k6(struct cpuinfo_x86 *c) 100 { 101 #ifdef CONFIG_X86_32 102 u32 l, h; 103 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 104 105 if (c->x86_model < 6) { 106 /* Based on AMD doc 20734R - June 2000 */ 107 if (c->x86_model == 0) { 108 clear_cpu_cap(c, X86_FEATURE_APIC); 109 set_cpu_cap(c, X86_FEATURE_PGE); 110 } 111 return; 112 } 113 114 if (c->x86_model == 6 && c->x86_mask == 1) { 115 const int K6_BUG_LOOP = 1000000; 116 int n; 117 void (*f_vide)(void); 118 u64 d, d2; 119 120 printk(KERN_INFO "AMD K6 stepping B detected - "); 121 122 /* 123 * It looks like AMD fixed the 2.6.2 bug and improved indirect 124 * calls at the same time. 125 */ 126 127 n = K6_BUG_LOOP; 128 f_vide = vide; 129 d = rdtsc(); 130 while (n--) 131 f_vide(); 132 d2 = rdtsc(); 133 d = d2-d; 134 135 if (d > 20*K6_BUG_LOOP) 136 printk(KERN_CONT 137 "system stability may be impaired when more than 32 MB are used.\n"); 138 else 139 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 140 } 141 142 /* K6 with old style WHCR */ 143 if (c->x86_model < 8 || 144 (c->x86_model == 8 && c->x86_mask < 8)) { 145 /* We can only write allocate on the low 508Mb */ 146 if (mbytes > 508) 147 mbytes = 508; 148 149 rdmsr(MSR_K6_WHCR, l, h); 150 if ((l&0x0000FFFF) == 0) { 151 unsigned long flags; 152 l = (1<<0)|((mbytes/4)<<1); 153 local_irq_save(flags); 154 wbinvd(); 155 wrmsr(MSR_K6_WHCR, l, h); 156 local_irq_restore(flags); 157 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 158 mbytes); 159 } 160 return; 161 } 162 163 if ((c->x86_model == 8 && c->x86_mask > 7) || 164 c->x86_model == 9 || c->x86_model == 13) { 165 /* The more serious chips .. */ 166 167 if (mbytes > 4092) 168 mbytes = 4092; 169 170 rdmsr(MSR_K6_WHCR, l, h); 171 if ((l&0xFFFF0000) == 0) { 172 unsigned long flags; 173 l = ((mbytes>>2)<<22)|(1<<16); 174 local_irq_save(flags); 175 wbinvd(); 176 wrmsr(MSR_K6_WHCR, l, h); 177 local_irq_restore(flags); 178 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 179 mbytes); 180 } 181 182 return; 183 } 184 185 if (c->x86_model == 10) { 186 /* AMD Geode LX is model 10 */ 187 /* placeholder for any needed mods */ 188 return; 189 } 190 #endif 191 } 192 193 static void init_amd_k7(struct cpuinfo_x86 *c) 194 { 195 #ifdef CONFIG_X86_32 196 u32 l, h; 197 198 /* 199 * Bit 15 of Athlon specific MSR 15, needs to be 0 200 * to enable SSE on Palomino/Morgan/Barton CPU's. 201 * If the BIOS didn't enable it already, enable it here. 202 */ 203 if (c->x86_model >= 6 && c->x86_model <= 10) { 204 if (!cpu_has(c, X86_FEATURE_XMM)) { 205 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 206 msr_clear_bit(MSR_K7_HWCR, 15); 207 set_cpu_cap(c, X86_FEATURE_XMM); 208 } 209 } 210 211 /* 212 * It's been determined by AMD that Athlons since model 8 stepping 1 213 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 214 * As per AMD technical note 27212 0.2 215 */ 216 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 217 rdmsr(MSR_K7_CLK_CTL, l, h); 218 if ((l & 0xfff00000) != 0x20000000) { 219 printk(KERN_INFO 220 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 221 l, ((l & 0x000fffff)|0x20000000)); 222 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 223 } 224 } 225 226 set_cpu_cap(c, X86_FEATURE_K7); 227 228 /* calling is from identify_secondary_cpu() ? */ 229 if (!c->cpu_index) 230 return; 231 232 /* 233 * Certain Athlons might work (for various values of 'work') in SMP 234 * but they are not certified as MP capable. 235 */ 236 /* Athlon 660/661 is valid. */ 237 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 238 (c->x86_mask == 1))) 239 return; 240 241 /* Duron 670 is valid */ 242 if ((c->x86_model == 7) && (c->x86_mask == 0)) 243 return; 244 245 /* 246 * Athlon 662, Duron 671, and Athlon >model 7 have capability 247 * bit. It's worth noting that the A5 stepping (662) of some 248 * Athlon XP's have the MP bit set. 249 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 250 * more. 251 */ 252 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 253 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 254 (c->x86_model > 7)) 255 if (cpu_has(c, X86_FEATURE_MP)) 256 return; 257 258 /* If we get here, not a certified SMP capable AMD system. */ 259 260 /* 261 * Don't taint if we are running SMP kernel on a single non-MP 262 * approved Athlon 263 */ 264 WARN_ONCE(1, "WARNING: This combination of AMD" 265 " processors is not suitable for SMP.\n"); 266 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 267 #endif 268 } 269 270 #ifdef CONFIG_NUMA 271 /* 272 * To workaround broken NUMA config. Read the comment in 273 * srat_detect_node(). 274 */ 275 static int nearby_node(int apicid) 276 { 277 int i, node; 278 279 for (i = apicid - 1; i >= 0; i--) { 280 node = __apicid_to_node[i]; 281 if (node != NUMA_NO_NODE && node_online(node)) 282 return node; 283 } 284 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 285 node = __apicid_to_node[i]; 286 if (node != NUMA_NO_NODE && node_online(node)) 287 return node; 288 } 289 return first_node(node_online_map); /* Shouldn't happen */ 290 } 291 #endif 292 293 /* 294 * Fixup core topology information for 295 * (1) AMD multi-node processors 296 * Assumption: Number of cores in each internal node is the same. 297 * (2) AMD processors supporting compute units 298 */ 299 #ifdef CONFIG_SMP 300 static void amd_get_topology(struct cpuinfo_x86 *c) 301 { 302 u32 cores_per_cu = 1; 303 u8 node_id; 304 int cpu = smp_processor_id(); 305 306 /* get information required for multi-node processors */ 307 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 308 u32 eax, ebx, ecx, edx; 309 310 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 311 nodes_per_socket = ((ecx >> 8) & 7) + 1; 312 node_id = ecx & 7; 313 314 /* get compute unit information */ 315 smp_num_siblings = ((ebx >> 8) & 3) + 1; 316 c->compute_unit_id = ebx & 0xff; 317 cores_per_cu += ((ebx >> 8) & 3); 318 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 319 u64 value; 320 321 rdmsrl(MSR_FAM10H_NODE_ID, value); 322 nodes_per_socket = ((value >> 3) & 7) + 1; 323 node_id = value & 7; 324 } else 325 return; 326 327 /* fixup multi-node processor information */ 328 if (nodes_per_socket > 1) { 329 u32 cores_per_node; 330 u32 cus_per_node; 331 332 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 333 cores_per_node = c->x86_max_cores / nodes_per_socket; 334 cus_per_node = cores_per_node / cores_per_cu; 335 336 /* store NodeID, use llc_shared_map to store sibling info */ 337 per_cpu(cpu_llc_id, cpu) = node_id; 338 339 /* core id has to be in the [0 .. cores_per_node - 1] range */ 340 c->cpu_core_id %= cores_per_node; 341 c->compute_unit_id %= cus_per_node; 342 } 343 } 344 #endif 345 346 /* 347 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 348 * Assumes number of cores is a power of two. 349 */ 350 static void amd_detect_cmp(struct cpuinfo_x86 *c) 351 { 352 #ifdef CONFIG_SMP 353 unsigned bits; 354 int cpu = smp_processor_id(); 355 unsigned int socket_id, core_complex_id; 356 357 bits = c->x86_coreid_bits; 358 /* Low order bits define the core id (index of core in socket) */ 359 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 360 /* Convert the initial APIC ID into the socket ID */ 361 c->phys_proc_id = c->initial_apicid >> bits; 362 /* use socket ID also for last level cache */ 363 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 364 amd_get_topology(c); 365 366 /* 367 * Fix percpu cpu_llc_id here as LLC topology is different 368 * for Fam17h systems. 369 */ 370 if (c->x86 != 0x17 || !cpuid_edx(0x80000006)) 371 return; 372 373 socket_id = (c->apicid >> bits) - 1; 374 core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3; 375 376 per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id; 377 #endif 378 } 379 380 u16 amd_get_nb_id(int cpu) 381 { 382 u16 id = 0; 383 #ifdef CONFIG_SMP 384 id = per_cpu(cpu_llc_id, cpu); 385 #endif 386 return id; 387 } 388 EXPORT_SYMBOL_GPL(amd_get_nb_id); 389 390 u32 amd_get_nodes_per_socket(void) 391 { 392 return nodes_per_socket; 393 } 394 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 395 396 static void srat_detect_node(struct cpuinfo_x86 *c) 397 { 398 #ifdef CONFIG_NUMA 399 int cpu = smp_processor_id(); 400 int node; 401 unsigned apicid = c->apicid; 402 403 node = numa_cpu_node(cpu); 404 if (node == NUMA_NO_NODE) 405 node = per_cpu(cpu_llc_id, cpu); 406 407 /* 408 * On multi-fabric platform (e.g. Numascale NumaChip) a 409 * platform-specific handler needs to be called to fixup some 410 * IDs of the CPU. 411 */ 412 if (x86_cpuinit.fixup_cpu_id) 413 x86_cpuinit.fixup_cpu_id(c, node); 414 415 if (!node_online(node)) { 416 /* 417 * Two possibilities here: 418 * 419 * - The CPU is missing memory and no node was created. In 420 * that case try picking one from a nearby CPU. 421 * 422 * - The APIC IDs differ from the HyperTransport node IDs 423 * which the K8 northbridge parsing fills in. Assume 424 * they are all increased by a constant offset, but in 425 * the same order as the HT nodeids. If that doesn't 426 * result in a usable node fall back to the path for the 427 * previous case. 428 * 429 * This workaround operates directly on the mapping between 430 * APIC ID and NUMA node, assuming certain relationship 431 * between APIC ID, HT node ID and NUMA topology. As going 432 * through CPU mapping may alter the outcome, directly 433 * access __apicid_to_node[]. 434 */ 435 int ht_nodeid = c->initial_apicid; 436 437 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 438 node = __apicid_to_node[ht_nodeid]; 439 /* Pick a nearby node */ 440 if (!node_online(node)) 441 node = nearby_node(apicid); 442 } 443 numa_set_node(cpu, node); 444 #endif 445 } 446 447 static void early_init_amd_mc(struct cpuinfo_x86 *c) 448 { 449 #ifdef CONFIG_SMP 450 unsigned bits, ecx; 451 452 /* Multi core CPU? */ 453 if (c->extended_cpuid_level < 0x80000008) 454 return; 455 456 ecx = cpuid_ecx(0x80000008); 457 458 c->x86_max_cores = (ecx & 0xff) + 1; 459 460 /* CPU telling us the core id bits shift? */ 461 bits = (ecx >> 12) & 0xF; 462 463 /* Otherwise recompute */ 464 if (bits == 0) { 465 while ((1 << bits) < c->x86_max_cores) 466 bits++; 467 } 468 469 c->x86_coreid_bits = bits; 470 #endif 471 } 472 473 static void bsp_init_amd(struct cpuinfo_x86 *c) 474 { 475 476 #ifdef CONFIG_X86_64 477 if (c->x86 >= 0xf) { 478 unsigned long long tseg; 479 480 /* 481 * Split up direct mapping around the TSEG SMM area. 482 * Don't do it for gbpages because there seems very little 483 * benefit in doing so. 484 */ 485 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 486 unsigned long pfn = tseg >> PAGE_SHIFT; 487 488 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 489 if (pfn_range_is_mapped(pfn, pfn + 1)) 490 set_memory_4k((unsigned long)__va(tseg), 1); 491 } 492 } 493 #endif 494 495 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 496 497 if (c->x86 > 0x10 || 498 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 499 u64 val; 500 501 rdmsrl(MSR_K7_HWCR, val); 502 if (!(val & BIT(24))) 503 printk(KERN_WARNING FW_BUG "TSC doesn't count " 504 "with P0 frequency!\n"); 505 } 506 } 507 508 if (c->x86 == 0x15) { 509 unsigned long upperbit; 510 u32 cpuid, assoc; 511 512 cpuid = cpuid_edx(0x80000005); 513 assoc = cpuid >> 16 & 0xff; 514 upperbit = ((cpuid >> 24) << 10) / assoc; 515 516 va_align.mask = (upperbit - 1) & PAGE_MASK; 517 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 518 519 /* A random value per boot for bit slice [12:upper_bit) */ 520 va_align.bits = get_random_int() & va_align.mask; 521 } 522 523 if (cpu_has(c, X86_FEATURE_MWAITX)) 524 use_mwaitx_delay(); 525 } 526 527 static void early_init_amd(struct cpuinfo_x86 *c) 528 { 529 early_init_amd_mc(c); 530 531 /* 532 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 533 * with P/T states and does not stop in deep C-states 534 */ 535 if (c->x86_power & (1 << 8)) { 536 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 537 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 538 if (!check_tsc_unstable()) 539 set_sched_clock_stable(); 540 } 541 542 #ifdef CONFIG_X86_64 543 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 544 #else 545 /* Set MTRR capability flag if appropriate */ 546 if (c->x86 == 5) 547 if (c->x86_model == 13 || c->x86_model == 9 || 548 (c->x86_model == 8 && c->x86_mask >= 8)) 549 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 550 #endif 551 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 552 /* 553 * ApicID can always be treated as an 8-bit value for AMD APIC versions 554 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 555 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 556 * after 16h. 557 */ 558 if (cpu_has_apic && c->x86 > 0x16) { 559 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 560 } else if (cpu_has_apic && c->x86 >= 0xf) { 561 /* check CPU config space for extended APIC ID */ 562 unsigned int val; 563 val = read_pci_config(0, 24, 0, 0x68); 564 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 565 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 566 } 567 #endif 568 569 /* 570 * This is only needed to tell the kernel whether to use VMCALL 571 * and VMMCALL. VMMCALL is never executed except under virt, so 572 * we can set it unconditionally. 573 */ 574 set_cpu_cap(c, X86_FEATURE_VMMCALL); 575 576 /* F16h erratum 793, CVE-2013-6885 */ 577 if (c->x86 == 0x16 && c->x86_model <= 0xf) 578 msr_set_bit(MSR_AMD64_LS_CFG, 15); 579 } 580 581 static const int amd_erratum_383[]; 582 static const int amd_erratum_400[]; 583 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 584 585 static void init_amd_k8(struct cpuinfo_x86 *c) 586 { 587 u32 level; 588 u64 value; 589 590 /* On C+ stepping K8 rep microcode works well for copy/memset */ 591 level = cpuid_eax(1); 592 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 593 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 594 595 /* 596 * Some BIOSes incorrectly force this feature, but only K8 revision D 597 * (model = 0x14) and later actually support it. 598 * (AMD Erratum #110, docId: 25759). 599 */ 600 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 601 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 602 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 603 value &= ~BIT_64(32); 604 wrmsrl_amd_safe(0xc001100d, value); 605 } 606 } 607 608 if (!c->x86_model_id[0]) 609 strcpy(c->x86_model_id, "Hammer"); 610 611 #ifdef CONFIG_SMP 612 /* 613 * Disable TLB flush filter by setting HWCR.FFDIS on K8 614 * bit 6 of msr C001_0015 615 * 616 * Errata 63 for SH-B3 steppings 617 * Errata 122 for all steppings (F+ have it disabled by default) 618 */ 619 msr_set_bit(MSR_K7_HWCR, 6); 620 #endif 621 } 622 623 static void init_amd_gh(struct cpuinfo_x86 *c) 624 { 625 #ifdef CONFIG_X86_64 626 /* do this for boot cpu */ 627 if (c == &boot_cpu_data) 628 check_enable_amd_mmconf_dmi(); 629 630 fam10h_check_enable_mmcfg(); 631 #endif 632 633 /* 634 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 635 * is always needed when GART is enabled, even in a kernel which has no 636 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 637 * If it doesn't, we do it here as suggested by the BKDG. 638 * 639 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 640 */ 641 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 642 643 /* 644 * On family 10h BIOS may not have properly enabled WC+ support, causing 645 * it to be converted to CD memtype. This may result in performance 646 * degradation for certain nested-paging guests. Prevent this conversion 647 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 648 * 649 * NOTE: we want to use the _safe accessors so as not to #GP kvm 650 * guests on older kvm hosts. 651 */ 652 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 653 654 if (cpu_has_amd_erratum(c, amd_erratum_383)) 655 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 656 } 657 658 static void init_amd_bd(struct cpuinfo_x86 *c) 659 { 660 u64 value; 661 662 /* re-enable TopologyExtensions if switched off by BIOS */ 663 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && 664 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 665 666 if (msr_set_bit(0xc0011005, 54) > 0) { 667 rdmsrl(0xc0011005, value); 668 if (value & BIT_64(54)) { 669 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 670 pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 671 } 672 } 673 } 674 675 /* 676 * The way access filter has a performance penalty on some workloads. 677 * Disable it on the affected CPUs. 678 */ 679 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 680 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 681 value |= 0x1E; 682 wrmsrl_safe(MSR_F15H_IC_CFG, value); 683 } 684 } 685 } 686 687 static void init_amd(struct cpuinfo_x86 *c) 688 { 689 u32 dummy; 690 691 early_init_amd(c); 692 693 /* 694 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 695 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 696 */ 697 clear_cpu_cap(c, 0*32+31); 698 699 if (c->x86 >= 0x10) 700 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 701 702 /* get apicid instead of initial apic id from cpuid */ 703 c->apicid = hard_smp_processor_id(); 704 705 /* K6s reports MCEs but don't actually have all the MSRs */ 706 if (c->x86 < 6) 707 clear_cpu_cap(c, X86_FEATURE_MCE); 708 709 switch (c->x86) { 710 case 4: init_amd_k5(c); break; 711 case 5: init_amd_k6(c); break; 712 case 6: init_amd_k7(c); break; 713 case 0xf: init_amd_k8(c); break; 714 case 0x10: init_amd_gh(c); break; 715 case 0x15: init_amd_bd(c); break; 716 } 717 718 /* Enable workaround for FXSAVE leak */ 719 if (c->x86 >= 6) 720 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 721 722 cpu_detect_cache_sizes(c); 723 724 /* Multi core CPU? */ 725 if (c->extended_cpuid_level >= 0x80000008) { 726 amd_detect_cmp(c); 727 srat_detect_node(c); 728 } 729 730 #ifdef CONFIG_X86_32 731 detect_ht(c); 732 #endif 733 734 init_amd_cacheinfo(c); 735 736 if (c->x86 >= 0xf) 737 set_cpu_cap(c, X86_FEATURE_K8); 738 739 if (cpu_has_xmm2) { 740 /* MFENCE stops RDTSC speculation */ 741 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 742 } 743 744 /* 745 * Family 0x12 and above processors have APIC timer 746 * running in deep C states. 747 */ 748 if (c->x86 > 0x11) 749 set_cpu_cap(c, X86_FEATURE_ARAT); 750 751 if (cpu_has_amd_erratum(c, amd_erratum_400)) 752 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E); 753 754 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 755 756 /* 3DNow or LM implies PREFETCHW */ 757 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 758 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 759 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 760 761 /* AMD CPUs don't reset SS attributes on SYSRET */ 762 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 763 } 764 765 #ifdef CONFIG_X86_32 766 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 767 { 768 /* AMD errata T13 (order #21922) */ 769 if ((c->x86 == 6)) { 770 /* Duron Rev A0 */ 771 if (c->x86_model == 3 && c->x86_mask == 0) 772 size = 64; 773 /* Tbird rev A1/A2 */ 774 if (c->x86_model == 4 && 775 (c->x86_mask == 0 || c->x86_mask == 1)) 776 size = 256; 777 } 778 return size; 779 } 780 #endif 781 782 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 783 { 784 u32 ebx, eax, ecx, edx; 785 u16 mask = 0xfff; 786 787 if (c->x86 < 0xf) 788 return; 789 790 if (c->extended_cpuid_level < 0x80000006) 791 return; 792 793 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 794 795 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 796 tlb_lli_4k[ENTRIES] = ebx & mask; 797 798 /* 799 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 800 * characteristics from the CPUID function 0x80000005 instead. 801 */ 802 if (c->x86 == 0xf) { 803 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 804 mask = 0xff; 805 } 806 807 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 808 if (!((eax >> 16) & mask)) 809 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 810 else 811 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 812 813 /* a 4M entry uses two 2M entries */ 814 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 815 816 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 817 if (!(eax & mask)) { 818 /* Erratum 658 */ 819 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 820 tlb_lli_2m[ENTRIES] = 1024; 821 } else { 822 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 823 tlb_lli_2m[ENTRIES] = eax & 0xff; 824 } 825 } else 826 tlb_lli_2m[ENTRIES] = eax & mask; 827 828 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 829 } 830 831 static const struct cpu_dev amd_cpu_dev = { 832 .c_vendor = "AMD", 833 .c_ident = { "AuthenticAMD" }, 834 #ifdef CONFIG_X86_32 835 .legacy_models = { 836 { .family = 4, .model_names = 837 { 838 [3] = "486 DX/2", 839 [7] = "486 DX/2-WB", 840 [8] = "486 DX/4", 841 [9] = "486 DX/4-WB", 842 [14] = "Am5x86-WT", 843 [15] = "Am5x86-WB" 844 } 845 }, 846 }, 847 .legacy_cache_size = amd_size_cache, 848 #endif 849 .c_early_init = early_init_amd, 850 .c_detect_tlb = cpu_detect_tlb_amd, 851 .c_bsp_init = bsp_init_amd, 852 .c_init = init_amd, 853 .c_x86_vendor = X86_VENDOR_AMD, 854 }; 855 856 cpu_dev_register(amd_cpu_dev); 857 858 /* 859 * AMD errata checking 860 * 861 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 862 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 863 * have an OSVW id assigned, which it takes as first argument. Both take a 864 * variable number of family-specific model-stepping ranges created by 865 * AMD_MODEL_RANGE(). 866 * 867 * Example: 868 * 869 * const int amd_erratum_319[] = 870 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 871 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 872 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 873 */ 874 875 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 876 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 877 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 878 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 879 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 880 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 881 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 882 883 static const int amd_erratum_400[] = 884 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 885 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 886 887 static const int amd_erratum_383[] = 888 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 889 890 891 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 892 { 893 int osvw_id = *erratum++; 894 u32 range; 895 u32 ms; 896 897 if (osvw_id >= 0 && osvw_id < 65536 && 898 cpu_has(cpu, X86_FEATURE_OSVW)) { 899 u64 osvw_len; 900 901 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 902 if (osvw_id < osvw_len) { 903 u64 osvw_bits; 904 905 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 906 osvw_bits); 907 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 908 } 909 } 910 911 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 912 ms = (cpu->x86_model << 4) | cpu->x86_mask; 913 while ((range = *erratum++)) 914 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 915 (ms >= AMD_MODEL_RANGE_START(range)) && 916 (ms <= AMD_MODEL_RANGE_END(range))) 917 return true; 918 919 return false; 920 } 921 922 void set_dr_addr_mask(unsigned long mask, int dr) 923 { 924 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 925 return; 926 927 switch (dr) { 928 case 0: 929 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 930 break; 931 case 1: 932 case 2: 933 case 3: 934 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 935 break; 936 default: 937 break; 938 } 939 } 940