1 #include <linux/export.h> 2 #include <linux/init.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <asm/processor.h> 10 #include <asm/apic.h> 11 #include <asm/cpu.h> 12 #include <asm/pci-direct.h> 13 14 #ifdef CONFIG_X86_64 15 # include <asm/mmconfig.h> 16 # include <asm/cacheflush.h> 17 #endif 18 19 #include "cpu.h" 20 21 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 22 { 23 u32 gprs[8] = { 0 }; 24 int err; 25 26 WARN_ONCE((boot_cpu_data.x86 != 0xf), 27 "%s should only be used on K8!\n", __func__); 28 29 gprs[1] = msr; 30 gprs[7] = 0x9c5a203a; 31 32 err = rdmsr_safe_regs(gprs); 33 34 *p = gprs[0] | ((u64)gprs[2] << 32); 35 36 return err; 37 } 38 39 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 40 { 41 u32 gprs[8] = { 0 }; 42 43 WARN_ONCE((boot_cpu_data.x86 != 0xf), 44 "%s should only be used on K8!\n", __func__); 45 46 gprs[0] = (u32)val; 47 gprs[1] = msr; 48 gprs[2] = val >> 32; 49 gprs[7] = 0x9c5a203a; 50 51 return wrmsr_safe_regs(gprs); 52 } 53 54 #ifdef CONFIG_X86_32 55 /* 56 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 57 * misexecution of code under Linux. Owners of such processors should 58 * contact AMD for precise details and a CPU swap. 59 * 60 * See http://www.multimania.com/poulot/k6bug.html 61 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 62 * (Publication # 21266 Issue Date: August 1998) 63 * 64 * The following test is erm.. interesting. AMD neglected to up 65 * the chip setting when fixing the bug but they also tweaked some 66 * performance at the same time.. 67 */ 68 69 extern __visible void vide(void); 70 __asm__(".globl vide\n\t.align 4\nvide: ret"); 71 72 static void init_amd_k5(struct cpuinfo_x86 *c) 73 { 74 /* 75 * General Systems BIOSen alias the cpu frequency registers 76 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 77 * drivers subsequently pokes it, and changes the CPU speed. 78 * Workaround : Remove the unneeded alias. 79 */ 80 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 81 #define CBAR_ENB (0x80000000) 82 #define CBAR_KEY (0X000000CB) 83 if (c->x86_model == 9 || c->x86_model == 10) { 84 if (inl(CBAR) & CBAR_ENB) 85 outl(0 | CBAR_KEY, CBAR); 86 } 87 } 88 89 90 static void init_amd_k6(struct cpuinfo_x86 *c) 91 { 92 u32 l, h; 93 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 94 95 if (c->x86_model < 6) { 96 /* Based on AMD doc 20734R - June 2000 */ 97 if (c->x86_model == 0) { 98 clear_cpu_cap(c, X86_FEATURE_APIC); 99 set_cpu_cap(c, X86_FEATURE_PGE); 100 } 101 return; 102 } 103 104 if (c->x86_model == 6 && c->x86_mask == 1) { 105 const int K6_BUG_LOOP = 1000000; 106 int n; 107 void (*f_vide)(void); 108 unsigned long d, d2; 109 110 printk(KERN_INFO "AMD K6 stepping B detected - "); 111 112 /* 113 * It looks like AMD fixed the 2.6.2 bug and improved indirect 114 * calls at the same time. 115 */ 116 117 n = K6_BUG_LOOP; 118 f_vide = vide; 119 rdtscl(d); 120 while (n--) 121 f_vide(); 122 rdtscl(d2); 123 d = d2-d; 124 125 if (d > 20*K6_BUG_LOOP) 126 printk(KERN_CONT 127 "system stability may be impaired when more than 32 MB are used.\n"); 128 else 129 printk(KERN_CONT "probably OK (after B9730xxxx).\n"); 130 } 131 132 /* K6 with old style WHCR */ 133 if (c->x86_model < 8 || 134 (c->x86_model == 8 && c->x86_mask < 8)) { 135 /* We can only write allocate on the low 508Mb */ 136 if (mbytes > 508) 137 mbytes = 508; 138 139 rdmsr(MSR_K6_WHCR, l, h); 140 if ((l&0x0000FFFF) == 0) { 141 unsigned long flags; 142 l = (1<<0)|((mbytes/4)<<1); 143 local_irq_save(flags); 144 wbinvd(); 145 wrmsr(MSR_K6_WHCR, l, h); 146 local_irq_restore(flags); 147 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 148 mbytes); 149 } 150 return; 151 } 152 153 if ((c->x86_model == 8 && c->x86_mask > 7) || 154 c->x86_model == 9 || c->x86_model == 13) { 155 /* The more serious chips .. */ 156 157 if (mbytes > 4092) 158 mbytes = 4092; 159 160 rdmsr(MSR_K6_WHCR, l, h); 161 if ((l&0xFFFF0000) == 0) { 162 unsigned long flags; 163 l = ((mbytes>>2)<<22)|(1<<16); 164 local_irq_save(flags); 165 wbinvd(); 166 wrmsr(MSR_K6_WHCR, l, h); 167 local_irq_restore(flags); 168 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 169 mbytes); 170 } 171 172 return; 173 } 174 175 if (c->x86_model == 10) { 176 /* AMD Geode LX is model 10 */ 177 /* placeholder for any needed mods */ 178 return; 179 } 180 } 181 182 static void amd_k7_smp_check(struct cpuinfo_x86 *c) 183 { 184 /* calling is from identify_secondary_cpu() ? */ 185 if (!c->cpu_index) 186 return; 187 188 /* 189 * Certain Athlons might work (for various values of 'work') in SMP 190 * but they are not certified as MP capable. 191 */ 192 /* Athlon 660/661 is valid. */ 193 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 194 (c->x86_mask == 1))) 195 return; 196 197 /* Duron 670 is valid */ 198 if ((c->x86_model == 7) && (c->x86_mask == 0)) 199 return; 200 201 /* 202 * Athlon 662, Duron 671, and Athlon >model 7 have capability 203 * bit. It's worth noting that the A5 stepping (662) of some 204 * Athlon XP's have the MP bit set. 205 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 206 * more. 207 */ 208 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 209 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 210 (c->x86_model > 7)) 211 if (cpu_has_mp) 212 return; 213 214 /* If we get here, not a certified SMP capable AMD system. */ 215 216 /* 217 * Don't taint if we are running SMP kernel on a single non-MP 218 * approved Athlon 219 */ 220 WARN_ONCE(1, "WARNING: This combination of AMD" 221 " processors is not suitable for SMP.\n"); 222 add_taint(TAINT_UNSAFE_SMP, LOCKDEP_NOW_UNRELIABLE); 223 } 224 225 static void init_amd_k7(struct cpuinfo_x86 *c) 226 { 227 u32 l, h; 228 229 /* 230 * Bit 15 of Athlon specific MSR 15, needs to be 0 231 * to enable SSE on Palomino/Morgan/Barton CPU's. 232 * If the BIOS didn't enable it already, enable it here. 233 */ 234 if (c->x86_model >= 6 && c->x86_model <= 10) { 235 if (!cpu_has(c, X86_FEATURE_XMM)) { 236 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 237 rdmsr(MSR_K7_HWCR, l, h); 238 l &= ~0x00008000; 239 wrmsr(MSR_K7_HWCR, l, h); 240 set_cpu_cap(c, X86_FEATURE_XMM); 241 } 242 } 243 244 /* 245 * It's been determined by AMD that Athlons since model 8 stepping 1 246 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 247 * As per AMD technical note 27212 0.2 248 */ 249 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 250 rdmsr(MSR_K7_CLK_CTL, l, h); 251 if ((l & 0xfff00000) != 0x20000000) { 252 printk(KERN_INFO 253 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 254 l, ((l & 0x000fffff)|0x20000000)); 255 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 256 } 257 } 258 259 set_cpu_cap(c, X86_FEATURE_K7); 260 261 amd_k7_smp_check(c); 262 } 263 #endif 264 265 #ifdef CONFIG_NUMA 266 /* 267 * To workaround broken NUMA config. Read the comment in 268 * srat_detect_node(). 269 */ 270 static int nearby_node(int apicid) 271 { 272 int i, node; 273 274 for (i = apicid - 1; i >= 0; i--) { 275 node = __apicid_to_node[i]; 276 if (node != NUMA_NO_NODE && node_online(node)) 277 return node; 278 } 279 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 280 node = __apicid_to_node[i]; 281 if (node != NUMA_NO_NODE && node_online(node)) 282 return node; 283 } 284 return first_node(node_online_map); /* Shouldn't happen */ 285 } 286 #endif 287 288 /* 289 * Fixup core topology information for 290 * (1) AMD multi-node processors 291 * Assumption: Number of cores in each internal node is the same. 292 * (2) AMD processors supporting compute units 293 */ 294 #ifdef CONFIG_X86_HT 295 static void amd_get_topology(struct cpuinfo_x86 *c) 296 { 297 u32 nodes, cores_per_cu = 1; 298 u8 node_id; 299 int cpu = smp_processor_id(); 300 301 /* get information required for multi-node processors */ 302 if (cpu_has_topoext) { 303 u32 eax, ebx, ecx, edx; 304 305 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 306 nodes = ((ecx >> 8) & 7) + 1; 307 node_id = ecx & 7; 308 309 /* get compute unit information */ 310 smp_num_siblings = ((ebx >> 8) & 3) + 1; 311 c->compute_unit_id = ebx & 0xff; 312 cores_per_cu += ((ebx >> 8) & 3); 313 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 314 u64 value; 315 316 rdmsrl(MSR_FAM10H_NODE_ID, value); 317 nodes = ((value >> 3) & 7) + 1; 318 node_id = value & 7; 319 } else 320 return; 321 322 /* fixup multi-node processor information */ 323 if (nodes > 1) { 324 u32 cores_per_node; 325 u32 cus_per_node; 326 327 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 328 cores_per_node = c->x86_max_cores / nodes; 329 cus_per_node = cores_per_node / cores_per_cu; 330 331 /* store NodeID, use llc_shared_map to store sibling info */ 332 per_cpu(cpu_llc_id, cpu) = node_id; 333 334 /* core id has to be in the [0 .. cores_per_node - 1] range */ 335 c->cpu_core_id %= cores_per_node; 336 c->compute_unit_id %= cus_per_node; 337 } 338 } 339 #endif 340 341 /* 342 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 343 * Assumes number of cores is a power of two. 344 */ 345 static void amd_detect_cmp(struct cpuinfo_x86 *c) 346 { 347 #ifdef CONFIG_X86_HT 348 unsigned bits; 349 int cpu = smp_processor_id(); 350 351 bits = c->x86_coreid_bits; 352 /* Low order bits define the core id (index of core in socket) */ 353 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 354 /* Convert the initial APIC ID into the socket ID */ 355 c->phys_proc_id = c->initial_apicid >> bits; 356 /* use socket ID also for last level cache */ 357 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 358 amd_get_topology(c); 359 #endif 360 } 361 362 u16 amd_get_nb_id(int cpu) 363 { 364 u16 id = 0; 365 #ifdef CONFIG_SMP 366 id = per_cpu(cpu_llc_id, cpu); 367 #endif 368 return id; 369 } 370 EXPORT_SYMBOL_GPL(amd_get_nb_id); 371 372 static void srat_detect_node(struct cpuinfo_x86 *c) 373 { 374 #ifdef CONFIG_NUMA 375 int cpu = smp_processor_id(); 376 int node; 377 unsigned apicid = c->apicid; 378 379 node = numa_cpu_node(cpu); 380 if (node == NUMA_NO_NODE) 381 node = per_cpu(cpu_llc_id, cpu); 382 383 /* 384 * On multi-fabric platform (e.g. Numascale NumaChip) a 385 * platform-specific handler needs to be called to fixup some 386 * IDs of the CPU. 387 */ 388 if (x86_cpuinit.fixup_cpu_id) 389 x86_cpuinit.fixup_cpu_id(c, node); 390 391 if (!node_online(node)) { 392 /* 393 * Two possibilities here: 394 * 395 * - The CPU is missing memory and no node was created. In 396 * that case try picking one from a nearby CPU. 397 * 398 * - The APIC IDs differ from the HyperTransport node IDs 399 * which the K8 northbridge parsing fills in. Assume 400 * they are all increased by a constant offset, but in 401 * the same order as the HT nodeids. If that doesn't 402 * result in a usable node fall back to the path for the 403 * previous case. 404 * 405 * This workaround operates directly on the mapping between 406 * APIC ID and NUMA node, assuming certain relationship 407 * between APIC ID, HT node ID and NUMA topology. As going 408 * through CPU mapping may alter the outcome, directly 409 * access __apicid_to_node[]. 410 */ 411 int ht_nodeid = c->initial_apicid; 412 413 if (ht_nodeid >= 0 && 414 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 415 node = __apicid_to_node[ht_nodeid]; 416 /* Pick a nearby node */ 417 if (!node_online(node)) 418 node = nearby_node(apicid); 419 } 420 numa_set_node(cpu, node); 421 #endif 422 } 423 424 static void early_init_amd_mc(struct cpuinfo_x86 *c) 425 { 426 #ifdef CONFIG_X86_HT 427 unsigned bits, ecx; 428 429 /* Multi core CPU? */ 430 if (c->extended_cpuid_level < 0x80000008) 431 return; 432 433 ecx = cpuid_ecx(0x80000008); 434 435 c->x86_max_cores = (ecx & 0xff) + 1; 436 437 /* CPU telling us the core id bits shift? */ 438 bits = (ecx >> 12) & 0xF; 439 440 /* Otherwise recompute */ 441 if (bits == 0) { 442 while ((1 << bits) < c->x86_max_cores) 443 bits++; 444 } 445 446 c->x86_coreid_bits = bits; 447 #endif 448 } 449 450 static void bsp_init_amd(struct cpuinfo_x86 *c) 451 { 452 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 453 454 if (c->x86 > 0x10 || 455 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 456 u64 val; 457 458 rdmsrl(MSR_K7_HWCR, val); 459 if (!(val & BIT(24))) 460 printk(KERN_WARNING FW_BUG "TSC doesn't count " 461 "with P0 frequency!\n"); 462 } 463 } 464 465 if (c->x86 == 0x15) { 466 unsigned long upperbit; 467 u32 cpuid, assoc; 468 469 cpuid = cpuid_edx(0x80000005); 470 assoc = cpuid >> 16 & 0xff; 471 upperbit = ((cpuid >> 24) << 10) / assoc; 472 473 va_align.mask = (upperbit - 1) & PAGE_MASK; 474 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 475 } 476 } 477 478 static void early_init_amd(struct cpuinfo_x86 *c) 479 { 480 early_init_amd_mc(c); 481 482 /* 483 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 484 * with P/T states and does not stop in deep C-states 485 */ 486 if (c->x86_power & (1 << 8)) { 487 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 488 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 489 if (!check_tsc_unstable()) 490 sched_clock_stable = 1; 491 } 492 493 #ifdef CONFIG_X86_64 494 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 495 #else 496 /* Set MTRR capability flag if appropriate */ 497 if (c->x86 == 5) 498 if (c->x86_model == 13 || c->x86_model == 9 || 499 (c->x86_model == 8 && c->x86_mask >= 8)) 500 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 501 #endif 502 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 503 /* check CPU config space for extended APIC ID */ 504 if (cpu_has_apic && c->x86 >= 0xf) { 505 unsigned int val; 506 val = read_pci_config(0, 24, 0, 0x68); 507 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) 508 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 509 } 510 #endif 511 } 512 513 static const int amd_erratum_383[]; 514 static const int amd_erratum_400[]; 515 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 516 517 static void init_amd(struct cpuinfo_x86 *c) 518 { 519 u32 dummy; 520 unsigned long long value; 521 522 #ifdef CONFIG_SMP 523 /* 524 * Disable TLB flush filter by setting HWCR.FFDIS on K8 525 * bit 6 of msr C001_0015 526 * 527 * Errata 63 for SH-B3 steppings 528 * Errata 122 for all steppings (F+ have it disabled by default) 529 */ 530 if (c->x86 == 0xf) { 531 rdmsrl(MSR_K7_HWCR, value); 532 value |= 1 << 6; 533 wrmsrl(MSR_K7_HWCR, value); 534 } 535 #endif 536 537 early_init_amd(c); 538 539 /* 540 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 541 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 542 */ 543 clear_cpu_cap(c, 0*32+31); 544 545 #ifdef CONFIG_X86_64 546 /* On C+ stepping K8 rep microcode works well for copy/memset */ 547 if (c->x86 == 0xf) { 548 u32 level; 549 550 level = cpuid_eax(1); 551 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 552 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 553 554 /* 555 * Some BIOSes incorrectly force this feature, but only K8 556 * revision D (model = 0x14) and later actually support it. 557 * (AMD Erratum #110, docId: 25759). 558 */ 559 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 560 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 561 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 562 value &= ~(1ULL << 32); 563 wrmsrl_amd_safe(0xc001100d, value); 564 } 565 } 566 567 } 568 if (c->x86 >= 0x10) 569 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 570 571 /* get apicid instead of initial apic id from cpuid */ 572 c->apicid = hard_smp_processor_id(); 573 #else 574 575 /* 576 * FIXME: We should handle the K5 here. Set up the write 577 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 578 * no bus pipeline) 579 */ 580 581 switch (c->x86) { 582 case 4: 583 init_amd_k5(c); 584 break; 585 case 5: 586 init_amd_k6(c); 587 break; 588 case 6: /* An Athlon/Duron */ 589 init_amd_k7(c); 590 break; 591 } 592 593 /* K6s reports MCEs but don't actually have all the MSRs */ 594 if (c->x86 < 6) 595 clear_cpu_cap(c, X86_FEATURE_MCE); 596 #endif 597 598 /* Enable workaround for FXSAVE leak */ 599 if (c->x86 >= 6) 600 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 601 602 if (!c->x86_model_id[0]) { 603 switch (c->x86) { 604 case 0xf: 605 /* Should distinguish Models here, but this is only 606 a fallback anyways. */ 607 strcpy(c->x86_model_id, "Hammer"); 608 break; 609 } 610 } 611 612 /* re-enable TopologyExtensions if switched off by BIOS */ 613 if ((c->x86 == 0x15) && 614 (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && 615 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 616 617 if (!rdmsrl_safe(0xc0011005, &value)) { 618 value |= 1ULL << 54; 619 wrmsrl_safe(0xc0011005, value); 620 rdmsrl(0xc0011005, value); 621 if (value & (1ULL << 54)) { 622 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 623 printk(KERN_INFO FW_INFO "CPU: Re-enabling " 624 "disabled Topology Extensions Support\n"); 625 } 626 } 627 } 628 629 /* 630 * The way access filter has a performance penalty on some workloads. 631 * Disable it on the affected CPUs. 632 */ 633 if ((c->x86 == 0x15) && 634 (c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 635 636 if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) { 637 value |= 0x1E; 638 wrmsrl_safe(0xc0011021, value); 639 } 640 } 641 642 cpu_detect_cache_sizes(c); 643 644 /* Multi core CPU? */ 645 if (c->extended_cpuid_level >= 0x80000008) { 646 amd_detect_cmp(c); 647 srat_detect_node(c); 648 } 649 650 #ifdef CONFIG_X86_32 651 detect_ht(c); 652 #endif 653 654 init_amd_cacheinfo(c); 655 656 if (c->x86 >= 0xf) 657 set_cpu_cap(c, X86_FEATURE_K8); 658 659 if (cpu_has_xmm2) { 660 /* MFENCE stops RDTSC speculation */ 661 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 662 } 663 664 #ifdef CONFIG_X86_64 665 if (c->x86 == 0x10) { 666 /* do this for boot cpu */ 667 if (c == &boot_cpu_data) 668 check_enable_amd_mmconf_dmi(); 669 670 fam10h_check_enable_mmcfg(); 671 } 672 673 if (c == &boot_cpu_data && c->x86 >= 0xf) { 674 unsigned long long tseg; 675 676 /* 677 * Split up direct mapping around the TSEG SMM area. 678 * Don't do it for gbpages because there seems very little 679 * benefit in doing so. 680 */ 681 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 682 unsigned long pfn = tseg >> PAGE_SHIFT; 683 684 printk(KERN_DEBUG "tseg: %010llx\n", tseg); 685 if (pfn_range_is_mapped(pfn, pfn + 1)) 686 set_memory_4k((unsigned long)__va(tseg), 1); 687 } 688 } 689 #endif 690 691 /* 692 * Family 0x12 and above processors have APIC timer 693 * running in deep C states. 694 */ 695 if (c->x86 > 0x11) 696 set_cpu_cap(c, X86_FEATURE_ARAT); 697 698 if (c->x86 == 0x10) { 699 /* 700 * Disable GART TLB Walk Errors on Fam10h. We do this here 701 * because this is always needed when GART is enabled, even in a 702 * kernel which has no MCE support built in. 703 * BIOS should disable GartTlbWlk Errors themself. If 704 * it doesn't do it here as suggested by the BKDG. 705 * 706 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 707 */ 708 u64 mask; 709 int err; 710 711 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); 712 if (err == 0) { 713 mask |= (1 << 10); 714 wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask); 715 } 716 717 /* 718 * On family 10h BIOS may not have properly enabled WC+ support, 719 * causing it to be converted to CD memtype. This may result in 720 * performance degradation for certain nested-paging guests. 721 * Prevent this conversion by clearing bit 24 in 722 * MSR_AMD64_BU_CFG2. 723 * 724 * NOTE: we want to use the _safe accessors so as not to #GP kvm 725 * guests on older kvm hosts. 726 */ 727 728 rdmsrl_safe(MSR_AMD64_BU_CFG2, &value); 729 value &= ~(1ULL << 24); 730 wrmsrl_safe(MSR_AMD64_BU_CFG2, value); 731 732 if (cpu_has_amd_erratum(c, amd_erratum_383)) 733 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 734 } 735 736 if (cpu_has_amd_erratum(c, amd_erratum_400)) 737 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E); 738 739 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 740 } 741 742 #ifdef CONFIG_X86_32 743 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 744 { 745 /* AMD errata T13 (order #21922) */ 746 if ((c->x86 == 6)) { 747 /* Duron Rev A0 */ 748 if (c->x86_model == 3 && c->x86_mask == 0) 749 size = 64; 750 /* Tbird rev A1/A2 */ 751 if (c->x86_model == 4 && 752 (c->x86_mask == 0 || c->x86_mask == 1)) 753 size = 256; 754 } 755 return size; 756 } 757 #endif 758 759 static void cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c) 760 { 761 tlb_flushall_shift = 5; 762 763 if (c->x86 <= 0x11) 764 tlb_flushall_shift = 4; 765 } 766 767 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 768 { 769 u32 ebx, eax, ecx, edx; 770 u16 mask = 0xfff; 771 772 if (c->x86 < 0xf) 773 return; 774 775 if (c->extended_cpuid_level < 0x80000006) 776 return; 777 778 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 779 780 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 781 tlb_lli_4k[ENTRIES] = ebx & mask; 782 783 /* 784 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 785 * characteristics from the CPUID function 0x80000005 instead. 786 */ 787 if (c->x86 == 0xf) { 788 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 789 mask = 0xff; 790 } 791 792 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 793 if (!((eax >> 16) & mask)) { 794 u32 a, b, c, d; 795 796 cpuid(0x80000005, &a, &b, &c, &d); 797 tlb_lld_2m[ENTRIES] = (a >> 16) & 0xff; 798 } else { 799 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 800 } 801 802 /* a 4M entry uses two 2M entries */ 803 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 804 805 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 806 if (!(eax & mask)) { 807 /* Erratum 658 */ 808 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 809 tlb_lli_2m[ENTRIES] = 1024; 810 } else { 811 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 812 tlb_lli_2m[ENTRIES] = eax & 0xff; 813 } 814 } else 815 tlb_lli_2m[ENTRIES] = eax & mask; 816 817 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 818 819 cpu_set_tlb_flushall_shift(c); 820 } 821 822 static const struct cpu_dev amd_cpu_dev = { 823 .c_vendor = "AMD", 824 .c_ident = { "AuthenticAMD" }, 825 #ifdef CONFIG_X86_32 826 .legacy_models = { 827 { .family = 4, .model_names = 828 { 829 [3] = "486 DX/2", 830 [7] = "486 DX/2-WB", 831 [8] = "486 DX/4", 832 [9] = "486 DX/4-WB", 833 [14] = "Am5x86-WT", 834 [15] = "Am5x86-WB" 835 } 836 }, 837 }, 838 .legacy_cache_size = amd_size_cache, 839 #endif 840 .c_early_init = early_init_amd, 841 .c_detect_tlb = cpu_detect_tlb_amd, 842 .c_bsp_init = bsp_init_amd, 843 .c_init = init_amd, 844 .c_x86_vendor = X86_VENDOR_AMD, 845 }; 846 847 cpu_dev_register(amd_cpu_dev); 848 849 /* 850 * AMD errata checking 851 * 852 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 853 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 854 * have an OSVW id assigned, which it takes as first argument. Both take a 855 * variable number of family-specific model-stepping ranges created by 856 * AMD_MODEL_RANGE(). 857 * 858 * Example: 859 * 860 * const int amd_erratum_319[] = 861 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 862 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 863 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 864 */ 865 866 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 867 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 868 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 869 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 870 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 871 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 872 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 873 874 static const int amd_erratum_400[] = 875 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 876 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 877 878 static const int amd_erratum_383[] = 879 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 880 881 882 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 883 { 884 int osvw_id = *erratum++; 885 u32 range; 886 u32 ms; 887 888 if (osvw_id >= 0 && osvw_id < 65536 && 889 cpu_has(cpu, X86_FEATURE_OSVW)) { 890 u64 osvw_len; 891 892 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 893 if (osvw_id < osvw_len) { 894 u64 osvw_bits; 895 896 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 897 osvw_bits); 898 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 899 } 900 } 901 902 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 903 ms = (cpu->x86_model << 4) | cpu->x86_mask; 904 while ((range = *erratum++)) 905 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 906 (ms >= AMD_MODEL_RANGE_START(range)) && 907 (ms <= AMD_MODEL_RANGE_END(range))) 908 return true; 909 910 return false; 911 } 912