1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/smp.h> 18 #include <asm/numa.h> 19 #include <asm/pci-direct.h> 20 #include <asm/delay.h> 21 #include <asm/debugreg.h> 22 #include <asm/resctrl.h> 23 24 #ifdef CONFIG_X86_64 25 # include <asm/mmconfig.h> 26 #endif 27 28 #include "cpu.h" 29 30 /* 31 * nodes_per_socket: Stores the number of nodes per socket. 32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 33 * Node Identifiers[10:8] 34 */ 35 static u32 nodes_per_socket = 1; 36 37 /* 38 * AMD errata checking 39 * 40 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 41 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 42 * have an OSVW id assigned, which it takes as first argument. Both take a 43 * variable number of family-specific model-stepping ranges created by 44 * AMD_MODEL_RANGE(). 45 * 46 * Example: 47 * 48 * const int amd_erratum_319[] = 49 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 50 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 51 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 52 */ 53 54 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 55 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 56 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 57 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 58 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 59 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 60 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 61 62 static const int amd_erratum_400[] = 63 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 64 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 65 66 static const int amd_erratum_383[] = 67 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 68 69 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */ 70 static const int amd_erratum_1054[] = 71 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); 72 73 static const int amd_zenbleed[] = 74 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf), 75 AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf), 76 AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf)); 77 78 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 79 { 80 int osvw_id = *erratum++; 81 u32 range; 82 u32 ms; 83 84 if (osvw_id >= 0 && osvw_id < 65536 && 85 cpu_has(cpu, X86_FEATURE_OSVW)) { 86 u64 osvw_len; 87 88 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 89 if (osvw_id < osvw_len) { 90 u64 osvw_bits; 91 92 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 93 osvw_bits); 94 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 95 } 96 } 97 98 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 99 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 100 while ((range = *erratum++)) 101 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 102 (ms >= AMD_MODEL_RANGE_START(range)) && 103 (ms <= AMD_MODEL_RANGE_END(range))) 104 return true; 105 106 return false; 107 } 108 109 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 110 { 111 u32 gprs[8] = { 0 }; 112 int err; 113 114 WARN_ONCE((boot_cpu_data.x86 != 0xf), 115 "%s should only be used on K8!\n", __func__); 116 117 gprs[1] = msr; 118 gprs[7] = 0x9c5a203a; 119 120 err = rdmsr_safe_regs(gprs); 121 122 *p = gprs[0] | ((u64)gprs[2] << 32); 123 124 return err; 125 } 126 127 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 128 { 129 u32 gprs[8] = { 0 }; 130 131 WARN_ONCE((boot_cpu_data.x86 != 0xf), 132 "%s should only be used on K8!\n", __func__); 133 134 gprs[0] = (u32)val; 135 gprs[1] = msr; 136 gprs[2] = val >> 32; 137 gprs[7] = 0x9c5a203a; 138 139 return wrmsr_safe_regs(gprs); 140 } 141 142 /* 143 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 144 * misexecution of code under Linux. Owners of such processors should 145 * contact AMD for precise details and a CPU swap. 146 * 147 * See http://www.multimania.com/poulot/k6bug.html 148 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 149 * (Publication # 21266 Issue Date: August 1998) 150 * 151 * The following test is erm.. interesting. AMD neglected to up 152 * the chip setting when fixing the bug but they also tweaked some 153 * performance at the same time.. 154 */ 155 156 #ifdef CONFIG_X86_32 157 extern __visible void vide(void); 158 __asm__(".text\n" 159 ".globl vide\n" 160 ".type vide, @function\n" 161 ".align 4\n" 162 "vide: ret\n"); 163 #endif 164 165 static void init_amd_k5(struct cpuinfo_x86 *c) 166 { 167 #ifdef CONFIG_X86_32 168 /* 169 * General Systems BIOSen alias the cpu frequency registers 170 * of the Elan at 0x000df000. Unfortunately, one of the Linux 171 * drivers subsequently pokes it, and changes the CPU speed. 172 * Workaround : Remove the unneeded alias. 173 */ 174 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 175 #define CBAR_ENB (0x80000000) 176 #define CBAR_KEY (0X000000CB) 177 if (c->x86_model == 9 || c->x86_model == 10) { 178 if (inl(CBAR) & CBAR_ENB) 179 outl(0 | CBAR_KEY, CBAR); 180 } 181 #endif 182 } 183 184 static void init_amd_k6(struct cpuinfo_x86 *c) 185 { 186 #ifdef CONFIG_X86_32 187 u32 l, h; 188 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 189 190 if (c->x86_model < 6) { 191 /* Based on AMD doc 20734R - June 2000 */ 192 if (c->x86_model == 0) { 193 clear_cpu_cap(c, X86_FEATURE_APIC); 194 set_cpu_cap(c, X86_FEATURE_PGE); 195 } 196 return; 197 } 198 199 if (c->x86_model == 6 && c->x86_stepping == 1) { 200 const int K6_BUG_LOOP = 1000000; 201 int n; 202 void (*f_vide)(void); 203 u64 d, d2; 204 205 pr_info("AMD K6 stepping B detected - "); 206 207 /* 208 * It looks like AMD fixed the 2.6.2 bug and improved indirect 209 * calls at the same time. 210 */ 211 212 n = K6_BUG_LOOP; 213 f_vide = vide; 214 OPTIMIZER_HIDE_VAR(f_vide); 215 d = rdtsc(); 216 while (n--) 217 f_vide(); 218 d2 = rdtsc(); 219 d = d2-d; 220 221 if (d > 20*K6_BUG_LOOP) 222 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 223 else 224 pr_cont("probably OK (after B9730xxxx).\n"); 225 } 226 227 /* K6 with old style WHCR */ 228 if (c->x86_model < 8 || 229 (c->x86_model == 8 && c->x86_stepping < 8)) { 230 /* We can only write allocate on the low 508Mb */ 231 if (mbytes > 508) 232 mbytes = 508; 233 234 rdmsr(MSR_K6_WHCR, l, h); 235 if ((l&0x0000FFFF) == 0) { 236 unsigned long flags; 237 l = (1<<0)|((mbytes/4)<<1); 238 local_irq_save(flags); 239 wbinvd(); 240 wrmsr(MSR_K6_WHCR, l, h); 241 local_irq_restore(flags); 242 pr_info("Enabling old style K6 write allocation for %d Mb\n", 243 mbytes); 244 } 245 return; 246 } 247 248 if ((c->x86_model == 8 && c->x86_stepping > 7) || 249 c->x86_model == 9 || c->x86_model == 13) { 250 /* The more serious chips .. */ 251 252 if (mbytes > 4092) 253 mbytes = 4092; 254 255 rdmsr(MSR_K6_WHCR, l, h); 256 if ((l&0xFFFF0000) == 0) { 257 unsigned long flags; 258 l = ((mbytes>>2)<<22)|(1<<16); 259 local_irq_save(flags); 260 wbinvd(); 261 wrmsr(MSR_K6_WHCR, l, h); 262 local_irq_restore(flags); 263 pr_info("Enabling new style K6 write allocation for %d Mb\n", 264 mbytes); 265 } 266 267 return; 268 } 269 270 if (c->x86_model == 10) { 271 /* AMD Geode LX is model 10 */ 272 /* placeholder for any needed mods */ 273 return; 274 } 275 #endif 276 } 277 278 static void init_amd_k7(struct cpuinfo_x86 *c) 279 { 280 #ifdef CONFIG_X86_32 281 u32 l, h; 282 283 /* 284 * Bit 15 of Athlon specific MSR 15, needs to be 0 285 * to enable SSE on Palomino/Morgan/Barton CPU's. 286 * If the BIOS didn't enable it already, enable it here. 287 */ 288 if (c->x86_model >= 6 && c->x86_model <= 10) { 289 if (!cpu_has(c, X86_FEATURE_XMM)) { 290 pr_info("Enabling disabled K7/SSE Support.\n"); 291 msr_clear_bit(MSR_K7_HWCR, 15); 292 set_cpu_cap(c, X86_FEATURE_XMM); 293 } 294 } 295 296 /* 297 * It's been determined by AMD that Athlons since model 8 stepping 1 298 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 299 * As per AMD technical note 27212 0.2 300 */ 301 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 302 rdmsr(MSR_K7_CLK_CTL, l, h); 303 if ((l & 0xfff00000) != 0x20000000) { 304 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 305 l, ((l & 0x000fffff)|0x20000000)); 306 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 307 } 308 } 309 310 /* calling is from identify_secondary_cpu() ? */ 311 if (!c->cpu_index) 312 return; 313 314 /* 315 * Certain Athlons might work (for various values of 'work') in SMP 316 * but they are not certified as MP capable. 317 */ 318 /* Athlon 660/661 is valid. */ 319 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 320 (c->x86_stepping == 1))) 321 return; 322 323 /* Duron 670 is valid */ 324 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 325 return; 326 327 /* 328 * Athlon 662, Duron 671, and Athlon >model 7 have capability 329 * bit. It's worth noting that the A5 stepping (662) of some 330 * Athlon XP's have the MP bit set. 331 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 332 * more. 333 */ 334 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 335 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 336 (c->x86_model > 7)) 337 if (cpu_has(c, X86_FEATURE_MP)) 338 return; 339 340 /* If we get here, not a certified SMP capable AMD system. */ 341 342 /* 343 * Don't taint if we are running SMP kernel on a single non-MP 344 * approved Athlon 345 */ 346 WARN_ONCE(1, "WARNING: This combination of AMD" 347 " processors is not suitable for SMP.\n"); 348 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 349 #endif 350 } 351 352 #ifdef CONFIG_NUMA 353 /* 354 * To workaround broken NUMA config. Read the comment in 355 * srat_detect_node(). 356 */ 357 static int nearby_node(int apicid) 358 { 359 int i, node; 360 361 for (i = apicid - 1; i >= 0; i--) { 362 node = __apicid_to_node[i]; 363 if (node != NUMA_NO_NODE && node_online(node)) 364 return node; 365 } 366 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 367 node = __apicid_to_node[i]; 368 if (node != NUMA_NO_NODE && node_online(node)) 369 return node; 370 } 371 return first_node(node_online_map); /* Shouldn't happen */ 372 } 373 #endif 374 375 /* 376 * Fix up cpu_core_id for pre-F17h systems to be in the 377 * [0 .. cores_per_node - 1] range. Not really needed but 378 * kept so as not to break existing setups. 379 */ 380 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 381 { 382 u32 cus_per_node; 383 384 if (c->x86 >= 0x17) 385 return; 386 387 cus_per_node = c->x86_max_cores / nodes_per_socket; 388 c->cpu_core_id %= cus_per_node; 389 } 390 391 /* 392 * Fixup core topology information for 393 * (1) AMD multi-node processors 394 * Assumption: Number of cores in each internal node is the same. 395 * (2) AMD processors supporting compute units 396 */ 397 static void amd_get_topology(struct cpuinfo_x86 *c) 398 { 399 int cpu = smp_processor_id(); 400 401 /* get information required for multi-node processors */ 402 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 403 int err; 404 u32 eax, ebx, ecx, edx; 405 406 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 407 408 c->cpu_die_id = ecx & 0xff; 409 410 if (c->x86 == 0x15) 411 c->cu_id = ebx & 0xff; 412 413 if (c->x86 >= 0x17) { 414 c->cpu_core_id = ebx & 0xff; 415 416 if (smp_num_siblings > 1) 417 c->x86_max_cores /= smp_num_siblings; 418 } 419 420 /* 421 * In case leaf B is available, use it to derive 422 * topology information. 423 */ 424 err = detect_extended_topology(c); 425 if (!err) 426 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 427 428 cacheinfo_amd_init_llc_id(c, cpu); 429 430 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 431 u64 value; 432 433 rdmsrl(MSR_FAM10H_NODE_ID, value); 434 c->cpu_die_id = value & 7; 435 436 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id; 437 } else 438 return; 439 440 if (nodes_per_socket > 1) { 441 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 442 legacy_fixup_core_id(c); 443 } 444 } 445 446 /* 447 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 448 * Assumes number of cores is a power of two. 449 */ 450 static void amd_detect_cmp(struct cpuinfo_x86 *c) 451 { 452 unsigned bits; 453 int cpu = smp_processor_id(); 454 455 bits = c->x86_coreid_bits; 456 /* Low order bits define the core id (index of core in socket) */ 457 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 458 /* Convert the initial APIC ID into the socket ID */ 459 c->phys_proc_id = c->initial_apicid >> bits; 460 /* use socket ID also for last level cache */ 461 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id; 462 } 463 464 u32 amd_get_nodes_per_socket(void) 465 { 466 return nodes_per_socket; 467 } 468 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 469 470 static void srat_detect_node(struct cpuinfo_x86 *c) 471 { 472 #ifdef CONFIG_NUMA 473 int cpu = smp_processor_id(); 474 int node; 475 unsigned apicid = c->apicid; 476 477 node = numa_cpu_node(cpu); 478 if (node == NUMA_NO_NODE) 479 node = get_llc_id(cpu); 480 481 /* 482 * On multi-fabric platform (e.g. Numascale NumaChip) a 483 * platform-specific handler needs to be called to fixup some 484 * IDs of the CPU. 485 */ 486 if (x86_cpuinit.fixup_cpu_id) 487 x86_cpuinit.fixup_cpu_id(c, node); 488 489 if (!node_online(node)) { 490 /* 491 * Two possibilities here: 492 * 493 * - The CPU is missing memory and no node was created. In 494 * that case try picking one from a nearby CPU. 495 * 496 * - The APIC IDs differ from the HyperTransport node IDs 497 * which the K8 northbridge parsing fills in. Assume 498 * they are all increased by a constant offset, but in 499 * the same order as the HT nodeids. If that doesn't 500 * result in a usable node fall back to the path for the 501 * previous case. 502 * 503 * This workaround operates directly on the mapping between 504 * APIC ID and NUMA node, assuming certain relationship 505 * between APIC ID, HT node ID and NUMA topology. As going 506 * through CPU mapping may alter the outcome, directly 507 * access __apicid_to_node[]. 508 */ 509 int ht_nodeid = c->initial_apicid; 510 511 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 512 node = __apicid_to_node[ht_nodeid]; 513 /* Pick a nearby node */ 514 if (!node_online(node)) 515 node = nearby_node(apicid); 516 } 517 numa_set_node(cpu, node); 518 #endif 519 } 520 521 static void early_init_amd_mc(struct cpuinfo_x86 *c) 522 { 523 #ifdef CONFIG_SMP 524 unsigned bits, ecx; 525 526 /* Multi core CPU? */ 527 if (c->extended_cpuid_level < 0x80000008) 528 return; 529 530 ecx = cpuid_ecx(0x80000008); 531 532 c->x86_max_cores = (ecx & 0xff) + 1; 533 534 /* CPU telling us the core id bits shift? */ 535 bits = (ecx >> 12) & 0xF; 536 537 /* Otherwise recompute */ 538 if (bits == 0) { 539 while ((1 << bits) < c->x86_max_cores) 540 bits++; 541 } 542 543 c->x86_coreid_bits = bits; 544 #endif 545 } 546 547 static void bsp_init_amd(struct cpuinfo_x86 *c) 548 { 549 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 550 551 if (c->x86 > 0x10 || 552 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 553 u64 val; 554 555 rdmsrl(MSR_K7_HWCR, val); 556 if (!(val & BIT(24))) 557 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 558 } 559 } 560 561 if (c->x86 == 0x15) { 562 unsigned long upperbit; 563 u32 cpuid, assoc; 564 565 cpuid = cpuid_edx(0x80000005); 566 assoc = cpuid >> 16 & 0xff; 567 upperbit = ((cpuid >> 24) << 10) / assoc; 568 569 va_align.mask = (upperbit - 1) & PAGE_MASK; 570 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 571 572 /* A random value per boot for bit slice [12:upper_bit) */ 573 va_align.bits = get_random_u32() & va_align.mask; 574 } 575 576 if (cpu_has(c, X86_FEATURE_MWAITX)) 577 use_mwaitx_delay(); 578 579 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 580 u32 ecx; 581 582 ecx = cpuid_ecx(0x8000001e); 583 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1; 584 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 585 u64 value; 586 587 rdmsrl(MSR_FAM10H_NODE_ID, value); 588 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1; 589 } 590 591 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 592 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 593 c->x86 >= 0x15 && c->x86 <= 0x17) { 594 unsigned int bit; 595 596 switch (c->x86) { 597 case 0x15: bit = 54; break; 598 case 0x16: bit = 33; break; 599 case 0x17: bit = 10; break; 600 default: return; 601 } 602 /* 603 * Try to cache the base value so further operations can 604 * avoid RMW. If that faults, do not enable SSBD. 605 */ 606 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 607 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 608 setup_force_cpu_cap(X86_FEATURE_SSBD); 609 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 610 } 611 } 612 613 resctrl_cpu_detect(c); 614 } 615 616 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 617 { 618 u64 msr; 619 620 /* 621 * BIOS support is required for SME and SEV. 622 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 623 * the SME physical address space reduction value. 624 * If BIOS has not enabled SME then don't advertise the 625 * SME feature (set in scattered.c). 626 * If the kernel has not enabled SME via any means then 627 * don't advertise the SME feature. 628 * For SEV: If BIOS has not enabled SEV then don't advertise the 629 * SEV and SEV_ES feature (set in scattered.c). 630 * 631 * In all cases, since support for SME and SEV requires long mode, 632 * don't advertise the feature under CONFIG_X86_32. 633 */ 634 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 635 /* Check if memory encryption is enabled */ 636 rdmsrl(MSR_AMD64_SYSCFG, msr); 637 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 638 goto clear_all; 639 640 /* 641 * Always adjust physical address bits. Even though this 642 * will be a value above 32-bits this is still done for 643 * CONFIG_X86_32 so that accurate values are reported. 644 */ 645 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 646 647 if (IS_ENABLED(CONFIG_X86_32)) 648 goto clear_all; 649 650 if (!sme_me_mask) 651 setup_clear_cpu_cap(X86_FEATURE_SME); 652 653 rdmsrl(MSR_K7_HWCR, msr); 654 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 655 goto clear_sev; 656 657 return; 658 659 clear_all: 660 setup_clear_cpu_cap(X86_FEATURE_SME); 661 clear_sev: 662 setup_clear_cpu_cap(X86_FEATURE_SEV); 663 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 664 } 665 } 666 667 static void early_init_amd(struct cpuinfo_x86 *c) 668 { 669 u64 value; 670 u32 dummy; 671 672 early_init_amd_mc(c); 673 674 if (c->x86 >= 0xf) 675 set_cpu_cap(c, X86_FEATURE_K8); 676 677 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 678 679 /* 680 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 681 * with P/T states and does not stop in deep C-states 682 */ 683 if (c->x86_power & (1 << 8)) { 684 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 685 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 686 } 687 688 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 689 if (c->x86_power & BIT(12)) 690 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 691 692 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 693 if (c->x86_power & BIT(14)) 694 set_cpu_cap(c, X86_FEATURE_RAPL); 695 696 #ifdef CONFIG_X86_64 697 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 698 #else 699 /* Set MTRR capability flag if appropriate */ 700 if (c->x86 == 5) 701 if (c->x86_model == 13 || c->x86_model == 9 || 702 (c->x86_model == 8 && c->x86_stepping >= 8)) 703 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 704 #endif 705 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 706 /* 707 * ApicID can always be treated as an 8-bit value for AMD APIC versions 708 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 709 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 710 * after 16h. 711 */ 712 if (boot_cpu_has(X86_FEATURE_APIC)) { 713 if (c->x86 > 0x16) 714 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 715 else if (c->x86 >= 0xf) { 716 /* check CPU config space for extended APIC ID */ 717 unsigned int val; 718 719 val = read_pci_config(0, 24, 0, 0x68); 720 if ((val >> 17 & 0x3) == 0x3) 721 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 722 } 723 } 724 #endif 725 726 /* 727 * This is only needed to tell the kernel whether to use VMCALL 728 * and VMMCALL. VMMCALL is never executed except under virt, so 729 * we can set it unconditionally. 730 */ 731 set_cpu_cap(c, X86_FEATURE_VMMCALL); 732 733 /* F16h erratum 793, CVE-2013-6885 */ 734 if (c->x86 == 0x16 && c->x86_model <= 0xf) 735 msr_set_bit(MSR_AMD64_LS_CFG, 15); 736 737 /* 738 * Check whether the machine is affected by erratum 400. This is 739 * used to select the proper idle routine and to enable the check 740 * whether the machine is affected in arch_post_acpi_init(), which 741 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 742 */ 743 if (cpu_has_amd_erratum(c, amd_erratum_400)) 744 set_cpu_bug(c, X86_BUG_AMD_E400); 745 746 early_detect_mem_encrypt(c); 747 748 /* Re-enable TopologyExtensions if switched off by BIOS */ 749 if (c->x86 == 0x15 && 750 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 751 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 752 753 if (msr_set_bit(0xc0011005, 54) > 0) { 754 rdmsrl(0xc0011005, value); 755 if (value & BIT_64(54)) { 756 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 757 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 758 } 759 } 760 } 761 762 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 763 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 764 } 765 766 static void init_amd_k8(struct cpuinfo_x86 *c) 767 { 768 u32 level; 769 u64 value; 770 771 /* On C+ stepping K8 rep microcode works well for copy/memset */ 772 level = cpuid_eax(1); 773 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 774 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 775 776 /* 777 * Some BIOSes incorrectly force this feature, but only K8 revision D 778 * (model = 0x14) and later actually support it. 779 * (AMD Erratum #110, docId: 25759). 780 */ 781 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 782 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 783 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 784 value &= ~BIT_64(32); 785 wrmsrl_amd_safe(0xc001100d, value); 786 } 787 } 788 789 if (!c->x86_model_id[0]) 790 strcpy(c->x86_model_id, "Hammer"); 791 792 #ifdef CONFIG_SMP 793 /* 794 * Disable TLB flush filter by setting HWCR.FFDIS on K8 795 * bit 6 of msr C001_0015 796 * 797 * Errata 63 for SH-B3 steppings 798 * Errata 122 for all steppings (F+ have it disabled by default) 799 */ 800 msr_set_bit(MSR_K7_HWCR, 6); 801 #endif 802 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 803 } 804 805 static void init_amd_gh(struct cpuinfo_x86 *c) 806 { 807 #ifdef CONFIG_MMCONF_FAM10H 808 /* do this for boot cpu */ 809 if (c == &boot_cpu_data) 810 check_enable_amd_mmconf_dmi(); 811 812 fam10h_check_enable_mmcfg(); 813 #endif 814 815 /* 816 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 817 * is always needed when GART is enabled, even in a kernel which has no 818 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 819 * If it doesn't, we do it here as suggested by the BKDG. 820 * 821 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 822 */ 823 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 824 825 /* 826 * On family 10h BIOS may not have properly enabled WC+ support, causing 827 * it to be converted to CD memtype. This may result in performance 828 * degradation for certain nested-paging guests. Prevent this conversion 829 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 830 * 831 * NOTE: we want to use the _safe accessors so as not to #GP kvm 832 * guests on older kvm hosts. 833 */ 834 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 835 836 if (cpu_has_amd_erratum(c, amd_erratum_383)) 837 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 838 } 839 840 static void init_amd_ln(struct cpuinfo_x86 *c) 841 { 842 /* 843 * Apply erratum 665 fix unconditionally so machines without a BIOS 844 * fix work. 845 */ 846 msr_set_bit(MSR_AMD64_DE_CFG, 31); 847 } 848 849 static bool rdrand_force; 850 851 static int __init rdrand_cmdline(char *str) 852 { 853 if (!str) 854 return -EINVAL; 855 856 if (!strcmp(str, "force")) 857 rdrand_force = true; 858 else 859 return -EINVAL; 860 861 return 0; 862 } 863 early_param("rdrand", rdrand_cmdline); 864 865 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 866 { 867 /* 868 * Saving of the MSR used to hide the RDRAND support during 869 * suspend/resume is done by arch/x86/power/cpu.c, which is 870 * dependent on CONFIG_PM_SLEEP. 871 */ 872 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 873 return; 874 875 /* 876 * The self-test can clear X86_FEATURE_RDRAND, so check for 877 * RDRAND support using the CPUID function directly. 878 */ 879 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 880 return; 881 882 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 883 884 /* 885 * Verify that the CPUID change has occurred in case the kernel is 886 * running virtualized and the hypervisor doesn't support the MSR. 887 */ 888 if (cpuid_ecx(1) & BIT(30)) { 889 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 890 return; 891 } 892 893 clear_cpu_cap(c, X86_FEATURE_RDRAND); 894 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 895 } 896 897 static void init_amd_jg(struct cpuinfo_x86 *c) 898 { 899 /* 900 * Some BIOS implementations do not restore proper RDRAND support 901 * across suspend and resume. Check on whether to hide the RDRAND 902 * instruction support via CPUID. 903 */ 904 clear_rdrand_cpuid_bit(c); 905 } 906 907 static void init_amd_bd(struct cpuinfo_x86 *c) 908 { 909 u64 value; 910 911 /* 912 * The way access filter has a performance penalty on some workloads. 913 * Disable it on the affected CPUs. 914 */ 915 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 916 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 917 value |= 0x1E; 918 wrmsrl_safe(MSR_F15H_IC_CFG, value); 919 } 920 } 921 922 /* 923 * Some BIOS implementations do not restore proper RDRAND support 924 * across suspend and resume. Check on whether to hide the RDRAND 925 * instruction support via CPUID. 926 */ 927 clear_rdrand_cpuid_bit(c); 928 } 929 930 void init_spectral_chicken(struct cpuinfo_x86 *c) 931 { 932 #ifdef CONFIG_CPU_UNRET_ENTRY 933 u64 value; 934 935 /* 936 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 937 * 938 * This suppresses speculation from the middle of a basic block, i.e. it 939 * suppresses non-branch predictions. 940 * 941 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H 942 */ 943 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) { 944 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 945 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 946 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 947 } 948 } 949 #endif 950 /* 951 * Work around Erratum 1386. The XSAVES instruction malfunctions in 952 * certain circumstances on Zen1/2 uarch, and not all parts have had 953 * updated microcode at the time of writing (March 2023). 954 * 955 * Affected parts all have no supervisor XSAVE states, meaning that 956 * the XSAVEC instruction (which works fine) is equivalent. 957 */ 958 clear_cpu_cap(c, X86_FEATURE_XSAVES); 959 } 960 961 static void init_amd_zn(struct cpuinfo_x86 *c) 962 { 963 set_cpu_cap(c, X86_FEATURE_ZEN); 964 965 #ifdef CONFIG_NUMA 966 node_reclaim_distance = 32; 967 #endif 968 969 /* Fix up CPUID bits, but only if not virtualised. */ 970 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 971 972 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 973 if (!cpu_has(c, X86_FEATURE_CPB)) 974 set_cpu_cap(c, X86_FEATURE_CPB); 975 976 /* 977 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 978 * Branch Type Confusion, but predate the allocation of the 979 * BTC_NO bit. 980 */ 981 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO)) 982 set_cpu_cap(c, X86_FEATURE_BTC_NO); 983 } 984 } 985 986 static bool cpu_has_zenbleed_microcode(void) 987 { 988 u32 good_rev = 0; 989 990 switch (boot_cpu_data.x86_model) { 991 case 0x30 ... 0x3f: good_rev = 0x0830107a; break; 992 case 0x60 ... 0x67: good_rev = 0x0860010b; break; 993 case 0x68 ... 0x6f: good_rev = 0x08608105; break; 994 case 0x70 ... 0x7f: good_rev = 0x08701032; break; 995 case 0xa0 ... 0xaf: good_rev = 0x08a00008; break; 996 997 default: 998 return false; 999 break; 1000 } 1001 1002 if (boot_cpu_data.microcode < good_rev) 1003 return false; 1004 1005 return true; 1006 } 1007 1008 static void zenbleed_check(struct cpuinfo_x86 *c) 1009 { 1010 if (!cpu_has_amd_erratum(c, amd_zenbleed)) 1011 return; 1012 1013 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 1014 return; 1015 1016 if (!cpu_has(c, X86_FEATURE_AVX)) 1017 return; 1018 1019 if (!cpu_has_zenbleed_microcode()) { 1020 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 1021 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 1022 } else { 1023 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 1024 } 1025 } 1026 1027 static void init_amd(struct cpuinfo_x86 *c) 1028 { 1029 early_init_amd(c); 1030 1031 /* 1032 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 1033 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 1034 */ 1035 clear_cpu_cap(c, 0*32+31); 1036 1037 if (c->x86 >= 0x10) 1038 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 1039 1040 /* AMD FSRM also implies FSRS */ 1041 if (cpu_has(c, X86_FEATURE_FSRM)) 1042 set_cpu_cap(c, X86_FEATURE_FSRS); 1043 1044 /* get apicid instead of initial apic id from cpuid */ 1045 c->apicid = hard_smp_processor_id(); 1046 1047 /* K6s reports MCEs but don't actually have all the MSRs */ 1048 if (c->x86 < 6) 1049 clear_cpu_cap(c, X86_FEATURE_MCE); 1050 1051 switch (c->x86) { 1052 case 4: init_amd_k5(c); break; 1053 case 5: init_amd_k6(c); break; 1054 case 6: init_amd_k7(c); break; 1055 case 0xf: init_amd_k8(c); break; 1056 case 0x10: init_amd_gh(c); break; 1057 case 0x12: init_amd_ln(c); break; 1058 case 0x15: init_amd_bd(c); break; 1059 case 0x16: init_amd_jg(c); break; 1060 case 0x17: init_spectral_chicken(c); 1061 fallthrough; 1062 case 0x19: init_amd_zn(c); break; 1063 } 1064 1065 /* 1066 * Enable workaround for FXSAVE leak on CPUs 1067 * without a XSaveErPtr feature 1068 */ 1069 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1070 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1071 1072 cpu_detect_cache_sizes(c); 1073 1074 amd_detect_cmp(c); 1075 amd_get_topology(c); 1076 srat_detect_node(c); 1077 1078 init_amd_cacheinfo(c); 1079 1080 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1081 /* 1082 * Use LFENCE for execution serialization. On families which 1083 * don't have that MSR, LFENCE is already serializing. 1084 * msr_set_bit() uses the safe accessors, too, even if the MSR 1085 * is not present. 1086 */ 1087 msr_set_bit(MSR_AMD64_DE_CFG, 1088 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1089 1090 /* A serializing LFENCE stops RDTSC speculation */ 1091 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1092 } 1093 1094 /* 1095 * Family 0x12 and above processors have APIC timer 1096 * running in deep C states. 1097 */ 1098 if (c->x86 > 0x11) 1099 set_cpu_cap(c, X86_FEATURE_ARAT); 1100 1101 /* 3DNow or LM implies PREFETCHW */ 1102 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1103 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1104 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1105 1106 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1107 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1108 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1109 1110 /* 1111 * Turn on the Instructions Retired free counter on machines not 1112 * susceptible to erratum #1054 "Instructions Retired Performance 1113 * Counter May Be Inaccurate". 1114 */ 1115 if (cpu_has(c, X86_FEATURE_IRPERF) && 1116 !cpu_has_amd_erratum(c, amd_erratum_1054)) 1117 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1118 1119 check_null_seg_clears_base(c); 1120 1121 /* 1122 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1123 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1124 * order to be replicated onto them. Regardless, set it here again, if not set, 1125 * to protect against any future refactoring/code reorganization which might 1126 * miss setting this important bit. 1127 */ 1128 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1129 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1130 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS)); 1131 1132 zenbleed_check(c); 1133 } 1134 1135 #ifdef CONFIG_X86_32 1136 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1137 { 1138 /* AMD errata T13 (order #21922) */ 1139 if (c->x86 == 6) { 1140 /* Duron Rev A0 */ 1141 if (c->x86_model == 3 && c->x86_stepping == 0) 1142 size = 64; 1143 /* Tbird rev A1/A2 */ 1144 if (c->x86_model == 4 && 1145 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1146 size = 256; 1147 } 1148 return size; 1149 } 1150 #endif 1151 1152 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1153 { 1154 u32 ebx, eax, ecx, edx; 1155 u16 mask = 0xfff; 1156 1157 if (c->x86 < 0xf) 1158 return; 1159 1160 if (c->extended_cpuid_level < 0x80000006) 1161 return; 1162 1163 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1164 1165 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1166 tlb_lli_4k[ENTRIES] = ebx & mask; 1167 1168 /* 1169 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1170 * characteristics from the CPUID function 0x80000005 instead. 1171 */ 1172 if (c->x86 == 0xf) { 1173 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1174 mask = 0xff; 1175 } 1176 1177 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1178 if (!((eax >> 16) & mask)) 1179 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1180 else 1181 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1182 1183 /* a 4M entry uses two 2M entries */ 1184 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1185 1186 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1187 if (!(eax & mask)) { 1188 /* Erratum 658 */ 1189 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1190 tlb_lli_2m[ENTRIES] = 1024; 1191 } else { 1192 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1193 tlb_lli_2m[ENTRIES] = eax & 0xff; 1194 } 1195 } else 1196 tlb_lli_2m[ENTRIES] = eax & mask; 1197 1198 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1199 } 1200 1201 static const struct cpu_dev amd_cpu_dev = { 1202 .c_vendor = "AMD", 1203 .c_ident = { "AuthenticAMD" }, 1204 #ifdef CONFIG_X86_32 1205 .legacy_models = { 1206 { .family = 4, .model_names = 1207 { 1208 [3] = "486 DX/2", 1209 [7] = "486 DX/2-WB", 1210 [8] = "486 DX/4", 1211 [9] = "486 DX/4-WB", 1212 [14] = "Am5x86-WT", 1213 [15] = "Am5x86-WB" 1214 } 1215 }, 1216 }, 1217 .legacy_cache_size = amd_size_cache, 1218 #endif 1219 .c_early_init = early_init_amd, 1220 .c_detect_tlb = cpu_detect_tlb_amd, 1221 .c_bsp_init = bsp_init_amd, 1222 .c_init = init_amd, 1223 .c_x86_vendor = X86_VENDOR_AMD, 1224 }; 1225 1226 cpu_dev_register(amd_cpu_dev); 1227 1228 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1229 1230 static unsigned int amd_msr_dr_addr_masks[] = { 1231 MSR_F16H_DR0_ADDR_MASK, 1232 MSR_F16H_DR1_ADDR_MASK, 1233 MSR_F16H_DR1_ADDR_MASK + 1, 1234 MSR_F16H_DR1_ADDR_MASK + 2 1235 }; 1236 1237 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1238 { 1239 int cpu = smp_processor_id(); 1240 1241 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1242 return; 1243 1244 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1245 return; 1246 1247 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1248 return; 1249 1250 wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); 1251 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1252 } 1253 1254 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1255 { 1256 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1257 return 0; 1258 1259 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1260 return 0; 1261 1262 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1263 } 1264 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); 1265 1266 u32 amd_get_highest_perf(void) 1267 { 1268 struct cpuinfo_x86 *c = &boot_cpu_data; 1269 1270 if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) || 1271 (c->x86_model >= 0x70 && c->x86_model < 0x80))) 1272 return 166; 1273 1274 if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) || 1275 (c->x86_model >= 0x40 && c->x86_model < 0x70))) 1276 return 166; 1277 1278 return 255; 1279 } 1280 EXPORT_SYMBOL_GPL(amd_get_highest_perf); 1281 1282 static void zenbleed_check_cpu(void *unused) 1283 { 1284 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1285 1286 zenbleed_check(c); 1287 } 1288 1289 void amd_check_microcode(void) 1290 { 1291 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1292 } 1293