1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/random.h> 10 #include <asm/processor.h> 11 #include <asm/apic.h> 12 #include <asm/cacheinfo.h> 13 #include <asm/cpu.h> 14 #include <asm/spec-ctrl.h> 15 #include <asm/smp.h> 16 #include <asm/pci-direct.h> 17 #include <asm/delay.h> 18 19 #ifdef CONFIG_X86_64 20 # include <asm/mmconfig.h> 21 # include <asm/set_memory.h> 22 #endif 23 24 #include "cpu.h" 25 26 static const int amd_erratum_383[]; 27 static const int amd_erratum_400[]; 28 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 29 30 /* 31 * nodes_per_socket: Stores the number of nodes per socket. 32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 33 * Node Identifiers[10:8] 34 */ 35 static u32 nodes_per_socket = 1; 36 37 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 38 { 39 u32 gprs[8] = { 0 }; 40 int err; 41 42 WARN_ONCE((boot_cpu_data.x86 != 0xf), 43 "%s should only be used on K8!\n", __func__); 44 45 gprs[1] = msr; 46 gprs[7] = 0x9c5a203a; 47 48 err = rdmsr_safe_regs(gprs); 49 50 *p = gprs[0] | ((u64)gprs[2] << 32); 51 52 return err; 53 } 54 55 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 56 { 57 u32 gprs[8] = { 0 }; 58 59 WARN_ONCE((boot_cpu_data.x86 != 0xf), 60 "%s should only be used on K8!\n", __func__); 61 62 gprs[0] = (u32)val; 63 gprs[1] = msr; 64 gprs[2] = val >> 32; 65 gprs[7] = 0x9c5a203a; 66 67 return wrmsr_safe_regs(gprs); 68 } 69 70 /* 71 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 72 * misexecution of code under Linux. Owners of such processors should 73 * contact AMD for precise details and a CPU swap. 74 * 75 * See http://www.multimania.com/poulot/k6bug.html 76 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 77 * (Publication # 21266 Issue Date: August 1998) 78 * 79 * The following test is erm.. interesting. AMD neglected to up 80 * the chip setting when fixing the bug but they also tweaked some 81 * performance at the same time.. 82 */ 83 84 extern __visible void vide(void); 85 __asm__(".globl vide\n" 86 ".type vide, @function\n" 87 ".align 4\n" 88 "vide: ret\n"); 89 90 static void init_amd_k5(struct cpuinfo_x86 *c) 91 { 92 #ifdef CONFIG_X86_32 93 /* 94 * General Systems BIOSen alias the cpu frequency registers 95 * of the Elan at 0x000df000. Unfortunately, one of the Linux 96 * drivers subsequently pokes it, and changes the CPU speed. 97 * Workaround : Remove the unneeded alias. 98 */ 99 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 100 #define CBAR_ENB (0x80000000) 101 #define CBAR_KEY (0X000000CB) 102 if (c->x86_model == 9 || c->x86_model == 10) { 103 if (inl(CBAR) & CBAR_ENB) 104 outl(0 | CBAR_KEY, CBAR); 105 } 106 #endif 107 } 108 109 static void init_amd_k6(struct cpuinfo_x86 *c) 110 { 111 #ifdef CONFIG_X86_32 112 u32 l, h; 113 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 114 115 if (c->x86_model < 6) { 116 /* Based on AMD doc 20734R - June 2000 */ 117 if (c->x86_model == 0) { 118 clear_cpu_cap(c, X86_FEATURE_APIC); 119 set_cpu_cap(c, X86_FEATURE_PGE); 120 } 121 return; 122 } 123 124 if (c->x86_model == 6 && c->x86_stepping == 1) { 125 const int K6_BUG_LOOP = 1000000; 126 int n; 127 void (*f_vide)(void); 128 u64 d, d2; 129 130 pr_info("AMD K6 stepping B detected - "); 131 132 /* 133 * It looks like AMD fixed the 2.6.2 bug and improved indirect 134 * calls at the same time. 135 */ 136 137 n = K6_BUG_LOOP; 138 f_vide = vide; 139 OPTIMIZER_HIDE_VAR(f_vide); 140 d = rdtsc(); 141 while (n--) 142 f_vide(); 143 d2 = rdtsc(); 144 d = d2-d; 145 146 if (d > 20*K6_BUG_LOOP) 147 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 148 else 149 pr_cont("probably OK (after B9730xxxx).\n"); 150 } 151 152 /* K6 with old style WHCR */ 153 if (c->x86_model < 8 || 154 (c->x86_model == 8 && c->x86_stepping < 8)) { 155 /* We can only write allocate on the low 508Mb */ 156 if (mbytes > 508) 157 mbytes = 508; 158 159 rdmsr(MSR_K6_WHCR, l, h); 160 if ((l&0x0000FFFF) == 0) { 161 unsigned long flags; 162 l = (1<<0)|((mbytes/4)<<1); 163 local_irq_save(flags); 164 wbinvd(); 165 wrmsr(MSR_K6_WHCR, l, h); 166 local_irq_restore(flags); 167 pr_info("Enabling old style K6 write allocation for %d Mb\n", 168 mbytes); 169 } 170 return; 171 } 172 173 if ((c->x86_model == 8 && c->x86_stepping > 7) || 174 c->x86_model == 9 || c->x86_model == 13) { 175 /* The more serious chips .. */ 176 177 if (mbytes > 4092) 178 mbytes = 4092; 179 180 rdmsr(MSR_K6_WHCR, l, h); 181 if ((l&0xFFFF0000) == 0) { 182 unsigned long flags; 183 l = ((mbytes>>2)<<22)|(1<<16); 184 local_irq_save(flags); 185 wbinvd(); 186 wrmsr(MSR_K6_WHCR, l, h); 187 local_irq_restore(flags); 188 pr_info("Enabling new style K6 write allocation for %d Mb\n", 189 mbytes); 190 } 191 192 return; 193 } 194 195 if (c->x86_model == 10) { 196 /* AMD Geode LX is model 10 */ 197 /* placeholder for any needed mods */ 198 return; 199 } 200 #endif 201 } 202 203 static void init_amd_k7(struct cpuinfo_x86 *c) 204 { 205 #ifdef CONFIG_X86_32 206 u32 l, h; 207 208 /* 209 * Bit 15 of Athlon specific MSR 15, needs to be 0 210 * to enable SSE on Palomino/Morgan/Barton CPU's. 211 * If the BIOS didn't enable it already, enable it here. 212 */ 213 if (c->x86_model >= 6 && c->x86_model <= 10) { 214 if (!cpu_has(c, X86_FEATURE_XMM)) { 215 pr_info("Enabling disabled K7/SSE Support.\n"); 216 msr_clear_bit(MSR_K7_HWCR, 15); 217 set_cpu_cap(c, X86_FEATURE_XMM); 218 } 219 } 220 221 /* 222 * It's been determined by AMD that Athlons since model 8 stepping 1 223 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 224 * As per AMD technical note 27212 0.2 225 */ 226 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 227 rdmsr(MSR_K7_CLK_CTL, l, h); 228 if ((l & 0xfff00000) != 0x20000000) { 229 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 230 l, ((l & 0x000fffff)|0x20000000)); 231 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 232 } 233 } 234 235 /* calling is from identify_secondary_cpu() ? */ 236 if (!c->cpu_index) 237 return; 238 239 /* 240 * Certain Athlons might work (for various values of 'work') in SMP 241 * but they are not certified as MP capable. 242 */ 243 /* Athlon 660/661 is valid. */ 244 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 245 (c->x86_stepping == 1))) 246 return; 247 248 /* Duron 670 is valid */ 249 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 250 return; 251 252 /* 253 * Athlon 662, Duron 671, and Athlon >model 7 have capability 254 * bit. It's worth noting that the A5 stepping (662) of some 255 * Athlon XP's have the MP bit set. 256 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 257 * more. 258 */ 259 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 260 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 261 (c->x86_model > 7)) 262 if (cpu_has(c, X86_FEATURE_MP)) 263 return; 264 265 /* If we get here, not a certified SMP capable AMD system. */ 266 267 /* 268 * Don't taint if we are running SMP kernel on a single non-MP 269 * approved Athlon 270 */ 271 WARN_ONCE(1, "WARNING: This combination of AMD" 272 " processors is not suitable for SMP.\n"); 273 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 274 #endif 275 } 276 277 #ifdef CONFIG_NUMA 278 /* 279 * To workaround broken NUMA config. Read the comment in 280 * srat_detect_node(). 281 */ 282 static int nearby_node(int apicid) 283 { 284 int i, node; 285 286 for (i = apicid - 1; i >= 0; i--) { 287 node = __apicid_to_node[i]; 288 if (node != NUMA_NO_NODE && node_online(node)) 289 return node; 290 } 291 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 292 node = __apicid_to_node[i]; 293 if (node != NUMA_NO_NODE && node_online(node)) 294 return node; 295 } 296 return first_node(node_online_map); /* Shouldn't happen */ 297 } 298 #endif 299 300 /* 301 * Fix up cpu_core_id for pre-F17h systems to be in the 302 * [0 .. cores_per_node - 1] range. Not really needed but 303 * kept so as not to break existing setups. 304 */ 305 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 306 { 307 u32 cus_per_node; 308 309 if (c->x86 >= 0x17) 310 return; 311 312 cus_per_node = c->x86_max_cores / nodes_per_socket; 313 c->cpu_core_id %= cus_per_node; 314 } 315 316 317 static void amd_get_topology_early(struct cpuinfo_x86 *c) 318 { 319 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 320 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 321 } 322 323 /* 324 * Fixup core topology information for 325 * (1) AMD multi-node processors 326 * Assumption: Number of cores in each internal node is the same. 327 * (2) AMD processors supporting compute units 328 */ 329 static void amd_get_topology(struct cpuinfo_x86 *c) 330 { 331 u8 node_id; 332 int cpu = smp_processor_id(); 333 334 /* get information required for multi-node processors */ 335 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 336 int err; 337 u32 eax, ebx, ecx, edx; 338 339 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 340 341 node_id = ecx & 0xff; 342 343 if (c->x86 == 0x15) 344 c->cu_id = ebx & 0xff; 345 346 if (c->x86 >= 0x17) { 347 c->cpu_core_id = ebx & 0xff; 348 349 if (smp_num_siblings > 1) 350 c->x86_max_cores /= smp_num_siblings; 351 } 352 353 /* 354 * In case leaf B is available, use it to derive 355 * topology information. 356 */ 357 err = detect_extended_topology(c); 358 if (!err) 359 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 360 361 cacheinfo_amd_init_llc_id(c, cpu, node_id); 362 363 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 364 u64 value; 365 366 rdmsrl(MSR_FAM10H_NODE_ID, value); 367 node_id = value & 7; 368 369 per_cpu(cpu_llc_id, cpu) = node_id; 370 } else 371 return; 372 373 if (nodes_per_socket > 1) { 374 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 375 legacy_fixup_core_id(c); 376 } 377 } 378 379 /* 380 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 381 * Assumes number of cores is a power of two. 382 */ 383 static void amd_detect_cmp(struct cpuinfo_x86 *c) 384 { 385 unsigned bits; 386 int cpu = smp_processor_id(); 387 388 bits = c->x86_coreid_bits; 389 /* Low order bits define the core id (index of core in socket) */ 390 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 391 /* Convert the initial APIC ID into the socket ID */ 392 c->phys_proc_id = c->initial_apicid >> bits; 393 /* use socket ID also for last level cache */ 394 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 395 } 396 397 u16 amd_get_nb_id(int cpu) 398 { 399 return per_cpu(cpu_llc_id, cpu); 400 } 401 EXPORT_SYMBOL_GPL(amd_get_nb_id); 402 403 u32 amd_get_nodes_per_socket(void) 404 { 405 return nodes_per_socket; 406 } 407 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 408 409 static void srat_detect_node(struct cpuinfo_x86 *c) 410 { 411 #ifdef CONFIG_NUMA 412 int cpu = smp_processor_id(); 413 int node; 414 unsigned apicid = c->apicid; 415 416 node = numa_cpu_node(cpu); 417 if (node == NUMA_NO_NODE) 418 node = per_cpu(cpu_llc_id, cpu); 419 420 /* 421 * On multi-fabric platform (e.g. Numascale NumaChip) a 422 * platform-specific handler needs to be called to fixup some 423 * IDs of the CPU. 424 */ 425 if (x86_cpuinit.fixup_cpu_id) 426 x86_cpuinit.fixup_cpu_id(c, node); 427 428 if (!node_online(node)) { 429 /* 430 * Two possibilities here: 431 * 432 * - The CPU is missing memory and no node was created. In 433 * that case try picking one from a nearby CPU. 434 * 435 * - The APIC IDs differ from the HyperTransport node IDs 436 * which the K8 northbridge parsing fills in. Assume 437 * they are all increased by a constant offset, but in 438 * the same order as the HT nodeids. If that doesn't 439 * result in a usable node fall back to the path for the 440 * previous case. 441 * 442 * This workaround operates directly on the mapping between 443 * APIC ID and NUMA node, assuming certain relationship 444 * between APIC ID, HT node ID and NUMA topology. As going 445 * through CPU mapping may alter the outcome, directly 446 * access __apicid_to_node[]. 447 */ 448 int ht_nodeid = c->initial_apicid; 449 450 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 451 node = __apicid_to_node[ht_nodeid]; 452 /* Pick a nearby node */ 453 if (!node_online(node)) 454 node = nearby_node(apicid); 455 } 456 numa_set_node(cpu, node); 457 #endif 458 } 459 460 static void early_init_amd_mc(struct cpuinfo_x86 *c) 461 { 462 #ifdef CONFIG_SMP 463 unsigned bits, ecx; 464 465 /* Multi core CPU? */ 466 if (c->extended_cpuid_level < 0x80000008) 467 return; 468 469 ecx = cpuid_ecx(0x80000008); 470 471 c->x86_max_cores = (ecx & 0xff) + 1; 472 473 /* CPU telling us the core id bits shift? */ 474 bits = (ecx >> 12) & 0xF; 475 476 /* Otherwise recompute */ 477 if (bits == 0) { 478 while ((1 << bits) < c->x86_max_cores) 479 bits++; 480 } 481 482 c->x86_coreid_bits = bits; 483 #endif 484 } 485 486 static void bsp_init_amd(struct cpuinfo_x86 *c) 487 { 488 489 #ifdef CONFIG_X86_64 490 if (c->x86 >= 0xf) { 491 unsigned long long tseg; 492 493 /* 494 * Split up direct mapping around the TSEG SMM area. 495 * Don't do it for gbpages because there seems very little 496 * benefit in doing so. 497 */ 498 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 499 unsigned long pfn = tseg >> PAGE_SHIFT; 500 501 pr_debug("tseg: %010llx\n", tseg); 502 if (pfn_range_is_mapped(pfn, pfn + 1)) 503 set_memory_4k((unsigned long)__va(tseg), 1); 504 } 505 } 506 #endif 507 508 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 509 510 if (c->x86 > 0x10 || 511 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 512 u64 val; 513 514 rdmsrl(MSR_K7_HWCR, val); 515 if (!(val & BIT(24))) 516 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 517 } 518 } 519 520 if (c->x86 == 0x15) { 521 unsigned long upperbit; 522 u32 cpuid, assoc; 523 524 cpuid = cpuid_edx(0x80000005); 525 assoc = cpuid >> 16 & 0xff; 526 upperbit = ((cpuid >> 24) << 10) / assoc; 527 528 va_align.mask = (upperbit - 1) & PAGE_MASK; 529 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 530 531 /* A random value per boot for bit slice [12:upper_bit) */ 532 va_align.bits = get_random_int() & va_align.mask; 533 } 534 535 if (cpu_has(c, X86_FEATURE_MWAITX)) 536 use_mwaitx_delay(); 537 538 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 539 u32 ecx; 540 541 ecx = cpuid_ecx(0x8000001e); 542 nodes_per_socket = ((ecx >> 8) & 7) + 1; 543 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 544 u64 value; 545 546 rdmsrl(MSR_FAM10H_NODE_ID, value); 547 nodes_per_socket = ((value >> 3) & 7) + 1; 548 } 549 550 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 551 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 552 c->x86 >= 0x15 && c->x86 <= 0x17) { 553 unsigned int bit; 554 555 switch (c->x86) { 556 case 0x15: bit = 54; break; 557 case 0x16: bit = 33; break; 558 case 0x17: bit = 10; break; 559 default: return; 560 } 561 /* 562 * Try to cache the base value so further operations can 563 * avoid RMW. If that faults, do not enable SSBD. 564 */ 565 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 566 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 567 setup_force_cpu_cap(X86_FEATURE_SSBD); 568 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 569 } 570 } 571 } 572 573 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 574 { 575 u64 msr; 576 577 /* 578 * BIOS support is required for SME and SEV. 579 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 580 * the SME physical address space reduction value. 581 * If BIOS has not enabled SME then don't advertise the 582 * SME feature (set in scattered.c). 583 * For SEV: If BIOS has not enabled SEV then don't advertise the 584 * SEV feature (set in scattered.c). 585 * 586 * In all cases, since support for SME and SEV requires long mode, 587 * don't advertise the feature under CONFIG_X86_32. 588 */ 589 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 590 /* Check if memory encryption is enabled */ 591 rdmsrl(MSR_K8_SYSCFG, msr); 592 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 593 goto clear_all; 594 595 /* 596 * Always adjust physical address bits. Even though this 597 * will be a value above 32-bits this is still done for 598 * CONFIG_X86_32 so that accurate values are reported. 599 */ 600 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 601 602 if (IS_ENABLED(CONFIG_X86_32)) 603 goto clear_all; 604 605 rdmsrl(MSR_K7_HWCR, msr); 606 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 607 goto clear_sev; 608 609 return; 610 611 clear_all: 612 clear_cpu_cap(c, X86_FEATURE_SME); 613 clear_sev: 614 clear_cpu_cap(c, X86_FEATURE_SEV); 615 } 616 } 617 618 static void early_init_amd(struct cpuinfo_x86 *c) 619 { 620 u64 value; 621 u32 dummy; 622 623 early_init_amd_mc(c); 624 625 #ifdef CONFIG_X86_32 626 if (c->x86 == 6) 627 set_cpu_cap(c, X86_FEATURE_K7); 628 #endif 629 630 if (c->x86 >= 0xf) 631 set_cpu_cap(c, X86_FEATURE_K8); 632 633 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 634 635 /* 636 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 637 * with P/T states and does not stop in deep C-states 638 */ 639 if (c->x86_power & (1 << 8)) { 640 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 641 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 642 } 643 644 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 645 if (c->x86_power & BIT(12)) 646 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 647 648 #ifdef CONFIG_X86_64 649 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 650 #else 651 /* Set MTRR capability flag if appropriate */ 652 if (c->x86 == 5) 653 if (c->x86_model == 13 || c->x86_model == 9 || 654 (c->x86_model == 8 && c->x86_stepping >= 8)) 655 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 656 #endif 657 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 658 /* 659 * ApicID can always be treated as an 8-bit value for AMD APIC versions 660 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 661 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 662 * after 16h. 663 */ 664 if (boot_cpu_has(X86_FEATURE_APIC)) { 665 if (c->x86 > 0x16) 666 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 667 else if (c->x86 >= 0xf) { 668 /* check CPU config space for extended APIC ID */ 669 unsigned int val; 670 671 val = read_pci_config(0, 24, 0, 0x68); 672 if ((val >> 17 & 0x3) == 0x3) 673 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 674 } 675 } 676 #endif 677 678 /* 679 * This is only needed to tell the kernel whether to use VMCALL 680 * and VMMCALL. VMMCALL is never executed except under virt, so 681 * we can set it unconditionally. 682 */ 683 set_cpu_cap(c, X86_FEATURE_VMMCALL); 684 685 /* F16h erratum 793, CVE-2013-6885 */ 686 if (c->x86 == 0x16 && c->x86_model <= 0xf) 687 msr_set_bit(MSR_AMD64_LS_CFG, 15); 688 689 /* 690 * Check whether the machine is affected by erratum 400. This is 691 * used to select the proper idle routine and to enable the check 692 * whether the machine is affected in arch_post_acpi_init(), which 693 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 694 */ 695 if (cpu_has_amd_erratum(c, amd_erratum_400)) 696 set_cpu_bug(c, X86_BUG_AMD_E400); 697 698 early_detect_mem_encrypt(c); 699 700 /* Re-enable TopologyExtensions if switched off by BIOS */ 701 if (c->x86 == 0x15 && 702 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 703 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 704 705 if (msr_set_bit(0xc0011005, 54) > 0) { 706 rdmsrl(0xc0011005, value); 707 if (value & BIT_64(54)) { 708 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 709 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 710 } 711 } 712 } 713 714 amd_get_topology_early(c); 715 } 716 717 static void init_amd_k8(struct cpuinfo_x86 *c) 718 { 719 u32 level; 720 u64 value; 721 722 /* On C+ stepping K8 rep microcode works well for copy/memset */ 723 level = cpuid_eax(1); 724 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 725 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 726 727 /* 728 * Some BIOSes incorrectly force this feature, but only K8 revision D 729 * (model = 0x14) and later actually support it. 730 * (AMD Erratum #110, docId: 25759). 731 */ 732 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 733 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 734 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 735 value &= ~BIT_64(32); 736 wrmsrl_amd_safe(0xc001100d, value); 737 } 738 } 739 740 if (!c->x86_model_id[0]) 741 strcpy(c->x86_model_id, "Hammer"); 742 743 #ifdef CONFIG_SMP 744 /* 745 * Disable TLB flush filter by setting HWCR.FFDIS on K8 746 * bit 6 of msr C001_0015 747 * 748 * Errata 63 for SH-B3 steppings 749 * Errata 122 for all steppings (F+ have it disabled by default) 750 */ 751 msr_set_bit(MSR_K7_HWCR, 6); 752 #endif 753 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 754 } 755 756 static void init_amd_gh(struct cpuinfo_x86 *c) 757 { 758 #ifdef CONFIG_MMCONF_FAM10H 759 /* do this for boot cpu */ 760 if (c == &boot_cpu_data) 761 check_enable_amd_mmconf_dmi(); 762 763 fam10h_check_enable_mmcfg(); 764 #endif 765 766 /* 767 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 768 * is always needed when GART is enabled, even in a kernel which has no 769 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 770 * If it doesn't, we do it here as suggested by the BKDG. 771 * 772 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 773 */ 774 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 775 776 /* 777 * On family 10h BIOS may not have properly enabled WC+ support, causing 778 * it to be converted to CD memtype. This may result in performance 779 * degradation for certain nested-paging guests. Prevent this conversion 780 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 781 * 782 * NOTE: we want to use the _safe accessors so as not to #GP kvm 783 * guests on older kvm hosts. 784 */ 785 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 786 787 if (cpu_has_amd_erratum(c, amd_erratum_383)) 788 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 789 } 790 791 #define MSR_AMD64_DE_CFG 0xC0011029 792 793 static void init_amd_ln(struct cpuinfo_x86 *c) 794 { 795 /* 796 * Apply erratum 665 fix unconditionally so machines without a BIOS 797 * fix work. 798 */ 799 msr_set_bit(MSR_AMD64_DE_CFG, 31); 800 } 801 802 static void init_amd_bd(struct cpuinfo_x86 *c) 803 { 804 u64 value; 805 806 /* 807 * The way access filter has a performance penalty on some workloads. 808 * Disable it on the affected CPUs. 809 */ 810 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 811 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 812 value |= 0x1E; 813 wrmsrl_safe(MSR_F15H_IC_CFG, value); 814 } 815 } 816 } 817 818 static void init_amd_zn(struct cpuinfo_x86 *c) 819 { 820 set_cpu_cap(c, X86_FEATURE_ZEN); 821 /* 822 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects 823 * all up to and including B1. 824 */ 825 if (c->x86_model <= 1 && c->x86_stepping <= 1) 826 set_cpu_cap(c, X86_FEATURE_CPB); 827 } 828 829 static void init_amd(struct cpuinfo_x86 *c) 830 { 831 early_init_amd(c); 832 833 /* 834 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 835 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 836 */ 837 clear_cpu_cap(c, 0*32+31); 838 839 if (c->x86 >= 0x10) 840 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 841 842 /* get apicid instead of initial apic id from cpuid */ 843 c->apicid = hard_smp_processor_id(); 844 845 /* K6s reports MCEs but don't actually have all the MSRs */ 846 if (c->x86 < 6) 847 clear_cpu_cap(c, X86_FEATURE_MCE); 848 849 switch (c->x86) { 850 case 4: init_amd_k5(c); break; 851 case 5: init_amd_k6(c); break; 852 case 6: init_amd_k7(c); break; 853 case 0xf: init_amd_k8(c); break; 854 case 0x10: init_amd_gh(c); break; 855 case 0x12: init_amd_ln(c); break; 856 case 0x15: init_amd_bd(c); break; 857 case 0x17: init_amd_zn(c); break; 858 } 859 860 /* 861 * Enable workaround for FXSAVE leak on CPUs 862 * without a XSaveErPtr feature 863 */ 864 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 865 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 866 867 cpu_detect_cache_sizes(c); 868 869 amd_detect_cmp(c); 870 amd_get_topology(c); 871 srat_detect_node(c); 872 873 init_amd_cacheinfo(c); 874 875 if (cpu_has(c, X86_FEATURE_XMM2)) { 876 unsigned long long val; 877 int ret; 878 879 /* 880 * A serializing LFENCE has less overhead than MFENCE, so 881 * use it for execution serialization. On families which 882 * don't have that MSR, LFENCE is already serializing. 883 * msr_set_bit() uses the safe accessors, too, even if the MSR 884 * is not present. 885 */ 886 msr_set_bit(MSR_F10H_DECFG, 887 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 888 889 /* 890 * Verify that the MSR write was successful (could be running 891 * under a hypervisor) and only then assume that LFENCE is 892 * serializing. 893 */ 894 ret = rdmsrl_safe(MSR_F10H_DECFG, &val); 895 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { 896 /* A serializing LFENCE stops RDTSC speculation */ 897 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 898 } else { 899 /* MFENCE stops RDTSC speculation */ 900 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 901 } 902 } 903 904 /* 905 * Family 0x12 and above processors have APIC timer 906 * running in deep C states. 907 */ 908 if (c->x86 > 0x11) 909 set_cpu_cap(c, X86_FEATURE_ARAT); 910 911 /* 3DNow or LM implies PREFETCHW */ 912 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 913 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 914 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 915 916 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 917 if (!cpu_has(c, X86_FEATURE_XENPV)) 918 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 919 } 920 921 #ifdef CONFIG_X86_32 922 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 923 { 924 /* AMD errata T13 (order #21922) */ 925 if ((c->x86 == 6)) { 926 /* Duron Rev A0 */ 927 if (c->x86_model == 3 && c->x86_stepping == 0) 928 size = 64; 929 /* Tbird rev A1/A2 */ 930 if (c->x86_model == 4 && 931 (c->x86_stepping == 0 || c->x86_stepping == 1)) 932 size = 256; 933 } 934 return size; 935 } 936 #endif 937 938 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 939 { 940 u32 ebx, eax, ecx, edx; 941 u16 mask = 0xfff; 942 943 if (c->x86 < 0xf) 944 return; 945 946 if (c->extended_cpuid_level < 0x80000006) 947 return; 948 949 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 950 951 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 952 tlb_lli_4k[ENTRIES] = ebx & mask; 953 954 /* 955 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 956 * characteristics from the CPUID function 0x80000005 instead. 957 */ 958 if (c->x86 == 0xf) { 959 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 960 mask = 0xff; 961 } 962 963 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 964 if (!((eax >> 16) & mask)) 965 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 966 else 967 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 968 969 /* a 4M entry uses two 2M entries */ 970 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 971 972 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 973 if (!(eax & mask)) { 974 /* Erratum 658 */ 975 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 976 tlb_lli_2m[ENTRIES] = 1024; 977 } else { 978 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 979 tlb_lli_2m[ENTRIES] = eax & 0xff; 980 } 981 } else 982 tlb_lli_2m[ENTRIES] = eax & mask; 983 984 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 985 } 986 987 static const struct cpu_dev amd_cpu_dev = { 988 .c_vendor = "AMD", 989 .c_ident = { "AuthenticAMD" }, 990 #ifdef CONFIG_X86_32 991 .legacy_models = { 992 { .family = 4, .model_names = 993 { 994 [3] = "486 DX/2", 995 [7] = "486 DX/2-WB", 996 [8] = "486 DX/4", 997 [9] = "486 DX/4-WB", 998 [14] = "Am5x86-WT", 999 [15] = "Am5x86-WB" 1000 } 1001 }, 1002 }, 1003 .legacy_cache_size = amd_size_cache, 1004 #endif 1005 .c_early_init = early_init_amd, 1006 .c_detect_tlb = cpu_detect_tlb_amd, 1007 .c_bsp_init = bsp_init_amd, 1008 .c_init = init_amd, 1009 .c_x86_vendor = X86_VENDOR_AMD, 1010 }; 1011 1012 cpu_dev_register(amd_cpu_dev); 1013 1014 /* 1015 * AMD errata checking 1016 * 1017 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1018 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1019 * have an OSVW id assigned, which it takes as first argument. Both take a 1020 * variable number of family-specific model-stepping ranges created by 1021 * AMD_MODEL_RANGE(). 1022 * 1023 * Example: 1024 * 1025 * const int amd_erratum_319[] = 1026 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1027 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1028 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1029 */ 1030 1031 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1032 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1033 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1034 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1035 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1036 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1037 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1038 1039 static const int amd_erratum_400[] = 1040 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1041 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1042 1043 static const int amd_erratum_383[] = 1044 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1045 1046 1047 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1048 { 1049 int osvw_id = *erratum++; 1050 u32 range; 1051 u32 ms; 1052 1053 if (osvw_id >= 0 && osvw_id < 65536 && 1054 cpu_has(cpu, X86_FEATURE_OSVW)) { 1055 u64 osvw_len; 1056 1057 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1058 if (osvw_id < osvw_len) { 1059 u64 osvw_bits; 1060 1061 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1062 osvw_bits); 1063 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1064 } 1065 } 1066 1067 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1068 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1069 while ((range = *erratum++)) 1070 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1071 (ms >= AMD_MODEL_RANGE_START(range)) && 1072 (ms <= AMD_MODEL_RANGE_END(range))) 1073 return true; 1074 1075 return false; 1076 } 1077 1078 void set_dr_addr_mask(unsigned long mask, int dr) 1079 { 1080 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1081 return; 1082 1083 switch (dr) { 1084 case 0: 1085 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1086 break; 1087 case 1: 1088 case 2: 1089 case 3: 1090 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1091 break; 1092 default: 1093 break; 1094 } 1095 } 1096